Semiconductor device

Abstract

The semiconductor device includes a sensing element and a filter. The sensing element includes a sensing electrode, and the filter covers the sensing electrode. The filter includes a first work function layer and a second work function layer. The first work function layer is disposed over the sensing electrode. The second work function layer is disposed over the first work function layer. The work function value of the second work function layer is greater than the work function value of the first work function layer, and the metal atom percentage of the second work function layer is greater than the metal atom percentage of the first work function layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth over the past several decades. Technological advances in semiconductor materials and design have produced increasingly smaller and more complex circuits. Technologies related to processing and manufacturing have also experienced technological advances that can be attributed to these material and design advances. During the course of semiconductor development, as the minimum component size that can be reliably manufactured has shrunk, the number of interconnected devices per unit area has also increased.

[0003] As dimensions shrink, it becomes more difficult to maintain the reliability of the patterning process and the yield produced by the patterning process. In some cases, the use of optical proximity correction and adjustment of lithography parameters such as process duration, wavelength, focus, and intensity of the light used can reduce some defects. However, current and systems for patterning material layers in semiconductor wafers have not been completely satisfactory. Utility Model Content

[0004] According to some embodiments of the present disclosure, a semiconductor device includes a sensing element and a filter. The sensing element includes a sensing electrode. The filter covers the sensing electrode and includes a first work function layer and a second work function layer. The first work function layer is disposed above the sensing electrode. The second work function layer is disposed above the first work function layer, and the work function value of the second work function layer is greater than the work function value of the first work function layer, and the metal atomic percentage of the second work function layer is greater than the metal atomic percentage of the first work function layer.

[0005] According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a sensing element and a filter. The substrate includes an isolation structure and an active area defined by the isolation structure. The sensing element is disposed on the substrate and includes a sensing electrode. The filter is disposed on the sensing electrode and includes a first work function layer and a second work function layer. The first work function layer is disposed on the sensing element and covers the sensing electrode. The second work function layer is disposed on the first work function layer. In addition, the work function value of the second work function layer is greater than the work function value of the first work function layer, and the metal atomic percentage of the second work function layer is greater than the metal atomic percentage of the first work function layer.

[0006] According to some embodiments of the present disclosure, a semiconductor device includes a sensing element and a filter. The sensing element includes a semiconductor fin, an isolation structure, a gate structure, a sensing contact, a sensing electrode and a read contact. The semiconductor fin is located above a substrate. The isolation structure laterally surrounds the bottom of the semiconductor fin. The gate structure spans the semiconductor fin. The sensing contact is directly disposed on the isolation structure and adjacent to the gate structure. The sensing electrode is electrically connected to the sensing contact. The read contact is directly located on the isolation structure and adjacent to the gate structure. The filter covers the sensing electrode and includes a first work function layer and a second work function layer located above the first work function layer. The work function value of the second work function layer is greater than the work function value of the first work function layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The embodiments of the present disclosure may be better understood from the following detailed description when read in conjunction with the accompanying drawings. It is noteworthy that, in accordance with standard practice in practice, the features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a schematic diagram of a semiconductor device according to some embodiments;

[0009] Figure 2A According to some embodiments Figure 1 A cross-sectional view of the sensing electrode and the filter in FIG.

[0010] Figure 2B According to some other embodiments Figure 1 A cross-sectional view of the sensing electrode and the filter in FIG.

[0011] Figure 3A is an energy band diagram of a sensing electrode according to some embodiments;

[0012] Figure 3B is an energy band diagram of a first work function layer and a second work function layer according to some embodiments;

[0013] Figure 4 is an IV characteristic diagram of a bit line of an exemplary semiconductor device with a filter and without a filter;

[0014] Figure 5-10B A method of manufacturing a semiconductor device at various stages according to some embodiments of the present disclosure is illustrated;

[0015] Fig.11 is a schematic diagrammatic view of a lithography exposure apparatus according to some embodiments;

[0016] Fig.12 is a cross-sectional view of a semiconductor device according to some embodiments; and

[0017] Fig.13 is a graph showing pH-Vth (threshold voltage of MOSFET) characteristics in an exemplary semiconductor device with a filter and without a filter.

[0018]

Explanation of symbols

[0019] 10,10':Semiconductor devices

[0020] 100:Filter

[0021] 102: Top surface

[0022] 105: Interface

[0023] 110: first work function layer

[0024] 110': first conductive film

[0025] 120: second work function layer

[0026] 120': second conductive film

[0027] 130: Adhesion layer

[0028] 200: Sensing element

[0029] 202: Top surface

[0030] 210:Substrate

[0031] 220: semiconductor fin

[0032] 222,224: Source / drain region

[0033] 230: Isolation Structure

[0034] 240: Gate structure

[0035] 242: Gate dielectric layer

[0036] 244: Work function metal layer

[0037] 246: Filler Metal

[0038] 250: Read contacts

[0039] 260: Sensing contact

[0040] 270: Sensing pad structure

[0041] 272: Conductive thread

[0042] 274: Conductive via

[0043] 276: spontaneous oxide layer

[0044] 282,284: Source / drain contacts

[0045] 290: Gate spacer

[0046] 310: Virtual gate structure

[0047] 312: Virtual gate dielectric layer

[0048] 314: Virtual gate electrode

[0049] 316: Nitride mask layer

[0050] 318: Oxide mask layer

[0051] 320: Contact Etch Stop Layer / CESL

[0052] 325: Interlayer dielectric layer / ILD layer

[0053] 330: Multilayer Interconnection Structure / MLI Structure

[0054] 332: Metallization layer

[0055] 333: Intermetallic dielectric layer / IMD layer

[0056] 334: Etching stop layer

[0057] 400: Sensing element

[0058] 410:Substrate

[0059] 412: Source region

[0060] 414: Drain region

[0061] 420: Source contact

[0062] 425: Drain contact

[0063] 430: Reference electrode

[0064] 440: Dielectric layer

[0065] 450: Packaging structure

[0066] 500: Electrolytes

[0067] 800: Photomask

[0068] 900: Lithography exposure equipment

[0069] 910: Light source

[0070] 912: Radiation

[0071] 920:Illuminator

[0072] 930: Projection Optical Module / Projection Optical Box / POB

[0073] 940:Substrate table

[0074] 950:Mask Suction Cup

[0075] BL: Bit Line

[0076] WL: Character Line

[0077] E c1 :Conductive tape

[0078] E f1 :Fermi level

[0079] E v1 :Price belt

[0080] E vaccum :Vacuum energy level

[0081] E c :Conductive tape

[0082] E f :Conductive tape

[0083] E v :Price belt

[0084] SE: Sensing Electrode

[0085] GND: Ground wire / ground voltage

[0086] T1, T2, T3, T4, T5: thickness

[0087] II: Section Line

[0088] IMP: Injection Process

[0089] ΔΦ: Obstacle height DETAILED DESCRIPTION

[0090] The content disclosed below provides many different embodiments or examples for implementing the different features of the disclosure provided. The specific examples of components and configurations described below are intended to simplify the disclosure, and of course, these are merely exemplary and not restrictive. For example, the first feature formed above or on the second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which other features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples, and such repetition is for the purpose of simplicity and clarity, and is not itself used to limit the relationship between the various embodiments and / or configurations discussed.

[0091] Additionally, for ease of description, spatially relative terms (e.g., "underlying," "beneath," "below," "above," "above," and the like) may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0092] As used in this disclosure, "approximately," "about," "closely," or "substantially" generally means within 20%, within 10%, or within 5% of a given value or range. The numerical values ​​given in this disclosure are approximate, which means that if not explicitly stated, the terms "approximately," "about," "closely," or "substantially" can be inferred. It can be understood by those of ordinary skill in the art that the dimensions can vary according to different technology nodes. It is known to those of ordinary skill in the art that the dimensions depend on the specific device type, technology generation, and minimum feature size, etc. Therefore, the term should be interpreted based on the technology being evaluated.

[0093] The term "high-k" as used in the present disclosure refers to a high dielectric constant. In the field of semiconductor device structures and their manufacturing processes, high-k refers to a dielectric constant greater than the dielectric constant of SiO2 (for example, greater than 3.9). The term "low-k" as used in the present disclosure refers to a low dielectric constant. In the field of semiconductor device structures and their manufacturing processes, low-k refers to a dielectric constant less than the dielectric constant of SiO2 (for example, less than 3.9). The term "p-type" as used in the present disclosure defines a structure, layer and / or region doped with a p-type dopant (for example, boron). The term "n-type" as used in the present disclosure defines a structure, layer and / or region doped with an n-type dopant (for example, phosphorus). The term "conductive" as used in the present disclosure refers to a structure, layer and / or region that is electrically conductive. The source / drain regions described in the present disclosure may refer to the source or drain individually or collectively depending on the context.

[0094] The present disclosure relates to semiconductor devices and methods of forming the same. More specifically, some embodiments of the present disclosure relate to semiconductor devices having a signal filter disposed on a sensing electrode of the semiconductor device. In some embodiments, the semiconductor device can be implemented on devices including planar devices, multi-gate devices, fin field-effect transistors (Fin Field-Effect Transistors, FinFETs), nanosheet gate FETs, and gate-all-around FETs.

[0095] Figure 1is a diagram of a semiconductor device 10 according to some embodiments. The semiconductor device 10 includes a sensing element 200 and a filter 100. The sensing element 200 includes a sensing electrode SE, and the filter 100 covers the sensing electrode SE. The sensing electrode SE is configured to receive a signal. The filter 100 is configured to filter (or rectify) the signal. For example, the filter 100 filters the positive carriers of the signal and allows the negative carriers of the signal to pass through to the sensing electrode SE, or vice versa. Therefore, the effects of positive charging and negative charging can be distinguished.

[0096] In some embodiments, the semiconductor device 10 may be an extreme ultraviolet (EUV) radiation detector. The EUV radiation source may generate EUV radiation using a laser-produced plasma (LPP) mechanism. Therefore, when the semiconductor device 10 detects the intensity of EUV radiation, plasma (i.e., background signal) may also be sensed, thereby reducing the accuracy of the sensing element 200. Therefore, the filter 100 is formed above the sensing electrode SE to filter the background signal. In some embodiments, the filter 100 completely covers the sensing electrode SE. That is, the area of ​​the top surface 102 of the filter 100 is equal to (e.g., Figure 1 10A and 10B) or is larger than the area of ​​the top surface 202 of the sensing electrode SE. In addition, there is no conductive via between the filter 100 and the sensing electrode SE.

[0097] Figure 2A According to some embodiments Figure 1 1 is a cross-sectional view of the sensing electrode SE and the filter 100 in FIG. 1. The filter 100 is formed above the sensing electrode SE. In some embodiments, the filter 100 includes a first work function layer 110 and a second work function layer 120, and the second work function layer 120 is located above the first work function layer 110. For example, the first work function layer 110 is in contact with the second work function layer 120. The first work function layer 110 has a lower work function value than the second work function layer 120, so that the barrier height ΔΦ (see FIG. Figure 3B ) is formed between the first work function layer 110 and the second work function layer 120 .

[0098] Figure 3A is an energy band diagram of the sensing electrode SE according to some embodiments, where E c1 Refers to the conductive band of the sensing electrode SE, E f1 is the Fermi level, E v1 It refers to the valence band. Figure 3B is an energy band diagram of the first work function layer 110 and the second work function layer 120 according to some embodiments, wherein E vaccum refers to the vacuum energy level, E crefers to the conductive band of the second work function layer 120, E f refers to the conductive band of the first work function layer 110, E v Refers to the valence band. Figure 3A As shown, since the sensing electrode SE is conductive, the conductive band E of the sensing electrode SE c1 Basically, the Fermi level E of the sensing electrode SE f1 Therefore, the signal carriers (positive carriers and negative carriers) can pass through the sensing electrode SE. Figure 3B As shown, due to the difference in work function between the first work function layer 110 and the second work function layer 120, a barrier height ΔΦ is formed at the interface 105 between the first work function layer 110 and the second work function layer 120. The barrier height ΔΦ blocks negative charge carriers (electrons) and allows positive charge carriers to pass through at the same time. Therefore, the background signal (in this case, negative charge carriers) can be filtered out from the signal incident on the filter 100.

[0099] See also Figure 2A The sensing electrode SE has a first work function value WF1, the first work function layer 110 has a second work function value WF2, and the second work function layer 120 has a third work function value WF3. As described above, WF3>WF2. In some embodiments, WF3>WF2>WF1. In some embodiments, WF3-WF2 is between about 0.05 eV and about 2 eV. If WF3-WF2 exceeds the above range, the barrier height ΔΦ (see Figure 3B ) may not be suitable for filtering signals (e.g., plasma in this case). In some embodiments, the barrier height ΔΦ (see Figure 3B ) is between about 0.2 eV and about 1.7 eV. As mentioned above, if the barrier height ΔΦ is outside this range, the barrier height ΔΦ may not be suitable for filtering signals.

[0100] In some embodiments, the second work function layer 120 is made of a metal, such as Au, Cu, or a combination thereof. For example, the metal atomic percentage of the second work function layer 120 is greater than about 95%. In some embodiments, the first work function layer 110 is made of a metal oxide or a metal nitride, such as TiO2, NiO, or a combination thereof. In some embodiments, the sensing electrode SE is made of a metal, such as Al or Ni. For example, the metal atomic percentage of the sensing electrode SE is greater than about 95%. In some embodiments, the metal atomic percentage of the second work function layer 120 is greater than the metal atomic percentage of the first work function layer 110. In addition, the oxygen atomic percentage of the sensing electrode SE is lower than the oxygen atomic percentage of the first work function layer 110. Similarly, the oxygen atomic percentage of the second work function layer 120 is lower than the oxygen atomic percentage of the first work function layer 110.

[0101] like Figure 2A As shown, in some embodiments, the self-generated oxide layer 276 can be formed above the sensing electrode SE. Therefore, the self-generated oxide layer 276 and the sensing electrode SE include the same metal. For example, when the sensing electrode SE is made of Al, the self-generated oxide layer 276 is made of aluminum oxide. In this case, the first work function layer 110 can be configured to serve as an adhesion layer to attach the second work function layer 120 to the sensing electrode SE (and the self-generated oxide layer 276). In some embodiments, the thickness of the self-generated oxide layer 276 is T4, and the thickness T4 is less than the thickness T2 of the first work function layer 110.

[0102] In some embodiments, the sensing electrode SE has a thickness T1, the first work function layer 110 has a thickness T2, and the second work function layer 120 has a thickness T3. In some embodiments, the thickness T2 is between about 10 nm and about 200 nm. When the thickness T2 is greater than about 200 nm, the first work function layer 110 may have a high resistance and reduce the sensing ability of the sensing element 200; when the thickness T2 is less than about 10 nm, the electrical properties of the first work function layer 110 may change. In some embodiments, the thickness T1 is between about 50 nm and about 1200 nm. In some embodiments, the thickness T3 of the second work function layer 120 is greater than or equal to the thickness T2 of the first work function layer 110, so that the filter 100 has good conductive properties. Similarly, the thickness T1 of the sensing electrode SE is greater than or equal to the thickness T2 of the first work function layer 110.

[0103] In some embodiments, the first work function layer 110 may be doped. That is, the first work function layer 110 may include an N-type dopant or a P-type dopant. The dopant in the first work function layer 110 is configured to change the work function value of the first work function layer 110 so that the barrier height ΔΦ (see FIG. 1 ) between the first work function layer 110 and the second work function layer 120 is greater than or equal to ΔΦ. Figure 3B ) can be adjusted to a suitable value. When the first work function layer 110 includes an N-type dopant (e.g., P or As, etc.), the Fermi level of the first work function layer 110 will shift toward the conduction band; when the first work function layer 110 includes a P-type dopant (e.g., B, etc.), the Fermi level of the first work function layer 110 will shift toward the valence band. In this way, by adjusting the concentration of the dopant and the conductivity type of the dopant, the degree and direction of the Fermi level of the first work function layer 110 can be determined.

[0104] Figure 2B According to some other embodiments Figure 1 A cross-sectional view of the sensing electrode SE and the filter 100 in FIG. Figure 2BIn the filter 100, the filter 100 further includes an adhesion layer 130 located between the first work function layer 110 and the second work function layer 120. In some embodiments, the second work function layer 120 can be formed on the adhesion layer 130 and then transferred to the top of the first work function layer 110. Therefore, the adhesion layer 130 can be a transfer layer of the second work function layer 120. In some embodiments, the adhesion layer 130 has a thickness T5, and the thickness T5 is less than the thickness T2 of the first work function layer 110.

[0105] In some embodiments, the adhesion layer 130 is made of a transition metal dichalcogenide (TMDC) material, which is a class of materials including those having the general chemical formula MX2, where M is a transition metal element and X is a chalcogen element. Exemplary materials of the transition metal M include Ti, V, Co, Ni, Zr, Mo, Tc, Rh, Pd, Hf, Ta, W, Re, Ir, In, Sn, or Pt. The element X may be S, Se, or Te. According to some exemplary embodiments, exemplary TMDC materials include MoS2, MoSe2, PtSe2, WS2, WSe2, MoTe2, and WTe2. TMDC forms a layered structure in the form of XMX, in which the chalcogen atoms X are distributed in two hexagonal planes separated by the plane of the metal atoms M. In other words, the adhesion layer 130 includes a first layer, a second layer located above the first layer, and a third layer located above the second layer. The first layer and the third layer include chalcogen atoms X, and the second layer includes the transition metal M. In some embodiments, the first layer, the second layer, and the third layer are single layers.

[0106] In some embodiments, the adhesion layer 130 is doped to form an NP-junction with the first work function layer 110. That is, the adhesion layer 130 and the first work function layer 110 have opposite conductivity types. For example, the first work function layer 110 is N-type doped and the first work function layer 110 is P-type doped, or vice versa. Figure 2B Other relevant structural details of the filter 100 in Figure 2A The filter 100 is similar to that in FIG. 1 , and therefore, the description in this regard will not be repeated in the following description.

[0107] See also Figure 1 The sensing element 200 includes a substrate 210, at least one active region, an isolation structure 230, a gate structure 240, at least one read contact 250, at least one sensing contact 260 and a sensing pad structure 270, and the sensing pad structure 270 includes a sensing electrode SE. The active region may be a semiconductor fin 220 protruding from the substrate 210.

[0108] The isolation structure 230 is located above the substrate 210 and laterally surrounds the bottom of the semiconductor fin 220. That is, the bottom of the semiconductor fin 220 is embedded in the isolation structure 230. The isolation structure 230 may be a shallow trench isolation (STI) region.

[0109] The gate structure 240 is located above the isolation structure 230 and across the semiconductor fin 220. The portion of the semiconductor fin 220 covered by the gate structure 240 is referred to as the channel portion of the semiconductor fin 220. In some embodiments, there is no conductive element physically connected to the gate structure 240, and therefore, the gate structure 240 can be referred to as a floating gate. The gate structure 240 further defines a source portion and a drain portion in the semiconductor fin 220.

[0110] The two read contacts 250 are adjacent to the gate structure 240 and are disposed directly on the isolation structure 230 such that the two read contacts 250 are spaced apart from the semiconductor fin 220. The read contacts 250 are located on opposite sides of the gate structure 240. The read contacts 250 are connected to the gate structure 240 through a dielectric material (e.g., Figure 6 The gate structure 240 is separated from the gate spacer 290, the contact etch stoplayer (CESL) 320 and / or the interlayer dielectric (ILD) layer 325. As a result, the gate structure 240, the read contact 250 and the dielectric material between the gate structure 240 and the read contact 250 form a capacitor. In some embodiments, the sensing element 200 includes a single read contact 250 disposed on one side of the gate structure 240.

[0111] The two sensing contacts 260 are adjacent to the gate structure 240 and are disposed directly on the isolation structure 230 such that the two sensing contacts 260 are spaced apart from the semiconductor fin 220. The sensing contacts 260 are located on opposite sides of the gate structure 240. In some embodiments, the sensing contacts 260 and the read contacts 250 are located on opposite sides of the semiconductor fin 220 such that the semiconductor fin 220 is located between the sensing contacts 260 and the read contacts 250. The sensing contacts 260 are connected to the semiconductor fin 220 by a dielectric material (e.g., Figure 6 The gate structure 240 is separated from the gate spacer 290, CESL 320 and / or ILD layer 325 in the semiconductor fin 220. As a result, the gate structure 240, the sense contact 260 and the dielectric material between the gate structure 240 and the sense contact 260 form a capacitor. In some embodiments, the sensing element 200 includes a single sense contact 260 disposed on one side of the gate structure 240. In addition, the isolation structure 230 contacts the read contact 250, the sense contact 260 and the semiconductor fin 220.

[0112] The sensing pad structure 270 is electrically connected to the sensing contact 260. In some embodiments, the sensing pad structure 270 is disposed above the sensing contact 260 and the gate structure 240. In some embodiments, the sensing pad structure 270 includes one or more conductive wires 272 and a plurality of conductive vias 274 located between adjacent conductive wires 272. Some of the conductive vias 274 interconnect the conductive wires 272 and the sensing electrodes SE, and some of the conductive vias 274 interconnect the conductive wires 272 and the sensing contacts 260. In some embodiments, some of the conductive vias 274 interconnect the conductive wires 272 of adjacent layers of the conductive wires 272. The conductive wires 272 and the conductive vias 274 are conductive materials so that signals (e.g., carriers) can flow from the conductive wires 272 to the sensing contacts 260.

[0113] In some embodiments, the sensing pad structure 270 includes a single conductive line 272, and the sensing pad structure 270 is connected to the sensing contact 260 through a conductive via 274. The single conductive line 272 can be located at the lowest layer (e.g., M0 layer) of the sensing pad structure 270. In some other embodiments, according to different requirements, the single conductive line 272 can be located at an intermediate layer (e.g., M1, M2, ... layers) or a topmost layer (e.g., Mn layer).

[0114] The sensing element 200 further includes a word line WL and a bit line BL. The word line WL is electrically connected to the read contact 250, and the bit line BL is electrically connected to the drain of the semiconductor fin 220. For example, the bit line BL is connected to the drain of the semiconductor fin 220 through the source / drain contact 282. In addition, the word line WL is electrically isolated from the gate structure 240. In some embodiments, the source of the semiconductor fin 220 is electrically connected to the ground (line) GND, so that a reference potential (e.g., approximately 0V) is provided to the semiconductor device 10 through the source / drain contact 284 during programming, erasing and / or reading processes.

[0115] The filter 100 covers the sensing electrode SE. Therefore, the filter 100 (i.e., the first work function layer 110, the second work function layer 120, and the adhesion layer 130 as shown in FIGS. 2A and 2B) covers and is directly located above the read contact 250, the sensing contact 260, the gate structure 240, the word line WL, the bit line BL, and the ground line GND.

[0116] The semiconductor device 10 has four different states: programming, erasing, sensing, and reading. The semiconductor device 10 performs the four different states (programming, erasing, sensing, and reading) as described below: Programming─The programming cycle of the semiconductor device 10 is started by applying a positive voltage +V1 to the word line WL and a negative voltage -V2 to the bit line BL. In addition, the source of the semiconductor fin 220 is connected to the ground line GND. Therefore, the gate structure 240 is floating, and an electric field is formed in the gate structure 240 to drive electrons from the substrate 210 to the gate structure 240 through a tunneling effect, and the electrons can be stored in the gate structure 240.

[0117] Erase-The erase cycle of the semiconductor device 10 is started by applying a negative voltage -V1 to the word line WL and a positive voltage +V2 to the bit line BL. In addition, the source of the semiconductor fin 220 is connected to the ground line GND. Therefore, the gate structure 240 is floating, and an electric field is formed in the gate structure 240 to drive electrons from the gate structure 240 to the substrate 210 through the tunneling effect, and the gate structure 240 is considered to be free of electrons.

[0118] Sensing - During the sensing cycle of the semiconductor device 10, no power is applied to the word line WL, the bit line BL and the source of the semiconductor fin 220. That is, in the sensing mode, the semiconductor device 10 is power-free. When the electron beam light is incident on the sensing pad structure 270, the electrons of the electron beam light enter the sensing pad structure 270 and flow to the sensing contact 260. Electrical coupling is formed between the sensing contact 260 and the gate structure 240, and the voltage in the gate structure 240 is changed.

[0119] Reading - The start of the reading cycle of the semiconductor device 10 is to apply a changing positive voltage +V3 to the word line WL and apply a ground voltage GND to the source of the semiconductor fin 220, and float the gate structure 240 to read the corresponding current under the changing positive voltage +V3 from the bit line BL. As the signal strength varies, the IV curves of the bit line BL and the word line WL will shift to different degrees. Therefore, the strength of the signal can be calculated from the IV curve.

[0120] Figure 4 1 is a graph of IV characteristics of bit lines in exemplary semiconductor devices having the filter 100 and not having the filter 100. The curve represented by square dots represents the IV characteristics of the semiconductor device 10 having the filter 100, and the curve represented by round dots represents the IV characteristics of the semiconductor device not having the filter 100. Figure 4As shown, with the filter 100, the IV curve shifts toward 0V, indicating that the background signal is filtered out. In addition, the change in the threshold voltage of the semiconductor device 10 is more significant.

[0121] Figures 5 to 10B 1 shows a method for manufacturing a semiconductor device 10 at various stages according to some embodiments of the present disclosure. In addition to the semiconductor device 10, Figures 5 to 7A Also shown is a perspective view of the semiconductor device 10 at an intermediate stage during fabrication according to some embodiments. FIG. 7B to FIG. 10B According to some embodiments, Fig. 7A FIG. 1 is a cross-sectional view of semiconductor device 10 at an intermediate stage during manufacturing along a first cross-sectional line (eg, cross-sectional line II).

[0122] See also Figure 5 . A substrate 210 is provided. In some embodiments, the substrate 210 is made of a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as a Group IV compound semiconductor (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), a Group III-V compound semiconductor (e.g., gallium arsenide, indium gallium arsenide InGaAs, indium arsenide, indium phosphide, indium antimonide, gallium arsenide phosphide, or indium gallium phosphide) or others. In addition, the substrate 210 may include an epitaxial layer (epi-layer), which may enhance performance through strain, and / or the substrate 210 may include a silicon-on-insulator (SOI) structure.

[0123] At least one semiconductor fin 220 is formed on the substrate 210. When forming the semiconductor fin 220, a patterning process may be used, for example, to form trenches, and the trenches may be formed on opposite sides of the semiconductor fin 220. As discussed in more detail below, the semiconductor fin 220 will be configured to form a FinFET. It should be understood that for illustrative purposes, only a single semiconductor fin 220 is depicted, but in other embodiments, any number of semiconductor fins may be included. In some embodiments, one or more dummy semiconductor fins are formed adjacent to the semiconductor fin 220.

[0124] An isolation structure 230 (e.g., a shallow trench isolation (STI)) is disposed in the trench and above the substrate 210. In some embodiments, the isolation structure 230 may be equivalently referred to as an isolation insulating layer. The isolation structure 230 may be made of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric (e.g., carbon-doped oxide), an ultra-low-k dielectric (e.g., porous carbon-doped silicon dioxide), a polymer (e.g., polyimide), or a combination thereof. In some embodiments, the isolation structure 230 is formed by, for example, chemical vapor deposition (CVD), flowable CVD (FCVD), or a spin-on glass process, but any acceptable process may be used. Next, the portion of the isolation structure 230 extending above the top surface of the semiconductor fin 220 is removed, for example, by an etch-back process, chemical mechanical polishing (CMP), or the like.

[0125] Then, the isolation structure 230 is recessed to expose the upper portion of the semiconductor fin 220. In some embodiments, the isolation structure 230 is recessed using a single etching process or multiple etching processes. In some embodiments where the isolation structure 230 is made of silicon oxide, the etching process can be, for example, a dry etching, a chemical etching, or a wet cleaning process. For example, the chemical etching can use a fluorine-containing chemical, such as diluted hydrofluoric acid (dHF).

[0126] After forming the semiconductor fin 220 and the isolation structure 230, at least one dummy gate structure 310 is formed over the substrate 210 and is at least partially disposed over the semiconductor fin 220. The portion of the semiconductor fin 220 located under the dummy gate structure 310 may be referred to as a channel region, and the semiconductor fin 220 may be referred to as a channel layer. The dummy gate structure 310 may also define a source / drain portion of the semiconductor fin 220, for example, a region of the semiconductor fin 220 adjacent to the channel region and located on opposite sides of the channel region is a source / drain portion.

[0127] First, the dummy gate formation step forms a dummy gate dielectric layer over the semiconductor fin 220. Next, a dummy gate electrode layer and a hard mask are formed over the dummy gate dielectric layer, wherein the hard mask may include multiple layers (e.g., an oxide layer and a nitride layer). Then, the hard mask is patterned to form an oxide mask layer 318 and a nitride mask layer 316, and then, the dummy gate electrode layer is patterned to form a dummy gate electrode 314 by using the oxide mask layer 318 and the nitride mask layer 316 as an etching mask. In some embodiments, after patterning the dummy gate electrode layer, the dummy gate dielectric layer is removed from the source / drain (S / D) region of the semiconductor fin 220 to form a dummy gate dielectric layer 312. The etching process may include wet etching, dry etching, and / or a combination thereof. The selective etching process selectively etches the dummy gate dielectric layer while substantially not etching the semiconductor fin 220 , the dummy gate electrode 314 , the nitride mask layer 316 , and the oxide mask layer 318 .

[0128] After the formation of the dummy gate structure 310 is completed, a gate spacer 290 is formed on the sidewall of the dummy gate structure 310. In some embodiments of the gate spacer formation step, a spacer material layer is deposited on the substrate 210. The spacer material layer can be a conformal layer, and then, the spacer material layer is etched back to form the gate spacer 290. In some embodiments, the spacer material layer includes multiple layers. The gate spacer 290 is made of a suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN and / or a combination thereof. As an example and not limiting, the spacer material layer can be formed by depositing a dielectric material over the dummy gate structure 310 using a process such as an atomic layer deposition (ALD) process, a plasma enhanced ALD (PEALD) process, a PECVD process, a subatmospheric CVD (SACVD) process, or other suitable processes. Then, an anisotropic etching process is performed on the spacer material layer to expose portions of the semiconductor fin 220 that are not covered by the dummy gate structure 310 (e.g., in the source / drain portion of the semiconductor fin 220). The portion of the spacer material layer located directly above the dummy gate structure 310 can be removed by the anisotropic etching process. Portions of the spacer material layer located on the sidewalls of the dummy gate structure 310 can be retained to form a gate sidewall spacer, and for simplicity, the gate sidewall spacer is represented as a gate spacer 290. In some embodiments, the gate spacer 290 can be used to separate subsequently formed doped regions, such as source / drain regions. The gate spacer 290 can also be used to design or modify the source / drain region profile.

[0129] In some embodiments, the source / drain regions 222 and 224 are formed in the source / drain portion of the semiconductor fin 220. For example, at least one implantation process is performed so that dopants are implanted into the source / drain portion of the semiconductor fin 220 to form the source / drain regions 222 and 224. The dummy gate structure 310 and the gate spacer 290 serve as a mask for the ion implantation. Optionally, the source / drain portion of the semiconductor fin 220 is recessed, and the source / drain epitaxial structure is formed in the recess and above the source / drain portion of the semiconductor fin 220.

[0130] See also Figure 6 An interlayer dielectric (ILD) layer 325 is formed on the substrate 210. In some embodiments, before forming the ILD layer 325, a contact etch stop layer (CESL) 320 is formed. In some embodiments, the CESL 320 includes a silicon nitride layer, a silicon oxynitride layer, and / or other suitable materials having a different etching selectivity from the ILD layer 325. The CESL 320 may be formed by a plasma enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 325 includes materials such as oxide formed from tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials having different etching selectivities from the CESL 320. The ILD layer 325 may be deposited by a sub-atmospheric CVD (SACVD) process, a flowable CVD process, or other suitable deposition techniques. In some embodiments, after forming the ILD layer 325, a high thermal budget process may be performed on the wafer to anneal the ILD layer 325.

[0131] In some examples, after forming the ILD layer 325, a planarization process may be performed to remove excess material of the ILD layer 325. For example, the planarization process includes a chemical mechanical planarization (CMP) process, and the planarization process removes portions of the ILD layer 325 (and the CESL 320, if present) covering the dummy gate structure 310. In some embodiments, the CMP process also removes the nitride mask layer 316 and the oxide mask layer 318 (such as Figure 5), and exposes the virtual gate electrode 314 (as shown Figure 5 shown).

[0132] Next, the dummy gate electrode 314 and the dummy gate dielectric layer 312 are removed (see Figure 5 ), thereby forming gate trenches between the gate spacers 290. A selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof) is used to etch the material of the dummy gate electrode 314 and the dummy gate dielectric layer 312 at a faster etching rate than etching other materials (e.g., the gate spacers 290, the CESL 320, and / or the ILD layer 325).

[0133] Thereafter, a replacement gate structure 240 is formed in the gate trench. The gate structure 240 may be the final gate of the FinFET. The final gate structure may be a high-k / metal gate stack, but may also be other combinations. In some embodiments, the gate structure 240 forms a gate associated with three sides of the channel region provided by the semiconductor fin 220. In other words, the gate structure 240 surrounds the semiconductor fin 220 on three sides. In various embodiments, the (high-k / metal) gate structure 240 includes a gate dielectric layer 242 lining the gate trench and a gate electrode above the gate dielectric layer 242. The gate electrode may include a work function metal layer 244 and a fill metal 246, and the work function metal layer 244 is formed above the gate dielectric layer 242, and the fill metal 246 is formed above the work function metal layer 244 and fills the remaining portion of the gate trench. The gate dielectric layer 242 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer located above the interface layer. As used herein, a high-k gate dielectric includes a dielectric material having a high dielectric constant, such as a dielectric constant greater than that of thermal silicon oxide (~3.9). The work function metal layer 244 and / or fill metal 246 used within the high-k / metal gate structure 240 may include a metal, a metal alloy, or a metal silicide. The formation of the high-k / metal gate structure 240 may include multiple deposition processes to form various gate materials, one or more liner layers, and one or more CMP processes to remove excess gate material.

[0134] In some embodiments, the interfacial layer of the gate dielectric layer 242 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 242 may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer 242 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum, yttrium oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanate (SrTiO3, STO), barium titanate (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitride (SiON), and combinations thereof.

[0135] The work function metal layer 244 may include a work function metal to provide a suitable work function for the high-k / metal gate structure 240. For an n-type FinFET, the work function metal layer 244 may include one or more n-type work function metals (N-metals). The n-type work function metal may exemplarily include, but is not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. The p-type work function metal may exemplarily include, but is not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials. In some embodiments, fill metal 246 may illustratively include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0136] One or more etching processes are performed to form contact openings extending through the ILD layer 325 to expose the semiconductor fin 220 or the isolation structure 230. The read contact 250, the sense contact 260, and the source / drain contacts 282 and 284 are formed in the contact openings, respectively. As an example and not limiting, the formation of the contacts includes depositing one or more conductive materials to overflow the contact openings, and then performing a CMP process to remove excess conductive materials outside the contact openings.

[0137] Next, see FIG. 7A to FIG. 7B ,in Figure 7B is along Fig. 7A The multilayer interconnection (MLI) structure 330 is formed on the Figure 6 The MLI structure 330 may include a plurality of metallization layers 332. The number of metallization layers 332 may vary according to the design specifications of the semiconductor device. Figure 7B The middle layer of the metallization layer 332 is omitted in FIG. The plurality of metallization layers 332 each include an inter-metal dielectric (IMD) layer 333 and an etch stop layer 334. For clarity, the IMD layer 333 and the etch stop layer 334 are shown in FIG. Figure 7B In the Fig. 7A The metallization layer 332 includes one or more horizontal interconnects, such as word lines WL, bit lines BL, ground lines GND (see Figure 1 ) and sensing electrodes SE, these horizontal interconnects will extend horizontally or laterally in the IMD layer 333 and vertically interconnect members (such as conductive vias 274). In addition, vertical interconnects will extend vertically in the IMD layer 333 and pass through the etching stop layer 334. As described above, the sensing electrodes SE, the conductive lines 272, and the conductive vias 274 form a sensing pad structure 270.

[0138] The word line WL, the bit line BL, the ground line GND, the sensing electrode SE, the conductive line 272 and the conductive via 274 can be formed using, for example, a single damascene process, a dual damascene process or a combination thereof. In some embodiments, the IMD layer 333 may include a low-k dielectric material disposed between the aforementioned conductive components, and the k value of the low-k dielectric material is, for example, lower than about 4.0 or even lower than 2.0. In some embodiments, the IMD layer 333 may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO x C y, spin-coated glass, spin-coated polymer, silicon oxide, silicon oxynitride or a combination thereof, and formed by any suitable method, such as spin coating, chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD). In some embodiments, the etch stop layer 334 may be deposited by CVD or PECVD technology, and the material of the etch stop layer 334 may be SiN x 、SiCN、SiO2、CN、AlO x N y or a combination thereof. The word line WL, the bit line BL, the ground line GND, the sensing electrode SE, the conductive line 272 and the conductive via 274 may include metal materials, such as copper, aluminum, tungsten or a combination thereof. In some embodiments, the word line WL, the bit line BL, the ground line GND, the sensing electrode SE, the conductive line 272 and the conductive via 274 may also include one or more barrier / adhesion layers (not shown) to protect the corresponding IMD layer 333 from metal diffusion (e.g., copper diffusion) and metal poisoning. One or more barrier / adhesion layers may include titanium, titanium nitride, tantalum or tantalum nitride, etc., and may be formed using physical vapor deposition (PVD), CVD or ALD, etc. As Figure 7B As shown, there are no vias provided to interconnect the horizontal interconnects and / or the vertical interconnects of the MLI structure 330 and the gate structure 240 .

[0139] See also Fig. 8A A first conductive film 110' is formed over the MLI structure 330. In some embodiments, a self-generated oxide layer 276 is formed over the sensing electrode SE (see Figure 2A ), so that the first conductive film 110' is formed on the native oxide layer 276. The first conductive film 110' may be made of a metal oxide, so that the first conductive film 110' has good adhesion to the native oxide layer 276. In some embodiments, the first conductive film 110' may directly contact the sensing electrode SE, such as Fig. 8A and Figure 8B As shown. In other words, the native oxide layer 276 can be removed before forming the first conductive film 110'. As an example and not a limitation, the first conductive film 110' can be formed by depositing a material over the MLI structure 330 using, for example, an ALD process, a PEALD (plasma enhanced ALD) process, a PECVD process, a sub-atmospheric pressure CVD (SACVD) process, or other suitable processes. In some embodiments, the work function value of the first conductive film 110' is greater than the work function value of the sensing electrode SE.

[0140] See also Figure 8BAs described above, in some embodiments, the first conductive film 110' may be doped. For example, an implantation process IMP is performed to dope the first conductive film 110'. In some exemplary embodiments, the p-type first conductive film 110' includes a boron (B) dopant, and the n-type first conductive film 110' includes a phosphorus (P) dopant.

[0141] See also Fig.9A . The second conductive film 120' is formed over the first conductive film 110'. The second conductive film 120' may be made of metal so that the second conductive film 120' has good conductivity to the sensing signal (charged carriers). As an example and not a limitation, the second conductive film 120' may be formed by depositing a metal material over the first conductive film 110' using, for example, an ALD process, a PEALD (plasma enhanced ALD) process, a PECVD process, a sub-atmospheric pressure CVD (SACVD) process, or other suitable processes. The work function value of the second conductive film 120' is greater than the work function value of the first conductive film 110'.

[0142] See also Fig. 9B In some embodiments, the second conductive film 120' is formed on another substrate (or wafer) and then transferred to the first conductive film 110'. For example, the adhesion layer 130' is attached to the second conductive film 120', and the second conductive film 120' and the adhesion layer 130' are both transferred to the first conductive film 110'. In this way, the adhesion layer 130' attaches the second conductive film 120' to the first conductive film 110'.

[0143] See also Fig. 10A and Fig. 10B The second conductive film 120', the adhesion layer 130' (if present), and the first conductive film 110' are patterned to form the filter 100. For example, one or more etching processes are performed to pattern the second conductive film 120' and the first conductive film 110'. In some embodiments, the area of ​​the top surface 102 of the filter 100 is substantially the same as that of the top surface 102 of the filter 100. Figure 1 The top surface 202 of the sensing electrode SE shown in FIG. 1 is the same as that of FIG. 1 . In some other embodiments, the top surface 102 of the filter 100 has an area larger than that of FIG. Fig. 10A and Fig. 10B The area of ​​the top surface 202 of the sensing electrode SE is shown. For example, the filter 100 may cover the entire top surface 202 of the sensing electrode SE.

[0144] Fig.119 is a schematic diagram of a lithography exposure apparatus 900 according to some embodiments. According to some embodiments, the lithography exposure apparatus 900 includes a light source 910, an illuminator 920, a projection optics module (or projection optics box (POB)) 930 and a substrate stage 940. The light source 910 is configured to generate radiation 912 having a wavelength between about 1 nm and about 100 nm. In some embodiments, the light source 910 generates EUV light having a wavelength centered at about 13.5 nm. Therefore, the light source 910 is also referred to as an EUV light source. However, it should be understood that the light source 910 should not be limited to emitting EUV light. The light source 910 can be used to perform any high-intensity photon emission from an excited target material.

[0145] In various embodiments, the illuminator 920 includes various refractive optical components, such as a single lens or a lens system having multiple lenses (wave zone plates), or a reflective optical device (for EUV lithography exposure equipment), such as a single mirror or a mirror system having multiple mirrors, so as to direct light from the light source 910 onto the mask 800 fixed on the mask suction cup 950.

[0146] The projection optical module (or projection optical box (POB)) 930 is configured to image the pattern of the mask 800 onto a semiconductor wafer fixed on a substrate stage 940 of the lithography exposure apparatus 900 for a lithography exposure process. However, during the detection of the EUV light intensity, the semiconductor device 10 is fixed on the substrate stage 940. In various embodiments, the POB 930 has a refractive optical device (for example, for UV lithography exposure equipment) or a reflective optical device (for example, for EUV lithography exposure equipment). The illuminator 920 and the POB 930 are collectively referred to as an optical module of the lithography exposure apparatus 900.

[0147] Fig.12 is a cross-sectional view of a semiconductor device 10' according to some embodiments. Fig.12 In the embodiment, the semiconductor device 10′ includes a sensing element 400 and a filter 100, and the filter 100 is disposed above the sensing electrode SE of the sensing element 400. The cross-sectional view of the filter 100 and the sensing electrode SE is similar to Figure 2A or Figure 2BThe structures shown are similar or identical, so the description of this aspect will not be repeated later. The sensing element 400 is an ion sensor and can be a metal-oxide-semiconductor field-effect transistor (MOSFET). The sensing element 400 includes a substrate 410, a source contact 420 and a drain contact 425, a sensing electrode SE and a reference electrode 430, and the substrate 410 has a source region 412 and a drain region 414. The source region 412 and the drain region 414 are doped regions. The source contact 420 is located above the source region 412 and is electrically connected to the source region 412, and the drain contact 425 is located above the drain region 414 and is electrically connected to the drain region 414. In some embodiments, the sensing element 400 also includes a dielectric layer 440, and the dielectric layer 440 surrounds the bottom of the source contact 420 and the drain contact 425 and is located between the substrate 410 and the sensing electrode SE. In some embodiments, the sensing element 400 further includes a packaging structure 450, and the packaging structure 450 covers the source contact 420 and the drain contact 425 respectively. In some embodiments, the packaging structure 450 is made of an electrically isolating material, such as a dielectric material. The electrolyte 500 is deposited above the sensing electrode SE, and the reference electrode 430 is immersed in the electrolyte 500 and is located above the sensing electrode SE.

[0148] Fig.13 is a graph of pH-Vth (threshold voltage of MOSFET) characteristics in exemplary semiconductor devices with and without the filter 100. The curve represented by square dots represents the pH-Vth characteristics of the semiconductor device 10' with the filter 100, and the curve represented by round dots represents the pH-Vth characteristics of the semiconductor device without the filter 100. Fig.13 As shown, with the filter 100, the pH-Vth curve moves upward, indicating that the background signal is filtered.

[0149] Based on the above discussion, it can be seen that the present disclosure provides multiple advantages. However, it should be understood that other embodiments may provide other advantages, and not all advantages must be disclosed in the present disclosure, and not all embodiments require specific advantages. One of the advantages is that the filter can filter out background signals to improve the accuracy of the sensing element. In addition, the filter can have good adhesion to the sensing electrode of the sensing element. In addition, dopants can be doped into the conductive layer of the filter to adjust the barrier height between the conductive layers of the filter.

[0150] According to some embodiments, a semiconductor device includes a sensing element and a filter, and the sensing element includes a sensing electrode, and the filter covers the sensing electrode. The filter includes a first work function layer and a second work function layer. The first work function layer is disposed above the sensing electrode. The second work function layer is disposed above the first work function layer. The work function value of the second work function layer is greater than the work function value of the first work function layer, and the metal atomic percentage of the second work function layer is greater than the metal atomic percentage of the first work function layer. In some embodiments, the work function value of the first work function layer is greater than the work function value of the sensing electrode. In some embodiments, the first work function layer is a metal oxide layer. In some embodiments, the second work function layer is a metal layer. In some embodiments, the filter covers the entire top surface of the sensing electrode. In some embodiments, the filter includes an adhesion layer, and the adhesion layer is disposed between the first work function layer and the second work function layer. In some embodiments, the thickness of the first work function layer is greater than the thickness of the adhesion layer. In some embodiments, the adhesion layer includes a transition metal dichalcogenide material. In some embodiments, the sensing element includes an oxide layer, and the oxide layer is disposed above the sensing electrode and contacts the first work function layer, and the oxide layer and the sensing electrode include the same metal. In some embodiments, the sensing element includes a floating gate, a sensing contact and a read contact, and the floating gate is disposed above a substrate; the sensing contact is disposed above the substrate and adjacent to the floating gate, wherein the sensing contact is connected to a sensing electrode; and the read contact is disposed above the substrate and adjacent to the floating gate.

[0151] According to some embodiments, a method of manufacturing a semiconductor device includes: providing a sensing element including a sensing electrode. Depositing a metal oxide layer on the sensing element to cover the sensing electrode. Forming a metal layer above the metal oxide layer, wherein a barrier height between the metal layer and the metal oxide layer is between about 0.2 eV and about 1.7 eV. Patterning the metal layer and the metal oxide layer to form a filter above the sensing electrode. The gate structure spans the semiconductor fin. The sensing contact is directly disposed on the isolation structure and adjacent to the gate structure. The sensing electrode is electrically connected to the sensing contact. The read contact is directly disposed on the isolation structure and adjacent to the gate structure. The filter covers the sensing electrode, and the filter includes a first work function layer and a second work function layer located above the first work function layer. The work function value of the second work function layer is greater than the work function value of the first work function layer. In some embodiments, forming the sensing element includes the following steps: forming an isolation structure above a substrate to define an active region in the substrate. Forming a gate structure above the substrate, and the gate structure spans the active region. Forming a read contact and a sensing contact above the isolation structure. An interconnect structure is formed over the gate structure, the read contact, and the sense contact, wherein the interconnect structure includes a sense electrode electrically connected to the sense contact. In some embodiments, the filter covers the read contact. In some embodiments, the filter covers the sense contact. In some embodiments, the read contact and the sense contact are disposed on opposite sides of the active region. In some embodiments, the interconnect structure includes a word line, and the word line is connected to the read contact. In some embodiments, forming the metal layer over the metal oxide layer includes the following steps: depositing a metal layer over the adhesion layer. Transferring the metal layer with the adhesion layer to the metal oxide layer. In some embodiments, the metal oxide layer is TiO2, NiO, or a combination thereof.

[0152] According to some embodiments, a semiconductor device includes a sensing element and a filter. The sensing element includes a semiconductor fin, an isolation structure, a gate structure, a sensing contact, a sensing electrode and a read contact. The semiconductor fin is located above the substrate. The isolation structure laterally surrounds the bottom of the semiconductor fin. The gate structure spans the semiconductor fin. The sensing contact is directly disposed on the isolation structure and adjacent to the gate structure. The sensing electrode is electrically connected to the sensing contact. The read contact is directly located on the isolation structure and adjacent to the gate structure. The filter covers the sensing electrode and includes a first work function layer and a second work function layer located above the first work function layer. The work function value of the second work function layer is greater than the work function value of the first work function layer. In some embodiments, the second work function layer is directly disposed above the read contact of the sensing element.

[0153] According to some embodiments, a semiconductor device includes a substrate, a sensing element and a filter. The substrate includes an active region and an isolation structure. The sensing element is disposed on the substrate and includes a sensing electrode. The filter is disposed above the sensing electrode and includes a first work function layer and a second work function layer. The first work function layer is disposed on the sensing element and covers the sensing electrode. The second work function layer is disposed on the first work function layer. The work function value of the second work function layer is greater than the work function value of the first work function layer, and the metal atomic percentage of the second work function layer is greater than the metal atomic percentage of the first work function layer. In some embodiments, the semiconductor device further includes a gate structure, a read contact, a sense contact and an interconnection structure. The gate structure is disposed on the substrate and spans the active region. The read contact is disposed on the gate structure. The sense contact is disposed on the gate structure. The interconnection structure is disposed on the read contact and the sense contact. In some embodiments, the read contact and the sense contact are disposed on opposite sides of the active region.

[0154] The present disclosure summarizes various embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a sensing element comprising a sensing electrode; a filter covering the sensing electrode and comprising: a first work function layer disposed above the sensing electrode; as well as A second work function layer is disposed above the first work function layer, wherein the work function value of the second work function layer is greater than the work function value of the first work function layer, and the metal atomic percentage of the second work function layer is greater than the metal atomic percentage of the first work function layer.

2. The semiconductor device according to claim 1, wherein The filter covers the entire top surface of the sensing electrode.

3. The semiconductor device according to claim 1, wherein The filter includes: An adhesion layer is disposed between the first work function layer and the second work function layer.

4. The semiconductor device according to claim 3, wherein The thickness of the first work function layer is greater than the thickness of the adhesion layer.

5. The semiconductor device according to claim 1, wherein The sensing element includes: a floating gate disposed above a substrate; a sensing contact disposed above the substrate and adjacent to the floating gate, wherein the sensing contact is connected to the sensing electrode; and A read contact is disposed above the substrate and adjacent to the floating gate.

6. A semiconductor device, characterized in that: include: A substrate including an isolation structure and an active region defined by the isolation structure; as well as a sensing element disposed on the substrate and comprising a sensing electrode; a filter disposed above the sensing electrode and comprising: a first work function layer disposed on the sensing element and covering the sensing electrode; as well as a second work function layer disposed on the first work function layer, The work function value of the second work function layer is greater than the work function value of the first work function layer, and the metal atomic percentage of the second work function layer is greater than the metal atomic percentage of the first work function layer.

7. The semiconductor device according to claim 6, wherein Further including: a gate structure disposed on the substrate and spanning the active region; a read contact disposed above the gate structure; a sensing contact disposed above the gate structure; and An interconnection structure is disposed above the read contact and the sensing contact, wherein the interconnection structure includes the sensing electrode electrically connected to the sensing contact.

8. The semiconductor device according to claim 7, wherein The read contact and the sensing contact are disposed on opposite sides of the active region.

9. A semiconductor device, characterized in that: include: A sensing element comprising: a semiconductor fin disposed above a substrate; an isolation structure laterally surrounding a bottom portion of the semiconductor fin; a gate structure spanning the semiconductor fin; a sensing contact disposed directly on the isolation structure and adjacent to the gate structure; a sensing electrode electrically connected to the sensing contact; a read contact disposed directly on the isolation structure and adjacent to the gate structure; and a filter covering the sensing electrode and comprising: a first work function layer; and A second work function layer is disposed above the first work function layer, wherein the work function value of the second work function layer is greater than the work function value of the first work function layer.

10. The semiconductor device according to claim 9, wherein The second work function layer is directly disposed above the read contact of the sensing element.

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