Array substrate, embedded touch display panel and display device

Abstract

The utility model discloses an array substrate, an embedded touch control display panel and a display device, the array substrate comprises a substrate, the substrate is provided with a plurality of scanning lines, a plurality of data lines, a plurality of touch control wires and a plurality of common electrode blocks, and each common electrode block is electrically connected with the corresponding touch control wire; the touch lines comprise first touch lines and second touch lines, the first touch lines and the data lines are located on the same layer and are alternately arranged in parallel, the second touch lines and the first touch lines are located on different layers and are in conductive connection with each other, and projections of the first touch lines and the second touch lines on the substrate coincide with each other. By arranging the first touch wire and the second touch wire which are located on different layers and are in conductive connection with each other to jointly form the touch wire, the touch wire is formed by connecting the first touch wire and the second touch wire in parallel, impedance of the touch wire is reduced, touch delay is reduced, and the display panel is suitable for a large-size display panel.

Description

Technical Field

[0001] The utility model relates to the technical field of displays, and in particular to an array substrate, an embedded touch display panel, and a display device. Background Art

[0002] Liquid crystal display panels have the advantages of good image quality, small size, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost, and they dominate the field of flat panel displays. With the rapid development of display technology, touch display panels have been widely accepted and used by people, such as smart phones and tablet computers. Touch display panels use embedded touch technology to combine touch panels and liquid crystal display panels into one, and embed the touch panel function into the liquid crystal display panel, so that the liquid crystal display panel has the functions of displaying and sensing touch input at the same time.

[0003] According to the different settings of the touch sensing layer in the display panel, the touch display panel is divided into add-on mode, in-cell and on-cell structures. The in-cell touch screen integrates the touch function into the display screen, so it can effectively reduce the thickness of the entire display and simplify the production process, making the product thinner and lighter, and the production cost is lower, so it is widely popular. At present, for the in-cell touch screen, the touch screen structure is usually directly set on the array substrate, mainly in the array substrate, some structural components used to transmit display signals are reused as touch electrodes. It is more common to reuse the common electrode block as a touch electrode to realize the touch function. Multiple common electrode blocks are used to receive touch signals and common voltages in a time-sharing manner. When the common electrode block is used as a touch electrode, the common electrode block is used to receive the touch signal; when the common electrode block is used as a common electrode, the common electrode block is used to receive the common voltage. The touch wiring is used to electrically connect the common electrode block and the touch chip. Therefore, not only scan lines and data lines need to be set on the array substrate, but also touch wiring is needed to transmit common signals and touch signals to the common electrode block through the touch wiring.

[0004] The size of existing display panels is getting bigger and bigger. For large-sized display panels, the length of the touch line will also increase, resulting in a relatively large impedance of the touch line, and the touch delay will also increase accordingly, greatly affecting the touch performance. In addition, in each column of common electrode blocks, the actual length of the touch line electrically connected to each common electrode block is not equal, that is, there is a difference in the resistance of the touch line involved in transmitting the signal. Since the common electrode block also serves as a common electrode, the common voltage uniformity on the common electrode block is poor, and black horizontal stripes will appear at the bottom, resulting in a poor display effect of the picture. Utility Model Content

[0005] In order to overcome the shortcomings and deficiencies in the prior art, the purpose of the present invention is to provide an array substrate, an embedded touch display panel, and a display device to solve the problem of large touch delay of large-size display panels in the prior art.

[0006] The purpose of the utility model is achieved through the following technical solutions:

[0007] The utility model provides an array substrate, comprising a substrate, on which a plurality of scan lines, a plurality of data lines, a plurality of touch lines and a plurality of common electrode blocks are arranged, the plurality of scan lines and the plurality of data lines are insulated from each other and cross-defined to form a plurality of pixel units, each of the pixel units is provided with a pixel electrode, the pixel electrode is conductively connected to the corresponding scan line and the data line through a thin film transistor, and each of the common electrode blocks is electrically connected to the corresponding touch line;

[0008] The touch routing includes a first touch routing and a second touch routing, the first touch routing and the data line are located in the same layer and are alternately arranged in parallel with each other, the second touch routing and the first touch routing are located in different layers and are conductively connected to each other, and the projections of the first touch routing and the second touch routing on the substrate overlap with each other.

[0009] Further, the area where the first touch line and the second touch line are conductively connected corresponds to the area where the common electrode block and the corresponding touch line are electrically and conductively connected;

[0010] Alternatively, the first touch control wiring and the second touch control wiring are in conductive contact in any region of the entire touch control wiring.

[0011] Furthermore, the common electrode block at a side away from the touch control chip is electrically connected to the plurality of touch control traces.

[0012] Furthermore, the common electrode blocks that are farther from the touch chip are connected to more touch lines.

[0013] Furthermore, the substrate is provided with a first lead and a second lead in the non-display area, the first lead and the data line are located in the same layer and are electrically connected, the second lead and the second touch line are located in the same layer and are electrically connected, and the projections of the first lead and the second lead on the substrate are arranged to cross each other;

[0014] The first leads include a first layer of leads and a second layer of leads, the first layer of leads and the scan lines are located in the same layer, the second layer of leads and the data lines are located in the same layer, and the projections of the first layer of leads and the second layer of leads on the substrate overlap with each other.

[0015] Furthermore, the substrate is provided with a first metal layer, a second metal layer and a third metal layer located in different layers, the first metal layer includes the scan line and the gate, and the gate is conductively connected to the scan line; the second metal layer includes the data line, the source, the drain and the first touch line, the data line is conductively connected to the source, the source and the drain are conductively connected through the active layer, and the pixel electrode is conductively connected to the corresponding drain; the third metal layer includes the second touch line.

[0016] Furthermore, a first transparent conductive layer and a second transparent conductive layer located at different layers are provided on the substrate, the first transparent conductive layer includes the pixel electrode, and the second transparent conductive layer includes the common electrode block.

[0017] Furthermore, the first transparent conductive layer is located above the second transparent conductive layer, or the first transparent conductive layer is located below the second transparent conductive layer.

[0018] The present application also provides an embedded touch display panel, comprising the array substrate as described above, a color film substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color film substrate.

[0019] The present application also provides a display device, comprising the embedded touch display panel as described above.

[0020] The beneficial effect of the utility model is that by arranging the first touch line and the second touch line located in different layers and conductively connected to each other to jointly form a touch line, the touch line is composed of the first touch line and the second touch line connected in parallel to each other, so as to reduce the impedance of the touch line, thereby reducing the touch delay, so as to be suitable for large-size display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the planar structure of the array substrate in the first embodiment of the utility model;

[0022] Figure 2 It is a schematic diagram of the cross-sectional structure at the connection between the common electrode block and the touch control wiring in the first embodiment of the utility model;

[0023] Figure 3 It is a schematic diagram of the cross-sectional structure at the non-connection portion between the common electrode block and the touch control wiring in the first embodiment of the utility model;

[0024] Figure 4a-Figure 4h-2 It is a cross-sectional schematic diagram of the steps of manufacturing the array substrate in the first embodiment of the utility model;

[0025] Figure 5It is a schematic diagram of the cross-sectional structure at the non-connection portion between the common electrode block and the touch control wiring in the second embodiment of the present utility model;

[0026] Figure 6 This is a schematic diagram of the planar structure of the array substrate in the third embodiment of the present utility model;

[0027] Figure 7 This is a schematic diagram of the planar structure of the array substrate in the non-display area in the fourth embodiment of the present utility model;

[0028] Figure 8 It is a schematic diagram of the structure of the display device in the utility model when it is in a dark state;

[0029] Fig. 9 It is a structural schematic diagram of the display device in the utility model when it is in a bright state. DETAILED DESCRIPTION

[0030] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined purpose of the present invention, the specific implementation methods, structures, features and effects of the array substrate, embedded touch display panel and display device proposed by the present invention are described in detail below in combination with the accompanying drawings and preferred embodiments:

[0031] [Example 1]

[0032] Figure 1 It is a schematic diagram of the planar structure of the array substrate in the first embodiment of the present utility model. Figure 2 It is a schematic diagram of the cross-sectional structure at the connection between the common electrode block and the touch wiring in the first embodiment of the utility model. Figure 3 It is a schematic diagram of the cross-sectional structure at the non-connection portion between the common electrode block and the touch wiring in the first embodiment of the utility model.

[0033] like Figures 1 to 3 As shown, an array substrate provided in the first embodiment of the present invention includes a substrate 10, on which a plurality of scanning lines 112 ( Figure 7 ), multiple data lines 131, multiple touch lines 1 and multiple common electrode blocks 161. Multiple scan lines 112 and multiple data lines 131 are insulated from each other and cross to define multiple pixel units (not shown), each pixel unit is provided with a pixel electrode 151, and the pixel electrode 151 is conductively connected to the corresponding scan line 112 and data line 131 through a thin film transistor. Each common electrode block 161 is electrically connected to the corresponding touch line 1, and a common signal and a touch signal are applied to the common electrode block 161 through the touch line 1, so that the common electrode block 161 is reused as a touch electrode.

[0034] like Figure 2 and Figure 3As shown, the touch line 1 includes a first touch line 134 and a second touch line 141. The first touch line 134 and the data line 131 are located in the same layer and are alternately arranged in parallel with each other, that is, the first touch line 134 and the data line 131 are etched from the same metal layer. The second touch line 141 and the first touch line 134 are located in different layers and are conductively connected to each other. The projections of the first touch line 134 and the second touch line 141 on the substrate 10 overlap with each other. By connecting the first touch line 134 and the second touch line 141 in parallel to each other, the impedance of the touch line 1 is reduced, thereby reducing the touch delay, so as to be suitable for large-size display panels.

[0035] In this embodiment, the area where the first touch line 134 and the second touch line 141 are electrically connected corresponds to the area where the common electrode block 161 and the corresponding touch line 1 are electrically connected. Figure 4d-1 ) is conductively connected, the common electrode block 161 and the corresponding touch line 1 are connected through the third contact hole H3 ( Figure 4f-1 ) are conductively connected, and the positions of the first contact hole H1 and the third contact hole H3 correspond to each other, so that when the first contact hole H1 and the third contact hole H3 are made, the same mask can be used to reduce the number of masks.

[0036] Furthermore, the substrate 10 is provided with a first metal layer 11 ( Figure 4a ), the second metal layer 13 and the third metal layer 14 ( Figure 4e-1), the first metal layer 11 includes a patterned scan line 112 and a gate 111, the gate 111 is conductively connected to the scan line 112; the second metal layer 13 includes a data line 131, a source 132, a drain 133 and a first touch wiring 134, the data line 131 is conductively connected to the source 132, the source 132 is conductively connected to the drain 133 through the active layer 121, the pixel electrode 151 is conductively connected to the corresponding drain 133, the gate 111, the source 132, the drain 133 and the active layer 121 together form a thin film transistor; the third metal layer 14 includes a second touch wiring 141. Among them, a first insulating layer 101 is provided between the first metal layer 11 and the second metal layer 13 and they are insulated and spaced apart from each other by the first insulating layer 101, and a second insulating layer 102 is provided between the second metal layer 13 and the third metal layer 14 and they are insulated and spaced apart from each other by the second insulating layer 102. The first metal layer 11, the second metal layer 13 and the third metal layer 14 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.; the material of the first insulating layer 101 and the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0037] Furthermore, the substrate 10 is provided with a first transparent conductive layer 15 and a second transparent conductive layer 16 located in different layers, the first transparent conductive layer 15 includes a pixel electrode 151, and the second transparent conductive layer 16 includes a common electrode block 161. In this embodiment, the first transparent conductive layer 15 is located below the second transparent conductive layer 16, that is, the pixel electrode 151 is located below the common electrode block 161, and the common electrode block 161 is a slit electrode with a plurality of electrode strips in the area corresponding to the pixel electrode, and the pixel electrode 151 is a slit electrode with a plurality of electrode strips to form a fringe field switching mode (Fringe Field Switching, FFS). Of course, in other embodiments, the first transparent conductive layer 15 can also be located above the second transparent conductive layer 16, that is, the pixel electrode 151 is located above the common electrode block 161. Among them, a third insulating layer 103 is provided between the first transparent conductive layer 15 and the third metal layer 14, and they are insulated and spaced apart from each other by the third insulating layer 103. The third insulating layer 103 can be a flat layer (OC) and plays an insulating and flattening role; a fourth insulating layer 104 is provided between the first transparent conductive layer 15 and the second transparent conductive layer 16, and they are insulated and spaced apart from each other by the fourth insulating layer 104. The second insulating layer 102 is provided with a second contact hole H2 ( Figure 4d-1 ), the third insulating layer 103 is provided with a fourth contact hole H4 corresponding to the second contact hole H2 ( Figure 4f-1), the pixel electrode 151 is conductively connected to the drain electrode 133 through the second contact hole H2 and the fourth contact hole H4. The material of the first transparent conductive layer 15 and the second transparent conductive layer 16 can be a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the material of the third insulating layer 103 and the fourth insulating layer 104 can be silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0038] Figure 4a-Figure 4h-2 FIG. 1 is a cross-sectional schematic diagram of the steps of manufacturing the array substrate in the first embodiment of the present utility model. Figure 4a to Figure 4h-2 As shown, the manufacturing process of the array substrate in this embodiment is as follows:

[0039] like Figure 4a As shown, a substrate 10 is provided. The substrate 10 can be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 can also be a flexible substrate. Suitable materials for the flexible substrate include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or a combination thereof.

[0040] A first metal layer 11 is formed above the substrate 10, and the first metal layer 11 is disposed directly on the upper surface of the substrate 10. The first metal layer 11 is etched by a first mask process, and the first metal layer 11 forms a patterned scan line 112 and a gate 111, and the gate 111 is conductively connected to the scan line 112. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0041] A first insulating layer 101 is formed above the first metal layer 11 to cover the scan line 112 and the gate 111. The first insulating layer 101 is directly disposed on the upper surface of the substrate 10 and the first metal layer 11 and covers the scan line and the gate 111. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0042] like Figure 4b As shown, a semiconductor layer 12 is formed on the first insulating layer 101 , and the semiconductor layer 12 is etched using a second mask process to form an active layer 121 corresponding to the gate 111 .

[0043] like Figure 4cAs shown, a second metal layer 13 is formed on the first insulating layer 101 and the semiconductor layer 12, and the second metal layer 13 covers the first insulating layer 101 and the semiconductor layer 12. The second metal layer 13 is etched by a third mask process, and the second metal layer 13 forms a patterned data line 131, a source electrode 132, a drain electrode 133 and a first touch control wiring 134. The data line 131 is conductively connected to the source electrode 132, and the source electrode 132 is conductively connected to the drain electrode 133 through the active layer 121. The gate 111, the source electrode 132, the drain electrode 133 and the active layer 121 together form a thin film transistor. Among them, the second metal layer 131 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0044] like Figure 4d-1 and Figure 4d-2 As shown, a second insulating layer 102 covering the data line 131, the source electrode 132, the drain electrode 133 and the first touch wiring 134 is formed on the second metal layer 13, and the second insulating layer 102 is etched by a fourth mask process to form a first contact hole H1 corresponding to the first touch wiring 134 and a second contact hole H2 corresponding to the drain electrode 133 on the second insulating layer 102. In this embodiment, the first contact hole H1 is provided in the area where the common electrode block 161 is electrically and conductively connected to the corresponding touch wiring 1, and the first touch wiring 134 in other areas is covered by the second insulating layer 102.

[0045] like Figure 4e-1 and Figure 4e-2 As shown, a third metal layer 14 is formed above the second insulating layer 102, and the third metal layer 14 is etched using a fifth mask process. The third metal layer 14 forms a second touch line 141 corresponding to the pattern of the first touch line 134, and the projections of the first touch line 134 and the second touch line 141 on the substrate 10 overlap with each other. The first touch line 134 and the second touch line 141 are conductively connected to each other through the first contact hole H1, so that the first touch line 134 and the second touch line 141 are connected in parallel to form a touch line 1, so as to reduce the impedance of the touch line 1, thereby reducing the touch delay, so as to be suitable for large-size display panels.

[0046] like Figure 4f-1 and Figure 4f-2As shown, a third insulating layer 103 covering the second touch line 141 is formed on the second insulating layer 102. The third insulating layer 103 is a flat layer (OC) and plays an insulating and flattening role. The third insulating layer 103 is etched by the sixth mask process. The third insulating layer 103 is provided with a third contact hole H3 corresponding to the second touch line 141 and a fourth contact hole H4 corresponding to the second contact hole H2. The third contact hole H3 corresponds to the first contact hole H1. The second touch line 141 is exposed from the third contact hole H3, and the drain 133 is exposed from the second contact hole H2 and the fourth contact hole H4. The sixth mask process and the fourth mask process can use the same mask plate, so that the number of mask plates can be reduced. The material of the third insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0047] like Figure 4g-1 and Figure 4g-2 As shown, a first transparent conductive layer 15 is formed on the third insulating layer 103, and the first transparent conductive layer 15 is etched by the seventh mask process, and the first transparent conductive layer 15 forms a pixel electrode 151 corresponding to the pixel unit. The pixel electrode 151 is a slit electrode with a plurality of electrode strips. The pixel electrode 151 is conductively connected to the drain electrode 133 through the second contact hole H2 and the fourth contact hole H4. The material of the first transparent conductive layer 15 can be a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0048] like Figure 4h-1 and Figure 4h-2 As shown, a fourth insulating layer 104 is formed on the first transparent conductive layer 15, and the fourth insulating layer 104 covers the pixel electrode 151. The fourth insulating layer 104 is etched simultaneously by the eighth mask process, and the fourth insulating layer 104 forms a fifth contact hole corresponding to the third contact hole H3, and the second touch wiring 141 is exposed from the third contact hole H3 and the fifth contact hole. The material of the fourth insulating layer 104 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0049] A second transparent conductive layer 16 is formed on the fourth insulating layer 104, and the second transparent conductive layer 16 is etched by the ninth mask process, so that the second transparent conductive layer 16 forms a plurality of patterned common electrode blocks 161, and each common electrode block 161 is electrically connected to the corresponding second touch control trace 141 through the third contact hole H3 and the fifth contact hole. The common electrode block 161 is a slit electrode having a plurality of electrode strips in the region corresponding to the pixel electrode 151. The material of the second transparent conductive layer 16 can be a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0050] [Example 2]

[0051] Figure 5 Schematic diagram of the cross-sectional structure of the non-connected portion between the common electrode block and the touch control wiring in the second embodiment of the present utility model. Figure 5 As shown, the array substrate provided in the second embodiment of the present invention is different from that in the first embodiment ( Figures 1 to 3 ) is basically the same as the array substrate in the embodiment, except that, in this embodiment: the first touch line 134 and the second touch line 141 are in conductive contact in any area of ​​the entire touch line 1, so that the first touch line 134 and the second touch line 141 are completely in contact with each other to ensure the conductivity of the touch line 1, and at the same time, the derivative capacitance generated by the second touch line 141 is also smaller. That is, when the second insulating layer 102 is etched during the manufacture of the array substrate, the first contact hole H1 is formed as a long strip and extends along the direction of the first touch line 134, so that the entire first touch line 134 is exposed from the first contact hole H1.

[0052] It should be understood by those skilled in the art that the rest of the structure and working principle of this embodiment are the same as those of the first embodiment and will not be described in detail here.

[0053] [Example 2]

[0054] Figure 6 Schematic diagram of the planar structure of the array substrate in the third embodiment of the present utility model. Figure 6 As shown, the array substrate provided in the second embodiment of the present invention is different from that in the first embodiment ( Figures 1 to 3 )、Example 2 ( Figure 5 ) are substantially the same, except that, in this embodiment:

[0055] The common electrode block 161 on the side away from the touch chip 100 is electrically connected to a plurality of touch lines 1. The more the common electrode block 161 on the side farther from the touch chip 100 is, the more touch lines 1 are connected. That is, the common electrode block 161 on the side away from the touch chip 100 is electrically connected in parallel with a plurality of touch lines 134, thereby further reducing the impedance and the touch delay, so as to be suitable for a large-size display panel; at the same time, the problem of poor display effect of the screen caused by the large difference in impedance of different touch lines 1 due to the unequal length of the actual transmission signal of the touch lines 1 is reduced. For example, a row of common electrode blocks 161 closest to the touch chip 100 is electrically connected to a touch trace 1, the common electrode block 161 farthest from the touch chip 100 is electrically connected to three touch traces 1, and the common electrode block 161 between the side closest to the touch chip 100 and the side farthest from the touch chip 100 is electrically connected to two touch traces 1, thereby reducing the impedance difference between different touch traces 1.

[0056] It should be understood by those skilled in the art that the rest of the structure and working principle of this embodiment are the same as those of Embodiment 1 and Embodiment 2, and will not be described in detail here.

[0057] [Example 2]

[0058] Figure 7 Schematic diagram of the planar structure of the array substrate in the non-display area in the fourth embodiment of the present utility model. Figure 7 As shown, the array substrate provided in the second embodiment of the present invention is different from that in the first embodiment ( Figures 1 to 3 )、Example 2 ( Figure 5 )、Example 3 ( Figure 6 ) are substantially the same, except that, in this embodiment:

[0059] The substrate 10 is provided with a first lead 135 and a second lead 142 in the non-display area. The first lead 135 and the data line 131 are located in the same layer and are electrically connected. The other end of the first lead 135 is located in the binding area for transmitting data signals to the data line 131. The second lead 142 and the second touch line 141 are located in the same layer and are electrically connected. The other end of the second lead 142 is located in the binding area for transmitting data signals to the second touch line 141. The projections of the first lead 135 and the second lead 142 on the substrate 10 are arranged to cross each other. By using the second lead 142 located in the same layer as the second touch wiring 141 to transmit signals to the touch wiring 1, the second lead 142 can be set in a different layer from the first lead 135, so that the line width of the second lead 142 can be made wider to reduce the impedance of the second lead 142; at the same time, the projections of the first lead 135 and the second lead 142 on the substrate 10 are cross-arranged with each other, which can reduce the relative overlapping area of ​​the second lead 142 and the first lead 135, and reduce the parasitic capacitance formed, so as to improve the signal transmission effect, and the cross-arrangement is conducive to reducing the frame.

[0060] Furthermore, the first lead 135 includes a first layer lead and a second layer lead, the first layer lead and the scan line 112 are located at the same layer, the second layer lead and the data line 131 are located at the same layer, and the projections of the first layer lead and the second layer lead on the substrate 10 overlap with each other. The first layer lead and the second layer lead are connected in parallel to form the first lead 135, so as to reduce the impedance of the first lead 135 and further improve the signal transmission effect.

[0061] Of course, the substrate 10 is further provided with a third lead (not shown) in the non-display area. One end of the third lead is electrically connected to the scan line 112 , and the other end is located in the binding area for transmitting data signals to the scan line 112 .

[0062] The first layer lead and the third lead are formed by etching the first metal layer 11 , the second layer lead is formed by etching the second metal layer 13 , and the second lead 142 is formed by etching the third metal layer 14 .

[0063] It should be understood by those skilled in the art that the rest of the structure and working principle of this embodiment are the same as those of Embodiment 1, Embodiment 2, and Embodiment 3, and will not be described in detail here.

[0064] Figure 8 It is a schematic diagram of the cross-sectional structure of the display device in the utility model when it is in a dark state. Fig. 9 Schematic diagram of the cross-sectional structure of the display device in the present utility model when in bright state. Figure 8 and Fig. 9 As shown, the present application also provides an embedded touch display panel, including the array substrate as described above. The display panel includes a color filter substrate 20 arranged opposite to the array substrate and a liquid crystal layer 30 located between the array substrate and the color filter substrate 20, an upper polarizer 41 is provided on the color filter substrate 20, and a lower polarizer 42 is provided on the array substrate, and the light transmission axis of the upper polarizer 41 and the light transmission axis of the lower polarizer 42 are perpendicular to each other. Among them, the liquid crystal molecules in the liquid crystal layer 30 use positive liquid crystal molecules (liquid crystal molecules with positive dielectric anisotropy). In the initial state, the positive liquid crystal molecules are in a lying posture, and the alignment direction of the positive liquid crystal molecules close to the color filter substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules close to the array substrate. It can be understood that the array substrate and the color filter substrate 20 are also provided with an alignment layer in a layer facing the liquid crystal layer 30, so as to align the positive liquid crystal molecules in the liquid crystal layer 30.

[0065] In this embodiment, a black matrix 21 and a color resist layer 22 are provided on the color filter substrate 20, and the black matrix 21 corresponds to the scan line, the data line, the touch line 12, the thin film transistor and the peripheral non-display area, and the black matrix 21 separates the plurality of color resist layers 22. The color resist layer 22 includes color resist materials of red (R), green (G) and blue (B), and correspondingly forms sub-pixels of red (R), green (G) and blue (B).

[0066] like Figure 8 and Fig. 9 As shown, the utility model further provides a display device, including the embedded touch display panel as described above and a backlight module 50. The backlight module 50 is located below the embedded touch display panel and is used to provide a backlight source for the display panel.

[0067] The backlight module 50 includes a backlight source 51 and an anti-peep layer 53, and the anti-peep layer 53 is used to narrow the range of the light emission angle. A brightness enhancement film 52 is also provided between the backlight source 51 and the anti-peep layer 53, and the brightness enhancement film 52 increases the brightness of the backlight module 50. Among them, the anti-peep layer 53 is equivalent to a miniature shutter structure, which can block light with a larger incident angle and allow light with a smaller incident angle to pass through, so that the angle range of light passing through the anti-peep layer 53 becomes smaller. The anti-peep layer 53 includes a plurality of parallel light-blocking walls and a light-transmitting hole located between two adjacent light-blocking walls, and light-absorbing materials are provided on both sides of the light-blocking walls. Of course, the backlight source 51 can also be a light-collecting backlight source, so there is no need to set the anti-peep layer 53, but the light-collecting backlight source is more expensive than the conventional backlight source.

[0068] The backlight module 50 can be an edge-type backlight module or a direct-type backlight module. Preferably, the backlight module 50 adopts a collimated backlight (CBL) mode, which can collect light and ensure the display effect.

[0069] In this document, the directional words such as up, down, left, right, front, and back are defined by the positions of the structures in the drawings and the positions of the structures relative to each other, just for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of the directional words should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second" used in this document are only used to distinguish names and are not used to limit quantity and order.

[0070] The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with the profession can make some changes or modifications to the technical contents disclosed above without departing from the scope of the technical solution of the present invention, which are equivalent embodiments of equivalent changes. However, any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. An array substrate, characterized in that: The invention comprises a substrate (10), wherein a plurality of scanning lines (112), a plurality of data lines (131), a plurality of touch control lines (1) and a plurality of common electrode blocks (161) are arranged on the substrate (10), wherein the plurality of scanning lines (112) and the plurality of data lines (131) are insulated from each other and cross-defined to form a plurality of pixel units, wherein each of the pixel units is provided with a pixel electrode (151), wherein the pixel electrode (151) is conductively connected to the corresponding scanning line (112) and the data line (131) through a thin film transistor, and each of the common electrode blocks (161) is electrically connected to the corresponding touch control line (1); The touch line (1) comprises a first touch line (134) and a second touch line (141); the first touch line (134) and the data line (131) are located in the same layer and are alternately arranged in parallel with each other; the second touch line (141) and the first touch line (134) are located in different layers and are conductively connected to each other; and the projections of the first touch line (134) and the second touch line (141) on the substrate (10) overlap with each other.

2. The array substrate according to claim 1, characterized in that: The area where the first touch control wiring (134) and the second touch control wiring (141) are electrically connected corresponds to the area where the common electrode block (161) and the corresponding touch control wiring (1) are electrically connected and electrically connected; Alternatively, the first touch-control wiring (134) and the second touch-control wiring (141) are in conductive contact in any region of the entire touch-control wiring (1).

3. The array substrate according to claim 1, characterized in that: The common electrode block (161) on a side away from the touch chip (100) is electrically connected to the plurality of touch traces (1).

4. The array substrate according to claim 3, characterized in that: The common electrode block (161) on a side that is farther from the touch control chip (100) is connected to a greater number of touch control traces (1).

5. The array substrate according to claim 1, characterized in that: The substrate (10) is provided with a first lead (135) and a second lead (142) in the non-display area, the first lead (135) and the data line (131) are located in the same layer and are electrically connected, the second lead (142) and the second touch line (141) are located in the same layer and are electrically connected, and the projections of the first lead (135) and the second lead (142) on the substrate (10) are arranged to cross each other; The first lead wires (135) include a first layer of lead wires and a second layer of lead wires, the first layer of lead wires and the scan lines (112) are located in the same layer, the second layer of lead wires and the data lines (131) are located in the same layer, and the projections of the first layer of lead wires and the second layer of lead wires on the substrate (10) overlap with each other.

6. The array substrate according to claim 1, characterized in that: The substrate (10) is provided with a first metal layer (11), a second metal layer (13) and a third metal layer (14) located at different layers, the first metal layer (11) comprising the scan line (112) and a gate electrode (111), the gate electrode (111) being conductively connected to the scan line (112); the second metal layer (13) comprising the data line (131), a source electrode (132), a drain electrode (133) and the first touch wiring (134), the data line (131) being conductively connected to the source electrode (132), the source electrode (132) being conductively connected to the drain electrode (133) via an active layer (121), the pixel electrode (151) being conductively connected to the corresponding drain electrode (133); and the third metal layer (14) comprising the second touch wiring (141).

7. The array substrate according to claim 1, characterized in that: A first transparent conductive layer (15) and a second transparent conductive layer (16) located at different layers are provided on the substrate (10); the first transparent conductive layer (15) comprises the pixel electrode (151); and the second transparent conductive layer (16) comprises the common electrode block (161).

8. The array substrate according to claim 7, characterized in that: The first transparent conductive layer (15) is located above the second transparent conductive layer (16), or the first transparent conductive layer (15) is located below the second transparent conductive layer (16).

9. An embedded touch display panel, characterized in that: It comprises the array substrate according to any one of claims 1 to 8, a color filter substrate (20) arranged opposite to the array substrate, and a liquid crystal layer (30) located between the array substrate and the color filter substrate (20).

10. A display device, characterized in that: It comprises the embedded touch display panel as claimed in claim 9.

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