Mainboard circuit for updating CPLD

Abstract

The utility model provides a mainboard circuit for updating a CPLD (Complex Programmable Logic Device), which relates to the technical field of computer mainboards, and is characterized in that a signal sent by a BMC (Baseboard Management Controller) management module daughter card is transmitted to a signal switching chip and a gigabit management network port through the connection of a memory connector and the BMC management module daughter card; the gigabit management network port receives signals and provides high-speed network transmission for remote online updating of the CPLD unit module; the signal switching chip receives a signal and switches a debugging mode of the CPLD unit module based on the signal, the CPLD unit module is connected with the firmware burning connector to carry out local offline debugging when the debugging mode is local offline debugging, and the CPLD unit module is connected with the BMC management module daughter card to carry out remote online debugging when the debugging mode is remote online debugging. Two debugging modes of local off-line debugging and remote on-line debugging are realized, and the coupling degree of each part in a mainboard circuit is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of computer mainboard design, in particular to a mainboard circuit for updating CPLD. Background Art

[0002] In recent years, with the continuous deepening of informatization in various industries, the popularity of server applications has also been rising, and with it come issues such as information security and product reliability. From the current domestic server market, foreign brands still occupy a large share; from the perspective of information security, the demand for localization of servers is imminent.

[0003] In the current information security context, a large number of domestic servers have emerged, and the fault debugging technical solutions are mainly divided into local offline debugging and remote online debugging. Local offline debugging requires technicians to go to the site to troubleshoot and debug, which is time-consuming and labor-intensive, inefficient, and difficult to maintain and manage. In comparison, remote online debugging can be used to troubleshoot and debug servers, saving manpower and material resources and improving work efficiency. However, the remote management function of the server depends on the BMC management module subcard. In the traditional onboard mode, once the BMC management module subcard fails or is damaged, the server will lose the remote online debugging function and cannot be monitored and debugged in real time. Utility Model Content

[0004] In view of this, the purpose of the utility model is to provide a mainboard circuit for updating CPLD to realize two debugging modes: local offline debugging and remote online debugging. When using the debugging mode of remote online debugging, not only manpower and material resources are saved, but also work efficiency is improved, and the coupling degree of each part in the mainboard circuit is reduced. When using the debugging mode of local offline debugging, it will not be time-consuming and laborious. Moreover, when remote online debugging cannot be realized, local offline debugging can be used to avoid losing the monitoring and debugging of CPLD.

[0005] The utility model embodiment provides a mainboard circuit for updating CPLD, which is used for remote online updating of the CPLD unit module in the mainboard circuit through a BMC management module daughter card outside the mainboard circuit; the mainboard circuit comprises: a memory connector, a gigabit management network port, a firmware burning connector, a signal switching chip and the CPLD unit module; the memory connector is used to connect the BMC management module daughter card, and transmit the signal sent by the BMC management module daughter card to the signal switching chip and the gigabit management network port; the gigabit management network port is used to receive the signal, and provide high-speed network transmission for remote online updating of the CPLD unit module; the signal switching chip is used to receive the signal, and switch the debugging mode of the CPLD unit module based on the signal; the CPLD unit module is used to connect to the firmware burning connector to perform local offline debugging when the debugging mode is local offline debugging; and to connect to the BMC management module daughter card to perform remote online debugging when the debugging mode is remote online debugging.

[0006] In a preferred embodiment of the utility model, the CPLD unit module is connected to the signal switching chip via the JTAG bus; the signal switching chip is also connected to the memory connector via the JTAG bus and the GPIO interface; the signal switching chip is connected to the CPLD unit module firmware burning connector via the JTAG bus; the BMC management module subcard is connected to the memory connector.

[0007] In a preferred embodiment of the present utility model, the BMC management module daughter card includes: a BMC management chip and a PHY chip; the BMC management chip is connected to the PHY chip via an RGMII bus.

[0008] In a preferred embodiment of the utility model, the PHY chip is connected to the gigabit management network port via the IPMI bus through the memory connector, providing high-speed network transmission for remote online updating of the CPLD unit module.

[0009] In a preferred embodiment of the utility model, the GPIO interface of the BMC management chip is connected to the signal switching chip through the GPIO bus via the memory connector; the BMC management chip is used to control the signal path of the signal switching chip to switch the debugging mode of the CPLD unit module.

[0010] In a preferred embodiment of the utility model, the CPLD unit module is provided with a JTAG interface; the signal switching chip is provided with a channel selection port, two input channels and one output channel; the firmware burning connector is provided with a JTAG interface; the memory connector is provided with a GPIO interface, a JTAG interface and an IPMI interface.

[0011] In a preferred embodiment of the utility model, when the GPIO interface of the BMC management chip is 0, the JTAG interface of the CPLD unit module is connected to the firmware burning connector by default for local offline debugging; when the GPIO interface of the BMC management chip is 1, the JTAG interface of the CPLD unit module is connected to the JTAG interface of the BMC management chip for remote online debugging.

[0012] In a preferred embodiment of the utility model, the signal sent by the BMC management module subcard includes the signal sent by the PHY chip; the signal sent by the PHY chip is transmitted to the gigabit management network port via the IPMI bus through the memory connector to establish a communication connection between the PHY chip and the gigabit management network port.

[0013] In a preferred embodiment of the utility model, the signal sent by the BMC management module subcard includes the signal sent by the BMC management chip; the signal sent by the BMC management chip is connected to the signal switching chip through the GPIO bus via the memory connector to establish a communication connection between the BMC management chip and the signal switching chip.

[0014] In a preferred embodiment of the utility model, the motherboard circuit is applied to a server motherboard based on Feiteng S5000C; the gigabit management network port is an RJ45 gigabit management network port; and the memory connector is a DDR4SO-DIMM connector.

[0015] The embodiments of the present invention bring the following beneficial effects:

[0016] The embodiment of the utility model provides a mainboard circuit for updating CPLD, and the mainboard circuit includes: a memory connector, a gigabit management network port, the firmware burning connector, a signal switching chip and the CPLD unit module. Through the connection between the memory connector and the BMC management module subcard, the signal sent by the BMC management module subcard is transmitted to the signal switching chip and the gigabit management network port, and the gigabit management network port receives the signal to provide high-speed network transmission for remote online update of the CPLD unit module; the signal switching chip receives the signal, and switches the debugging mode of the CPLD unit module based on the signal. When the debugging mode is local offline debugging, the CPLD unit module is connected to the firmware burning connector for local offline debugging, and when the debugging mode is remote online debugging, the CPLD unit module is connected to the BMC management module subcard for remote online debugging. Two debugging modes, local offline debugging and remote online debugging, can be realized. When using the remote online debugging mode, it can not only save manpower and material resources, but also improve work efficiency and reduce the coupling degree of each part in the motherboard circuit. When using the local offline debugging mode, it will not be time-consuming and laborious. Moreover, when remote online debugging cannot be realized, local offline debugging can be used to avoid losing the monitoring and debugging of CPLD.

[0017] Other features and advantages of the present disclosure will be set forth in the following description, or some features and advantages may be inferred or unambiguously determined from the description, or may be learned by implementing the above-mentioned technology of the present disclosure.

[0018] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A structural diagram of a mainboard circuit for updating a CPLD provided by an embodiment of the utility model;

[0021] Figure 2 Another structural diagram of a mainboard circuit for updating a CPLD provided by an embodiment of the utility model;

[0022] Figure 3A structural diagram of a BMC management module daughter card provided by an embodiment of the utility model;

[0023] Figure 4 A structural diagram of a BMC management module daughter card provided in an embodiment of the utility model.

[0024] Diagram:

[0025] 10-memory connector; 20-Gigabit management network port; 30-firmware burning connector; 40-signal switching chip; 50-CPLD unit module; 60-BMC management module daughter card; 61-BMC management chip; 62-PHY chip. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the utility model clearer, the technical solution of the utility model will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0027] In recent years, with the continuous deepening of informatization in various industries, the popularity of server applications has also been rising, and with it come issues such as information security and product reliability. From the current domestic server market, foreign brands still occupy a large share; from the perspective of information security, the demand for localization of servers is imminent.

[0028] In the current information security context, a large number of domestic servers have emerged, and the fault debugging technical solutions are mainly divided into local offline debugging and remote online debugging. Local offline debugging requires technicians to go to the site to troubleshoot and debug, which is time-consuming and labor-intensive, inefficient, and difficult to maintain and manage. In comparison, remote online debugging can be used to troubleshoot and debug servers, saving manpower and material resources and improving work efficiency. However, the remote management function of the server depends on the BMC management module subcard. In the traditional onboard mode, once the BMC management module subcard fails or is damaged, the server will lose the remote online debugging function and cannot be monitored and debugged in real time.

[0029] Based on this, the embodiment of the utility model provides a mainboard circuit for updating CPLD, and the mainboard circuit includes: a memory connector, a gigabit management network port, a firmware burning connector, a signal switching chip and a CPLD unit module. Through the connection between the memory connector and the BMC management module subcard, the signal sent by the BMC management module subcard is transmitted to the signal switching chip and the gigabit management network port, and the gigabit management network port receives the signal to provide high-speed network transmission for remote online update of the CPLD unit module; the signal switching chip receives the signal, and switches the debugging mode of the CPLD unit module based on the signal. When the debugging mode of the CPLD unit module is local offline debugging, it is connected to the firmware burning connector for local offline debugging, and when the debugging mode of the CPLD unit module is remote online debugging, it is connected to the BMC management module subcard for remote online debugging. Two debugging modes, local offline debugging and remote online debugging, can be realized. When using the remote online debugging mode, it can not only save manpower and material resources, but also improve work efficiency and reduce the coupling degree of each part in the motherboard circuit. When using the local offline debugging mode, it will not be time-consuming and laborious. Moreover, when remote online debugging cannot be realized, local offline debugging can be used to avoid losing the monitoring and debugging of CPLD.

[0030] To facilitate understanding of this embodiment, firstly, a mainboard circuit for updating CPLD disclosed in an embodiment of the utility model is introduced in detail.

[0031] Example 1

[0032] The embodiment of the utility model provides a mainboard circuit for updating CPLD, which is used for remote online debugging of the CPLD unit module in the mainboard circuit through a BMC management module daughter card outside the mainboard circuit, and local offline debugging of the CPLD unit module through a firmware burning connector in the mainboard circuit.

[0033] Figure 1 A structural diagram of a mainboard circuit for updating a CPLD provided by an embodiment of the utility model. Figure 1 As shown, the mainboard circuit for updating the CPLD may include the following structure:

[0034] Memory connector 10 , Gigabit management network port 20 , firmware burning connector 30 , signal switching chip 40 and CPLD unit module 50 .

[0035] Among them, the CPLD unit module 50 is a digital integrated circuit that users construct logical functions according to their own needs. The CPLD unit module 50 adopts the EF3L90CG400B model. On the one hand, it is used for signal level conversion so that the signal can communicate normally before each part of each mainboard line. On the other hand, it controls the power-on timing and power control of the mainboard to realize specific logical functions according to requirements. It has the characteristics of instantaneous power-on, non-volatile storage, high I / O count, etc. The signal switching chip 40 is a 1:2 multiplexer, using the TS3A27518E model. The signal bandwidth it supports can reach up to 240MHz to ensure normal signal transmission.

[0036] The memory connector 10 is used to connect to the BMC management module daughter card 60 , and transmit the signal sent by the BMC management module daughter card 60 to the signal switching chip 40 and the gigabit management network port 20 .

[0037] The gigabit management network port 20 is used to receive signals and provide high-speed network transmission for remote online update of the CPLD unit module 50 .

[0038] The signal switching chip 40 is used to receive signals and switch the debugging mode of the CPLD unit module 50 based on the signals.

[0039] The CPLD unit module 50 is used to connect to the firmware burning connector 30 for local offline debugging when the debugging mode is local offline debugging; and to connect to the BMC management module daughter card 60 for remote online debugging when the debugging mode is remote online debugging.

[0040] BMC management module daughter card 60 is an important part of realizing remote online debugging. For ease of understanding, Figure 2 The structure diagram of a BMC management module provided by the embodiment of the utility model. Figure 2 As shown, the BMC management module daughter card 60 includes: a BMC management chip 61 and a PHY chip 62 .

[0041] Among them, the BMC management chip 61 is a baseboard management controller, the PHY chip 62 is a port physical layer, and the PHY chip 62 adopts the JL2101 model and supports the RGMII interface specification.

[0042] Specifically, the BMC management chip 61 is connected to the PHY chip 62 via the RGMII bus. RGMII is a Gigabit Medium Independent Interface, which uses a 4-bit data interface, has a working clock of 125MHz, and transmits data at both the rising and falling edges, so the transmission rate can reach up to 1000Mbps. Specifically, the BMC management chip 61 is integrated with an RGMII serial port, and the PHY chip 62 can be mounted via the RGMII bus.

[0043] The mainboard circuit for updating the CPLD provided in the embodiment of the utility model can transmit the signal sent by the BMC management module daughter card 60 to the signal switching chip 40 and the gigabit management network port 20 through the connection between the memory connector 10 and the BMC management module daughter card 60. The gigabit management network port 20 receives the signal to provide high-speed network transmission for the remote online update of the CPLD unit module 50; the signal switching chip 40 receives the signal and switches the debugging mode of the CPLD unit module 50 based on the signal. When the debugging mode of the CPLD unit module 50 is local offline debugging, the CPLD unit module 50 is connected to the firmware burning connector 30 for local offline debugging. When the debugging mode of the CPLD unit module 50 is remote online debugging, the CPLD unit module 50 is connected to the BMC management module daughter card 60 for remote online debugging. Two debugging modes, local offline debugging and remote online debugging, can be realized. When using the remote online debugging mode, it can not only save manpower and material resources, but also improve work efficiency and reduce the coupling degree of each part in the motherboard circuit. When using the local offline debugging mode, it will not be time-consuming and laborious. Moreover, when remote online debugging cannot be realized, local offline debugging can be used to avoid losing the monitoring and debugging of CPLD.

[0044] Example 2

[0045] The embodiment of the utility model further provides a mainboard circuit for updating CPLD; the mainboard circuit is implemented on the basis of the mainboard circuit of the above embodiment.

[0046] Figure 3 A structural diagram of a mainboard circuit for updating a CPLD provided by an embodiment of the utility model. Figure 3 As shown, the structure in the mainboard circuit for updating the CPLD is specifically as follows:

[0047] Based on the mainboard circuit of the above embodiment, the CPLD unit module 50 is provided with a JTAG interface; the signal switching chip 40 is provided with a channel selection port SEL, two input channels input and one output channel output, and the firmware burning connector 30 is provided with a JTAG interface; the memory connector 10 is provided with a GPIO interface, a JTAG interface and an IPMI interface.

[0048] The CPLD unit module 50 can be used to update its own firmware information through the provided JTAG interface, and the JTAG interface is a joint debugging interface.

[0049] Furthermore, the CPLD unit module 50 is connected to the signal switching chip 40 via the JTAG bus, and the signal switching chip 40 is also connected to the memory connector 10 via the JTAG bus and the GPIO interface. The signal switching chip 40 is connected to the CPLD unit module 50 firmware burning connector 30 via the JTAG bus, and the BMC management module subcard 60 is connected to the memory connector 10.

[0050] Specifically, the PHY chip 62 is connected to the gigabit management network port 20 through the IPMI bus via the memory connector 10, providing high-speed network transmission for the remote online update of the CPLD unit module 50. The GPIO interface of the BMC management chip 61 is connected to the signal switching chip 40 through the GPIO bus via the memory connector 10; the BMC management chip 61 is used to control the signal path of the signal switching chip 40 to switch the debugging mode of the CPLD unit module 50.

[0051] Specifically, when the GPIO interface of the BMC management chip 61 is 0, the JTAG interface of the CPLD unit module 50 is connected to the firmware burning connector 30 by default for local offline debugging; when the GPIO interface of the BMC management chip 61 is 1, the JTAG interface of the CPLD unit module 50 is connected to the JTAG interface of the BMC management chip 61 for remote online debugging. For ease of understanding, Figure 4 A JTAG interface connection switching truth table corresponding to the GPIO interface state provided in an embodiment of the utility model.

[0052] Among them, the signal sent by the BMC management module subcard 60 includes the signal sent by the PHY chip 62; the signal sent by the PHY chip 62 is transmitted to the gigabit management network port 20 through the IPMI bus and the memory connector 10 to establish a communication connection between the PHY chip 62 and the gigabit management network port 20.

[0053] Among them, the signal sent by the BMC management module daughter card 60 includes the signal sent by the BMC management chip 61; the signal sent by the BMC management chip 61 is connected to the signal switching chip 40 through the GPIO bus through the memory connector 10 to establish a communication connection between the BMC management chip 61 and the signal switching chip 40.

[0054] Specifically, the motherboard circuit can be applied to a server motherboard based on Feiteng S5000C, and of course can also be applied to other server motherboards, which is not limited here, and supports connecting different BMC management module daughter cards 60 under the condition of interface compatibility, thereby improving the flexibility of hardware design, and remotely debugging the CPLD unit module 50 online through the BMC management module daughter card 60. The maintainability of existing domestic servers can be improved to meet the user's demand for storage products.

[0055] The gigabit management network port 20 may be an RJ45 gigabit management network port 20. The memory connector 10 may be a DDR4 SO-DIMM connector, which is a small-profile dual in-line memory module connector.

[0056] The mainboard circuit for updating CPLD provided by the embodiment of the utility model can reduce the cost of the server mainboard through the modular design of the BMC management module daughter card 60, and can realize two debugging modes of local offline debugging and remote online debugging. When the debugging mode of remote online debugging is used, it not only saves manpower and material resources, but also improves work efficiency and reduces the coupling degree of various parts in the mainboard circuit. When the debugging mode of local offline debugging is used, it will not be time-consuming and labor-intensive. Moreover, when remote online debugging cannot be realized, local offline debugging can be used to avoid losing the monitoring and debugging of CPLD.

[0057] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0058] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the utility model, which are used to illustrate the technical solution of the utility model, rather than to limit it. The protection scope of the utility model is not limited thereto. Although the utility model is described in detail with reference to the above-mentioned embodiments, ordinary technicians in this field should understand that any technician familiar with the technical field can still modify the technical solution recorded in the above-mentioned embodiments within the technical scope disclosed by the utility model, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solution of the embodiment of the utility model, and should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model shall be based on the protection scope of the claims.

Claims

1. A mainboard circuit for updating CPLD, characterized in that: Used to remotely debug the CPLD unit module in the mainboard circuit online through the BMC management module daughter card outside the mainboard circuit, and to debug the CPLD unit module locally offline through the firmware burning connector in the mainboard circuit; The mainboard circuit includes: a memory connector, a gigabit management network port, the firmware burning connector, a signal switching chip and the CPLD unit module; The memory connector is used to connect the BMC management module daughter card and transmit the signal sent by the BMC management module daughter card to the signal switching chip and the gigabit management network port; The Gigabit management network port is used to receive the signal and provide high-speed network transmission for remote online update of the CPLD unit module; The signal switching chip is used to receive the signal and switch the debugging mode of the CPLD unit module based on the signal; The CPLD unit module is used to connect to the firmware burning connector for local offline debugging when the debugging mode is local offline debugging; and to connect to the BMC management module daughter card for remote online debugging when the debugging mode is remote online debugging.

2. The mainboard circuit according to claim 1, characterized in that: The CPLD unit module is connected to the signal switching chip via the JTAG bus; the signal switching chip is also connected to the memory connector via the JTAG bus and the GPIO interface; the signal switching chip is connected to the CPLD unit module firmware burning connector via the JTAG bus; the BMC management module subcard is connected to the memory connector.

3. The mainboard circuit according to claim 1, characterized in that: The BMC management module daughter card comprises: a BMC management chip and a PHY chip; the BMC management chip is connected to the PHY chip via an RGMII bus.

4. The mainboard circuit according to claim 3, characterized in that: The PHY chip is connected to the gigabit management network port via the IPMI bus through the memory connector, providing high-speed network transmission for remote online updating of the CPLD unit module.

5. The mainboard circuit according to claim 3, characterized in that: The GPIO interface of the BMC management chip is connected to the signal switching chip via the GPIO bus through the memory connector; the BMC management chip is used to control the signal path of the signal switching chip to switch the debugging mode of the CPLD unit module.

6. The mainboard circuit according to claim 4, characterized in that: The CPLD unit module is provided with a JTAG interface; the signal switching chip is provided with a channel selection port, two input channels and one output channel; the firmware burning connector is provided with a JTAG interface; the memory connector is provided with a GPIO interface, a JTAG interface and an IPMI interface.

7. The mainboard circuit according to claim 6, characterized in that: When the GPIO interface of the BMC management chip is 0, the JTAG interface of the CPLD unit module is connected to the firmware burning connector by default for local offline debugging; when the GPIO interface of the BMC management chip is 1, the JTAG interface of the CPLD unit module is connected to the JTAG interface of the BMC management chip for remote online debugging.

8. The mainboard circuit according to claim 3, characterized in that: The signal sent by the BMC management module daughter card includes the signal sent by the PHY chip; the signal sent by the PHY chip is transmitted to the gigabit management network port through the IPMI bus and the memory connector to establish a communication connection between the PHY chip and the gigabit management network port.

9. The mainboard circuit according to claim 3, characterized in that: The signal sent by the BMC management module daughter card includes the signal sent by the BMC management chip; the signal sent by the BMC management chip is connected to the signal switching chip through the GPIO bus through the memory connector to establish a communication connection between the BMC management chip and the signal switching chip.

10. The mainboard circuit according to any one of claims 1 to 9, characterized in that: The motherboard circuit is applied to a server motherboard based on Feiteng S5000C; the gigabit management network port is an RJ45 gigabit management network port; and the memory connector is a DDR4 SO-DIMM connector.

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