Wiring structure of common bonding pad area of semiconductor device and semiconductor device

Abstract

The utility model provides a wiring structure of a bonding pad area in a semiconductor device and the semiconductor device. The wiring structure is characterized in that the wiring structure comprises a common bonding pad area; the wiring structure at least comprises a first circuit and a second circuit which are used for connecting the first chip and the second chip; the first circuit and the second circuit both extend from the first chip to the interior of the common bonding pad area, and then extend out of the common bonding pad area to be connected with a second chip; the wiring structure further comprises a selection module, and the selection module selects to conduct the first circuit or the second circuit based on a preset integrated circuit wiring rule. The wiring structure provided by the embodiment of the utility model can eliminate the residual error in the circuit and improve the communication performance of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the technical field of printed circuit board (PCB) design, and in particular to a wiring structure of a common pad area of ​​a semiconductor device and a semiconductor device. Background Art

[0002] Layout is one of the most basic working skills for printed circuit board (PCB) design engineers. In PCB design, layout is an important step to complete product design. The quality of PCB routing directly affects the performance of the entire system. Layout is crucial in high-speed PCB design. The design process of layout is highly limited, with fine skills and a large workload.

[0003] In the traditional PCB design, when the co-layout circuit is laid out, there will be lines that support different speeds. When selecting these lines, people tend to choose a wiring method with a small resistance value (for example, 0 ohm resistance). However, when one of the lines is selected, another line will often produce a stub, causing noise interference to the signal quality of the semiconductor device. Especially in high-speed transmission lines, the traditional wiring structure cannot meet the electrical characteristics specifications of semiconductor devices. Utility Model Content

[0004] In view of at least one of the above technical problems existing in the prior art, the present application is proposed. According to one aspect of the present application, a wiring structure of a common pad area of ​​a semiconductor device is provided, the wiring structure comprising:

[0005] The wiring structure includes a common pad area;

[0006] The wiring structure at least includes a first line and a second line for connecting the first chip and the second chip; the first line and the second line both extend from the first chip to the inside of the common pad area, and then extend out of the common pad area to connect with the second chip;

[0007] The wiring structure further includes a selection module, and the selection module selects to conduct the first line or the second line based on a preset integrated circuit wiring rule.

[0008] In some embodiments, the common pad area has two surfaces; the first chip and / or the second chip are mounted on one of the surfaces of the common pad area; the common pad area is provided with at least one via hole, and the first circuit and / or the second circuit passes through the at least one via hole to be connected to the second ball pin of the second chip.

[0009] In some embodiments, the first chip and the second chip are mounted on the first surface of the common pad area; the common pad area is provided with a first via hole, a second via hole and a third via hole;

[0010] One end of the circuit is connected to the first chip, extends to the inside of the common pad area through a first via hole, and is divided into the first circuit and the second circuit at a predetermined position;

[0011] At the predetermined position, the first circuit passes through the first surface of the common pad area along the second via hole and is connected to the first ball pin of the second chip;

[0012] The second circuit passes through the second surface of the common pad area along the second via hole, and then passes through the third via hole to be connected to the second ball pin of the second chip.

[0013] In some embodiments, the first chip is mounted on the first surface of the common pad area, and the second chip is mounted on the second surface of the common pad area; the common pad area is provided with a first via hole and a second via hole

[0014] One end of the circuit is connected to the first chip, extends to the inside of the common pad area through the first via hole, and is divided into the first circuit and the second circuit at a predetermined position;

[0015] At the predetermined position, the first circuit passes through the first surface of the common pad area along the second via hole and is connected to the first ball pin of the second chip;

[0016] The second circuit passes through the second surface of the common pad area along the second via hole and is connected to the second ball pin of the second chip.

[0017] In some embodiments, the first line and the second line support two different transmission rates.

[0018] In some embodiments, the first line supports the fifth generation high-speed serial computer expansion bus standard;

[0019] The second line supports a high speed serial computer expansion bus standard.

[0020] In some embodiments, the preset integrated circuit wiring rule at least includes selecting a circuit with a smaller resistance between the first circuit and the second circuit.

[0021] In some embodiments, the line resistance of the first line is 0 ohm and / or the line resistance of the second line is a 0 ohm circuit.

[0022] In some embodiments, the first chip includes at least a memory or a central processing unit; correspondingly, the second chip includes at least a central processing unit or a memory.

[0023] Another aspect of an embodiment of the present application provides a semiconductor device, which includes the wiring structure of the common pad area of ​​the semiconductor device mentioned above.

[0024] The wiring structure of the common pad area of ​​the semiconductor device in the embodiment of the present application is that in the common pad area, the first line and the second line both extend from the first chip to the inside of the common pad area, and then extend out of the common pad area to connect with the second chip, and based on the preset integrated circuit wiring rules, the first line or the second line is selected to be turned on. This connection method can eliminate residuals in the line and improve the communication performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0026] Figure 1 A schematic cross-sectional view showing a wiring structure of a common pad area of ​​a semiconductor device according to an embodiment of the present application;

[0027] Figure 2 A schematic diagram showing a wiring structure of a semiconductor device of conventional technology;

[0028] Figure 3 A schematic diagram showing a wiring structure of a semiconductor device according to an embodiment of the present application is shown;

[0029] Figure 4 A schematic block diagram of a semiconductor device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] Based on at least one of the aforementioned technical problems, the present application provides a wiring structure of a pad area in a semiconductor device, the circuit comprising: the wiring structure comprises a common pad area; the wiring structure comprises at least a first line and a second line for connecting a first chip and a second chip; the first line and the second line both extend from the first chip to the inside of the common pad area, and then extend out of the pad area to connect with the second chip; the wiring structure also comprises a selection module, and the selection module selects to conduct the first line or the second line based on a preset integrated circuit wiring rule. In the wiring structure of the common pad area of ​​the semiconductor device of the embodiment of the present application, in the common pad area, the first line and the second line both extend from the first chip to the inside of the common pad area, and then extend out of the common pad area to connect with the second chip, and based on the preset integrated circuit wiring rule, the first line or the second line is selected to be conducted. This connection method can eliminate the residual in the line and improve the communication performance of the semiconductor device.

[0032] Figure 1 A schematic cross-sectional view showing a wiring structure of a pad area in a semiconductor device according to an embodiment of the present application; Figure 1 As shown, the wiring structure 100 of the pad area in the semiconductor device according to the embodiment of the present application may include a common pad area 107; the wiring structure 100 also includes at least a first line 101 and a second line 102 for connecting the first chip 103 and the second chip 104; the first line 101 and the second line 102 both extend from the first chip 103 to the inside of the common pad area 107, and then extend out of the common pad area 107 to connect with the second chip 104;

[0033] The wiring structure further includes a selection module, and the selection module selects to conduct the first line 101 or the second line 102 based on a preset integrated circuit wiring rule.

[0034] like Figure 2 , which is a schematic diagram of a wiring structure 200 of a semiconductor device of conventional technology. A central processing unit (CPU) has a plurality of ball pins. For example, a first ball pin supports the fifth generation high-speed serial computer expansion bus standard (Gen5 PCIE). A second ball pin supports the fourth generation high-speed serial computer expansion bus standard (Gen4 PCIE). Figure 2 The middle oblique line shaded part is the first line (the first line and the second line are both displayed as patterns on the pad), that is, the line that supports Gen5PCIE. Figure 2 The shaded part of the vertical line is the second line, which is the line that supports Gen4 PCIE. Whether the first line or the second line is used to transmit signals, a stub will be generated.

[0035] like Figure 3 , a schematic diagram of a wiring structure 300 of a semiconductor device according to an embodiment of the present application is shown. The central processing unit (CPU) has a plurality of ball pins. For example, the first ball pin supports the fifth generation high-speed serial computer expansion bus standard (Gen5 PCIE). The second ball pin supports the fourth generation high-speed serial computer expansion bus standard (Gen4 PCIE). Figure 3 The middle oblique line shaded part is the first line (the first line and the second line are both displayed as patterns on the pad), that is, the line that supports Gen5 PCIE. Figure 3 The shaded part of the middle vertical line is the second line, which is the line that supports Gen4PCIE. The first line and the second line are stacked and share the pad. Therefore, no matter whether the first line or the second line is used to transmit the signal, since the pads of the first line and the second line are overlapped, no stub will be generated.

[0036] In one embodiment of the present application, the common pad area 107 has two sides; the first chip 103 and / or the second chip 104 are both mounted on one side of the common pad area 107; the common pad area 107 is provided with at least one via, and the first line 101 and / or the second line 102 is connected to the second ball needle 106 of the second chip 104 through the at least one via.

[0037] In one embodiment of the present application, the first chip 103 and the second chip 104 are mounted on the first surface of the common pad area 107; the common pad area 107 is provided with a first via 108, a second via 109 and a third via 110;

[0038] One end of the circuit is connected to the first chip 103, extends to the inside of the common pad area 107 through the first via 108, and is divided into the first circuit 101 and the second circuit 102 at a predetermined position;

[0039] At the predetermined position, the first circuit 101 passes through the first surface of the common pad area 107 along the second via hole 109 and is connected to the first ball pin 105 of the second chip 104;

[0040] The second circuit 102 passes through the second surface of the common pad area 107 along the second via hole 109 , and then passes through the third via hole 110 to be connected to the second ball pin 106 of the second chip 104 .

[0041] In one embodiment of the present application, the first chip 103 is mounted on the first surface of the common pad area 107 , and the second chip 104 is mounted on the second surface of the common pad area 107 ; the common pad area 107 is provided with a first via 108 and a second via 109 .

[0042] One end of the circuit is connected to the first chip 103, extends to the inside of the common pad area 107 through the first via 108, and is divided into the first circuit 101 and the second circuit 102 at a predetermined position;

[0043] At the predetermined position, the first circuit 101 passes through the first surface of the common pad area 107 along the second via hole 109 and is connected to the first ball pin 105 of the second chip 104;

[0044] The second circuit 102 passes through the second surface of the common pad area 107 along the second via hole 109 and is connected to the second ball pin 106 of the second chip 104 .

[0045] In an embodiment of the present application, the first line 101 and the second line 102 support two different transmission rates.

[0046] For example, the first line 101 supports the fifth generation high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE). The second line 102 supports the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE).

[0047] In one embodiment of the present application, the preset integrated circuit wiring rule at least includes selecting the circuit with smaller resistance in the first circuit 101 and the second circuit 102. For example, the circuit resistance of the first circuit 101 is 0 ohm and / or the circuit resistance of the second circuit 102 is 0 ohm circuit. If the circuit resistance of the first circuit 101 is 0 ohm and the circuit resistance of the second circuit 102 is not 0 ohm, the first circuit 101 is selected to be turned on. If the circuit resistance of the second circuit 102 is 0 ohm and the circuit resistance of the first circuit 101 is not 0 ohm, the second circuit 102 is selected to be turned on. If the circuit resistance of the first circuit 101 and the second circuit 102 are both 0 ohms, the faster one of the two is selected, for example, the fifth generation PCIE circuit. Those skilled in the art can know that this is only used as an example to illustrate the present application. In actual implementation, it is also necessary to consider many factors to select conduction.

[0048] In one embodiment of the present application, the first chip 103 includes at least a memory (SSD, M.2) or a central processing unit (CPU); correspondingly, the second chip 104 includes at least a central processing unit (CPU) or a memory (SSD, M.2).

[0049] The wiring structure of the common pad area 107 of the semiconductor device of the embodiment of the present application is that in the common pad area 107, the first line 101 and the second line 102 both extend from the first chip 103 to the inside of the common pad area 107, and then extend out of the common pad area 107 to connect with the second chip 104, and based on the preset integrated circuit wiring rules, the first line 101 or the second line 102 is selected to be turned on. This connection method can eliminate residuals in the line and improve the communication performance of the semiconductor device.

[0050] Figure 4 Schematic block diagram of a semiconductor device according to an embodiment of the present application is shown. Figure 4 As shown, the semiconductor device 400 includes the wiring structure 100 of the pad region in the semiconductor device described above.

[0051] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0052] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0053] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various utility model aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features explicitly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with features that are less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0054] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0055] The above is only a specific implementation or description of a specific implementation of the present application, and the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A wiring structure of a common pad area of ​​a semiconductor device, It is characterized in that The wiring structure comprises: The wiring structure includes a common pad area; The wiring structure at least includes a first line and a second line for connecting the first chip and the second chip; the first line and the second line both extend from the first chip to the inside of the common pad area, and then extend out of the common pad area to connect with the second chip; The wiring structure further includes a selection module, and the selection module selects to conduct the first line or the second line based on a preset integrated circuit wiring rule.

2. The wiring structure according to claim 1, It is characterized in that The common pad area has two surfaces; the first chip and / or the second chip are mounted on one of the surfaces of the common pad area; the common pad area is provided with at least one via hole, and the first circuit and / or the second circuit passes through the at least one via hole to be connected to the second ball pin of the second chip.

3. The wiring structure according to claim 2, It is characterized in that The first chip and the second chip are mounted on the first surface of the common pad area; the common pad area is provided with a first via hole, a second via hole and a third via hole; One end of the circuit is connected to the first chip, extends to the inside of the common pad area through a first via hole, and is divided into the first circuit and the second circuit at a predetermined position; At the predetermined position, the first circuit passes through the first surface of the common pad area along the second via hole and is connected to the first ball pin of the second chip; The second circuit passes through the second surface of the common pad area along the second via hole, and then passes through the third via hole to be connected to the second ball pin of the second chip.

4. The wiring structure according to claim 2, It is characterized in that The first chip is mounted on the first surface of the common pad area, and the second chip is mounted on the second surface of the common pad area; the common pad area is provided with a first via hole and a second via hole; One end of the circuit is connected to the first chip, extends to the inside of the common pad area through the first via hole, and is divided into the first circuit and the second circuit at a predetermined position; At the predetermined position, the first circuit passes through the first surface of the common pad area along the second via hole and is connected to the first ball pin of the second chip; The second circuit passes through the second surface of the common pad area along the second via hole and is connected to the second ball pin of the second chip.

5. The wiring structure according to claim 1, It is characterized in that The first line and the second line support two different transmission rates.

6. The wiring structure according to claim 5, It is characterized in that The first line supports the fifth generation high-speed serial computer expansion bus standard; The second line supports a high speed serial computer expansion bus standard.

7. The wiring structure according to claim 1, It is characterized in that The preset integrated circuit wiring rule at least includes selecting a circuit with a smaller resistance between the first circuit and the second circuit.

8. The wiring structure according to claim 7, It is characterized in that The line resistance of the first line is 0 ohm and / or the line resistance of the second line is 0 ohm circuit.

9. The wiring structure according to claim 1, It is characterized in that The first chip at least includes a memory or a central processing unit; correspondingly, the second chip at least includes a central processing unit or a memory.

10. A semiconductor device, It is characterized in that The semiconductor device comprises the wiring structure of the common pad region of the semiconductor device according to any one of claims 1 to 9.

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