Debugging system of communication module
Through the combination of live-erase programmable read-only memory and dual-control switches, flexible configuration of power management integrated circuits is achieved, cumbersome problems of one-time burning and debugging are solved, and project progress and customer satisfaction are improved.
Patent Information
- Application Number
- CN202420984604.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-08
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2034-05-08
AI Technical Summary
The debugging of the power management integrated circuit with one-time burning is cumbersome, and the voltage and power-up and down sequence of the SOC cannot be flexibly adjusted, resulting in waste of costs and impact on project progress.
It uses live-erase programmable read-only memory to connect to the dual-control switch, and interacts with the microcontrol unit and communication module through the I2C bus, storing and reading configuration information and register operation instructions, so as to achieve rapid optimization and adjustment of output voltage and up-down timing.
It reduces the tedious steps of OTP work burning, speeds up project progress, and improves customer satisfaction.
Smart Images
Figure CN222232994U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of power supply debugging, and in particular to a debugging system for a communication module. Background Art
[0002] In the current environment of consumption and automotive electronics, with more and more peripheral modules, more and more complex functions, and higher and higher requirements for size and power consumption, PMI C (Power Management IC) has gradually become the power supply unit of mainstream SOC (System on Chip). Generally, PMI C needs to support burning of firmware with different configurations, such as default output voltage, power-on and power-off timing, etc., so OTP (one time program) came into being. In the platform hardware development and design stage, since the voltage and power-on and power-off timing required by SOC have not been fully finalized, they need to be continuously optimized and adjusted. Therefore, the debugging of PMI C for one-time burning is cumbersome and very inflexible. It is necessary to change the OTP configuration and let the factory burn and produce according to requirements, which wastes costs and manpower, and also affects the development progress of the entire project. Utility Model Content
[0003] The present application provides a debugging system for a communication module to solve the technical problem that debugging of a one-time burned power management integrated circuit is relatively complicated.
[0004] The present application provides a debugging system for a communication module, comprising: a powered erasable programmable read-only memory connected to one side of a double-control switch; a first contact on the other side of the double-control switch connected to a micro-control unit, and a second contact on the other side of the double-control switch connected to a communication module; the powered erasable programmable read-only memory forms a closed circuit with one of the micro-control unit or the communication module by turning on and off the contacts of the double-control switch.
[0005] As an optional example, the communication module includes a SOC chip and a PMI C chip, and the PMI C chip is connected to the SOC chip and powers on the SOC chip according to the configuration information.
[0006] As an optional example, the system further includes: an I2C bus, the electrically erasable programmable read-only memory is connected to one side of the dual-control switch via the I2C bus; the first contact on the other side of the dual-control switch is connected to the microcontroller unit via the I2C bus, and the second contact on the other side of the dual-control switch is connected to the communication module via the I2C bus.
[0007] As an optional example, when the first contact on the other side of the above-mentioned double-control switch is closed and the second contact is opened, the above-mentioned microcontroller unit is the master device of the above-mentioned I2C bus, the above-mentioned electrically erasable programmable read-only memory is the slave device of the above-mentioned I2C bus, and the above-mentioned microcontroller unit burns the configuration information into the above-mentioned electrically erasable programmable read-only memory.
[0008] As an optional example, when the first contact on the other side of the double-control switch is disconnected and the second contact is closed, the communication module is the master device of the I2C bus, the electrically erasable programmable read-only memory is the slave device of the I2C bus, the communication module reads configuration information from the electrically erasable programmable read-only memory, and the PMI C chip powers on the SOC chip according to the configuration information.
[0009] As an optional example, the system further includes: a power supply module, a first end of the power supply module is connected to the electrically erasable programmable read-only memory, and the other end of the power supply module is respectively connected to the micro control unit and the PMIC chip.
[0010] As an optional example, the system further includes: a low voltage dropout linear regulator, wherein the low voltage dropout linear regulator is located between the first end of the power supply module and the electrically erasable programmable read-only memory.
[0011] As an optional example, one end of the low voltage dropout linear regulator connected to the electrically erasable programmable read-only memory is also connected to the micro control unit.
[0012] As an optional example, when the first contact on the other side of the double-control switch is closed and the second contact is disconnected, the low-voltage dropout linear regulator is located in a closed circuit where the microcontrol unit and the electrically erasable programmable read-only memory are located; when the first contact on the other side of the double-control switch is disconnected and the second contact is closed, the low-voltage dropout linear regulator is located in a closed circuit where the PMI C chip and the electrically erasable programmable read-only memory are located.
[0013] As an optional example, the system further includes: a host computer, which is connected to the micro control unit via an asynchronous receiver-transmitter or a universal serial bus.
[0014] In the embodiment of the present application, a powered erasable programmable read-only memory is used and connected to one side of a double-control switch; a first contact on the other side of the above-mentioned double-control switch is connected to a micro-control unit, and a second contact on the above-mentioned other side of the above-mentioned double-control switch is connected to a communication module; the above-mentioned powered erasable programmable read-only memory forms a closed circuit system with the above-mentioned micro-control unit or one of the above-mentioned communication modules through the on-off of the contacts of the above-mentioned double-control switch. In the above-mentioned system, based on a general low-speed micro-control unit, relying on the powered erasable programmable read-only memory, the burning information and register operation instructions that need to be flexibly configured are stored in the powered erasable programmable read-only memory, so as to achieve the effect of quickly optimizing and adjusting the output voltage and the power-on and power-off timing of the communication module, thereby reducing the cumbersome steps such as the work burning required by the existing OTP, accelerating the project progress, and improving the purpose of customer satisfaction, thereby solving the technical problem that the debugging of the communication module with one-time burning is relatively cumbersome. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0017] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.
[0018] Figure 1 is a structural diagram of a debugging system of an optional communication module according to an embodiment of the present application;
[0019] Figure 2 It is an overall circuit structure diagram of a debugging system of an optional communication module according to an embodiment of the present application. DETAILED DESCRIPTION
[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0021] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.
[0022] According to a first aspect of an embodiment of the present application, a debugging system for a communication module is provided. Optionally, as Figure 1 As shown, the above system includes:
[0023] A powered erasable programmable read-only memory 102 is connected to one side of the double-control switch;
[0024] The first contact on the other side of the double-control switch is connected to the micro-control unit 104, and the second contact on the other side of the double-control switch is connected to the communication module 106;
[0025] The electrically erasable programmable read-only memory 102 forms a closed circuit with the micro control unit 104 or the communication module 106 through the on and off of the contacts of the double-control switch.
[0026] Optionally, in this embodiment, the microcontroller unit MCU is also called a single-chip microcomputer. The electrically erasable programmable read-only memory EEPROM is a storage chip in which data is not lost after power failure.
[0027] Optionally, in this embodiment, if Figure 2As shown in the overall circuit structure diagram, the first end of the electrically erasable programmable read-only memory EEPROM is connected to the first side of the double-control switch switch, the first end of the micro-control unit MCU is connected to the first end of the second side of the double-control switch switch, and the first end of the power management integrated circuit PMIC chip of the communication module is connected to the second end of the second side of the double-control switch switch. Through the on-off of the contacts of the double-control switch switch, the electrically erasable programmable read-only memory EEPROM and the micro-control unit MCU or the power management integrated circuit PMIC chip of the communication module are controlled to form a closed circuit. When the double-control switch switch contacts the first contact point A, the first end of the electrically erasable programmable read-only memory EEPROM is connected to the first end of the micro-control unit MCU, and the second end of the micro-control unit MCU is connected to the second end of the electrically erasable programmable read-only memory EEPROM. The electrically erasable programmable read-only memory EEPROM and the micro-control unit MCU form a closed circuit, and the micro-control unit MCU stores the power-on and power-off timing, voltage and other related configuration information and register operation instructions required for configuring the system-level chip SOC in the electrically erasable programmable read-only memory EEPROM. When the double-control switch switch contacts the second contact point B, the first end of the power management integrated circuit PMIC chip of the communication module is connected to the first end of the electrically erasable programmable read-only memory EEPROM, the electrically erasable programmable read-only memory EEPROM and the power management integrated circuit PMIC chip of the communication module form a closed circuit, and the power management integrated circuit PMIC chip of the communication module reads relevant configuration information and register operation instructions from the electrically erasable programmable read-only memory EEPROM and completes power-on.
[0028] Optionally, in this embodiment, based on a general low-speed microcontroller unit MCU, relying on an electrically erasable programmable read-only memory EEPROM, the relevant configuration information and register operation instructions that need to be flexibly configured are stored in the electrically erasable programmable read-only memory EEPROM, so as to achieve the effect of quickly optimizing and adjusting the output voltage and power-on and power-off timing of the power management integrated circuit PMIC chip of the communication module, thereby reducing the cumbersome steps such as the work burning required by the existing OTP, speeding up the project progress, and improving customer satisfaction, thereby solving the technical problem of the cumbersome debugging of the communication module that is burned once.
[0029] As an optional example, the communication module includes a SOC chip and a PMI C chip, and the PMI C chip is connected to the SOC chip and powers on the SOC chip according to the configuration information.
[0030] Optionally, in this embodiment, the power management integrated circuit PMI C (Power Management IC) is used to manage the power supply device in the host system, and is commonly used in mobile phones and various mobile terminal devices. System on chip SOC (System on Chip) is an integrated circuit with a dedicated purpose, which contains all the contents of the complete system and embedded software. Figure 2 As shown in the overall circuit structure diagram, the system-on-chip SOC is connected to the first end of the power management integrated circuit PMI C. After the power management integrated circuit PMI C reads the relevant configuration information and register operation instructions from the electrically erasable programmable read-only memory EEPROM and completes power-on, the system-on-chip SOC starts to run.
[0031] As an optional example, the above system further includes:
[0032] The electrically erasable programmable read-only memory is connected to one side of the double-control switch through the I2C bus; the first contact on the other side of the double-control switch is connected to the microcontrol unit through the I2C bus, and the second contact on the other side of the double-control switch is connected to the communication module through the I2C bus.
[0033] As an optional example, when the first contact on the other side of the double-control switch is closed and the second contact is open, the microcontroller unit is the master device of the I2C bus, the electrically erasable programmable read-only memory is the slave device of the I2C bus, and the microcontroller unit burns the configuration information into the electrically erasable programmable read-only memory.
[0034] As an optional example, when the first contact on the other side of the double-control switch is disconnected and the second contact is closed, the communication module is the master device of the I2C bus, the electrically erasable programmable read-only memory is the slave device of the I2C bus, the communication module reads configuration information from the electrically erasable programmable read-only memory, and the PMI C chip powers on the SOC chip according to the configuration information.
[0035] Optionally, in this embodiment, the I2C bus, i.e., the communication bus I2C, is a simple, bidirectional two-wire synchronous serial bus. It only needs two wires to transmit information between devices connected to the bus. The master device is used to start the bus to transmit data and generate a clock to open the device to be transmitted. At this time, any addressed device is considered to be a slave device. The relationship between the master and the slave, the send and receive on the bus is not constant, but depends on the data transmission direction at this time. If the master device wants to send data to the slave device, the master device first addresses the slave device, then actively sends data to the slave device, and finally the master device terminates the data transmission; if the master device wants to receive data from the slave device, the master device first addresses the slave device, then the master device receives the data sent by the slave device, and finally the master device terminates the receiving process. In this case, the master device is responsible for generating a timing clock and terminating data transmission.
[0036] Optionally, in this embodiment, if Figure 2 As shown in the overall circuit structure diagram, the microcontroller unit MCU, the electrically erasable programmable read-only memory EEPROM and the power management integrated circuit PM IC are connected through the communication bus I 2C. Specifically, when the double-control switch switch of the communication bus I 2C contacts the first contact point A of the communication bus I 2C, the first end of the electrically erasable programmable read-only memory EEPROM is connected to the first end of the microcontroller unit MCU through the communication bus I 2C. The microcontroller unit MCU is the master device of the communication bus I 2C, and the electrically erasable programmable read-only memory EEPROM is the slave device of the communication bus I 2C. The microcontroller unit MCU stores the power-on and power-off timing, voltage and other related configuration information and register operation instructions required for configuring the system-level chip SOC in the electrically erasable programmable read-only memory EEPROM through the communication bus I 2C. When the switch switch of the communication bus I 2C contacts the second contact point B of the communication bus I 2C, the first end of the electrically erasable programmable read-only memory EEPROM is connected to the first end of the power management integrated circuit PM IC through the communication bus I 2C. The system-on-chip SOC is the master device of the communication bus I2C, the electrically erasable programmable read-only memory EEPROM is the slave device of the communication bus I2C, and the power management integrated circuit PMIC reads relevant configuration information and register operation instructions from the electrically erasable programmable read-only memory EEPROM through the communication bus I2C and completes power-on.
[0037] As an optional example, the above system further includes:
[0038] A power supply module, wherein a first end of the power supply module is connected to the electrically erasable programmable read-only memory, and the other end of the power supply module is respectively connected to the micro control unit and the PM IC chip.
[0039] As an optional example, the above system further includes:
[0040] A low voltage dropout linear regulator is located between the first end of the power supply module and the electrically erasable programmable read-only memory.
[0041] As an optional example, one end of the low voltage dropout linear regulator connected to the electrically erasable programmable read-only memory is also connected to the micro control unit.
[0042] As an optional example, when the first contact on the other side of the double-control switch is closed and the second contact is open, the low-voltage dropout linear regulator is located in a closed circuit where the microcontroller unit and the electrically erasable programmable read-only memory are located; when the first contact on the other side of the double-control switch is open and the second contact is closed, the low-voltage dropout linear regulator is located in a closed circuit where the PM IC chip and the electrically erasable programmable read-only memory are located.
[0043] Optionally, in this embodiment, if Figure 2 As shown in the overall circuit structure diagram, the power supply module includes a main power supply VBAT and a low voltage drop linear regulator LDO. The main power supply VBAT is connected to the third end of the microcontroller unit MCU and the second end of the power management integrated circuit PM IC to meet the power supply of the third end of the microcontroller unit MCU and the power management integrated circuit PM IC. The first end of the low voltage drop linear regulator LDO is connected to the main power supply VBAT, and the second end of the low voltage drop linear regulator LDO is connected to the second end of the electrically erasable programmable read-only memory EEPROM to convert the voltage of the main power supply VBAT to achieve 5V to 3.3V to meet the power supply of the electrically erasable programmable read-only memory EEPROM. When the double-control switch switch contacts the first contact point A, the first end of the electrically erasable programmable read-only memory EEPROM is connected to the first end of the microcontrol unit MCU, the second end of the microcontrol unit MCU is connected to the second end of the electrically erasable programmable read-only memory EEPROM, the electrically erasable programmable read-only memory EEPROM and the microcontrol unit MCU form a closed circuit, and the low-voltage dropout linear regulator LDO is located in the closed circuit where the microcontrol unit MCU and the electrically erasable programmable read-only memory EEPROM are located. When the double-control switch switch contacts the second contact point B, the first end of the power management integrated circuit PM IC is connected to the first end of the electrically erasable programmable read-only memory EEPROM, the electrically erasable programmable read-only memory EEPROM and the power management integrated circuit PM IC form a closed circuit, and the low-voltage dropout linear regulator LDO is located in the closed circuit where the power management integrated circuit PM IC and the electrically erasable programmable read-only memory EEPROM are located.
[0044] As an optional example, the above system further includes:
[0045] The host computer is connected to the microcontroller unit via an asynchronous receiver-transmitter or a universal serial bus.
[0046] Optionally, in this embodiment, the host computer PC (personal computer) refers to a multi-purpose computer whose size, price and performance are suitable for personal use. Figure 2 As shown in the overall circuit structure diagram, the host computer PC is connected to the microcontroller unit MCU through the asynchronous receiver-transmitter UART or the universal serial bus USB. The host computer PC and the microcontroller unit MCU exchange information through the asynchronous receiver-transmitter UART or the universal serial bus USB. Through the friendly user configuration interface of the host computer, the power-on and power-off timing, voltage and other related configuration information and register operation instructions required by the system-level chip SOC can be flexibly and conveniently configured.
[0047] It should be noted that, for the sake of simplicity, the aforementioned system embodiments are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.
Claims
1. A debugging system for a communication module, characterized in that: include: A powered erasable programmable read-only memory is connected to one side of the double-control switch; The first contact on the other side of the double-control switch is connected to the micro-control unit, and the second contact on the other side of the double-control switch is connected to the communication module; The electrically erasable programmable read-only memory forms a closed circuit with the micro control unit or the communication module through the on-off of the contacts of the double-control switch.
2. The system according to claim 1, characterized in that The communication module includes a SOC chip and a PMIC chip. The PMIC chip is connected to the SOC chip and powers on the SOC chip according to configuration information.
3. The system according to claim 2, characterized in that The system further comprises: An I2C bus, the electrically erasable programmable read-only memory is connected to one side of the double-control switch through the I2C bus; a first contact on the other side of the double-control switch is connected to the microcontroller unit through the I2C bus, and a second contact on the other side of the double-control switch is connected to the communication module through the I2C bus.
4. The system according to claim 3, characterized in that When the first contact on the other side of the double-control switch is closed and the second contact is open, the microcontroller unit is the master device of the I2C bus, the electrically erasable programmable read-only memory is the slave device of the I2C bus, and the microcontroller unit burns configuration information into the electrically erasable programmable read-only memory.
5. The system according to claim 3, characterized in that When the first contact on the other side of the double-control switch is disconnected and the second contact is closed, the communication module is the master device of the I2C bus, the electrically erasable programmable read-only memory is the slave device of the I2C bus, the communication module reads configuration information from the electrically erasable programmable read-only memory, and the PMIC chip powers on the SOC chip according to the configuration information.
6. The system according to claim 2, characterized in that The system further comprises: A power supply module, wherein a first end of the power supply module is connected to the electrically erasable programmable read-only memory, and the other end of the power supply module is respectively connected to the micro control unit and the PMIC chip.
7. The system according to claim 6, characterized in that The system further comprises: A low voltage dropout linear regulator is located between the first end of the power supply module and the electrically erasable programmable read-only memory.
8. The system according to claim 7, characterized in that One end of the low voltage difference linear regulator connected to the electrically erasable programmable read-only memory is also connected to the micro control unit.
9. The system according to claim 8, characterized in that When the first contact on the other side of the double-control switch is closed and the second contact is disconnected, the low-voltage dropout linear regulator is located in a closed circuit where the microcontrol unit and the electrically erasable programmable read-only memory are located; when the first contact on the other side of the double-control switch is disconnected and the second contact is closed, the low-voltage dropout linear regulator is located in a closed circuit where the PMIC chip and the electrically erasable programmable read-only memory are located.
10. The system according to any one of claims 1 to 9, characterized in that: The system further comprises: a host computer, which is connected to the micro control unit via an asynchronous receiver-transmitter or a universal serial bus.