Semiconductor device
By designing semiconductor layers and electrodes with different doping types in semiconductor devices, forming a PN junction structure in reverse parallel, combining LED epitaxial structure and ESD protection structure, the breakdown problem caused by electrostatic discharge is solved, and the static electricity is achieved. Effective protection to ensure device stability and function.
Patent Information
- Application Number
- CN202323497117.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-19
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2033-12-19
AI Technical Summary
Existing semiconductor devices are easily broken down during electrostatic discharge, resulting in damage or failure. In particular, the light emitting diodes are very sensitive to static electricity, and are prone to instantaneous discharge and temperature increase, resulting in leakage and short circuit problems.
A semiconductor device is designed, including semiconductor layers and electrodes with different doping types, forming a PN junction structure in reverse parallel, through the combination of a first structure (LED epitaxial structure) and a second structure (ESD protection structure) and using The difference in doping type plays a protective role in electrostatic discharge to avoid breakdown by reverse current or voltage.
During electrostatic discharge, semiconductor devices can effectively avoid breakdown, ensure the stability and function of the device, prevent damage caused by electrostatic discharge, and improve the protection performance of static electricity.
Smart Images
Figure CN222233639U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor device. Background Art
[0002] Electrostatic discharge (ESD) refers to the transfer of charge caused by objects with different electrostatic potentials approaching or directly contacting each other. Generally speaking, the human body, machines for packaging integrated circuits, instruments for testing integrated circuits, etc. are common charged objects. When a charged object comes into contact with a chip or wafer, the charged object will discharge to the chip or wafer. The instantaneous power of electrostatic discharge may cause damage or failure of the integrated circuit in the chip or wafer. Utility Model Content
[0003] In view of this, an embodiment of the utility model provides a semiconductor device that will not be broken down when subjected to forward and reverse electrostatic discharge.
[0004] An embodiment of the utility model provides a semiconductor device, which includes: a substrate; a first structure formed on the substrate, the first structure including a first semiconductor layer and a second semiconductor layer stacked in sequence from bottom to top; a second structure formed above the first structure, the second structure including a third semiconductor layer and a fourth semiconductor layer stacked in sequence from bottom to top; a first electrode electrically connected to the first semiconductor layer and the third semiconductor layer, respectively; a second electrode electrically connected to the second semiconductor layer and the fourth semiconductor layer, respectively; a bonding layer arranged between the first structure and the second structure; wherein the first semiconductor layer and the fourth semiconductor layer have a first doping type, the second semiconductor layer and the third semiconductor layer have a second doping type, and the first doping type and the second doping type are opposite.
[0005] Further, the first semiconductor layer includes a first ohmic contact layer, a first window layer and a first confinement layer stacked in sequence from bottom to top, and the first electrode is electrically connected to the first ohmic contact layer; the second semiconductor layer includes a second confinement layer and a second ohmic contact layer stacked in sequence from bottom to top, and the second electrode is electrically connected to the second ohmic contact layer; the third semiconductor layer includes a third ohmic contact layer and a third confinement layer stacked in sequence from bottom to top, and the first electrode is electrically connected to the third ohmic contact layer; the fourth semiconductor layer includes a fourth confinement layer, a fourth window layer and a fourth ohmic contact layer stacked in sequence from bottom to top, and the second electrode is electrically connected to the fourth ohmic contact layer.
[0006] Further, the first structure further includes a first active layer formed between the first semiconductor layer and the second semiconductor layer; and / or, the second structure further includes a second active layer formed between the third semiconductor layer and the fourth semiconductor layer.
[0007] Further, the semiconductor device includes a first step, the lower step surface of the first step is the second step surface located in the first semiconductor layer, and the upper step surface of the first step is the first step surface located in the third semiconductor layer; the bottom of the first electrode is arranged on the second step surface, and the top portion of the first electrode covers the first step surface. The semiconductor device includes a first dielectric layer arranged on the second step surface, one side of the first dielectric layer covers the side wall of the first step, and the first electrode is arranged on the other side of the first dielectric layer.
[0008] Furthermore, the semiconductor device also includes a second step, the lower step surface of the second step is a fourth step surface located on the second semiconductor layer, and the upper step surface of the second step is a third step surface located on the fourth semiconductor layer; the bottom of the second electrode is arranged on the fourth step surface, and the top portion of the second electrode covers the third step surface. The semiconductor device also includes a second dielectric layer arranged on the fourth step surface, one side of the second dielectric layer covers the side wall of the second step, and the second electrode is arranged on the other side of the second dielectric layer.
[0009] Furthermore, the semiconductor device also includes a third step, the lower step surface of the third step is the first step surface located in the third semiconductor layer, and the upper step surface of the third step is the third step surface located in the fourth semiconductor layer; the semiconductor device also includes a fifth dielectric layer arranged on the first step surface, and the fifth dielectric layer covers the side wall of the third step, the first step surface not covered by the first electrode and the second electrode, and the third step surface.
[0010] Furthermore, the semiconductor device also includes a third dielectric layer partially covering the first electrode and a fourth dielectric layer partially covering the second electrode. The third dielectric layer is arranged on a side of the first electrode away from the first dielectric layer, and the fourth dielectric layer is arranged on a side of the second electrode away from the second dielectric layer.
[0011] Furthermore, the semiconductor device also includes a third electrode electrically connected to the first electrode and a fourth electrode electrically connected to the second electrode, the third dielectric layer and the fifth dielectric layer surround a first opening, the third electrode extends into the first opening and is connected to the first electrode; the fourth dielectric layer and the fifth dielectric layer surround a second opening, the fourth electrode extends into the second opening and is connected to the second electrode.
[0012] Furthermore, the semiconductor device includes a plurality of first electrodes and a second electrode, the plurality of first electrodes are arranged around the second electrode, the first electrodes are all arranged in the first structure and the second structure, the second electrode is partially arranged in the first structure and the second structure, and another part of the second electrode is arranged on a side of the second structure away from the first structure; the semiconductor device also includes a bottom electrode arranged on a side of the substrate away from the first structure, and the bottom electrode is electrically connected to the first semiconductor layer, the first electrode and the third semiconductor layer through the substrate.
[0013] Furthermore, the semiconductor device also includes a first through hole, a second through hole and a third through hole; the first through hole penetrates the fourth semiconductor layer and a portion of the third semiconductor layer; the second through hole penetrates the remaining third semiconductor layer, the bonding layer, the second semiconductor layer and a portion of the first semiconductor layer from the bottom of the first through hole, the second through hole is connected to the first through hole, the diameter of the first through hole is greater than the diameter of the second through hole, and the first through hole and the second through hole are concentrically arranged; the first dielectric layer is located on the side walls of the first through hole and the second through hole, the first electrode is located in the first through hole and the second through hole to be electrically connected to the third semiconductor layer and the first semiconductor layer, and the first dielectric layer also covers the top surface of the first electrode; the second dielectric layer is located on the side walls of the third through hole, the second electrode is located in the third through hole and extends to cover a portion of the surface of the fourth semiconductor layer to be electrically connected to the second semiconductor layer and the fourth semiconductor layer.
[0014] Furthermore, the first structure is an electrostatic discharge protection structure, and the second structure is a light-emitting diode epitaxial structure or a common diode; or, the first structure is a light-emitting diode epitaxial structure or a common diode, and the second structure is an electrostatic discharge protection structure.
[0015] The embodiment of the utility model discloses a semiconductor device. The semiconductor device includes a substrate, a first structure, a second structure, a first electrode, and a second electrode. The first structure includes a first semiconductor layer with a first doping type and a second semiconductor layer with a second doping type, and the second structure includes a fourth semiconductor layer with the first doping type and a third semiconductor layer with the second doping type. The first electrode and the second electrode connect the first structure and the second structure in reverse parallel, so that the semiconductor device has two PN junctions connected in parallel in opposite directions. The semiconductor device of the embodiment of the utility model will not be broken down by reverse current or voltage when electrostatic discharge occurs through the above structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0017] Figure 1 is a cross-sectional view of a semiconductor device of a front-mounted structure provided in Embodiment 1 of the present utility model;
[0018] Figure 2 is a cross-sectional view of a semiconductor device with a flip-chip structure provided in the second embodiment of the present utility model;
[0019] Figure 3 This is a flow chart of a method for forming a semiconductor device with a positive structure provided in the first embodiment of the utility model;
[0020] Figure 4-Figure 8 It is a cross-sectional view of a semiconductor device of a front-mounted structure at different stages provided by the first embodiment of the utility model;
[0021] Fig. 9 is a cross-sectional view of a semiconductor device with an incompletely formed flip-chip structure provided in the second embodiment of the present utility model;
[0022] Fig.10 is a top view of a vertically structured semiconductor device provided in Embodiment 3 of the present utility model;
[0023] Fig.11 It is a partial cross-sectional view of the vertical structure semiconductor device provided by the third embodiment of the present utility model at AA;
[0024] Fig.12 It is a cross-sectional view taken at BB of a vertically structured semiconductor device provided in the third embodiment of the present invention.
[0025] Description of reference numerals:
[0026] 100-substrate;
[0027] 200-first structure; 210-first semiconductor layer; 211-first ohmic contact layer; 212-first window layer; 213-first confinement layer; 220-first active layer; 230-second semiconductor layer; 231-second confinement layer; 232-second ohmic contact layer;
[0028] 300-bonding layer;
[0029] 400-second structure; 410-third semiconductor layer; 411-third ohmic contact layer; 412-third confinement layer; 420-second active layer; 430-fourth semiconductor layer; 431-fourth confinement layer; 432-fourth window layer; 433-fourth ohmic contact layer;
[0030] 500 - first electrode; 510 - bottom electrode; 600 - second electrode; 710 - third electrode; 720 - fourth electrode;
[0031] 801 - first dielectric layer; 802 - second dielectric layer; 803 - third dielectric layer; 804 - fourth dielectric layer; 805 - fifth dielectric layer; 806 - sixth dielectric layer; 810 - first opening; 820 - second opening;
[0032] 910 - first step surface; 920 - second step surface; 930 - third step surface; 940 - fourth step surface. DETAILED DESCRIPTION
[0033] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for those skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, flows, components and circuits are not described in detail.
[0034] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.
[0035] For ease of explanation, spatially relative terms such as "inside", "outside", "below", "below", "lower", "above", "upper", etc. are used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. It will be understood that spatially relative terms may be intended to include different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figure is turned over, an element described as being "below" or "below" other elements or features will then be positioned as being "above" the other elements or features. Thus, the example term "below" can include both the orientations of above and below. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.
[0036] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".
[0037] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.
[0038] In the embodiment of the utility model, the semiconductor device is described by taking LED (Light Emitting Diode) as an example, so the semiconductor device includes at least one PN junction that can emit light, that is, the semiconductor device includes at least one LED structure. It is easy to understand that the semiconductor device can also be other devices that are prone to electrostatic discharge, and the PN junctions in the device may not emit light, that is, the semiconductor device may not include an LED structure.
[0039] Since LEDs are very sensitive to static electricity, ESD protection is an important indicator of LEDs. When the static voltage between electrodes is too high, instantaneous discharge occurs between the positive and negative electrodes, and the temperature inside the LED is higher than the junction temperature. The high temperature causes local melting into small holes, which causes LED leakage, damage to the light-emitting structure, short circuit, etc., causing permanent damage to the LED.
[0040] Figure 1 1 is a cross-sectional view of a semiconductor device of a vertical structure provided in the first embodiment of the present invention. Figure 1 In the cross-sectional view shown, the semiconductor device includes: a substrate 100, a first structure 200, a second structure 400, a first electrode 500 and a second electrode 600. The first structure 200 and the second structure 400 are stacked on the substrate 100 from bottom to top. The first structure 200 includes a first semiconductor layer 210, a first active layer 220 and a second semiconductor layer 230 stacked from bottom to top, and the second structure 400 includes a third semiconductor layer 410, a second active layer 420 and a fourth semiconductor layer 430 stacked from bottom to top. The first electrode 500 is electrically connected to the first semiconductor layer 210 and the third semiconductor layer 410, respectively, and the second electrode 600 is electrically connected to the second semiconductor layer 230 and the fourth semiconductor layer 430, respectively, so that the first structure 200 is in reverse parallel with the second structure 400.
[0041] Specifically, the first semiconductor layer 210 includes but is not limited to a first ohmic contact layer 211, a first window layer 212, and a first confinement layer 213 stacked sequentially from bottom to top, and the first electrode 500 is electrically connected to the first ohmic contact layer 211. The second semiconductor layer 220 includes but is not limited to a second confinement layer 231 and a second ohmic contact layer 232 stacked sequentially from bottom to top, and the second electrode 600 is electrically connected to the second ohmic contact layer 232. The third semiconductor layer 410 includes but is not limited to a third ohmic contact layer 411 and a third confinement layer 412 stacked sequentially from bottom to top, and the first electrode 500 is electrically connected to the third ohmic contact layer 411. The fourth semiconductor layer 430 includes but is not limited to a fourth confinement layer 431, a fourth window layer 432, and a fourth ohmic contact layer 433 stacked sequentially from bottom to top, and the second electrode 600 is electrically connected to the fourth ohmic contact layer 433.
[0042] In this embodiment, the first structure 200 is a light emitting diode (LED) epitaxial structure, and the second structure 400 is an electrostatic discharge (ESD) protection structure. In the first structure 200, the first semiconductor layer 210 has a first doping type, and the second semiconductor layer 230 has a second doping type. Among them, the first doping type is one of N-type and P-type doping, and the second doping type is one of P-type and N-type doping, and the first doping type and the second doping type are different. In this embodiment, the first doping type is N-type doping, which is to dope Si, Ge, Sn and other N-type dopants in the semiconductor layer; the second doping type is P-type doping, which is to dope C, Mg, Zn, Ca, Sr, Ba and other P-type dopants in the substrate. The first active layer 220 is a multi-quantum well. In the second structure 400, the third semiconductor layer 410 has the second doping type, and the fourth semiconductor layer 430 has the first doping type. Among them, the first doping type is one of N-type and P-type doping, the second doping type is one of P-type and N-type doping, and the first doping type and the second doping type are different. In this embodiment, the first doping type is N-type doping, which is to dope Si, Ge, Sn and other N-type dopants in the substrate; the second doping type is P-type doping, which is to dope C, Mg, Zn, Ca, Sr, Ba and other P-type dopants in the substrate. The second active layer 420 is also a multi-quantum well. When the semiconductor device is driven by current or voltage, and the second electrode 600 side is a forward voltage, the LED epitaxial structure is forward-conducted, the ESD protection structure is not conductive, and the electrons and holes recombine in the first active layer 220 and radiate energy outward in the form of photons to emit light, and the radiation wavelength is, for example, 190nm-960nm. The semiconductor device emits light from the front side (that is, the side away from the substrate 100).
[0043] When the semiconductor device is driven by current or voltage and the first electrode 500 has a forward voltage, the LED epitaxial structure is not turned on, the ESD protection structure is turned on and protects the LED epitaxial structure, and the semiconductor device emits light or does not emit light.
[0044] In addition, the first active layer 220 of the first structure 200 as an LED epitaxial structure can also be a single quantum well, a double quantum well, a single quantum wire or an organic material, so that the first structure 200 constitutes an LED structure. The second active layer 420 in the second structure 400 as an ESD protection structure can be a structure such as an avalanche region, a Schottky junction, etc., so that the second structure 400 constitutes a structure such as an avalanche diode, a Schottky diode, etc. When one side of the first electrode 500 is a forward voltage, the second structure 400 is turned on and consumes electrical energy without emitting light. In addition, the second active layer 420 may not be provided in the second structure 400, so that the second structure 400 is an ordinary diode that consumes electrical energy when turned on.
[0045] In some embodiments, the first structure 200 is an ESD protection structure, and the second structure 400 is an LED epitaxial structure. In this embodiment, the first active region 200 in the first structure 200 as an ESD protection structure can be a multi-quantum well, an avalanche region, a Schottky junction, etc., so that the first structure 200 is a light-emitting diode, an avalanche diode, a Schottky diode, etc. The first active region 200 may not be provided in the first structure 200, so that the first structure 200 is a common diode. The second active layer 420 of the second structure 400 as an LED epitaxial structure can be a multi-quantum well, a single quantum well, a double quantum well, a single quantum wire or an organic material, so that the second structure 400 constitutes a light-emitting diode, and the radiation wavelength of the light-emitting diode is 190nm-960nm.
[0046] Preferably, when the semiconductor device is a face-up structure, the first structure 200 is an ESD protection structure, and the second structure 400 farther from the substrate 100 is an LED epitaxial structure. Thus, when the LED epitaxial structure emits light, the ESD protection structure will not block the light emitted from the LED epitaxial structure from a direction away from the substrate 100, and the light emission effect of the semiconductor device is better. When the semiconductor device is a flip-chip structure, the first structure 200 closer to the substrate 100 is an LED epitaxial structure, and the second structure 400 is an ESD protection structure. Thus, when the LED epitaxial structure emits light, the ESD protection structure will not block the light emitted from the LED epitaxial structure from one side of the substrate 100, and the light emission effect of the semiconductor device is better.
[0047] like Figure 1As shown, the semiconductor device includes a first step. The first step has a second step surface 920 as a lower step surface, and the second step surface 920 is the surface of the first semiconductor layer 210 (first ohmic contact layer 211); the first step has a first step surface 910 as an upper step surface, and the first step surface 910 is the surface of the third semiconductor layer 410 (third ohmic contact layer 411). The bottom of the first electrode 500 is arranged on the second step surface 920, and the top part of the first electrode 500 covers the first step surface 910, so that the first electrode 500 is electrically connected to the first semiconductor layer 210 (first ohmic contact layer 211) and the third semiconductor layer 410 (third ohmic contact layer 411) respectively. A first dielectric layer 801 is also arranged on the first step, and the bottom of the first dielectric layer 801 is arranged on the second step surface 920, and the first dielectric layer 801 covers the side wall of the first step. That is, the first dielectric layer 801 covers the third ohmic contact layer 411, the bonding layer 300, the second ohmic contact layer 232, the second limiting layer 231, the first active layer 220, the first limiting layer 213, the first window layer 212 and the first ohmic contact layer 211, so that the first electrode 500 does not contact the above-mentioned structure of the side wall of the first step. The semiconductor device also includes a third dielectric layer 803, the bottom of the third dielectric layer 803 is arranged on the substrate 100, and the side wall of the third dielectric layer 803 covers the side of the first electrode 500 away from the first structure 200, so as to protect the first electrode 500. That is, the first dielectric layer 801 is located on the side of the first electrode 500 close to the first step, and the third dielectric layer 803 is located on the side of the first electrode 500 away from the first step.
[0048] The semiconductor device further includes a second step. The second step has a fourth step surface 940 as a lower step surface, and the fourth step surface 940 is the surface of the second semiconductor layer 230 (the second ohmic contact layer 232); the second step has a third step surface 930 as an upper step surface, and the third step surface 930 is the surface of the fourth semiconductor layer 430 (the fourth ohmic contact layer 433). The bottom of the second electrode 600 is arranged on the fourth step surface 940, and the top portion of the second electrode 600 covers the third step surface 930, so that the second electrode 600 is electrically connected to the second semiconductor layer 230 (the second ohmic contact layer 232) and the fourth semiconductor layer 430 (the fourth ohmic contact layer 433), respectively. A second dielectric layer 802 is also arranged on the second step, and the second dielectric layer 802 covers the sidewall of the second step. That is, the second dielectric layer 802 covers the fourth window layer 432, the fourth limiting layer 431, the second active layer 420, the third limiting layer 412, the third ohmic contact layer 411, the bonding layer 300 and the second ohmic contact layer 232, so that the second electrode 600 does not contact the above-mentioned structure of the side wall of the second step. The semiconductor device also includes a fourth dielectric layer 804, the bottom of the fourth dielectric layer 804 is arranged on the substrate 100, and the side wall of the fourth dielectric layer 804 covers the side of the second electrode 600 away from the second structure 400, so as to protect the second electrode 600. That is, the second dielectric layer 802 is located on the side of the second electrode 600 close to the second step, and the fourth dielectric layer 804 is located on the side of the second electrode 600 away from the second step.
[0049] The semiconductor device further includes a third step. The third step has the first step surface 910 as a lower step surface, and the third step has the third step surface 930 as an upper step surface. A fifth dielectric layer 805 is disposed on the third step, and the fifth dielectric layer 805 covers the sidewall of the third step. That is, the fifth dielectric layer 805 covers the fourth ohmic contact layer 433, the fourth window layer 432, the fourth restriction layer 431, the second active layer 420, the third restriction layer 412, and the third ohmic contact layer 411. The fifth dielectric layer 805 also covers the first step surface 910 and the third step surface 930 that are not covered by the first electrode 500 and the second electrode 600, thereby protecting the second structure 400.
[0050] In this embodiment, the first electrode 500 and the second electrode 600 are both provided with an extension strip (not shown in the figure), and the extension strip is arranged near the second active layer 420 and / or the first active layer 220. Here, the extension strip arranged next to the first active layer 220 is taken as an example for explanation. The extension strip can extend the electric field to the first active layer 220 region. When the first structure 200 is forward biased, electrons diffuse from the first confinement layer 213 to the second confinement layer 231, and holes diffuse from the second confinement layer 231 to the first confinement layer 213. Due to the effect of the electric field brought by the extension strip, electrons and holes are forced to move to the first active layer 220, thereby reducing the carrier recombination near the first active layer 220 and improving the conduction performance of the first structure 200. The materials of the first electrode 500 and the second electrode 600 may include one or more of Cr, Ti, Pt, Au, Al, Ge, and Be.
[0051] In some embodiments, a first through hole connected to the first step surface 910 and a second through hole connected to the second step surface 920, and a first electrode plate connecting the first through hole and the second through hole may be provided. The first through hole, the second through hole, and the first electrode plate constitute the first electrode 500; a third through hole connected to the fourth step surface 940 and a second electrode plate connecting the third step surface 930 and the third through hole are provided. The third through hole and the second electrode plate constitute the second electrode 600.
[0052] In the present embodiment, the semiconductor device further includes a bonding layer 300 disposed between the first structure 200 and the second structure 400. The first structure 200 and the second structure 400 in the present embodiment are respectively formed on two different substrates, and the first structure 200 and the second structure 400 are bonded and connected by the bonding layer 300, and then one of the substrates is removed, and the remaining substrate is used as the substrate 100, forming the first structure 200 and the second structure 400 stacked on the substrate 100 from bottom to top. The bonding layer 300 can be oxide bonding, metal bonding, organic adhesive bonding, etc. Specifically, the bonding layer 300 can be composed of one or more layers of an aluminum oxide layer, a silicon oxide layer, an indium oxide layer, a tin oxide layer, a silver layer, a gold layer, an organic adhesive layer, etc.
[0053] Figure 2 2 is a cross-sectional view of a semiconductor device with a flip-chip structure provided by the second embodiment of the present invention. Figure 2As shown, the semiconductor device with flip-chip structure has the same substrate 100, first structure 200, bonding layer 300, second structure 400, first electrode 500 and second electrode 600 as the semiconductor device with face-up structure. In this embodiment, the first structure 200 is an LED epitaxial structure, and the second structure 400 is an ESD protection structure, or the first structure 200 is an ESD protection structure, and the second structure 400 is an LED epitaxial structure. The first electrode 500 is electrically connected to the first semiconductor layer 210 and the third semiconductor layer 410, respectively, and the second electrode 600 is electrically connected to the second semiconductor layer 230 and the fourth semiconductor layer 430, respectively, so that the first structure 200 and the second structure 400 are reversely connected in parallel. When static electricity causes the LED epitaxial structure to emit light, the semiconductor device emits light from the back side (i.e., from the side of the substrate 100).
[0054] Specifically, the first semiconductor layer 210 includes but is not limited to a first ohmic contact layer 211, a first window layer 212, and a first confinement layer 213 stacked sequentially from bottom to top, and the first electrode 500 is electrically connected to the first ohmic contact layer 211. The second semiconductor layer 220 includes but is not limited to a second confinement layer 231 and a second ohmic contact layer 232 stacked sequentially from bottom to top, and the second electrode 600 is electrically connected to the second ohmic contact layer 232. The third semiconductor layer 410 includes but is not limited to a third ohmic contact layer 411 and a third confinement layer 412 stacked sequentially from bottom to top, and the first electrode 500 is electrically connected to the third ohmic contact layer 411. The fourth semiconductor layer 430 includes but is not limited to a fourth confinement layer 431, a fourth window layer 432, and a fourth ohmic contact layer 433 stacked sequentially from bottom to top, and the second electrode 600 is electrically connected to the fourth ohmic contact layer 433.
[0055] The semiconductor device provided in the second embodiment has the same first step, second step and third step as the semiconductor device in the first embodiment. In the second embodiment, the third dielectric layer 803 partially covers the top of the first electrode 500 and extends to the fifth dielectric layer 805; the fifth dielectric layer 805 also partially covers the top of the first electrode 500 and extends to the third dielectric layer 803. The structure of the fifth dielectric layer 805 and the third dielectric layer 803 on the top of the first electrode 500 encloses a first opening 810. The fourth dielectric layer 804 partially covers the top of the second electrode 600 and extends to the fifth dielectric layer 805; the fifth dielectric layer 805 also partially covers the top of the second electrode 600 and extends to the fourth dielectric layer 804. The structure of the fourth dielectric layer 804 and the fifth dielectric layer 805 on the top of the second electrode 600 encloses a second opening 820.
[0056] Since the semiconductor device is a flip-chip structure, the semiconductor device further includes a third electrode 710 electrically connected to the first electrode 500 and a fourth electrode 720 electrically connected to the second electrode 600. The third electrode 710 covers the third dielectric layer 803 and the fifth dielectric layer 805 and extends from the first opening 810, thereby covering the first electrode 500 and being electrically connected to the first electrode 500. The fourth electrode 720 covers the fourth dielectric layer and the fifth dielectric layer 805 and extends from the second opening 820, thereby covering the second electrode 600 and being electrically connected to the second electrode 600.
[0057] Figure 3 This is a flow chart of a method for forming a semiconductor device with a front-mounted structure provided in the first embodiment of the present invention. The method for forming a semiconductor device includes the following steps:
[0058] Step S101: providing a substrate, a first structure and a second structure.
[0059] Step S201: forming a first step and a third step.
[0060] Step S301: forming a first dielectric layer and a first electrode on a first step.
[0061] Step S401: forming a second step.
[0062] Step S501 , forming a second dielectric layer and a second electrode on the second step.
[0063] Step S601 , forming a third dielectric layer, a fourth dielectric layer and a fifth dielectric layer.
[0064] Figure 4-Figure 8 It is a cross-sectional view of a semiconductor device of a stand-up structure at different stages provided by the first embodiment of the utility model.
[0065] like Figure 4 As shown, in step S101 , a substrate 100 , a first structure 200 , and a second structure 400 are provided.
[0066] A first substrate is provided and a first structure 200 is formed on the first substrate, wherein the first structure 200 includes a first semiconductor layer 210, a first active layer 220, and a second semiconductor layer 220 stacked sequentially from bottom to top. The first semiconductor layer 210 includes, but is not limited to, a first ohmic contact layer 211, a first window layer 212, and a first confinement layer 213 stacked sequentially from bottom to top. The second semiconductor layer 220 includes, but is not limited to, a second confinement layer 231 and a second ohmic contact layer 232 stacked sequentially from bottom to top.
[0067] A second substrate is provided and a second structure 400 is formed on the second substrate, wherein the second structure 400 includes a fourth semiconductor layer 430, a second active layer 420, and a third semiconductor layer 410 stacked sequentially from bottom to top. The third semiconductor layer 410 includes, but is not limited to, a third confinement layer 412 and a third ohmic contact layer 411 stacked sequentially from bottom to top. The fourth semiconductor layer 430 includes, but is not limited to, a fourth ohmic contact layer 433, a fourth window layer 432, and a fourth confinement layer 431 stacked sequentially from bottom to top.
[0068] The first structure 200 and the second structure 400 are bonded together through the bonding layer 300 , the second substrate is removed, and the first substrate is used as the substrate 100 .
[0069] The substrate 100 may be aluminum oxide, gallium arsenide, gallium nitride, gallium oxide, silicon or silicon carbide, and the thickness of the substrate 100 is 50 μm-500 μm. Preferably, the substrate 100 is aluminum oxide.
[0070] In step S201, a first step and a third step are formed, and the cross-sectional view of the semiconductor device after etching is as follows: Figure 5 Specifically, step S201 includes:
[0071] Step S201 a , forming a patterned first mask layer on the fourth ohmic contact layer 433 .
[0072] Specifically, a photoresist is coated on the fourth ohmic contact layer 433 , and then the photoresist in a specific area is cured through a series of steps such as exposure and development to form a patterned first mask layer.
[0073] Step S201b, etching the fourth ohmic contact layer, the fourth window layer, the fourth confinement layer, the second active layer, the third confinement layer and a portion of the third ohmic contact layer.
[0074] Specifically, the fourth ohmic contact layer 433, the fourth window layer 432, the fourth confinement layer 431, the second active layer 420, the third confinement layer 412 and part of the third ohmic contact layer 411 are etched by dry etching process. After the etching is completed, the remaining first mask layer is removed to form a first step surface 910.
[0075] Step S201c: forming a patterned second mask layer on the third ohmic contact layer.
[0076] Specifically, a photoresist is coated on the third ohmic contact layer 411 , and then the photoresist in a specific area is cured through a series of steps such as exposure and development to form a patterned second mask layer.
[0077] Step S201d, etching the third ohmic contact layer, the bonding layer, the second ohmic contact layer, the second confinement layer, the first active layer, the first confinement layer, the first window layer and a portion of the first ohmic contact layer.
[0078] Specifically, the third ohmic contact layer 411, the bonding layer 300, the second ohmic contact layer 232, the second confinement layer 231, the first active layer 220, the first confinement layer 213, the first window layer 212 and part of the first ohmic contact layer 211 are etched by dry etching. After the etching is completed, the remaining second mask layer is removed to form a second step surface 920, and the following is obtained: Figure 5 The semiconductor device shown.
[0079] In step S301, a first dielectric layer 801 and a first electrode 500 are formed on the first step. The semiconductor device having the first dielectric layer 801 and the first electrode 500 is as follows: Figure 6 Specifically, step S301 includes:
[0080] Step S301a, evaporating a first dielectric layer.
[0081] The first dielectric layer 801 may be formed by any technique known to those skilled in the art. Preferably, a chemical vapor deposition (CVD) method is used, such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), etc.
[0082] The material of the first dielectric layer 801 includes one or more combinations of SiO2, Si3N4, MgF2, Al2O3, TiO2, and ZrO2. The thickness of the first dielectric layer 801 ranges from 10 nm to 1000 nm, for example.
[0083] Step S301b, etching the first dielectric layer.
[0084] Specifically, firstly, a photoresist is coated on the front side of the semiconductor device, and then a patterned third mask layer is formed by curing the photoresist in a specific area through a series of steps such as exposure and development, and wet or dry etching is performed on the first dielectric layer 801. After the etching is completed, the remaining third mask layer is removed. The first dielectric layer 801 finally obtained at least covers the third ohmic contact layer 411, the bonding layer 300, the second ohmic contact layer 232, the second restriction layer 231, the first active layer 220, the first restriction layer 213, the first window layer 212 and part of the side wall of the first ohmic contact layer 211.
[0085] Step S301c, evaporating a first electrode.
[0086] Specifically, firstly, photoresist is coated, and then a series of steps such as exposure and development are performed to cure the photoresist in a specific area to form a patterned fourth mask layer. The fourth mask layer can help achieve precise control of the electrode plating process. Subsequently, the first electrode 500 is evaporated, and the remaining fourth mask layer is removed after the evaporation and etching. The first electrode 500 is disposed on the first step, and the first dielectric layer 801 enables the first electrode 500 to contact only the third ohmic contact layer 411 and the first ohmic contact layer 211.
[0087] The material of the first electrode 500 may include one or more of Cr, Ti, Pt, Au, Al, Ge, and Be.
[0088] In step S401, a second step is formed, and after etching is completed, the following is obtained: Figure 7 Specifically, step S401 includes:
[0089] Step S401a, forming a patterned fifth mask layer on the fourth ohmic contact layer.
[0090] Specifically, a photoresist is coated on the fourth ohmic contact layer 433 , and then the photoresist in a specific area is cured through a series of steps such as exposure and development to form a patterned fifth mask layer.
[0091] Step S401b, etching the fourth ohmic contact layer, the fourth window layer, the fourth confinement layer, the second active layer, the third confinement layer, the third ohmic contact layer, the bonding layer and a portion of the second ohmic contact layer.
[0092] Specifically, the fourth ohmic contact layer 433, the fourth window layer 432, the fourth confinement layer 431, the second active layer 420, the third confinement layer 412, the third ohmic contact layer 411, the bonding layer 300 and part of the second ohmic contact layer 232 are etched by dry etching. After the etching is completed, the remaining fifth mask layer is removed to form a fourth step surface 940, and the following is obtained: Figure 7 The semiconductor device shown.
[0093] In step S501, a second dielectric layer 802 and a second electrode 600 are formed on the second step. After the second dielectric layer 802 and the second electrode 600 are formed, the semiconductor device is as follows: Figure 8 Specifically, step S501 includes:
[0094] Step S501a, evaporating a second dielectric layer.
[0095] The material of the second dielectric layer 802 includes one or more combinations of SiO2, Si3N4, MgF2, Al2O3, TiO2, and ZrO2. The thickness of the second dielectric layer 802 ranges from 10 nm to 1000 nm, for example.
[0096] Step S501b, etching the second dielectric layer.
[0097] Specifically, firstly, a photoresist is coated on the front side of the semiconductor device, and then a series of steps such as exposure and development are performed to cure the photoresist in a specific area to form a patterned sixth mask layer, and the second dielectric layer 802 is wet or dry etched. After the etching is completed, the remaining sixth mask layer is removed. The second dielectric layer 802 finally obtained at least covers the sidewalls of the fourth window layer 432, the fourth restriction layer 431, the second active layer 420, the third restriction layer 412, the third ohmic contact layer 411, the bonding layer 300 and part of the second ohmic contact layer 232.
[0098] Step S501c, evaporating a second electrode.
[0099] Specifically, firstly, photoresist is coated, and then a series of steps such as exposure and development are performed to cure the photoresist in a specific area to form a patterned seventh mask layer. The seventh mask layer can help achieve precise control of the electrode plating process. Subsequently, the second electrode 600 is evaporated, and the remaining seventh mask layer is removed after the evaporation and etching. The second electrode 600 is disposed on the second step, and the second dielectric layer 802 enables the second electrode 600 to contact only the second ohmic contact layer 232 and the fourth ohmic contact layer 433.
[0100] The material of the second electrode 600 may include one or more of Cr, Ti, Pt, Au, Al, Ge, and Be.
[0101] Step S601, forming a third dielectric layer, a fourth dielectric layer and a fifth dielectric layer. Step 601 includes:
[0102] Step S601a, evaporating a third dielectric layer, a fourth dielectric layer and a fifth dielectric layer.
[0103] The third dielectric layer 803, the fourth dielectric layer 804 and the fifth dielectric layer 805 may be formed by any technique known to those skilled in the art. Preferably, a chemical vapor deposition (CVD) method is used, such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), etc.
[0104] The materials of the third dielectric layer 803 , the fourth dielectric layer 804 and the fifth dielectric layer 805 include one or more combinations of SiO 2 , Si 3 N 4 , MgF 2 , Al 2 O 3 , TiO 2 and ZrO 2 .
[0105] Step S601b, etching the third dielectric layer, the fourth dielectric layer and the fifth dielectric layer.
[0106] Specifically, firstly, photoresist is coated on the front side of the semiconductor device, and then the photoresist in a specific area is cured through a series of steps such as exposure and development to form a patterned eighth mask layer, and the third dielectric layer 803, the fourth dielectric layer 804 and the fifth dielectric layer 805 are wet or dry etched. After the etching is completed, the remaining eighth mask layer is removed. The third dielectric layer 803 finally obtained covers the side wall of the first electrode 500 away from the first dielectric layer 801; the fourth dielectric layer 804 covers the side wall of the second electrode 600 away from the second dielectric layer 802; the fifth dielectric layer 805 covers the third ohmic contact layer 411 and the fourth ohmic contact layer 433. The top part and the side wall of the third ohmic contact layer 411, the third limiting layer 412, the second active layer 420, the fourth limiting layer 431, the fourth window layer 432 and the fourth ohmic contact layer 433.
[0107] Step S601c, etching the cutting paths and performing grinding.
[0108] Specifically, etching forms cutting paths, and then grinding and cutting are performed according to the cutting paths to produce Figure 1 The semiconductor device shown.
[0109] In a second embodiment, a method for forming a semiconductor device with a flip-chip structure includes the following steps:
[0110] Step S102: providing a substrate, a first structure and a second structure.
[0111] Step S202: forming a first step and a third step.
[0112] Step S302: forming a first dielectric layer and a first electrode on the first step.
[0113] Step S402: forming a second step.
[0114] Step S502 , forming a second dielectric layer and a second electrode on the second step.
[0115] Step S602 , forming a third dielectric layer, a fourth dielectric layer and a fifth dielectric layer.
[0116] Step S702: evaporating a third electrode and a fourth electrode.
[0117] Steps S102 to S502 are the same as steps S101 to S501 in the first embodiment.
[0118] In step S602 , a third dielectric layer 803 , a fourth dielectric layer 804 and a fifth dielectric layer 805 are formed.
[0119] Specifically, the third dielectric layer 803, the fourth dielectric layer 804 and the fifth dielectric layer 805 are formed by evaporation, the third dielectric layer 803 covers the outer wall and part of the top of the first electrode 500, the fourth dielectric layer 804 covers the outer wall and part of the top of the second electrode 600, and the fifth dielectric layer 805 covers the third step, part of the top of the first electrode 500 and part of the top of the second electrode 600. The third dielectric layer 803 and the fifth dielectric layer 805 surround a first opening 810 at the top of the first electrode 500, and the fourth dielectric layer 804 and the fifth dielectric layer 805 surround a second opening 820 at the top of the second electrode 600, so as to form a substrate as shown in FIG. Fig. 9 The semiconductor device shown.
[0120] In step S702 , the third electrode 710 and the fourth electrode 720 are evaporated.
[0121] Specifically, in step S702, first Fig. 9The front side of the semiconductor device shown is coated with photoresist. First, the photoresist is coated, and then a series of steps such as exposure and development are performed to solidify the photoresist in a specific area to form a patterned ninth mask layer. The ninth mask layer can help achieve precise control of the electrode plating process. Then, the third electrode 710 and the fourth electrode 720 are evaporated. The third electrode 710 covers the third dielectric layer 803 and the fifth dielectric layer 805 and extends from the first opening 810. The fourth electrode 720 covers the fourth dielectric layer and the fifth dielectric layer 805 and extends from the second opening 820. After the evaporation is completed and the etching is completed, the remaining ninth mask layer is removed. Finally, grinding and cutting are performed according to the cutting path to produce the following. Figure 2 The semiconductor device shown.
[0122] Figure 10-12 It is a schematic diagram of the structure of a semiconductor device of a vertical structure provided in the third embodiment of the present utility model. The semiconductor device provided in the third embodiment includes a second electrode 600 and a plurality of first electrodes 500, and the plurality of first electrodes 500 are arranged around the second electrode 600. In other embodiments, the second electrode 600 may also be located at the edge of the semiconductor device, and the first electrode 500 is arranged to semi-surround the second electrode 600. Among them, the material and thickness of the substrate 100, the first structure 200, the bonding layer 300, the second structure 400, the first electrode 500 and the second electrode 600 of the third embodiment may be the same as those of the first embodiment. The third embodiment also includes a bottom electrode 510 arranged on the side of the substrate 100 away from the first structure 200, the bottom electrode 510 is electrically connected to the first semiconductor layer 210 through the substrate 100, and thus connected to the first electrode 500 connected to the first semiconductor layer 210, and the bottom electrode 510 is electrically connected to the third semiconductor layer 410 through the first electrode 500.
[0123] In this embodiment, the first structure 200 is an LED epitaxial structure, and the second structure 400 is an ESD protection structure, or the first structure 200 is an ESD protection structure, and the second structure 400 is an LED epitaxial structure. The first electrode 500 is electrically connected to the first semiconductor layer 210 and the third semiconductor layer 410, respectively, and the second electrode 600 is electrically connected to the second semiconductor layer 230 and the fourth semiconductor layer 430, respectively, so that the first structure 200 and the second structure 400 are reversely connected in parallel. When electrostatic discharge causes the LED epitaxial structure to emit light, the semiconductor device emits light from the front (i.e., emits light from the side away from the substrate 100). Preferably, the substrate 100 is a silicon substrate.
[0124] like Fig.10 and Fig.11As shown, a plurality of first electrodes 500 are uniformly arranged in the semiconductor device. The semiconductor device also includes a first through hole and a second through hole, the first through hole penetrates the fourth semiconductor layer 430 and a portion of the third semiconductor layer 410, the second through hole penetrates the remaining third semiconductor layer 410, the bonding layer 300, the second semiconductor layer 230 and a portion of the first semiconductor layer 210 from the bottom of the first through hole, the second through hole is connected to the first through hole, the diameter of the first through hole is greater than the diameter of the second through hole, and the first through hole and the second through hole are concentrically arranged. Specifically, the first through hole penetrates the fourth ohmic contact layer 433, the fourth window layer 432, the fourth restriction layer 431, the second active layer 420, the third restriction layer 412 and a portion of the third ohmic contact layer 411, and the bottom of the first through hole exposes the third ohmic contact layer 411, and the second through hole penetrates the remaining third ohmic contact layer 411 from the bottom of the first through hole and continues to penetrate the bonding layer 300, the second ohmic contact layer 232, the second restriction layer 231, the first active layer 220, the first restriction layer 213, the first window layer 212 and a portion of the first ohmic contact layer 211. The first dielectric layer 801 covers the hole walls of the first through hole and the second through hole, the first electrode 500 is located in the first through hole and the second through hole and is electrically connected to the third semiconductor layer 410 (third ohmic contact layer 411) and the first semiconductor layer 210 (first ohmic contact layer 211), and the first dielectric layer 801 also covers the top surface of the first electrode 500, that is, the first dielectric layer 801 wraps the first electrode 500, so that the first electrode 500 is only in contact with the first ohmic contact layer 211 and the third ohmic contact layer 411.
[0125] like Fig.10 and Fig.12As shown, the semiconductor device further includes a third through hole, which penetrates the fourth semiconductor layer 430, the third semiconductor layer 410 and the bonding layer 300. Specifically, the third through hole penetrates the fourth ohmic contact layer 433, the fourth window layer 432, the fourth restriction layer 431, the second active layer 420, the third restriction layer 412, the third ohmic contact layer 411, the bonding layer 300 and a portion of the second ohmic contact layer 232. The second dielectric layer 802 is located on the sidewall of the third through hole, the second electrode 600 is located in the third through hole and extends to cover a portion of the surface of the fourth semiconductor layer 430 (the fourth ohmic contact layer 433), and the second electrode 600 is electrically connected to the second semiconductor layer 230 (the second ohmic contact layer 232) and the fourth semiconductor layer 430 (the fourth ohmic contact layer 433). That is, the second electrode 600 includes a first portion disposed in the first structure 200 and the second structure 400 and a second portion disposed on the second structure 400. The first part is in contact with the second ohmic contact layer 232, and the second part is connected to the fourth ohmic contact layer 433 and extends on the fourth ohmic contact layer 433 to play a role in current expansion. The first part has a second dielectric layer 802 around it, and the second dielectric layer 802 separates the first part from the second ohmic contact layer 232, the bonding layer 300, the third ohmic contact layer 411, the third limiting layer 412, the second active layer 420, the fourth limiting layer 431, the fourth window layer 432 and the sidewall of the fourth ohmic contact layer 433.
[0126] The semiconductor device provided in the third embodiment of the present invention is a vertical structure, and the method for forming the semiconductor device includes the following steps:
[0127] Step S103: providing a substrate, a first structure and a second structure.
[0128] Step S203: forming a first step and a third step.
[0129] Step S303: forming a first dielectric layer and a first electrode on the first step.
[0130] Step S403: forming a second step.
[0131] Step S503: forming a second dielectric layer and a second electrode on the second step.
[0132] Step S603: forming a bottom electrode on the back side of the substrate.
[0133] Steps S103 to S503 are similar to steps S101 to S501 in the first embodiment. The processing method and processing parameters (such as the materials used, etching depth, mask layer size, etc.) of steps S103 to S503 are the same as those of steps 101 to S501, and are not described here. The processing positions and quantities of steps S103 to S603 are shown in Figure 10-12 same.
[0134] In step S603 , a bottom electrode 510 is formed on the back side of the substrate 100 . The bottom electrode 510 is disposed on a side of the substrate 100 away from the first structure 200 , and the bottom electrode 510 is electrically connected to the first semiconductor layer 210 through the substrate 100 .
[0135] The material of the bottom electrode 510 may include one or more of Cr, Ti, Pt, Au, Al, Ge, and Be.
[0136] In addition, after step S603, the method further includes etching the first ohmic contact layer 211, the first window layer 212, the first confinement layer 213, the first active layer 220, the second confinement layer 231, the second ohmic contact layer 232, the bonding layer 300, the third ohmic contact layer 411, the third confinement layer 412, the second active layer 420, the fourth confinement layer 431, the fourth window layer 432 and the fourth ohmic contact layer 433, thereby exposing a portion of the substrate, and then forming a sixth dielectric layer 806 on the substrate 100. The sixth dielectric layer 806 surrounds the first structure 200 and the second structure 400.
[0137] Then, the scribe lines are etched and ground.
[0138] Finally, the sixth dielectric layer 806 is cut along a side away from the first structure 200 and the second structure 400 to obtain Figure 10-12 The semiconductor device shown.
[0139] The embodiment of the utility model discloses a semiconductor device. The semiconductor device includes a substrate, a first structure, a second structure, a first electrode, and a second electrode. The first structure includes a first semiconductor layer with a first doping type and a second semiconductor layer with a second doping type, and the second structure includes a fourth semiconductor layer with the first doping type and a third semiconductor layer with the second doping type. The first electrode and the second electrode connect the first structure and the second structure in parallel, so that the semiconductor device has two PN junctions connected in parallel in opposite directions. The semiconductor device of the embodiment of the utility model will not be broken down by reverse current or voltage when electrostatic discharge occurs through the above structure.
[0140] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A semiconductor device, characterized in that: The semiconductor device comprises: substrate; A first structure is formed on the substrate, wherein the first structure includes a first semiconductor layer and a second semiconductor layer stacked sequentially from bottom to top; A second structure is formed above the first structure, the second structure comprising a third semiconductor layer and a fourth semiconductor layer stacked sequentially from bottom to top; a first electrode, electrically connected to the first semiconductor layer and the third semiconductor layer respectively; a second electrode, electrically connected to the second semiconductor layer and the fourth semiconductor layer respectively; a bonding layer, disposed between the first structure and the second structure; The first semiconductor layer and the fourth semiconductor layer have a first doping type, the second semiconductor layer and the third semiconductor layer have a second doping type, and the first doping type is opposite to the second doping type.
2. The semiconductor device according to claim 1, wherein: The first semiconductor layer includes a first ohmic contact layer, a first window layer and a first confinement layer stacked in sequence from bottom to top, and the first electrode is electrically connected to the first ohmic contact layer; The second semiconductor layer includes a second confinement layer and a second ohmic contact layer stacked sequentially from bottom to top, and the second electrode is electrically connected to the second ohmic contact layer; The third semiconductor layer includes a third ohmic contact layer and a third confinement layer stacked in sequence from bottom to top, and the first electrode is electrically connected to the third ohmic contact layer; The fourth semiconductor layer includes a fourth confinement layer, a fourth window layer, and a fourth ohmic contact layer stacked in sequence from bottom to top, and the second electrode is electrically connected to the fourth ohmic contact layer.
3. The semiconductor device according to claim 1, wherein: The first structure further includes a first active layer formed between the first semiconductor layer and the second semiconductor layer; and / or, The second structure further includes a second active layer formed between the third semiconductor layer and the fourth semiconductor layer.
4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The semiconductor device comprises a first step, a lower step surface of the first step is a second step surface located on the first semiconductor layer, and an upper step surface of the first step is a first step surface located on the third semiconductor layer; The bottom of the first electrode is arranged on the second step surface, the top portion of the first electrode covers the first step surface, the semiconductor device includes a first dielectric layer arranged on the second step surface, one side of the first dielectric layer covers the side wall of the first step, and the first electrode is arranged on the other side of the first dielectric layer.
5. The semiconductor device according to claim 4, characterized in that The semiconductor device further includes a second step, a lower step surface of the second step is a fourth step surface located on the second semiconductor layer, and an upper step surface of the second step is a third step surface located on the fourth semiconductor layer; The bottom of the second electrode is arranged on the fourth step surface, and the top portion of the second electrode covers the third step surface. The semiconductor device also includes a second dielectric layer arranged on the fourth step surface, one side of the second dielectric layer covers the side wall of the second step, and the second electrode is arranged on the other side of the second dielectric layer.
6. The semiconductor device according to claim 5, characterized in that The semiconductor device further comprises a third step, a lower step surface of the third step is a first step surface located in the third semiconductor layer, and an upper step surface of the third step is a third step surface located in the fourth semiconductor layer; The semiconductor device further includes a fifth dielectric layer disposed on the first step surface, wherein the fifth dielectric layer covers the sidewall of the third step, the first step surface not covered by the first electrode and the second electrode, and the third step surface.
7. The semiconductor device according to claim 6, characterized in that The semiconductor device further includes a third dielectric layer partially covering the first electrode and a fourth dielectric layer partially covering the second electrode, wherein the third dielectric layer is arranged on a side of the first electrode away from the first dielectric layer, and the fourth dielectric layer is arranged on a side of the second electrode away from the second dielectric layer.
8. The semiconductor device according to claim 7, characterized in that The semiconductor device further comprises a third electrode electrically connected to the first electrode and a fourth electrode electrically connected to the second electrode, the third dielectric layer and the fifth dielectric layer enclose a first opening, and the third electrode extends into the first opening and is connected to the first electrode; The fourth dielectric layer and the fifth dielectric layer form a second opening, and the fourth electrode extends into the second opening and is connected to the second electrode.
9. The semiconductor device according to any one of claims 1 to 3, characterized in that: The semiconductor device comprises a plurality of the first electrodes and one second electrode, wherein the plurality of the first electrodes are arranged around the second electrode, the first electrodes are all arranged in the first structure and the second structure, the second electrode is partially arranged in the first structure and the second structure, and another part of the second electrode is arranged on a side of the second structure away from the first structure; The semiconductor device further comprises a bottom electrode disposed on a side of the substrate away from the first structure, and the bottom electrode is electrically connected to the first semiconductor layer, the first electrode and the third semiconductor layer through the substrate.
10. The semiconductor device according to claim 9, characterized in that The semiconductor device further comprises a first through hole, a second through hole and a third through hole; The first through hole penetrates the fourth semiconductor layer and a portion of the third semiconductor layer; The second through hole penetrates the remaining third semiconductor layer, the bonding layer, the second semiconductor layer and a portion of the first semiconductor layer from the bottom of the first through hole, the second through hole is connected to the first through hole, the diameter of the first through hole is larger than the diameter of the second through hole, and the first through hole and the second through hole are concentrically arranged; The third through hole penetrates the fourth semiconductor layer, the third semiconductor layer and the bonding layer; The first dielectric layer is located on the sidewalls of the first through hole and the second through hole, the first electrode is located in the first through hole and the second through hole to be electrically connected to the third semiconductor layer and the first semiconductor layer, and the first dielectric layer also covers the top surface of the first electrode; The second dielectric layer is located on the sidewall of the third through hole, and the second electrode is located in the third through hole and extends to cover a portion of the surface of the fourth semiconductor layer to be electrically connected to the second semiconductor layer and the fourth semiconductor layer.
11. The semiconductor device according to claim 1, wherein: The first structure is an electrostatic discharge protection structure, and the second structure is a light emitting diode epitaxial structure or a common diode; or, The first structure is a light emitting diode epitaxial structure or a common diode, and the second structure is an electrostatic discharge protection structure.