PCB bonding pad arrangement structure and chip packaging structure
By setting up multiple pad groups and pad groups on the PCB substrate and connecting them with copper wires, the IC compatibility problem with large package size differences is solved, and ICs with different sizes and pin properties are realized under the same PCB layout. Compatible packaging, improves substitutability and reduces production costs.
Patent Information
- Application Number
- CN202420488844.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-11
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2034-03-11
AI Technical Summary
The existing PCB pad design is not compatible with ICs with large differences in packaging sizes, especially ICs with different number of PIN pins and spacing, which makes it impossible to achieve compatible packaging in the same PCB layout design.
A PCB pad layout structure is designed. By setting two first pad groups and two second pad groups on the PCB substrate, connecting copper wires to form a second area to achieve different sizes and pin properties. compatible packages of ICs are used for electrical connection to large and small chips, respectively.
While reducing the fabric area, it improves the substitutability of PCB layout design, reduces production costs, and realizes compatible packaging for ICs with different sizes and pin settings.
Smart Images
Figure CN222235136U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of PCB packaging structures, in particular to a PCB pad arrangement structure and a chip packaging structure. Background Art
[0002] With the diversification of IC packaging and use, considering the needs of multi-function, low cost, and substitutability, ICs with different package designs often need to be used in the same PCB design solution. How to achieve the smallest layout area and the largest device compatibility during the PCB layout design process has become a key issue in PCB pad design.
[0003] For this purpose, a variety of conventional PCB compatible design solutions have been developed in the prior art, which are suitable for a variety of ICs with compatible packages, that is, obtaining the common pin size information of PIN to PIN (PIN TO PIN, which means that the position and number of the chip functional pins are the same and the chips can be interchangeable) between different ICs, drawing the package silk screen in consideration of the distance and position between the common pins, and selecting the maximum pin opening size as the opening size of the common pin. The above-mentioned solutions in the prior art can solve the compatible packaging between different ICs with small package size differences and PIN to PIN pin relationships.
[0004] However, when an IC with a significantly different package size is used as a replacement material on the same PCB board, for example, the number of PIN pins of the replacement IC and the original IC is different or the PIN pin spacing is significantly different, then the conventional PCB compatible design solution cannot be used. Utility Model Content
[0005] The embodiments of the utility model provide a PCB pad arrangement structure and a chip packaging structure to solve the problem that the existing PCB packaging structure is not compatible with ICs with greatly different packaging sizes or different pin numbers.
[0006] In order to solve the above technical problems, the embodiments of the present utility model disclose the following technical solutions:
[0007] According to a first aspect of the utility model, a PCB pad arrangement structure is provided, comprising a PCB substrate, two first pad groups and two second pad groups; the two first pad groups and the two second pad groups are both arranged on the PCB substrate; the two first pad groups are arranged at intervals along a second direction to separate a first area, and the two second pad groups are arranged at intervals along the first direction within the first area.
[0008] Furthermore, the second direction is perpendicular to the first direction.
[0009] Furthermore, the two first pad groups and the two second pad groups surround a second area.
[0010] Further, each of the first pad groups includes a plurality of first pads, which are arranged at intervals to form a first pad group; each of the second pad groups includes a plurality of second pads, which are arranged at intervals to form a second pad group.
[0011] Furthermore, each of the first pad groups and one of the second pad groups are arranged in pairs, and a plurality of first pads and a plurality of second pads having the same potential in a pair of the first pad group and the second pad group are connected in a one-to-one correspondence.
[0012] Furthermore, the plurality of first pads and the plurality of second pads are connected to each other via copper wires, and the copper wires are disposed in the second region.
[0013] Furthermore, the two first pad groups are used to be electrically connected to pins of a first chip, and the two second pad groups are used to be electrically connected to pins of a second chip, and the package sizes of the first chip and the second chip are different.
[0014] Furthermore, a package size of the first chip is larger than a package size of the second chip.
[0015] Furthermore, the pin attributes of the first chip are different from the pin attributes of the second chip.
[0016] According to a second aspect of the utility model, a chip packaging structure is provided, comprising a chip and a PCB pad arrangement structure according to any one of the above-mentioned first aspects, wherein the chip is connected to the first pad group or the second pad group.
[0017] One of the above technical solutions has the following advantages or beneficial effects:
[0018] The PCB pad position design scheme in the prior art is only suitable for the design of PIN-to-PIN compatibility between the original IC and the replacement IC with small package size differences. The utility model sets two second pad groups in the first area separated by the two first pad groups. The first pad group can be used to weld a packaged IC with one size and pin setting, and the second pad group can be used to weld a packaged IC with another size and pin setting, so that two compatible packages of packaged ICs with different sizes and pin settings are realized on the same PCB layout design, which greatly improves the substitutability of the PCB layout design while reducing the layout area, and effectively reduces the production cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.
[0020] Figure 1 It is a schematic diagram of a large-size packaged chip provided according to an embodiment of the utility model;
[0021] Figure 2 It is a schematic diagram of a small-size packaged chip provided according to an embodiment of the utility model;
[0022] Figure 3 It is a schematic diagram of a PCB pad arrangement structure provided according to an embodiment of the utility model;
[0023] Figure 4 It is a schematic diagram of a first direction and a second direction provided according to an embodiment of the utility model;
[0024] Figure 5 It is a schematic diagram of the dimensions of a first chip and a second chip provided according to an embodiment of the utility model;
[0025] The meanings of the reference numerals are as follows: 10 - PCB substrate; 20 - first pad group; 21 - first pad; 30 - second pad group; 31 - second pad; 40 - copper wire; 50 - first chip; 60 - second chip. DETAILED DESCRIPTION
[0026] In order to make the purpose, technical solution and beneficial effects of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. It should be understood that the specific implementation methods described in this specification are only for explaining the utility model, and are not intended to limit the utility model.
[0027] In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present utility model, the meaning of "multiple" refers to two or more, unless otherwise clearly and specifically defined.
[0028] In the description of the present utility model, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0029] In the present utility model, unless otherwise clearly stipulated and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.
[0030] The PCB compatible design scheme in the prior art is usually applicable to ICs with compatible packages, that is, the shared pin size information of PIN to PIN between different ICs is obtained, the package silk screen is drawn considering the distance and position between the shared pins, and the maximum pin opening size is selected as the opening size of the shared pin. The above-mentioned scheme in the prior art can solve the compatible packaging with small package size differences and PIN to PIN pin relationships between different ICs.
[0031] However, when an IC with a different package size is used as a replacement on the same PCB board, for example, the original IC is Figure 1 The large-size package IC shown has two rows of 8 pins, namely "CO, DO, VM, NC, VSS, VDD, CS and CNT". Replace the IC with Figure 2 The small-size packaged IC shown has two rows of six pins, namely "VM, DO, CO, CS, VDD, and VSS". At this time, the number of PIN pins of the replacement IC and the original IC is different and the PIN pin spacing is greatly different, so the conventional PCB compatible design solution cannot be adopted.
[0032] Aiming at the problem that the PCB packaging structure in the prior art is not compatible with ICs with large package size differences or different pin numbers, the utility model provides a PCB pad arrangement structure. Figure 3 A schematic diagram of the PCB pad arrangement structure is shown.
[0033] like Figure 3 to Figure 4As shown, the PCB pad arrangement structure includes: a PCB substrate 10, two first pad groups 20 and two second pad groups 30. The two first pad groups 20 and the two second pad groups 30 are both arranged on the PCB substrate 10.
[0034] In some embodiments, the package of the chip to be welded is usually rectangular, and the pins are symmetrically arranged on two parallel sides of the rectangle. The number of pads in each pad group is consistent with the number of pins on one side of the chip package, and they are respectively arranged on both sides of the chip. The two first pad groups 20 are arranged at intervals along the second direction BB' to separate the first area. The width of the first area is determined according to the size of the original chip, and its width is the distance between the two first pad groups 20. Its length is not limited. Preferably, the two first pad groups 20 can be arranged in parallel along the second direction BB'. The two second pad groups 30 are arranged at intervals along the first direction AA' in the first area. Preferably, the two second pad groups 30 can be arranged in parallel along the first direction AA'. The second direction BB' is perpendicular to the first direction AA', and the two first pad groups 20 and the two second pad groups 30 surround the second area. The positions of the two second pad groups 30 are set according to the package size of the replacement IC.
[0035] In some embodiments, the plurality of pins of the chip package are arranged at intervals, and to adapt to the plurality of pins of the chip package, each first pad group 20 includes a plurality of first pads 21, and the plurality of first pads 21 are arranged at intervals to form the first pad group 20. Each second pad group 30 includes a plurality of second pads 31, and the plurality of second pads 31 are arranged at intervals to form the second pad group 30. The first pads 21 and / or the second pads 31 are usually made of metal copper, and can be interconnected with the copper wires and copper solder joints on the surface of the PCB substrate 10.
[0036] In some embodiments, each first pad group 20 and a second pad group 30 are arranged in pairs, and a plurality of first pads 21 and a plurality of second pads 31 with the same potential in a pair of first pad groups 20 and second pad groups 30 are connected one by one. The first pad group 20 may further include a plurality of first pads 21 that are not connected to the second pads 31 in the second pad group 30, and the second pad group 30 may further include a plurality of second pads 31 that are not connected to the first pads 21 in the first pad group 20. Figure 3 As shown in , each first pad group 20 has four first pads 21 , three of which are connected to multiple second pads 31 in the second pad group 30 , and the remaining one first pad 21 has no connection with any second pad 31 in the second pad group 30 .
[0037] In some embodiments, multiple first pads 21 in the first pad group 20 and multiple second pads 31 in the second pad group 30 are connected by copper wires 40. Preferably, the copper wires 40 are arranged in the second area. The copper wires arranged in the second area can reduce the wiring area. When the copper wire size is large and the wiring in the second area is crowded, the copper wires can also be arranged outside the second area.
[0038] In some embodiments, the two first pad groups 20 are used to electrically connect to the pins of the first chip 50, and the two second pad groups 30 are used to electrically connect to the pins of the second chip 60. Figure 5 As shown, the package size of the first chip 50 is different from that of the second chip 60. The package size of the first chip 50 is larger than that of the second chip 60. The pin attributes of the first chip 50 are the same as or different from those of the second chip 60. Figure 5 2 shows the situation when the pin attributes of the first chip 50 are different from the pin attributes of the second chip 60. This pad arrangement structure effectively utilizes the blank space at the bottom of the first chip 50 with a larger size, and achieves the effect that the same PCB layout design can be normally applied to any packaged IC in the soldering, thereby reducing production costs.
[0039] The existing PCB pad position design scheme is only suitable for the design of PIN-to-PIN compatibility between the original IC and the replacement IC with small package size differences. However, the pad arrangement structure provided by the utility model can achieve compatibility with two IC soldering packages with different numbers and types of PIN pins and large differences in PIN pin size spacing, greatly improving the compatibility and substitutability of the same PCB design.
[0040] The utility model also provides a chip packaging structure, comprising a chip and the above-mentioned PCB pad arrangement structure. According to the packaging size, the chip is connected to the first pad group or the second pad group.
[0041] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0042] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.
Claims
1. A PCB pad arrangement structure, characterized in that: include: A PCB substrate, two first pad groups and two second pad groups; The two first pad groups and the two second pad groups are both arranged on the PCB substrate; The two first pad groups are arranged at intervals along the second direction to separate a first area, and the two second pad groups are arranged at intervals along the first direction within the first area.
2. The PCB pad arrangement structure according to claim 1, characterized in that: The second direction is perpendicular to the first direction.
3. The PCB pad arrangement structure according to claim 2, characterized in that: The two first pad groups and the two second pad groups surround a second area.
4. The PCB pad arrangement structure according to any one of claims 1 to 3, characterized in that: Each of the first pad groups includes a plurality of first pads, which are arranged at intervals to form a first pad group; each of the second pad groups includes a plurality of second pads, which are arranged at intervals to form a second pad group.
5. The PCB pad arrangement structure according to claim 4, characterized in that: Each of the first pad groups and one of the second pad groups are arranged in pairs, and a plurality of first pads and a plurality of second pads having the same potential in a pair of the first pad group and the second pad group are connected in a one-to-one correspondence.
6. The PCB pad arrangement structure according to claim 5, characterized in that: The two first pad groups and the two second pad groups surround a second area, the plurality of first pads and the plurality of second pads are connected to each other via copper wires, and the copper wires are disposed in the second area.
7. The PCB pad arrangement structure according to claim 1, characterized in that: The two first pad groups are used to be electrically connected to the pins of the first chip, and the two second pad groups are used to be electrically connected to the pins of the second chip. The package sizes of the first chip and the second chip are different.
8. The PCB pad arrangement structure according to claim 7, characterized in that: The package size of the first chip is larger than the package size of the second chip.
9. The PCB pad arrangement structure according to claim 7, characterized in that: The pin attributes of the first chip are different from the pin attributes of the second chip.
10. A chip packaging structure, comprising a chip, characterized in that: It also includes the PCB pad arrangement structure according to any one of claims 1 to 9, wherein the chip is connected to the first pad group or the second pad group.