Large-bandwidth intermediate-frequency signal high-speed acquisition device

Abstract

The utility model discloses a large-bandwidth intermediate-frequency signal high-speed acquisition device, which comprises a structural bottom plate, a structural shielding upper cover, a radiator, a fan and a circuit board, the circuit board is installed and fixed on the structure bottom plate; the structure shielding upper cover is arranged above the circuit board and is fixed with the structure bottom plate; the bottom of the radiator is attached to a chip on the circuit board through a heat conduction silica gel pad and is locked and fixed to the structure bottom plate, and the fan is installed on the radiator and fixed to the radiator. A data output unit, a processor unit, a clock unit, a self-calibration signal output unit, a high-speed A / D acquisition unit, a detection trigger unit, an intermediate frequency signal conditioning unit and a signal switching unit are integrated on the circuit board. According to the large-bandwidth intermediate-frequency signal high-speed acquisition device provided by the utility model, a large-bandwidth intermediate-frequency signal high-speed acquisition function is realized on an independent circuit board, and the device is simple in structure and strong in universality.

Description

Technical Field

[0001] The invention relates to high-speed signal acquisition, in particular to a high-speed acquisition device for large-bandwidth intermediate frequency signals. Background Art

[0002] At present, the application demand for large-bandwidth intermediate frequency signal acquisition and analysis in the fields of communications and radar is increasing, and the corresponding requirements for signal acquisition and analysis equipment are also getting higher and higher. On the one hand, large-bandwidth intermediate frequency signals require high-speed signal acquisition and processing and analysis capabilities; on the other hand, large-bandwidth intermediate frequency signals have high requirements for the stability of the amplitude and phase characteristics of the signal conditioning channel, and real-time calibration and compensation are required in various equipment use environments and operating conditions; furthermore, the signal bandwidths and modulation methods used by various communication protocols are diverse and different, requiring the acquisition equipment to have good automatic adjustment and adaptation capabilities; in addition, the signals that need to be collected in many application fields are not continuous signals, but specific high-speed pulse signals, so the equipment is also required to have the ability to collect and analyze such signals. Utility Model Content

[0003] The utility model aims to overcome the deficiencies of the prior art and provide a high-speed acquisition device for intermediate frequency signals with large bandwidth, which realizes the high-speed acquisition function of intermediate frequency signals with large bandwidth on an independent circuit board, and has a simple structure and strong versatility.

[0004] The purpose of the utility model is achieved through the following technical solutions: a high-speed acquisition device for intermediate frequency signals with large bandwidth, including a structural bottom plate, a structural shielding upper cover, a radiator, a fan and a circuit board;

[0005] The circuit board is installed and fixed on the structural bottom plate; the structural shielding cover is installed above the circuit board and fixed to the structural bottom plate; the bottom of the radiator is attached to the chip on the circuit board through a thermal conductive silicone pad and is locked and fixed to the structural bottom plate; the fan is installed on the radiator and fixed to the radiator;

[0006] The circuit board is integrated with a data output unit, a processor unit, a clock unit, a self-calibration signal output unit, a high-speed A / D acquisition unit, a detection trigger unit, an intermediate frequency signal conditioning unit and a signal switching unit;

[0007] One input end of the signal switching unit receives an external intermediate frequency signal, and another input end is connected to the self-calibration signal output unit. The output end of the signal switching unit is connected to the intermediate frequency signal conditioning unit; the output end of the intermediate frequency signal conditioning unit is respectively connected to the high-speed A / D acquisition unit and the detection trigger unit, and the output ends of the detection trigger unit and the high-speed A / D acquisition unit are both connected to the processor unit;

[0008] The input end of the data output unit is connected to the processor unit, and is used to communicate with an external device and output a signal of the processor unit;

[0009] The clock unit is used to receive an externally input reference clock, and the output end of the clock unit is respectively connected to the processor unit, the high-speed A / D acquisition unit and the self-calibration signal output unit, and is used to provide the required clock for the connected units based on the externally input or built-in reference clock;

[0010] The input end of the self-calibration signal output unit is connected to the processor unit, and the output end is connected to the signal switching unit, and is used to provide a self-calibration signal to the signal switching unit.

[0011] Preferably, the high-speed acquisition device further comprises a structural side plate arranged on the right side of the circuit board;

[0012] The input and output interfaces of the circuit board high-speed acquisition device are integrated on the circuit board. A plurality of small holes are provided on the structural side plate. The input and output interfaces on the circuit board extend through the small holes to the outside of the structural side plate to interact with external devices for signals or power supply.

[0013] Preferably, the structural base plate is provided with a plurality of screw holes I for fixing the circuit board, and the circuit board is installed and fixed on the structural base plate by screws penetrating the circuit board and cooperating with the screw holes I on the structural base plate.

[0014] Preferably, the structural base plate is provided with a plurality of screw holes II for fixing the structural shielding upper cover, and screws are passed through the structural shielding upper cover and cooperate with the screw holes II on the structural base plate to lock and fix the structural shielding upper cover to the structural base plate.

[0015] Preferably, the structural base plate is provided with a plurality of screw holes III for fixing the radiator, and the screws penetrate the radiator, the thermal conductive silicone pad and the circuit board, and cooperate with the screw holes III on the structural base plate to lock and fix the radiator to the structural base plate.

[0016] Preferably, the radiator is provided with a plurality of screw holes IV, the fan is provided with a mounting plate, and screws are passed through the mounting plate of the fan and cooperate with the plurality of screw holes IV on the radiator to lock and fix the fan to the radiator.

[0017] Preferably, a power supply unit and a storage unit are also integrated on the circuit board, and the power supply unit receives external power input through a power connector and supplies power to the entire circuit board after DC-DC power conversion;

[0018] The storage unit is directly connected to the processor unit and is used to provide data buffer storage for the processor unit during operation.

[0019] Preferably, the storage unit includes a FLASH memory and a DDR4 storage array;

[0020] The data output unit includes a PCIE interface, a QSFP28 optical fiber module interface and a high-speed digital signal output interface;

[0021] The processor unit is implemented using FPGA;

[0022] The self-calibration signal output unit adopts a high-speed D / A converter, which is used to convert the digital self-calibration signal output by the FPGA and transmit it to the signal switching unit.

[0023] Preferably, the clock unit includes a power divider, a first clock chip and a second clock chip. The input end of the power divider is connected to an external reference clock through a radio frequency interface, and the output end of the power divider is respectively connected to the first clock chip and the second clock chip. The first clock chip is respectively connected to a self-calibration signal output unit and a processor unit; the second clock chip is respectively connected to a high-speed A / D acquisition unit and a processor unit.

[0024] Preferably, the intermediate frequency signal conditioning unit comprises a first amplifier, a first attenuator, a first signal switching switch, a second signal switching switch, a second amplifier, a second attenuator and a plurality of filters with different passbands, the input end of the first amplifier is connected to the output end of the signal switching unit, the output end of the first amplifier is connected to the first attenuator, the output of the first attenuator is respectively connected to each filter through the first signal switching switch, the output end of each filter is connected to the second attenuator through the second signal switching switch, and the output end of the second attenuator is connected to the second amplifier;

[0025] The detection trigger unit includes a broadband directional coupler, a logarithmic detector, a low-speed D / A converter and a comparator. The first end of the broadband directional coupler is connected to the output end of the second amplifier, and the second end is connected to the high-speed A / D acquisition unit; the coupling end of the broadband directional coupler is connected to the detector, the output end of the detector is connected to the in-phase input end of the comparator, the input end of the low-speed D / A converter is connected to the processor unit, the output end of the low-speed D / A converter is connected to the inverting input end of the comparator, and the output end of the comparator is connected to the processor unit.

[0026] The beneficial effects of the utility model are as follows: 1. The utility model realizes the high-speed acquisition and analysis function of large-bandwidth intermediate frequency signals on an independent module, which simplifies the complexity of the device and has certain versatility compared with other complex interconnected system architectures;

[0027] 2. The utility model can realize high-speed acquisition functions of various large-bandwidth intermediate frequency signals through the switching selection of high-speed A / D sampling rate and filter group;

[0028] 3. The utility model has the function of self-calibration of signal channel amplitude and phase;

[0029] 4. The utility model has RF detection and triggering functions, and can set trigger conditions to accurately collect and capture broadband high-speed pulse signals and perform signal analysis;

[0030] 5. The utility model also has the function of high-speed real-time output of original data after large-bandwidth intermediate frequency signal acquisition, meeting the needs of data storage and subsequent analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the structure of the utility model;

[0032] Figure 2 This is the electrical principle block diagram inside the circuit board;

[0033] Figure 3 It is a schematic diagram of the structure inside the circuit board;

[0034] In the figure, 1-structural bottom plate, 2-structural side plate, 3-structural shielding upper cover, 4-radiator, 5-fan, 6-circuit board, 7-power supply unit, 8-storage unit, 9-data output unit, 10-processor unit, 11-clock unit, 12-self-calibration signal output unit, 13-high-speed A / D acquisition unit, 14-detection trigger unit, 15-intermediate frequency signal conditioning unit, 16-signal switching unit. DETAILED DESCRIPTION

[0035] The technical solution of the present utility model is further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present utility model is not limited to the following.

[0036] like Figure 1As shown, the utility model is mainly composed of structural parts and circuit boards, specifically including a structural bottom plate 1, a structural side plate 2, a structural shielding cover 3, a radiator 4, a fan 5, a circuit board 6 and components on the circuit board. The structural bottom plate 1 combines the shielding cover design into one, and a plurality of screw holes are also distributed and designed on it, which mainly supports and fixes the entire device and shields the analog intermediate frequency circuit. The circuit board 6 is installed and fixed on the structural bottom plate 1 by screws, and various circuit units for realizing the functions of the device are distributed on it. At the same time, all external input and output interfaces of the device are also located on the circuit board 6. The shielding cover 3 is installed on the circuit board 6 and is locked and fixed with the structural bottom plate 1 by distributed screws. The bottom of the radiator 4 is bonded with the chip on the circuit board 6 by a thermal conductive silicone pad, and is locked and fixed with the structural bottom plate 1 by screws. The fan 5 is installed on the radiator 4 and fixed with the radiator 4 by screws. The structural side plate 2 is installed and fixed with the structural bottom plate 1 by screws, and a plurality of external interface holes of the device are opened on it.

[0037] The circuit board is the core of the device's functions. Figure 2 As shown is its overall principle block diagram, it mainly consists of a power supply unit 7, a storage unit 8, a data output unit 9, a processor unit 10, a clock unit 11, a self-calibration signal output unit 12, a high-speed A / D acquisition unit 13, a detection trigger unit 14, an intermediate frequency signal conditioning unit 15, a signal switching unit 16 and other parts.

[0038] Specifically, Figure 3 As shown, the power supply unit receives external power input through the power connector, and after DC-DC power conversion, supplies power according to the power supply requirements of each unit of the system. The storage unit is subdivided into FLASH memory and DDR4 storage array. The FLASH memory stores system configuration and calibration compensation data. The storage array composed of multiple DDR4 chips provides data buffer storage for digital signal processing during operation; FLASH memory stores system configuration; the data output unit is subdivided into PCIE interface, QSFP28 optical fiber module interface and high-speed digital signal output interface. The PCIE interface performs high-speed bidirectional data transmission and control communication with other devices of the user. The QSFP28 optical fiber and high-speed digital signal output interface collect the large broadband intermediate frequency signal at high speed and output the original IQ data. The processor unit is implemented by a high-performance FPGA to control the operation of the entire system and complete high-speed digital signal processing and analysis after signal acquisition. The input and output interfaces on the circuit board include: an intermediate frequency signal input interface for external signal input and transmission to the signal switching unit; a signal output interface connected to the data output unit for the data output unit to output signals to the outside, and an external clock input interface connected to the clock unit for external clock input;

[0039] The clock unit uses an internal or external reference clock, and provides sampling and reference clocks for high-speed A / D, D / A and FPGA respectively through a clock synthesis chip. The self-calibration signal output unit outputs a comb wave calibration signal by a high-speed D / A converter under the control of the FPGA. The high-speed A / D acquisition unit performs analog-to-digital conversion of a wide-band IF signal by a high-speed A / D converter. The detection trigger unit is composed of a wide-band directional coupler, a logarithmic detector, a low-speed D / A converter and a comparator. The high-speed pulse signal enters the detector through the coupler and is converted into a DC level. After the comparison with the trigger level set by the low-speed D / A is performed in the comparator, a trigger signal is sent to the FPGA. The IF signal conditioning unit realizes the gain adjustment of the IF signal and the switching of the filter bandwidth to adapt to signals with different bandwidths and modulation modes. The signal switching unit dynamically inputs the input signal or the self-calibration signal into the IF signal conditioning unit according to the needs of the operating state.

[0040] The workflow of this utility model is as follows:

[0041] After the system is powered on normally, the FPGA reads the configuration file from the FLASH memory to complete its own system configuration, and then initializes the entire system through the preset working mode saved in the FLASH memory. The clock unit synthesizes and outputs the default sampling clock, device clock and system synchronization clock.

[0042] The digital signal generated by FPGA is output by the high-speed D / A converter as a standard comb wave calibration signal. The signal switching switch is switched to the calibration signal input path. The FPGA controls the intermediate frequency signal conditioning unit to switch the bandwidth and gain path. The calibration signal passes through the intermediate frequency signal conditioning unit and enters the high-speed A / D converter to complete the analog-to-digital conversion. It is output together with the digital signal generated by FPGA as the basis for calculating the signal amplitude and phase compensation value.

[0043] The FPGA control signal switching switch switches to the external signal input path, the wide-bandwidth analog intermediate frequency signal enters the intermediate frequency signal conditioning unit, and the signal after gain adjustment and filtering enters the A / D acquisition unit. The high-speed A / D chip first completes the analog-to-digital conversion, and then transmits the high-speed digital signal to the FPGA. Finally, the result is output through the PCIE bus interface, and can also be output through the QSFP28 optical fiber and high-speed digital signal interface.

[0044] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-speed acquisition device for intermediate frequency signals with large bandwidth, characterized in that: It comprises a structural base plate (1), a structural shielding upper cover (3), a radiator (4), a fan (5) and a circuit board (6); The circuit board (6) is mounted and fixed on the structural base plate (1); the structural shielding upper cover (3) is mounted above the circuit board (6) and fixed to the structural base plate (1); the bottom of the radiator (4) is bonded to the chip on the circuit board via a thermally conductive silicone pad and is locked and fixed to the structural base plate (1); the fan (5) is mounted on the radiator (4) and fixed to the radiator (4); The circuit board is integrated with a data output unit (9), a processor unit (10), a clock unit (11), a self-calibration signal output unit (12), a high-speed A / D acquisition unit (13), a detection trigger unit (14), an intermediate frequency signal conditioning unit (15) and a signal switching unit (16); One input end of the signal switching unit (16) receives an external intermediate frequency signal, and another input end is connected to the self-calibration signal output unit (12); the output end of the signal switching unit (16) is connected to the intermediate frequency signal conditioning unit (15); the output end of the intermediate frequency signal conditioning unit (15) is respectively connected to the high-speed A / D acquisition unit (13) and the detection trigger unit (14); the output ends of the detection trigger unit (14) and the high-speed A / D acquisition unit (13) are both connected to the processor unit (10); The input end of the data output unit (9) is connected to the processor unit (10) and is used to communicate with an external device and output a signal of the processor unit; The clock unit (11) is used to receive an externally input reference clock, and the output end of the clock unit (11) is respectively connected to the processor unit (10), the high-speed A / D acquisition unit (13) and the self-calibration signal output unit (12), and is used to provide the required clock for the connected units based on the externally input or built-in reference clock; The input end of the self-calibration signal output unit (12) is connected to the processor unit (10), and the output end is connected to the signal switching unit (16), and is used to provide a self-calibration signal to the signal switching unit.

2. The high-speed acquisition device for intermediate frequency signals with large bandwidth according to claim 1, characterized in that: The high-speed acquisition device further comprises a structural side plate (2) arranged on the right side of the circuit board (6); The input and output interfaces of the high-speed acquisition device of the circuit board (6) are integrated on the circuit board (6), and a plurality of small holes are provided on the structural side plate (2). The input and output interfaces on the circuit board extend through the small holes to the outside of the structural side plate (2) to perform signal or power supply interaction with external devices.

3. The high-speed acquisition device for large-bandwidth intermediate frequency signals according to claim 1, characterized in that: The structural base plate (1) is provided with a plurality of screw holes I for fixing the circuit board (6), and the circuit board (6) is installed and fixed on the structural base plate (1) by screws penetrating the circuit board (6) and cooperating with the screw holes I on the structural base plate (1).

4. The high-speed acquisition device for intermediate frequency signals with large bandwidth according to claim 1, characterized in that: The structural base plate (1) is provided with a plurality of screw holes II for fixing the structural shielding upper cover (3), and screws are passed through the structural shielding upper cover (3) and cooperate with the screw holes II on the structural base plate (1) to lock and fix the structural shielding upper cover (3) to the structural base plate (1).

5. The high-speed acquisition device for large-bandwidth intermediate frequency signals according to claim 1, characterized in that: The structural base plate (1) is provided with a plurality of screw holes III for fixing the radiator (4), and screws are passed through the radiator (4), the thermal conductive silicone pad and the circuit board (6) and cooperate with the screw holes III on the structural base plate (1) to lock and fix the radiator (4) to the structural base plate.

6. The high-speed acquisition device for intermediate frequency signals with large bandwidth according to claim 1, characterized in that: The radiator (4) is provided with a plurality of screw holes IV, and the fan (5) is provided with a mounting plate. Screws penetrate the mounting plate of the fan (5) and cooperate with the plurality of screw holes IV on the radiator (4) to lock and fix the fan (5) to the radiator (4).

7. The high-speed acquisition device for intermediate frequency signals with large bandwidth according to claim 1, characterized in that: The circuit board is also integrated with a power supply unit (7) and a storage unit (8); the power supply unit (7) receives an external power supply input through a power connector and supplies power to the entire circuit board after DC-DC power conversion; The storage unit (8) is directly connected to the processor unit (10) and is used to provide data buffer storage for the processor unit (10) during operation.

8. The high-speed acquisition device for intermediate frequency signals with large bandwidth according to claim 7, characterized in that: The storage unit (8) comprises a FLASH memory and a DDR4 storage array; The data output unit (9) comprises a PCIE interface, a QSFP28 optical fiber module interface and a high-speed digital signal output interface; The processor unit is implemented using FPGA; The self-calibration signal output unit (12) adopts a high-speed D / A converter, which is used to convert the digital self-calibration signal output by the FPGA and transmit it to the signal switching unit.

9. The high-speed acquisition device for large-bandwidth intermediate frequency signals according to claim 1, characterized in that: The clock unit (11) comprises a power divider, a first clock chip and a second clock chip; the input end of the power divider is connected to an external reference clock via a radio frequency interface; the output end of the power divider is respectively connected to the first clock chip and the second clock chip; the first clock chip is respectively connected to a self-calibration signal output unit (12) and a processor unit (10); and the second clock chip is respectively connected to a high-speed A / D acquisition unit (13) and a processor unit (10).

10. The high-speed acquisition device for intermediate frequency signals with large bandwidth according to claim 1, characterized in that: The intermediate frequency signal conditioning unit (15) comprises a first amplifier, a first attenuator, a first signal switching switch, a second signal switching switch, a second amplifier, a second attenuator and a plurality of filters with different passbands, wherein the input end of the first amplifier is connected to the output end of the signal switching unit, the output end of the first amplifier is connected to the first attenuator, the output of the first attenuator is respectively connected to each filter via the first signal switching switch, the output end of each filter is connected to the second attenuator via the second signal switching switch, and the output end of the second attenuator is connected to the second amplifier; The detection trigger unit includes a broadband directional coupler, a logarithmic detector, a low-speed D / A converter and a comparator. The first end of the broadband directional coupler is connected to the output end of the second amplifier, and the second end is connected to the high-speed A / D acquisition unit; the coupling end of the broadband directional coupler is connected to the detector, the output end of the detector is connected to the in-phase input end of the comparator, the input end of the low-speed D / A converter is connected to the processor unit, the output end of the low-speed D / A converter is connected to the inverting input end of the comparator, and the output end of the comparator is connected to the processor unit.

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