Hardware transmission circuit

Abstract

The utility model relates to a hardware transmission circuit. The hardware transmission circuit comprises a receiver and a digital isolator, the receiver is provided with more than two signal transmission circuits; the input ends of the more than two signal transmission circuits are suitable for accessing electric signals, and the output ends of the more than two signal transmission circuits are electrically connected with the input end of the receiver; the output end of the receiver is electrically connected with the digital isolator, and the digital isolator is suitable for being electrically connected with a CPU; each of the more than two signal transmission circuits is provided with a voltage stabilizing module and an anti-interference module. The digital isolator is added between the CPU and the transceiver, interference between systems is reduced by isolating digital signals, and stable transmission of the signals is guaranteed. The voltage stabilizing module is suitable for improving the stability of the signal transmission circuit, and the anti-interference module is suitable for optimizing the high-speed signal transmission quality and the anti-interference capability of the signal transmission circuit.

Description

Technical Field

[0001] The present application relates to the technical field of transmission circuits, and in particular to a hardware transmission circuit. Background Art

[0002] In modern aviation onboard computers, asynchronous serial communication bus RS-422 is widely used to complete information exchange between onboard devices. The main control computer and the controlled system realize signal transmission through RS-422 interface, and the application of the controlled system is often more complicated, and there may be high voltage, lightning strikes, high current, strong electromagnetic coupling, etc. If it is directly connected to the main control computer system, the signal anti-interference ability of the communication circuit is poor and the reliability is low, thus affecting the normal communication between the upper computer and the lower computer. It may even destroy the communication system and cause great harm to the entire onboard computer system.

[0003] In view of the above-mentioned shortcomings of direct cross-linking, how to solve the anti-interference of signal transmission in communication applications and improve the stability and reliability of signal transmission has become an urgent problem to be solved. Summary of the invention

[0004] In view of this, the present application proposes a hardware transmission circuit suitable for improving the stability of signal transmission.

[0005] According to one aspect of the present application, there is provided a hardware transmission circuit, comprising: a receiver and a digital isolator;

[0006] The receiver is provided with more than two signal transmission circuits; the input ends of the more than two signal transmission circuits are suitable for receiving electrical signals, and the output ends of the more than two signal transmission circuits are electrically connected to the input end of the receiver; the output end of the receiver is electrically connected to the digital isolator, and the digital isolator is suitable for being electrically connected to the CPU;

[0007] More than two signal transmission circuits are equipped with a voltage stabilizing module and an anti-interference module.

[0008] In a possible implementation, four signal transmission circuits are provided;

[0009] The four signal transmission circuits are electrically connected to the four transceiver ports of the receiver respectively.

[0010] In a possible implementation, the voltage stabilization module is a transient voltage suppressor;

[0011] One end of the transient voltage suppressor is electrically connected to the signal transmission circuit, and the other end of the transient voltage suppressor is grounded.

[0012] In a possible implementation, the anti-interference module is a common-mode inductor.

[0013] In a possible implementation manner, the signal transmission circuit is provided with a filtering module.

[0014] In a possible implementation, the filter module is provided with a capacitor;

[0015] One electrode of the capacitor is electrically connected to the signal transmission circuit, and the other electrode of the capacitor is grounded.

[0016] In a possible implementation, the digital isolator uses a dual-channel digital isolator.

[0017] Beneficial effects: The receiver, as a serial communication interface, is suitable for receiving signals from the host computer and transmitting data to the CPU. The receiver adopts differential signal transmission and has high anti-interference ability and reliability. A digital isolator is added between the CPU and the transceiver to isolate the digital signal, reduce interference between systems, and ensure stable signal transmission. The voltage stabilization module is suitable for improving the stability of the signal transmission circuit, and the anti-interference module is suitable for optimizing the high-speed signal transmission quality and anti-interference ability of the signal transmission circuit.

[0018] Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present application and, together with the description, serve to explain the principles of the present application.

[0020] Figure 1 A circuit diagram showing a hardware transmission circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0022] Among them, it needs to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the utility model or simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the utility model.

[0023] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0024] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0025] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0026] Figure 1 FIG. 2 is a circuit diagram showing a hardware transmission circuit according to an embodiment of the present application. Figure 1 As shown, the hardware transmission circuit is characterized in that it includes: a receiver U17 and a digital isolator U18; the receiver U17 is provided with more than two signal transmission circuits; the input ends of the more than two signal transmission circuits are suitable for receiving signals, and the output ends of the signal transmission circuits are electrically connected to the input ends of the receiver U17; the output end of the receiver U17 is electrically connected to the digital isolator U18, and the digital isolator U18 is suitable for being electrically connected to the CPU; the more than two signal transmission circuits are provided with a voltage stabilizing module 100 and an anti-interference module 200.

[0027] Here, it should be noted that the present application is a hardware transmission circuit for the 422 communication protocol, and efficient data transmission is performed based on the 422 communication protocol. Receiver U17 is used as a serial communication interface, which is suitable for receiving signals sent by the host computer and transmitting data to the CPU. Receiver U17 adopts differential signal transmission, which has high anti-interference ability and reliability. The signal transmission circuit is suitable for receiving and transmitting signals sent by the host computer to the receiver U17 as a communication bridge between the host computer and the CPU. A digital isolator U18 is added between the CPU and the transceiver to reduce interference between systems by isolating digital signals and ensure stable signal transmission. The voltage stabilizing module 100 is suitable for improving the stability of the signal transmission circuit, and the anti-interference module 200 is suitable for optimizing the high-speed signal transmission quality and anti-interference ability of the signal transmission circuit. The present application has fast signal transmission speed, strong anti-interference ability, high stability, adapts to the transmission requirements of the 422 communication protocol, and can effectively meet the needs of modern communication systems.

[0028] In a possible implementation, four signal transmission circuits are provided; the four signal transmission circuits are electrically connected to the four transceiver ports of the receiver U17 respectively. Figure 1 As shown, the four signal transmission circuits are: a first signal transmission circuit, a second signal transmission circuit, a third signal transmission circuit and a fourth signal transmission circuit; the output end of the first signal transmission circuit is electrically connected to the 8th pin (receiving A end) of the receiver U17; the output end of the second signal transmission circuit is electrically connected to the 7th pin (receiving B end) of the receiver U17; the output end of the third signal transmission circuit is electrically connected to the 6th pin (receiving Z end) of the receiver U17; the output end of the transmission circuit is electrically connected to the 5th pin (receiving Y end) of the receiver U17.

[0029] In a possible implementation, the voltage stabilizing module 100 is a transient voltage suppressor; one end of the transient voltage suppressor is electrically connected to the signal transmission circuit, and the other end of the transient voltage suppressor is grounded. A transient voltage suppressor is added to the signal transmission circuit, which will quickly guide the excessive voltage to the ground line or the power line to prevent the transient voltage from damaging other components in the circuit. Furthermore, the transient voltage suppressor uses a bidirectional TVS transient suppression diode. The bidirectional TVS transient suppression diode absorbs surge power and can withstand reverse voltage shocks in a very short time, so that the voltage between the two poles is clamped at a specific voltage to prevent the subsequent circuit from being impacted.

[0030] In a possible implementation, four transient voltage suppressors are provided, and the four transient voltage suppressors are respectively arranged on four signal transmission circuits. One pole of the TVS transient voltage suppressor diode D3 is electrically connected to the first signal transmission circuit, and the other pole of the TVS transient voltage suppressor diode D3 is grounded; one pole of the TVS transient voltage suppressor diode D4 is electrically connected to the second signal transmission circuit, and the other pole of the TVS transient voltage suppressor diode D3 is grounded; one pole of the TVS transient voltage suppressor diode D5 is electrically connected to the third signal transmission circuit, and the other pole of the TVS transient voltage suppressor diode D5 is grounded; one pole of the TVS transient voltage suppressor diode D6 is electrically connected to the fourth signal transmission circuit, and the other pole of the TVS transient voltage suppressor diode D4 is grounded.

[0031] In a possible implementation, the anti-interference module 200 is a common-mode inductor. By adding a common-mode inductor to the input end of the signal transmission circuit, the common-mode noise on the signal transmission circuit is suppressed, the electromagnetic interference is reduced, and the high-speed signal transmission quality and anti-interference capability are optimized. In addition, the common-mode inductor can reduce the common-mode interference caused by sudden voltage in the circuit and other reasons, and improve the security and reliability of 422 communication.

[0032] In a possible implementation, two common-mode inductors are provided, and the two common-mode inductors are respectively provided on four signal transmission circuits. Figure 1As shown, the 3rd pin and the 2nd pin of the common-mode inductor T16 are connected to the first signal transmission circuit; the 4th pin and the 1st pin of the common-mode inductor T16 are connected to the second signal transmission circuit; the 3rd pin and the 2nd pin of the common-mode inductor T17 are connected to the third signal transmission circuit; the 4th pin and the 1st pin of the common-mode inductor T17 are connected to the fourth signal transmission circuit.

[0033] In a possible implementation, the signal transmission circuit is provided with an inductor; one end of the inductor is electrically connected to the receiver U17; and the other end of the inductor is electrically connected to the anti-interference module 200.

[0034] Furthermore, there are four inductors, which are respectively arranged on four signal transmission circuits. One end of the inductor L4 is electrically connected to the 8th pin (receiving A end) of the receiver U17, and the other end of the inductor L4 is electrically connected to the common mode inductor T16; one end of the inductor L5 is electrically connected to the 7th pin (receiving B end) of the receiver U17, and the other end of the inductor L5 is electrically connected to the common mode inductor T16; one end of the inductor L6 is electrically connected to the 6th pin (receiving Z end) of the receiver U17, and the other end of the inductor L6 is electrically connected to the common mode inductor 17; one end of the inductor L7 is electrically connected to the 5th pin (receiving Y end) of the receiver U17, and the other end of the inductor L8 is electrically connected to the common mode inductor T17.

[0035] In a possible implementation, the signal transmission circuit is provided with a filter module. Further, the filter module is provided with a capacitor; one pole of the capacitor is electrically connected to the signal transmission circuit, and the other pole of the capacitor is grounded; it should be noted that the capacitance of the capacitor and the resistance of the resistor can be modified according to requirements to achieve the required communication quality.

[0036] Furthermore, there are four capacitors, which are respectively arranged on four signal transmission circuits. One pole of capacitor C64 is electrically connected to the 8th pin (receiving A end) of the receiver U17, and the other pole of capacitor C64 is grounded; one pole of capacitor C65 is electrically connected to the 7th pin (receiving B end) of the receiver U17, and the other pole of capacitor C65 is grounded; one pole of capacitor C69 is electrically connected to the 6th pin (receiving Z end) of the receiver U17, and the other pole of capacitor C69 is grounded; one pole of capacitor C70 is electrically connected to the 5th pin (receiving Y end) of the receiver U17, and the other pole of capacitor C70 is grounded.

[0037] Furthermore, there are four resistors; the four resistors are respectively arranged on four signal transmission circuits. One end of the first resistor R18 is electrically connected to the first signal transmission circuit, and the other end of the first resistor R18 is connected to the voltage; one end of the second resistor R19 is electrically connected to the first signal transmission circuit, and the other end of the second resistor R19 is electrically connected to the second signal transmission circuit; one end of the third resistor R20 is electrically connected to the third signal transmission circuit, and the other end of the third resistor R20 is grounded; one end of the fourth resistor R21 is electrically connected to the third signal transmission circuit, and the other end of the fourth resistor R21 is electrically connected to the fourth signal transmission circuit.

[0038] Furthermore, the first pin (VCC terminal) of the receiver U17 is connected to a +5V voltage; the second pin (RO terminal) of the receiver U17 is electrically connected to the digital isolator U18; the third pin (DI terminal) of the receiver U17 is electrically connected to the digital isolator U18; the fourth pin of the receiver U17 is grounded. The fifth to eighth pins of the receiver U17 are respectively connected to four signal transmission circuits.

[0039] In a possible implementation, the receiver U17 is provided with a capacitor C66; one electrode of the capacitor C66 is electrically connected to a circuit to which the first pin (VCC terminal) of the receiver U17 is connected to a voltage, and the other electrode of the capacitor C66 is grounded.

[0040] In a possible implementation, the digital isolator U18 uses a dual-channel digital isolator. Further, the first pin (VDD1 terminal) of the digital isolator U18 is connected to a +3.3V operating voltage; the second pin (VOA terminal) of the digital isolator U18 is electrically connected to the CPU; the third pin (VIB terminal) of the digital isolator U18 is electrically connected to the CPU; the fourth pin (ground terminal) of the digital isolator U18 is grounded; the fifth pin (ground terminal) of the digital isolator U18 is grounded; the seventh pin (VIA terminal) of the digital isolator U18 is electrically connected to the second pin (RO terminal) of the receiver U17; the sixth pin of the digital isolator U18 is electrically connected to the third pin (DI terminal) of the receiver U17; and the eighth pin (VDD2 terminal) of the digital isolator U18 is connected to a +5V voltage.

[0041] In a possible implementation, the digital isolator U18 is provided with a capacitor C67 and a capacitor C68, one electrode of the capacitor C67 is connected to a circuit connected to a voltage at the first pin (VDDI terminal) of the digital isolator U18, and the other electrode of the capacitor C67 is grounded. One electrode of the capacitor C68 is connected to a circuit connected to a voltage at the eighth pin (VDD2 terminal) of the digital isolator U18, and the other electrode of the capacitor C68 is grounded.

[0042] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A hardware transmission circuit, characterized in that: include: Receivers and digital isolators; The receiver is provided with more than two signal transmission circuits; The input ends of two or more of the signal transmission circuits are suitable for receiving electrical signals, and the output ends of two or more of the signal transmission circuits are electrically connected to the input end of the receiver; the output end of the receiver is electrically connected to the digital isolator, and the digital isolator is suitable for being electrically connected to the CPU; More than two of the signal transmission circuits are each provided with a voltage stabilizing module and an anti-interference module.

2. The hardware transmission circuit according to claim 1, characterized in that: The signal transmission circuit is provided with four; The four signal transmission circuits are electrically connected to the four transceiver ports of the receiver respectively.

3. The hardware transmission circuit according to claim 2, characterized in that: The voltage stabilizing module is a transient voltage suppressor; One end of the transient voltage suppressor is electrically connected to the signal transmission circuit, and the other end of the transient voltage suppressor is grounded.

4. The hardware transmission circuit according to claim 2, characterized in that: The anti-interference module is a common mode inductor.

5. The hardware transmission circuit according to claim 2, characterized in that: The signal transmission circuit is provided with a filtering module.

6. The hardware transmission circuit according to claim 5, characterized in that: The filter module is provided with a capacitor; One electrode of the capacitor is electrically connected to the signal transmission circuit, and the other electrode of the capacitor is grounded.

7. The hardware transmission circuit according to claim 2, characterized in that: The digital isolator adopts a dual-channel digital isolator.

Images