OTP and electronic device
By using OTP cells of three transistors, sharing the N-type doping region and reasonably setting the signal voltage, the problems of large memory cell size and low transistor utilization in the prior art are solved, and smaller memory cells and higher transistors are realized Utilization.
Patent Information
- Application Number
- CN202421094257.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-20
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2034-05-20
AI Technical Summary
The existing OTP memory cell has large size, large size and low transistor utilization.
A cell consisting of three transistors is adopted, the middle transistor is used as the programming transistor, and the other two are selection transistors, sharing an N-type doped region as the source, and programming and reading are achieved by reasonably setting the voltage of the gate and selection signal. Get the operation.
On the basis of maintaining high reliability and high security, the number of transistors stored in one bit cell is reduced, from four to three, significantly reducing the size and volume of the memory cell and improving the utilization of transistors.
Smart Images
Figure CN222260529U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of electronic devices, and in particular to an OTP and an electronic device. Background Art
[0002] OTP (One Time Programmable) is a special type of non-volatile memory that can be programmed only once. Once programmed, the data is permanently valid.
[0003] Compared with MTP (Multi-Time Programmable) such as EEPROM (Electrically Erasable Programmable Read-Only Memory), OTP has a smaller area and does not require additional manufacturing steps. Therefore, it is widely used in low-cost chips. OTP is often used to store reliable and repeatable data, such as boot programs, encryption keys, analog device configuration parameters, etc.
[0004] Anti-Fuse is an OTP that applies a high voltage to a thin gate oxide to short the gate and source of the transistor through avalanche breakdown for programming. The basic unit of Anti-Fuse is composed of two transistors, one is a programming transistor and the other is a read or select transistor (referred to as select transistor) used to store a bit.
[0005] In order to improve reliability and security, two programming transistors and two selection transistors are now used as a unit to store one bit. The two programming transistors back up each other, and the two selection transistors back up each other. However, using four transistors to store one bit will result in a large memory cell size, a large memory volume, and low transistor utilization. Utility Model Content
[0006] The technical problem to be solved by the present disclosure is to provide an OTP and an electronic device in order to overcome the defects of the prior art that the memory unit has a large size, the memory has a large volume, and the utilization rate of transistors is low.
[0007] The present invention solves the above technical problems through the following technical solutions:
[0008] The present disclosure provides an OTP, the OTP comprising: an array consisting of a plurality of units;
[0009] Each of the units includes three transistors arranged in sequence;
[0010] In each of the units, the middle transistor is used as a programming transistor, and the remaining two transistors are used as selection transistors. The programming transistor and any one of the two selection transistors share an N-type doping region as a source.
[0011] Optionally, a first gate signal is introduced into the top of the programming transistor, a second gate signal is introduced from the top of the selection transistor, and a selection signal is introduced from an N-type doped region of the selection transistor on a side away from the programming transistor.
[0012] Optionally, selection transistors in the same row receive the same selection signal.
[0013] Optionally, programming transistors in the same column are introduced with the same first gate signal;
[0014] The selection transistors in the same column receive the same second gate signal.
[0015] Optionally, in a programming scenario, for a target cell to be programmed, the first gate signal is set to a preset first voltage, the second gate signal is set to a preset second voltage, and the selection signal is set to a preset third voltage;
[0016] The first voltage is greater than the second voltage, the second voltage is greater than the third voltage, and the third voltage is greater than or equal to zero.
[0017] Optionally, in a programming scenario, for other cells in the same column other than the target cell, the selection signal is set to the second voltage;
[0018] For other cells in different columns other than the target cell, the selection signal is set to the second voltage, and the first gate signal and the second gate signal are both set to the third voltage.
[0019] Optionally, in a reading scenario, for a target cell to be read, the first gate signal is set to the third voltage, the second gate signal is set to the second voltage, and the selection signal is set to the second voltage.
[0020] Optionally, in a reading scenario, for other cells in the same column other than the target cell, the selection signal is set to the third voltage;
[0021] For other cells in different columns other than the target cell, the selection signal is set to the third voltage, and both the first gate signal and the second gate signal are set to the third voltage.
[0022] The present disclosure also provides an electronic device, which includes the above-mentioned OTP.
[0023] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.
[0024] The positive progressive effect of the present disclosure is that, on the basis of maintaining high reliability and high security, the number of transistors in a unit storing one bit is reduced, and the number of transistors required in a unit is reduced from four transistors to only three transistors, which greatly reduces the size of the memory unit, reduces the volume of the memory, and improves the utilization rate of the transistors. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 A schematic diagram of the structure of an OTP provided in Example 1 of the present disclosure;
[0026] Figure 2 A schematic diagram of the structure of an Anti-Fuse basic unit of an OTP provided in Example 1 of the present disclosure;
[0027] Figure 3 A schematic diagram of a structure of a prior art OTP using two programming transistors and two selection transistors as a unit provided in Embodiment 1 of the present disclosure;
[0028] Figure 4 A structural schematic diagram of an example of setting a signal voltage of an OTP in a programming scenario provided in Embodiment 1 of the present disclosure;
[0029] Figure 5 A structural diagram of a target unit of an OTP in a programming scenario provided in Embodiment 1 of the present disclosure;
[0030] Figure 6 A structural diagram of a non-target unit of an OTP in a programming scenario provided in Embodiment 1 of the present disclosure;
[0031] Figure 7 A structural diagram of an example of setting the signal voltage of an OTP in a reading scenario provided in Embodiment 1 of the present disclosure. DETAILED DESCRIPTION
[0032] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.
[0033] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.
[0034] Example 1
[0035] Figure 1 The schematic diagram of the structure of an OTP provided by an exemplary embodiment of the present disclosure includes: an array composed of a plurality of units, and the solid-line frame and the dotted-line frame in the figure each represent a unit.
[0036] Each cell consists of three transistors arranged in series.
[0037] The three transistors in each unit are divided into a programming transistor and two selection transistors, that is, in each unit, the middle transistor is used as a programming transistor, and the remaining two transistors are used as selection transistors. The programming transistor and any one of the two selection transistors share an N-type doped region as a source. Figure 1 In the embodiment, the N-type doped regions are arranged alternately with the gates of the transistors, each of the gates of the transistors has an N-type doped region on both sides, and adjacent transistors share one N-type doped region.
[0038] Among them, the OTP of this embodiment adopts Anti-Fuse, and the basic unit of Anti-Fuse is composed of two adjacent transistors, one is a programming transistor and the other is a selection transistor, which is used to store a bit, such as Figure 2 A high voltage is applied to the thin gate oxide to short the gate and source of the transistor through avalanche breakdown for programming. Figure 2 The programming transistor is WLP, the selection transistor is WLR, the oval box shows the avalanche breakdown on the gate oxide, and the N-type doped region (N+) between the programming transistor and the selection transistor is the common source of the programming transistor and the selection transistor.
[0039] When the programming transistor is not broken down by avalanche, the programming transistor is equivalent to a large resistor. Even if voltage is applied to the gate of the programming transistor (the top of WLP), the gate of the selection transistor (the top of WLR), and the side of the selection transistor away from the programming transistor (at SL), the current collected by the selection transistor (at SL) is still very small and less than the current threshold.
[0040] When the programming transistor is avalanche-broken, the programming transistor and the selection transistor are equivalent to a short circuit with very small resistance. Voltage is applied to the gate of the programming transistor (top of WLP), the gate of the selection transistor (top of WLR), and the side of the selection transistor away from the programming transistor (at SL). The current generated by the selection transistor passes through the shared source in the middle and the avalanche breakdown channel in the programming transistor. The current collected by the selection transistor (at SL) is greater than the current threshold.
[0041] By setting the current threshold properly, the bits stored in the programming transistor can be identified. When the current is greater than the current threshold, the state can be identified as bit "1", and when the current is less than the current threshold, the state can be identified as bit "0"; or when the current is greater than the current threshold, the state can be identified as bit "0", and when the current is less than the current threshold, the state can be identified as bit "1".
[0042] Two programming transistors and two selection transistors are used as a unit to store a bit (the structural diagram is shown in FIG. Figure 3 As shown), and in the case where one programming transistor and two selection transistors are used as a unit to store one bit, the programming and reading principles are similar to those described above and will not be repeated here.
[0043] In this embodiment, on the basis of maintaining high reliability and high security, the number of transistors in a unit storing one bit is reduced, and the number of transistors required in a unit is reduced from four transistors to only three transistors, which greatly reduces the size of the memory unit, reduces the volume of the memory, and improves the utilization rate of the transistors.
[0044] In one embodiment, a first gate signal is introduced from the top of the programming transistor, a second gate signal is introduced from the top of the selection transistor, and a selection signal is introduced from an N-type doping region on a side of the selection transistor away from the programming transistor.
[0045] The top of the transistor is the gate of the transistor.
[0046] In one embodiment, the select transistors in the same row receive the same select signal.
[0047] It can be understood that rows and columns are relative concepts for display, indicating two mutually perpendicular directions in the display and positions in these two directions.
[0048] Since transistors are densely arranged, in order to facilitate manufacturing, control and use, the gates of the selection transistors in the same row are electrically connected and the same selection signal is introduced. Figure 1 In the figure, SL0, SL1 and SL2 are selection signals, corresponding to three rows of selection transistors respectively.
[0049] In one embodiment, programming transistors in the same column receive the same first gate signal.
[0050] The selection transistors in the same column receive the same second gate signal.
[0051] It can be understood that rows and columns are relative concepts for display, indicating two mutually perpendicular directions in the display and positions in these two directions.
[0052] Since transistors are densely arranged, in order to facilitate manufacturing, control and use, the gates of programming transistors in the same column are electrically connected ( Figure 1 The same first gate signal is introduced; the gates of the selection transistors in the same column are electrically connected ( Figure 1 The same second gate signal is introduced. For example, Figure 1 In the figure, WLP0 and WLP2 are both first gate signals, corresponding to two columns of programming transistors respectively; WLR0 and WLR2 are both second gate signals, where the selection transistors in the same unit introduce the same second gate signal, and WLR0 and WLR2 correspond to four columns of selection transistors respectively.
[0053] In one embodiment, in a programming scenario, for a target cell to be programmed, the first gate signal is set to a preset first voltage, the second gate signal is set to a preset second voltage, and the selection signal is set to a preset third voltage.
[0054] The first voltage is greater than the second voltage, the second voltage is greater than the third voltage, and the third voltage is greater than or equal to zero.
[0055] Among them, OTP only programs one unit at a time in the programming scenario. Figure 4 An example of setting the signal voltage of OTP in a programming scenario is shown. The solid-line box represents the target cell to be programmed, the dotted-line box represents the cell other than the target cell, the first voltage is set to 5.2V (volts), the second voltage is set to 0.9V, and the third voltage is set to 0V.
[0056] The first voltage, the second voltage and the third voltage can be set according to actual conditions. In the programming scenario, the voltage above the gate oxide (WLP0) of the programming transistor in the target cell is the first voltage, and the voltage below the gate oxide (SL1) is the third voltage. Figure 5 The voltage difference between the first voltage and the third voltage needs to be large enough to achieve avalanche breakdown of the gate oxide of the programming transistor, so that the target cell can be programmed successfully.
[0057] In one embodiment, referring to Figure 4In a programming scenario, for other cells in the same column other than the target cell (ie, non-target cells in the same column), the selection signal is set to the second voltage.
[0058] For other cells in different columns other than the target cell (ie, non-target cells in different columns), the selection signal is set to the second voltage, and the first gate signal and the second gate signal are both set to the third voltage.
[0059] In the programming scenario, the voltage above the gate oxide (WLP0) of the programming transistor in the non-target cells of the same column is a first voltage, and the voltage below the gate oxide (SL0 and SL2) is a second voltage. Figure 6 As shown. The voltage difference between the first voltage and the second voltage needs to be small enough to prevent the gate oxide of the programming transistor in the non-target cell from being avalanche-broken. The voltage above the gate oxide of the programming transistor in the non-target cell of different columns (WLP1) is the third voltage, and the voltage below the gate oxide (SL0 and SL2) is the second voltage, which makes it even more impossible to avalanche-broken the gate oxide.
[0060] In this way, when the programming transistor in the target cell is programmed, the programming transistor in the non-target cell will not be programmed, thereby avoiding program disturbance.
[0061] In one embodiment, in a read scenario, for a target cell to be read, the first gate signal is set to the third voltage, the second gate signal is set to the second voltage, and the selection signal is set to the second voltage.
[0062] The first voltage is greater than the second voltage, the second voltage is greater than the third voltage, and the third voltage is greater than or equal to zero.
[0063] In the read scenario, OTP reads only one unit at a time. Figure 7 An example of setting the signal voltage of OTP in a reading scenario is shown, where the solid-line frame represents the target cell to be read, the dotted-line frame represents the cell other than the target cell, the first voltage is set to 5.2V, the second voltage is set to 0.9V, and the third voltage is set to 0V.
[0064] The first voltage, the second voltage, and the third voltage can be set according to actual conditions. In a read scenario, the gate voltage (WLR0) of the selection transistor in the target cell is the second voltage, the selection voltage (SL1) is the second voltage, the gate voltage (WLP0) of the programming transistor is the third voltage, and a voltage difference is formed between the gate of the selection transistor and the gate of the programming transistor. Under the positive excitation of the selection voltage (SL1), a large current is generated when the programming transistor has been avalanche-broken, and a current greater than the current threshold is generated on the side of the selection transistor away from the programming transistor.
[0065] In one embodiment, referring to Figure 7,In the read scenario, for other cells in the same column except the target cell, the selection signal is set to a third voltage.
[0066] For other cells in different columns other than the target cell, the selection signal is set to a third voltage, and both the first gate signal and the second gate signal are set to the third voltage.
[0067] Among them, in the reading scenario, the gate voltage (WLR0) of the selection transistor in the non-target unit in the same column is the second voltage, the selection voltage (SL0 and SL2) is the third voltage, and the gate voltage (WLP0) of the programming transistor is the third voltage. The gate of the selection transistor forms a voltage difference with respect to the gate of the programming transistor. Since the selection voltage (SL0 and SL2) does not form a positive excitation, even if the programming transistor has been avalanche broken down, a large current cannot be generated. A current greater than the current threshold cannot be generated on the side of the selection transistor away from the programming transistor, and no erroneous reading results will occur.
[0068] The gate voltage (WLR1) of the selection transistor in non-target cells of different columns is the third voltage, the selection voltages (SL0 and SL2) are the third voltage, and the gate voltage (WLP1) of the programming transistor is also the third voltage. A current greater than the current threshold cannot be generated on the side of the selection transistor away from the programming transistor, and no erroneous reading results will occur.
[0069] Example 2
[0070] This embodiment provides an electronic device, and the electronic device includes the OTP described in any of the above embodiments.
[0071] In this embodiment, on the basis of maintaining high reliability and high security, the number of transistors in a unit storing one bit is reduced, and the number of transistors required in a unit is reduced from four transistors to only three transistors, which greatly reduces the size of the memory unit, reduces the volume of the memory, and improves the utilization rate of the transistors.
[0072] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.
Claims
1. An OTP, characterized in that: The OTP comprises: an array consisting of a number of units; Each of the units includes three transistors arranged in sequence; In each of the units, the middle transistor is used as a programming transistor, and the remaining two transistors are used as selection transistors. The programming transistor and any one of the two selection transistors share an N-type doping region as a source.
2. The OTP according to claim 1, wherein: A first gate signal is introduced from the top of the programming transistor, a second gate signal is introduced from the top of the selection transistor, and a selection signal is introduced from an N-type doping region on a side of the selection transistor away from the programming transistor.
3. The OTP as claimed in claim 2, characterized in that The selection transistors in the same row receive the same selection signal.
4. The OTP as claimed in claim 2, characterized in that The programming transistors in the same column are introduced with the same first gate signal; The selection transistors in the same column receive the same second gate signal.
5. The OTP according to claim 2, wherein: In a programming scenario, for a target cell to be programmed, the first gate signal is set to a preset first voltage, the second gate signal is set to a preset second voltage, and the selection signal is set to a preset third voltage; The first voltage is greater than the second voltage, the second voltage is greater than the third voltage, and the third voltage is greater than or equal to zero.
6. The OTP according to claim 5, wherein: In a programming scenario, for other cells in the same column other than the target cell, the selection signal is set to the second voltage; For other cells in different columns other than the target cell, the selection signal is set to the second voltage, and the first gate signal and the second gate signal are both set to the third voltage.
7. The OTP according to claim 5, wherein: In a reading scenario, for a target cell to be read, the first gate signal is set to the third voltage, the second gate signal is set to the second voltage, and the selection signal is set to the second voltage.
8. The OTP according to claim 7, wherein: In a read scenario, for other cells in the same column other than the target cell, the selection signal is set to the third voltage; For other cells in different columns other than the target cell, the selection signal is set to the third voltage, and both the first gate signal and the second gate signal are set to the third voltage.
9. An electronic device, characterized in that: The electronic device comprises the OTP according to any one of claims 1 to 8.