Multi-chip packaging structure

Abstract

The utility model provides a multi-chip packaging structure. The multi-chip packaging structure comprises a carrier plate; the plurality of chips are arranged on the carrier plate in an inverted manner, and a channel is formed between every two adjacent chips; the plug-in is arranged in the channel and in the direction perpendicular to the carrier plate, the plug-in comprises a first section close to the carrier plate and a second section arranged on the first section, and the first section is of a mesh structure; the bottom filling layer is filled between the chip and the carrier plate, and the first section of the plug-in is filled with the bottom filling layer; and the plastic packaging layer covers the carrier plate, the chip, the plug-in and the bottom filling layer. According to the multi-chip packaging structure provided by the embodiment of the utility model, the probability of cavities in the channels is reduced, the situation that the glue amount at other positions of the chip exceeds the design limit due to the fact that enough glue amount is filled in the channels is avoided, the glue stress is reduced, and the probability of hidden cracks of the chip is further reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of packaging, in particular to a multi-chip packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, a new design method of chiplet technology has emerged, which packages small chips with different functions together to form a heterogeneous integrated chip packaging structure. As the input and output density of chips becomes higher and higher, the number of chips integrated in a single package has increased significantly.

[0003] The existing 2.5D packaging technology is to package multiple small chips onto a carrier board as a multi-chip packaging solution to connect adjacent chip pads in a single package to improve its packaging integration. It mainly mounts multiple flip chips on the carrier board, and then uses the bottom filling colloid as a protective layer to protect the solder joints of the flip chips. However, there is a channel between the chips. When the bottom of the chip is filled, the bottom filling glue relies on capillary action to fill the bottom of multiple chips, and it will also fill the channel. On the one hand, the channel width is wide, which is not conducive to the bottom filling glue climbing by capillary action. If the amount of glue filled in the channel is too little, it is easy to cause voids; on the other hand, if it is necessary to fill the channel with enough glue, the amount of glue in other positions of the chip will greatly exceed the design limit, and it is easy to cause chip cracks due to the stress generated by the colloid. Summary of the invention

[0004] The technical problem to be solved by the utility model is to improve the problem of hidden cracks of chips and the appearance of voids in channels in a multi-chip packaging structure, and to improve the reliability and yield of the packaging structure.

[0005] In order to solve the above technical problems, an embodiment of the utility model provides a multi-chip packaging structure, including: a carrier; a plurality of chips, the chips are flip-chip arranged on the carrier, and there is a channel between adjacent chips; a plug-in, arranged in the channel, in a direction perpendicular to the carrier, the plug-in includes a first section close to the carrier and a second section arranged on the first section, wherein the first section is a mesh structure; a bottom filling layer, filled between the chip and the carrier, and filled with the first section of the plug-in; a plastic encapsulation layer, covering the carrier, the chip, the plug-in and the bottom filling layer.

[0006] In one embodiment, the second section of the insert is a solid structure.

[0007] In one embodiment, in a direction perpendicular to the carrier, the distance between the bottom surface of the second section of the plug-in and the carrier is smaller in the middle and larger at both ends.

[0008] In one embodiment, in a direction perpendicular to the carrier, a plane where the highest point of the first section is located is located between the upper surface and the lower surface of the chip.

[0009] In one embodiment, the packaging structure includes a first chip, a second chip and a third chip. In a first direction, the second chip and the third chip are arranged on the same side of the first chip. A first sub-channel is provided between the first chip and the second chip and the third chip, and a second sub-channel is provided between the second chip and the third chip. The first sub-channel and the second sub-channel are interconnected. The plug-in includes a first sub-plug-in provided in the first sub-channel and a second sub-plug-in provided in the second sub-channel, and the middle part of the first sub-plug-in intersects with the end part of the second sub-plug-in.

[0010] In one embodiment, in a direction perpendicular to the carrier, from the end of the first sub-package to the intersection, the distance between the bottom surface of the second section of the first sub-package and the carrier gradually decreases.

[0011] In one embodiment, in a direction perpendicular to the carrier, from the end of the second sub-package away from the first sub-package to the intersection, the distance between the bottom surface of the second section of the second sub-package and the carrier gradually decreases.

[0012] In one embodiment, at the intersection, the distance between the bottom surface of the second section of the first sub-plug and the carrier board is equal to the distance between the bottom surface of the second section of the second sub-plug and the carrier board.

[0013] In one embodiment, there is a gap between the second section of the plug and the side wall of the chip, and the bottom filling layer and / or the plastic packaging layer fills the gap.

[0014] In one embodiment, the second section of the plug-in includes a mesh structure, and the plastic packaging layer is fully filled with the mesh structure.

[0015] In one embodiment, the second sections of the plug-in are all mesh structures, or the second sections of the plug-in include a solid structure and a mesh structure, and the solid structure connects the mesh structure and the first section.

[0016] In the multi-chip packaging structure provided by the embodiment of the utility model, the plug-in is arranged in the groove between the chips, and the end of the plug-in close to the carrier board is a mesh structure. When the bottom filling glue is filled to form a bottom filling layer, the mesh structure enables the bottom filling glue to climb up and fill the groove by capillary action, thereby increasing the amount of glue filled in the groove and reducing the probability of voids in the groove; at the same time, the plug-in occupies part of the space of the groove, so that the amount of bottom filling glue in the groove is controlled, and the demand for the amount of bottom filling glue in the groove is also greatly reduced, thereby avoiding the situation where the amount of glue at other positions of the chip exceeds the design limit in order to fill the groove with enough glue, reducing the colloid stress, thereby reducing the probability of chip hidden cracks, and improving the reliability and yield of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a top view schematic diagram of a multi-chip packaging structure provided by an embodiment of the utility model;

[0019] Figure 2 is along Figure 1 Cross-section along line AA;

[0020] Figure 3 is along Figure 1 Cross-section along line BB;

[0021] Figure 4 is along Figure 1 Cross-section of the mid-CC line;

[0022] Figure 5 yes Figure 1 A schematic diagram showing the distribution of chips of a multi-chip package structure on a carrier board;

[0023] Figure 6 This is a schematic diagram of the distribution of chips on a carrier board of a multi-chip packaging structure provided by another embodiment of the utility model;

[0024] Figure 7 So Figure 6 A cross-sectional view of a package structure formed by the distribution of the chips shown along line DD;

[0025] Figure 8 is a schematic diagram of a plug-in provided in another embodiment of the utility model;

[0026] Fig. 9 It is a schematic diagram of a plug-in provided in yet another embodiment of the utility model. DETAILED DESCRIPTION

[0027] The specific implementation of the multi-chip packaging structure provided by the utility model is described in detail below with reference to the accompanying drawings.

[0028] Figure 1 is a top view schematic diagram of a multi-chip packaging structure provided by an embodiment of the utility model, Figure 2 is along Figure 1 The cross-section diagram along the AA line. Figure 3 is along Figure 1 The cross-section of the BB line. Figure 4 is along Figure 1 For a cross-sectional view of the CC line, please refer to Figure 1 to Figure 4 A multi-chip packaging structure includes: a carrier 100; a plurality of chips, wherein the chips are flip-chip mounted on the carrier 100, and there are channels between adjacent chips; a plug-in, which is arranged in the channel, and in a direction perpendicular to the carrier 100, the plug-in includes a first section 110 close to the carrier 100 and a second section 120 arranged on the first section 110, wherein the first section 110 is a mesh structure; a bottom filling layer 130, which is filled between the chip and the carrier 100 and fills the first section 110 of the plug-in; and a plastic sealing layer 140, which covers the carrier 100, the chip, the plug-in and the bottom filling layer 130. In order to clearly show the features of the multi-chip packaging structure of the present invention, Figure 1 The plastic encapsulation layer 140 is not shown.

[0029] In the multi-chip packaging structure provided by the embodiment of the utility model, the plug-in is arranged in the groove between the chips, and the end of the plug-in close to the carrier board 100 is a mesh structure. When the bottom filling glue is filled to form the bottom filling layer 130, the mesh structure enables the bottom filling glue to climb up and fill the groove by capillary action, thereby increasing the amount of glue filled in the groove and reducing the probability of voids in the groove; at the same time, the plug-in occupies part of the space of the groove, so that the amount of the bottom filling glue in the groove is controlled, and the demand for the amount of the bottom filling glue in the groove is also greatly reduced, thereby avoiding the situation where the amount of glue at other positions of the chip exceeds the design limit in order to fill the groove with enough glue, reducing the colloid stress, thereby reducing the probability of chip hidden cracks, and improving the reliability and yield of the packaging structure.

[0030] The carrier 100 is used to carry the chip and realize the electrical connection between the chip and external devices. The carrier 100 includes but is not limited to a substrate and an adapter board. In this embodiment, the chip is flipped on the carrier 100, and a solder ball 200 is arranged on the surface of the carrier 100 away from the chip. The chip is electrically connected to the solder ball 200 through the carrier 100, and the solder ball 200 can be electrically connected to an external device, for example, the solder ball 200 is electrically connected to a PCB board, so as to realize the function of the packaging structure.

[0031] The packaging structure includes a plurality of the chips, and the plurality of the chips are flip-mounted on the carrier 100 . There is a channel between adjacent chips, and the channel exposes the carrier 100 . The plug-in is disposed in the channel.

[0032] Specifically, if Figure 5 As shown, it is Figure 1 The schematic diagram of the distribution of chips of the multi-chip package structure on the carrier is shown. In this embodiment, three chips are flip-chip mounted on the carrier 100, namely, a first chip 151, a second chip 152 and a third chip 153. In the first direction D1, the second chip 152 and the third chip 153 are arranged on the same side of the first chip 151, and the second chip 152 and the third chip 153 are arranged along the second direction D2. The first direction D1 and the second direction D2 are both parallel to the surface of the carrier 100, and the first direction D1 is perpendicular to the second direction D2. A first sub-channel 161 is provided between the first chip 151 and the second chip 152 and the third chip 153, and a second sub-channel 162 is provided between the second chip 152 and the third chip 153. The first sub-channel 161 and the second sub-channel 162 are connected to each other and exposed from the carrier 100. In this embodiment, the size of the first chip 151 is larger than that of the second chip 152 and the third chip 153, so that one side of the first chip 151 can form the first sub-channel 161 with the second chip 152 and the third chip 153, and the first sub-channel 161 and the second sub-channel 162 are connected to each other to form a T-shaped channel. The sizes of the second chip 152 and the third chip 153 can be equal or different.

[0033] The plug is disposed in the channel. Figure 1 to Figure 5In this embodiment, the plug-in includes a first sub-plug-in 171 disposed in the first sub-channel 161 and a second sub-plug-in 172 disposed in the second sub-channel 162. The middle of the first sub-plug-in 171 intersects with the end of the second sub-plug-in 172 to form a T-shaped plug-in. The connection position of the first sub-plug-in 171 and the second sub-plug-in 172 depends on the relative position of the first sub-channel 161 and the second sub-channel 162. It can be understood that the first sub-plug-in 171 and the second sub-plug-in 172 can be integrally formed. Figure 3 In order to clearly show the structure, dotted lines are used to schematically separate the first sub-plug-in 171 and the second sub-plug-in 172 .

[0034] In another embodiment, if Figure 6 As shown, it is a schematic diagram of the distribution of chips of a multi-chip package structure provided by another embodiment of the utility model on the carrier 100. In this embodiment, two chips are flip-chip mounted on the carrier 100, namely, a fourth chip 154 ​​and a fifth chip 155. In the first direction D1, the fifth chip 155 is arranged on one side of the fourth chip 154. There is a third sub-channel 163 between the fourth chip 154 ​​and the fifth chip 155, and the third sub-channel 163 exposes the carrier 100. In this embodiment, the third sub-channel 163 is a linear channel.

[0035] The plug is disposed in the channel. Figure 7 , which is based on Figure 6 The cross-sectional view of the package structure formed by the distribution of the chips shown is taken along the DD line. The plug-in includes a third sub-plug-in 173 disposed in the third sub-channel 163. The third sub-plug-in 173 is a linear plug-in.

[0036] It can be understood that the above-mentioned embodiment only schematically lists the distribution method of the chips on the carrier 100 and the structural form of the plug-in. In other embodiments of the utility model, four or more chips can be flip-chip set on the carrier 100, and the distribution of multiple chips can be set according to actual needs. There is a channel between adjacent chips, and the structural form of the plug-in can be set according to the arrangement of the channel.

[0037] In some embodiments, the plug-in is an insulating plug-in to insulate and isolate the adjacent chips. The material of the plug-in can be the same as the material of the molding compound or the material of the chip.

[0038] In this embodiment, the upper surface of the insert is flush with the upper surface of the chip, and the lower surface of the insert contacts the surface of the carrier 100. In another embodiment, the upper surface of the insert may be slightly higher or lower than the upper surface of the chip.

[0039] In a direction perpendicular to the carrier 100, for example, the third direction D3, i.e., the depth direction of the channel, the plug-in includes a first section 110 and a second section 120. The first section 110 is a region of the plug-in close to the carrier 100, and the lower surface of the first section 110 is the lower surface of the plug-in. The lower surface of the first section 110 can contact the carrier 100 or have a set gap with the carrier 100. The second section 120 is a region of the plug-in away from the carrier 100, and the upper surface of the second section 120 is the upper surface of the plug-in.

[0040] The first section 110 is a mesh structure. For example, in the first section 110, the plug-in is composed of a plurality of insulating strips crisscrossed to form a mesh structure. In the packaging process, when the bottom of the chip is filled, the bottom filling glue relies on capillary action to fill the bottom of multiple chips, and the mesh structure of the first section 110 makes it easier for the bottom filling glue to climb and fill in the channel by its capillary action, filling the channel completely and not prone to voids.

[0041] In this embodiment, the second section 120 of the plug-in is a solid structure, that is, the second section 120 does not have a mesh structure, which can increase the strength of the plug-in, improve the reliability of the packaging structure, and can further occupy part of the space of the channel, so that the amount of bottom filling glue in the channel can be controlled, and the demand for the amount of bottom filling glue in the channel is also greatly reduced, avoiding the situation where the amount of glue at other positions of the chip exceeds the design limit in order to fill the channel with enough glue, reducing the colloid stress, thereby reducing the probability of chip hidden cracks, and improving the reliability and yield of the packaging structure.

[0042] In one embodiment, in a direction perpendicular to the carrier 100, the distance between the bottom surface of the second section 120 of the plug-in and the carrier 100 is smaller in the middle and larger at both ends. When the bottom of the chip is filled, bubbles can be discharged from both sides of the second section 120, thereby further avoiding the generation of voids.

[0043] In one embodiment, in a direction perpendicular to the carrier 100 , for example, the third direction D3 , the plane where the highest point of the first section 110 is located is located between the upper surface and the lower surface of the chip.

[0044] For example, see Figure 7In a direction perpendicular to the carrier 100, for example, in the third direction D3, i.e., the height direction of the plug-in, the distance between the bottom surface of the second section 120 of the third sub-plug-in 173 and the carrier 100 is smaller in the middle and larger at both ends, i.e., the bottom surface of the second section 120 of the third sub-plug-in 173 is V-shaped, and the distance from the edge of the bottom surface of the second section 120 to the carrier 100 is greater than the distance from the middle of the bottom surface of the second section 120 to the carrier 100. When the bottom of the chip is filled, bubbles can be discharged from the middle to the edge along the bottom surface of the second section 120, thereby further avoiding the generation of voids.

[0045] For another example, see Figure 1 to Figure 4 , in the direction perpendicular to the carrier 100, from the end of the first sub-plug 171 to the intersection, the distance between the bottom surface of the second section 120 of the first sub-plug 171 and the carrier 100 gradually decreases, that is, the bottom surface of the second section 120 of the first sub-plug 171 is V-shaped, when the bottom of the chip is filled, the bubbles can be discharged from the intersection to the edge along the bottom surface of the second section 120 of the first sub-plug 171, thereby further avoiding the generation of voids. In this embodiment, from the end of the second sub-plug 172 away from the first sub-plug 171 to the intersection, the distance between the bottom surface of the second section 120 of the second sub-plug 172 and the carrier 100 gradually decreases, that is, the bottom surface of the second section 120 of the second sub-plug 172 is sloped, when the bottom of the chip is filled, the bubbles can be discharged from the intersection to the edge along the bottom surface of the second section 120 of the second sub-plug 172, thereby further avoiding the generation of voids.

[0046] Furthermore, in the present embodiment, at the intersection, the distance between the bottom surface of the second section 120 of the first sub-plug-in 171 and the carrier 100, and the distance between the bottom surface of the second section 120 of the second sub-plug-in 172 and the carrier 100 are equal, so as to avoid the retention of bubbles due to the height difference between the bottom surfaces of the second sections 120 of the first sub-plug-in 171 and the second sub-plug-in 172 at the intersection, thereby further avoiding the generation of voids.

[0047] Furthermore, in some embodiments, there is a gap between the second section 120 of the plug-in and the side wall of the chip, and the bottom filling layer 130 and / or the plastic encapsulation layer 140 fill the gap. In the packaging process, limited by the process conditions, there may be a gap between the second section 120 of the plug-in and the side wall of the chip. The gap is very small, so when the bottom of the chip is filled, the bottom filling glue can rely on capillary action to fill in the gap. In other embodiments, if the bottom filling glue cannot completely climb up and fill the gap due to capillary action, the plastic encapsulation material can be filled from the top of the gap, so that the remaining area of ​​the gap is filled with the plastic encapsulation layer 140.

[0048] In the above-mentioned embodiment, the second section 120 is a solid structure. In other embodiments, the second section 120 of the plug-in includes a mesh structure, and the plastic sealing layer 140 is filled with the mesh structure.

[0049] For example, see Figure 8 , which is a schematic diagram of a plug-in provided by another embodiment of the utility model. In this embodiment, the second section 120 of the plug-in is a mesh structure. In the packaging structure, the plastic sealing layer 140 fills the mesh structure. In this embodiment, the entire area of ​​the plug-in (including the first section 110 and the second section 120) is a mesh structure. The bottom of the structure (i.e., the first section 110) is filled with the bottom filling layer 130, and the top of the structure (i.e., the second section 120) is filled with the plastic sealing layer 140. In the packaging process, when the bottom of the chip is filled, the bottom filling glue relies on its capillary action to climb and fill in the plug-in. It may only climb to a certain height, and the remaining area of ​​the plug-in is not filled with the bottom filling glue. In the subsequent plastic sealing process, the plastic sealing glue can penetrate into the plug-in and fill the remaining space of the plug-in, so that the channel is filled with the bottom filling layer 130 and the plastic sealing layer 140, thereby avoiding the occurrence of voids. It can be understood that the mesh structure of the first section 110 and the mesh structure of the second section 120 are integrally formed. Figure 8 A dotted line is used to schematically indicate the boundary between the two.

[0050] For another example, see Fig. 9, which is a schematic diagram of a plug-in provided in yet another embodiment of the present invention, wherein the second section 120 of the plug-in includes a solid structure 121 and a mesh structure 122, wherein the solid structure 121 connects the mesh structure 122 and the first section 110, and the plastic encapsulation layer 140 fills the mesh structure 122. In this embodiment, the solid structure 121 can further enhance the strength of the plug-in, and can reduce the demand for the amount of bottom filling glue in the channel, thereby avoiding the situation where the amount of glue in other parts of the chip exceeds the design limit in order to fill the channel with enough glue, thereby reducing the glue stress, thereby reducing the probability of chip cracking, and improving the reliability and yield of the packaging structure. Furthermore, in some embodiments, the shape design of the bottom surface of the second section 120 can refer to Figure 2 to Figure 4 .

[0051] It can be understood that the above is only an example of the plug-in. Under the condition of meeting the purpose of the utility model, the specific form of the plug-in can be set according to actual needs.

[0052] The multi-chip packaging structure provided by the embodiment of the utility model reduces the probability of voids appearing in the channel and greatly reduces the demand for the amount of bottom filling glue in the channel, thereby avoiding the situation where the amount of glue in other positions of the chip exceeds the design limit in order to fill the channel with enough glue, reducing the colloid stress, and further reducing the probability of chip hidden cracks, thereby improving the reliability and yield of the packaging structure.

[0053] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present utility model are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates, and it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context, and can be used to describe features, structures or characteristics in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow the presence of other factors that are not necessarily explicitly described. In addition, in the absence of conflict, the embodiments of the present utility model and the features in the embodiments can be combined with each other. In addition, in the above description, the description of known components and technologies is omitted to avoid unnecessary confusion of the concept of the present utility model. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0054] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A multi-chip packaging structure, characterized in that: include: Carrier board; A plurality of chips, wherein the chips are flip-chip mounted on the carrier, and channels are provided between adjacent chips; A plug-in is arranged in the channel, and in a direction perpendicular to the carrier, the plug-in includes a first section close to the carrier and a second section arranged on the first section, wherein the first section is a mesh structure; A bottom filling layer, filled between the chip and the carrier board and completely filling the first section of the plug-in; The plastic packaging layer covers the carrier board, the chip, the plug-in and the bottom filling layer.

2. The multi-chip package structure according to claim 1, characterized in that: The second section of the insert is a solid structure.

3. The multi-chip package structure according to claim 2, characterized in that: In a direction perpendicular to the carrier, the distance between the bottom surface of the second section of the plug-in and the carrier is smaller in the middle and larger at both ends.

4. The multi-chip package structure according to claim 3, characterized in that: The plane where the highest point of the first section is located is located between the upper surface and the lower surface of the chip.

5. The multi-chip package structure according to claim 2, characterized in that: The packaging structure includes a first chip, a second chip and a third chip. In a first direction, the second chip and the third chip are arranged on the same side of the first chip. A first sub-channel is provided between the first chip and the second chip and the third chip, and a second sub-channel is provided between the second chip and the third chip. The first sub-channel and the second sub-channel are interconnected. The plug-in includes a first sub-plug-in provided in the first sub-channel and a second sub-plug-in provided in the second sub-channel, and the middle part of the first sub-plug-in intersects with the end part of the second sub-plug-in.

6. The multi-chip package structure according to claim 5, characterized in that: In a direction perpendicular to the carrier, from the end of the first sub-plug-in to the intersection, the distance between the bottom surface of the second section of the first sub-plug-in and the carrier gradually decreases.

7. The multi-chip package structure according to claim 6, characterized in that: In the direction perpendicular to the carrier, from the end of the second sub-plug away from the first sub-plug to the intersection, The distance between the bottom surface of the second section of the second sub-plug and the carrier board gradually decreases.

8. The multi-chip package structure according to claim 7, characterized in that: At the intersection, the distance between the bottom surface of the second section of the first sub-plug and the carrier board is equal to the distance between the bottom surface of the second section of the second sub-plug and the carrier board.

9. The multi-chip package structure according to claim 2, characterized in that: There is a gap between the second section of the plug and the side wall of the chip, and the bottom filling layer and / or the plastic packaging layer fills the gap.

10. The multi-chip package structure according to claim 1, characterized in that: The second section of the plug-in includes a mesh structure, and the plastic packaging layer is fully filled with the mesh structure.

11. The multi-chip package structure according to claim 10, characterized in that: The second sections of the plug-in are all mesh structures, or the second sections of the plug-in include a solid structure and a mesh structure, and the solid structure connects the mesh structure and the first section.

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