Semiconductor device

Abstract

In one embodiment of the present disclosure, there is provided a semiconductor device comprising: a source / drain region over a semiconductor fin; the gate structure is located on the semiconductor fin and is adjacent to the source / drain region, the gate structure comprises a gate spacer layer, and the gate spacer layer has first roughness; a plurality of dielectric layers over the source / drain regions; a first contact plug electrically coupled to the source / drain region and extending through the first dielectric layer; and a first nitride liner between the first contact plug and the first dielectric layer, the first nitride liner having a second roughness, the second roughness being less than the first roughness.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly to semiconductor devices. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate and patterning the various material layers using photolithography to form circuit elements and components thereon.

[0003] The semiconductor industry continues to increase the packing density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, thereby allowing more components to be integrated into a specific area. However, as the minimum feature size decreases, other issues arise that should be addressed. Summary of the invention

[0004] The present disclosure provides a semiconductor device, comprising: a source / drain region located on a semiconductor fin; a gate structure located on the semiconductor fin and adjacent to the source / drain region, the gate structure comprising a gate spacer layer, the gate spacer layer having a first roughness; a plurality of dielectric layers located on the source / drain region; a first contact plug electrically coupled to the source / drain region and extending through the first dielectric layer; and a first nitride liner between the first contact plug and the first dielectric layer, the first nitride liner having a second roughness, the second roughness being less than the first roughness.

[0005] In one embodiment, a second contact plug is further included that is electrically coupled to the source / drain region and extends through the semiconductor fin.

[0006] In one embodiment, the second contact plug is a single-layer structure.

[0007] In one embodiment, the second contact plug is a multi-layer structure.

[0008] In one embodiment, the method further includes a second nitride liner between the second contact plug and the semiconductor fin, wherein the second nitride liner has a third roughness smaller than the first roughness.

[0009] In one embodiment, the second nitride liner has substantially parallel sidewalls.

[0010] In one embodiment, the second nitride liner extends along the semiconductor fin and along an isolation region adjacent to the semiconductor fin.

[0011] In one embodiment, the isolation region is a shallow trench isolation region.

[0012] In one embodiment, a silicide region is further included between the source / drain region and the second contact plug.

[0013] In one embodiment, an epitaxial cap is further included between the source / drain region and the silicide region. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention is best understood by the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various elements may be arbitrarily enlarged or reduced to clearly show the components of the present invention.

[0015] Figure 1 An example of a nanostructure field-effect transistor (nFET) is illustrated in a three-dimensional view according to some embodiments.

[0016] Figure 2 , 3 ,4,5,6A,6B,7A,7B,8A,8B,9A,9B,10A,10B,11A,11B,11C,12A,12B,12C,12D, 13A, 13B, 13C, 13D, 13E, 13F, 14A, 14B, 14C, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18 19A, 19B, 19C, 20A, 20B, 20C, 21A, 21B, 21C, 22A, 22B, 22C, 23A, 23B, 23C, 24A, 24B, 24C, 25A, 25B, 25C, 26A, 26B, 26C, 27A, 27B, 27C, 28A, 28B, 28C, 29A, 29B, and Fig.29C is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured field effect transistor according to some embodiments.

[0017] Fig. 30A , Fig. 30B and Fig. 30C is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured field effect transistor according to some embodiments.

[0018] Description of reference numerals:

[0019] 20: Separator

[0020] 50: Substrate

[0021] 50N: N-type area

[0022] 50P: P-type area

[0023] 51: First semiconductor layer

[0024] 51A: First semiconductor layer

[0025] 51B: First semiconductor layer

[0026] 51C: First semiconductor layer

[0027] 52: The First Nanostructure

[0028] 52A: First Nanostructure

[0029] 52B: First Nanostructure

[0030] 52C: First Nanostructure

[0031] 53: Second semiconductor layer

[0032] 53A: Second semiconductor layer

[0033] 53B: Second semiconductor layer

[0034] 53C: Second semiconductor layer

[0035] 54: Second Nanostructure

[0036] 54A: Second Nanostructure

[0037] 54B: Second Nanostructure

[0038] 54C: Second Nanostructure

[0039] 55: Nanostructures

[0040] 58: Shallow trench isolation (STI) area

[0041] 64: Multi-layer stacking

[0042] 66: Fins

[0043] 68: Shallow trench isolation (STI) area

[0044] 70: Virtual dielectric layer

[0045] 71: Virtual Gate Dielectric

[0046] 72: Virtual gate layer

[0047] 74: Mask layer

[0048] 76: Virtual gate

[0049] 78: Mask

[0050] 80: First spacer layer

[0051] 81: First spacer layer

[0052] 82: Second spacer layer

[0053] 83: Second spacer layer

[0054] 86: First groove

[0055] 88: Sidewall groove

[0056] 90: First inner spacer

[0057] 92: Epitaxial source / drain region

[0058] 94: Contact etch stop layer (CESL)

[0059] 96: First interlayer dielectric

[0060] 96: Second groove

[0061] 100: Gate dielectric layer

[0062] 102: Gate electrode

[0063] 102N: Gate electrode

[0064] 102P: Gate electrode

[0065] 104: Gate mask

[0066] 106: Second interlayer dielectric

[0067] 108: Third groove

[0068] 110: Contact

[0069] 112: Contact etch stop layer (CESL)

[0070] 114: Third interlayer dielectric

[0071] 116: Fourth groove

[0072] 118: Dielectric lining

[0073] 120: Epitaxial cover

[0074] 120N: Nodule

[0075] 120P: Nodules

[0076] 124: Silicide region

[0077] 130: Contact

[0078] 140: Insulation layer

[0079] 144: Fifth groove

[0080] 148: Dielectric lining

[0081] 150: Epitaxial cover

[0082] 150N: Nodule

[0083] 150P: Nodules

[0084] 154: Silicide region

[0085] 160: Contact

[0086] A-A': section line

[0087] B-B': Section line

[0088] C-C': Section line DETAILED DESCRIPTION

[0089] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the novel embodiment. Of course, the above are merely examples and are not intended to limit the novel embodiment. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the novel embodiment may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0090] Furthermore, spatially relative terms such as "under", "below", "lower", "above", "upper" and the like may be used to facilitate description of the relationship between one component or parts and another component or parts in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the turned orientation.

[0091] Various embodiments provide methods for forming a grain including a semiconductor device such as a nanostructured field effect transistor (nanoFET). The method includes forming a stack of semiconductor layers above a front surface of a substrate, etching the stack, and forming an epitaxial source / drain region therein. In particular, depositing crystalline semiconductor material to form the epitaxial source / drain region may result in nodules of semiconductor material being deposited in a non-crystalline (e.g., amorphous and / or polycrystalline) form at other locations. One or more cleaning processes may be performed to remove the nodules in a manner that avoids etching or damaging the epitaxial source / drain region and other exposed components. A gate structure may then be formed over the stack of semiconductor layers to form a transistor structure. In addition, a subsequent epitaxial growth process may also result in nodules, similar to that discussed above. One or more similar cleaning processes may be performed to remove the nodules while preventing damage to the epitaxial source / drain region and other exposed components. However, various embodiments may be applied to other epitaxial processes discussed herein or otherwise and include other types of transistors (eg, fin field effect transistors (FinFETs), planar transistors, etc.) instead of or in combination with nanoFETs.

[0092] Embodiments may include manufacturing the die at the chip level so that active devices such as transistors are formed along the front side of a substrate (e.g., a semiconductor substrate) and a front side interconnect structure may be formed thereon and electrically connected to the front side active devices. In some embodiments, a back side interconnect structure may be formed on the back side of the semiconductor substrate (or after removing some or all of the semiconductor substrate) and electrically connected to the active devices.

[0093] Figure 1Examples of nano-FETs (e.g., nanowire FETs, nanosheet FETs (Nano-FETs), etc.) are illustrated in a three-dimensional view according to some embodiments. The nano-FET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region of the nano-FET. The nanostructure 55 may include a P-type nanostructure, an N-type nanostructure, or a combination thereof. An isolation region 68 is disposed between adjacent fins 66, and the fins 66 may protrude above and between adjacent isolation regions 68. Although the isolation region 68 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate or a combination of a semiconductor substrate and an isolation region. In addition, although both the bottom of the fin 66 and the substrate 50 are illustrated as a single, continuous material, the bottom of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation regions 68 .

[0094] The gate dielectric layer 100 is over the top surface of the fin 66 and along the top surface, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is located over the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102. The source / drain regions 92 may be referred to individually or collectively as a source or a drain, depending on the context.

[0095] Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of gate electrode 102 and in a direction, for example, perpendicular to the direction of current flow between epitaxial source / drain regions 92 of the nanoFET. Cross section BB' is perpendicular to cross section AA' and parallel to the longitudinal axis of fin 66 of the nanoFET and in a direction of current flow between epitaxial source / drain regions 92 of the nanoFET. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions of the nanoFET. For clarity, subsequent figures will refer to these reference cross sections.

[0096] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate use in planar devices, such as planar FETs or in fin field effect transistors (FinFETs).

[0097] Figures 2 to 30C is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figures 2 to 5, 6A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, 29A and Fig. 30A Examples include Figure 1 Reference section AA' is illustrated. Figure 6B , 7B , 8B, 9B, 10B, 11B, 11C, 12B, 12D, 13B, 13D, 13E, 13F, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, 24B, 25B, 26B, 27B, 28B, 29B and Fig. 30B Examples include Figure 1 Reference section BB' is illustrated. Fig. 7A , 8A , 9A, 10A, 11A, 12A, 12C, 13A, 13C, 14C, 19C, 20C, 21C, 22C, 23C, 24C, 25C, 26C, 27C, 28C, 29C and Fig. 30C Examples include Figure 1 The illustrated reference section CC'.

[0098] exist Figure 2 In the embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with a P-type or N-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. According to some embodiments, the substrate 50 is an SOI substrate. Generally speaking, an SOI substrate is a layer of semiconductor material formed on an insulating layer (see, e.g., Figures 27A-30C The insulating layer 140 is shown. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0099] The substrate 50 has an N-type region 50N and a P-type region 50P. The N-type region 50N can be used to form an N-type device, such as an NMOS transistor, such as an N-type field effect transistor (NFET), such as an N-type nano FET, and the P-type region 50P can be used to form a P-type device, such as a PMOS transistor, such as a P-type field effect transistor (PFET), such as a P-type nano FET. The N-type region 50N can be physically separated from the P-type region 50P (as shown in the separator 20), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the N-type region 50N and the P-type region 50P. Although one N-type region 50N and one P-type region 50P are illustrated, any number of N-type regions 50N and P-type regions 50P can be provided.

[0100] In addition Figure 2 In the embodiment of the present invention, a multilayer stack 64 is formed on a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For the purpose of illustration and as discussed in more detail below, the second semiconductor layer 53 will be removed and the first semiconductor layer 51 will be patterned to form a channel region of the nanoFET in the P-type region 50P. In addition, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form a channel region of the nanoFET in the N-type region 50N. However, in some embodiments, the first semiconductor layer 51 can be removed and the second semiconductor layer 53 can be patterned to form a channel region of the nanoFET in the N-type region 50N, and the second semiconductor layer 53 can be removed and the first semiconductor layer 51 can be patterned to form a channel region of the nanoFET in the P-type region 50P.

[0101] In other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanoFET in both the N-type region 50N and the P-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in both the N-type region 50N and the P-type region 50P. In such embodiments, the channel regions in the N-type region 50N and the P-type region 50P may have the same material composition (e.g., silicon, or another semiconductor material) and be formed simultaneously. Fig. 30A , Fig. 30B and Fig. 30C A structure resulting from such an embodiment is illustrated in which the channel regions in the P-type region 50P and the N-type region 50N include, for example, silicon.

[0102] For the purpose of illustration, the multilayer stack 64 is illustrated as a first semiconductor layer 51 and a second semiconductor layer 53 of three layers each. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE) or the like. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a P-type nano FET, such as silicon germanium, and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for a P-type nano FET, such as silicon, silicon carbon, etc. For the purpose of illustration, the multilayer stack 64 is illustrated as having a bottommost semiconductor layer suitable for a P-type nano FET. In some embodiments, the multilayer stack 64 may be formed so that the bottommost layer is a semiconductor layer suitable for an N-type nano FET.

[0103] The first semiconductor material and the second semiconductor material can be materials with high etching selectivity to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material in the N-type region 50N, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the N-type nanoFET. Similarly, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material in the P-type region 50P, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the P-type nanoFET.

[0104] Reference now Figure 3According to some embodiments, the fin 66 is formed in the substrate 50 and the nanostructure 55 is formed in the multilayer stack 64. In some embodiments, the nanostructure 55 and the fin 66 can be formed in the multilayer stack 64 and the substrate 50, respectively, by etching grooves in the multilayer stack 64 and the substrate 50. Etching can be any acceptable etching process, such as reactive-ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching can be anisotropic. Forming the nanostructure 55 by etching the multilayer stack 64 can further define the first nanostructure 52A-C (collectively referred to as the first nanostructure 52) from the first semiconductor layer 51 and define the second nanostructure 54A-C (collectively referred to as the second nanostructure 54A-C) from the second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 can also be collectively referred to as the nanostructure 55.

[0105] The fins 66 and nanostructures 55 can be patterned by any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more optical lithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine optical lithography and self-alignment processes, allowing the creation of patterns with, for example, a pitch smaller than that obtainable using a single, direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0106] For illustration purposes, Figure 3 The fins 66 in the N-type region 50N and the P-type region 50P are illustrated as having substantially equal widths. In some embodiments, the width of the fins 66 in the N-type region 50N may be greater than or less than the width of the fins 66 in the P-type region 50P. In addition, although each fin 66 and nanostructure 55 is illustrated as having a uniform width throughout, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each fin 66 and / or nanostructure 55 increases continuously in a direction toward the substrate 50. In such an embodiment, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0107] exist Figure 4In the embodiment shown, a shallow trench isolation (STI) region 68 (e.g., an isolation region) is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66, and the nanostructure 55 and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitride, or the like, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed so that an excess of insulating material covers the nanostructure 55. Although the insulating material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not illustrated separately) can first be formed along the surface of the substrate 50, the fin 66, and the nanostructure 55. Thereafter, a filler material, such as those discussed above, may be formed over the liner.

[0108] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination of the above, etc. may be utilized. The planarization process exposes the nanostructure 55 so that the top surface of the nanostructure 55 and the insulating material are flush after the planarization process is completed.

[0109] The insulating material is then etched back to form STI regions 68. The insulating material is etched back so that the upper portions of the fins 66 in the N-type region 50N and the P-type region 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (e.g., a dish shape), or a combination thereof as shown. The top surface of the STI region 68 may be formed flat, convex, and / or concave by appropriate etching. The STI region 68 may be etched back using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fins 66 and the nanostructure 55). For example, an oxide removal step such as using dilute hydrofluoric (dHF) may be used.

[0110] The above about Figures 2 to 4The process described is only one example of how fins 66, nanostructures 55, and STI regions 68 are formed. In some embodiments, fins 66 and / or nanostructures 55 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed above the top surface of substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form fins 66 and / or nanostructures 55. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be in-situ doped during growth, which may avoid prior and / or subsequent implantation, although in-situ doping and implantation doping may be used together.

[0111] In addition, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are illustrated and discussed herein as including the same material 50N in the P-type region 50P and the N-type region for illustrative purposes only. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or formed in a different order in the P-type region 50P and the N-type region 50N.

[0112] In addition Figure 4 In the embodiment with different well types, different implantation steps of N-type region 50N and P-type region 50P can be implemented using photoresist or other masks (not separately illustrated). For example, photoresist can be formed over fin 66 and STI region 68 in N-type region 50N and P-type region 50P. Pattern the photoresist to expose P-type region 50P. The photoresist can be formed by using spin coating technology and can be patterned using acceptable optical lithography technology. After the photoresist is patterned, N-type impurity implantation is performed in P-type region 50P, and the photoresist can act as a mask to substantially prevent N-type impurities from being implanted into N-type region 50N. N-type impurities can be implanted into the region in a concentration range of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 of phosphorus, arsenic, antimony, etc. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0113] After or before implanting the P-type region 50P, a photoresist or other mask (not separately illustrated) is formed over the fins 66, nanostructures 55, and STI regions 68 in the P-type region 50P and the N-type region 50N. The photoresist is patterned to expose the N-type region 50N. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable optical lithography technique. Once the photoresist is patterned, a P-type impurity implant may be performed in the N-type region 50N, and the photoresist may serve as a mask to substantially prevent the P-type impurity from being implanted into the P-type region 50P. The P-type impurity may be boron, boron fluoride, indium, etc., with a density of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 A concentration in the range of 1000 nm is implanted into the region. After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0114] After implanting the N-type region 50N and the P-type region 50P, an annealing process may be performed to repair implant damage and activate the implanted P-type and / or N-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation, although in-situ doping and implantation doping may be used together.

[0115] exist Figure 5In the embodiment of the present invention, a dummy dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed above the dummy dielectric layer 70, and a mask layer 74 is formed above the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 may be made of other materials having high etching selectivity to the etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In the example, a single dummy gate layer 72 and a single mask layer 74 are formed across the N-type region 50N and the P-type region 50P. It should be noted that this is for illustrative purposes only, and the dummy dielectric layer 70 is illustrated as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited so that the dummy dielectric layer 70 covers the STI region 68, thereby extending the dummy dielectric layer 70 between the dummy gate layer 72 and the STI region 68.

[0116] FIG. 6A to FIG. 29C Various additional steps in the fabrication of the embodiment devices are illustrated. Fig. 6A , 7A , 8A, 9A, 10A, 11A, 12A, 12C, 13A, 13C, 14A, 14C, 15A, 15B, 16A, 19C, 20C, 21C, 22C, 23C, 24C, 25C, 26C, 27C, 28C and Fig.29C Components in region 50N or region 50P are illustrated. Fig. 6A and Figure 6B In the embodiment, the mask layer 74 can be patterned using acceptable optical lithography and etching techniques (see Figure 5 ) to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from an adjacent dummy gate 76. The dummy gate 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding fin 66.

[0117] exist Fig. 7A and Figure 7B In the embodiment, the first spacer layer 80 and the second spacer layer 82 are respectively formed on Fig. 6A and Figure 6B The first spacer layer 80 and the second spacer layer 82 will then be patterned to serve as spacers for forming self-aligned source / drain regions. Fig. 7A and Figure 7B In the embodiment, the first spacer 80 is formed on the top surface of the STI region 68; the top surface and sidewalls of the fin 66, the nanostructure 55 and the mask 78; and the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. The second spacer 82 is deposited on the first spacer 80. The first spacer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, etc. by thermal oxidation or deposition techniques such as CVD, ALD, etc. The second spacer 82 can be formed of a material having a different etching rate from the material of the first spacer 80, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, etc., and can be deposited by CVD, ALD, etc.

[0118] After forming the first spacer layer 80 and before forming the second spacer layer 82, an implantation for a lightly doped source / drain (LDD) region (not separately illustrated) may be performed. Figure 4 As discussed in the implantation, a mask such as a photoresist may be formed over the N-type region 50N while exposing the P-type region 50P, and an appropriate type (e.g., P-type) impurity may be implanted into the fins 66 and nanostructures 55 exposed in the P-type region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over the P-type region 50P while exposing the N-type region 50N, and an appropriate type of impurity (e.g., N-type) may be implanted into the fins 66 and nanostructures 55 exposed in the N-type region 50N. The mask may then be removed. The N-type impurity may be any of the N-type impurities discussed previously, and the P-type impurity may be any of the P-type impurities discussed previously. The impurity concentration of the lightly doped source / drain region may be about 10 15 Atom / cm 3 to about 10 19 Atom / cm 3 The annealing process can be used to repair implant damage and activate the implanted impurities.

[0119] exist Fig. 8A and Figure 8B, the first spacer 80 and the second spacer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used to self-align the subsequently formed source / drain and to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processes. The first spacer 80 and the second spacer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of the second spacer 82 has a different etching rate than the material of the first spacer 80, so that the first spacer 80 can serve as an etching stop layer when patterning the second spacer 82 and so that the second spacer 82 can serve as a mask when patterning the first spacer 80. For example, the second spacer 82 can be etched using an anisotropic etching process, wherein the first spacer 80 serves as an etching stop layer, and wherein the remaining portion of the second spacer 82 forms the second spacer 83, such as Fig. 8A Thereafter, the second spacer 83 is used as a mask while etching the exposed portion of the first spacer layer 80, thereby forming the first spacer 81, as shown in FIG. Fig. 8A shown.

[0120] like Fig. 8A As shown in , the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B As shown, in some embodiments, the second spacer layer 82 can be removed from above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer layer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy dielectric layer 70. In other embodiments, a portion of the second spacer layer 82 can remain above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0121] It should be noted that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be patterned before the second spacer layer 82 is deposited), additional spacers may be formed and removed, and / or the like. In addition, N-type and P-type devices may be formed using different structures and steps.

[0122] exist Fig. 9A and Fig. 9BIn some embodiments, a first recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region is then formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. Fig. 9A As shown in , the top surface of the STI region 58 can be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 can be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68; and so on. The first recess 86 can be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first recess 86, the first spacer 81, the second spacer 83, and the mask 78 shield portions of the fin 66, the nanostructure 55, and the substrate 50. A single etching process or multiple etching processes can be used to etch each layer of the nanostructure 55 and / or the fin 66. After the first recess 86 reaches the desired depth, a timed etching process can be used to stop etching the first recess 86.

[0123] exist Fig. 10A and Fig. 10B In the embodiment, the portion of the sidewall of the layer of the nanostructure 55 formed of the first semiconductor material (e.g., the first nanostructure 52) exposed by the first groove 86 is etched to form a sidewall groove 88 in the N-type region 50N, and the portion of the sidewall of the layer of the nanostructure 55 formed of the second semiconductor material (e.g., the second nanostructure 54) exposed by the first groove 86 is etched to form a sidewall groove 88 in the P-type region 50P. Although the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall groove 88 are Fig. 10B50P, while the first nanostructure 52 is etched using an etchant selective to the first semiconductor material, so that the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52 in the N-type region 50N. Similarly, the N-type region 50N can be protected using a mask (not illustrated) while the second nanostructure 54 is etched using an etchant selective to the second semiconductor material, so that the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the first nanostructure 52 and the substrate 50. In an embodiment where the first nanostructure 52 includes, for example, SiGe and the second nanostructure 54 includes, for example, Si or SiC, a dry etching process using tetramethyl ammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. can be used to etch the sidewalls of the first nanostructure 52 in the N-type region 50N, and a wet or dry etching process with hydrogen fluoride, another fluorine-based etchant, etc. can be used to etch the sidewalls of the second nanostructure 54 in the P-type region 50P.

[0124] exist Figures 11A-11C In the embodiment, the first inner spacer 90 is formed in the sidewall groove 88. The first inner spacer 90 can be formed by Fig. 10A and Fig. 10B The structure shown is formed by depositing an inner spacer layer (not separately illustrated). The first inner spacer 90 serves as an isolation component between the subsequently formed source / drain region and the gate structure. As will be discussed in more detail below, the source / drain region will be formed in the first recess 86, and the first nanostructure 52 in the N-type region 50N and the second nanostructure 54 in the P-type region 50P will be replaced with the corresponding gate structure.

[0125] The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, etc. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, but any suitable material may be used, such as a low-k material having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are illustrated as being flush with the sidewalls of the second nanostructure 54 in the N-type region 50N and flush with the sidewalls of the first nanostructure 52 in the P-type region 50P, the first inner spacer 90 may extend beyond the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively, or be recessed from both.

[0126] In addition, although Fig. 11BThe outer sidewall of the first inner spacer 90 is illustrated as being straight, but the outer sidewall of the first inner spacer 90 may be concave or convex. As an example, Fig. 11C An embodiment is illustrated in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54 in the N-type region 50N. An embodiment is also illustrated in which the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the first nanostructure 52 in the P-type region 50P. The inner spacer layer can be etched by an anisotropic etching process such as RIE, NBE, etc. The first inner spacer 90 can be used to prevent a subsequent etching process (e.g., an etching process for forming a gate structure) from affecting a subsequently formed source / drain region (e.g., an epitaxial source / drain region 92, as described below with reference to Figures 12A-12C discussed) damage.

[0127] exist Figures 12A-12D In the embodiment of the present invention, epitaxial source / drain regions 92 are formed in the first recesses 86, and nodules 92N of epitaxial material (which may also be referred to as epitaxial material nodules or epitaxial nodules) may be formed on other surfaces within the N-type region 50N, and nodules 92P may be formed on other surfaces within the P-type region 50P. Nodules 92N (e.g., in the N-type region 50N) and nodules 92P (e.g., in the P-type region 50P) may be amorphous (e.g., amorphous and / or polycrystalline), including the same epitaxial material as that used to form epitaxial source / drain regions 92 in the N-type region 50N and the P-type region 50P, respectively.

[0128] In some embodiments, the source / drain region 92 may apply stress to the second nanostructure 54 in the N-type region 50N and the first nanostructure 52 in the P-type region 50P, thereby improving performance. Fig. 12B As shown in FIG. 8 , epitaxial source / drain regions 92 are formed in first recesses 86 such that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate epitaxial source / drain regions 92 from dummy gates 76, and first inner spacers 90 are used to separate epitaxial source / drain regions 92 from nanostructures 55 by an appropriate lateral distance so that epitaxial source / drain regions 92 do not short circuit with a subsequently formed gate of the resulting nanoFET.

[0129] The epitaxial source / drain region 92 in the N-type region 50N (e.g., NMOS region) can be formed by shielding the P-type region 50P (e.g., PMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the N-type region 50N. The epitaxial source / drain region 92 may include any acceptable material suitable for an N-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 may have a surface protruding from the corresponding upper surface of the nanostructure 55 and may have facets.

[0130] The epitaxial source / drain region 92 in the P-type region 50P (e.g., a PMOS region) can be formed by shielding the N-type region 50N (e.g., an NMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the P-type region 50P. The epitaxial source / drain region 92 may include any acceptable material suitable for a P-type nano FET. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source / drain region 92 may include a material that applies compressive strain to the first nanostructure 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain region 92 may also have a surface protruding from the corresponding surface of the nanostructure 55 and may have a facet.

[0131] According to some embodiments, during the formation of the epitaxial source / drain regions 92 in the N-type region 50N, nodules 92N (e.g., clusters of corresponding epitaxial materials) may grow over the exposed gate structure in the N-type region 50N. Similarly, during the formation of the epitaxial source / drain regions 92 in the P-type region 50P, nodules 92P (e.g., small clusters of corresponding epitaxial materials) may grow over the exposed gate structure in the P-type region 50P. In particular, nodules 92N, 92P may be formed along the exposed surfaces of the gate structure (e.g., the first spacer 81, the second spacer 83, the mask 78) and the exposed surfaces of the STI regions 68. For example, nodules 92N may include silicon, phosphorus-doped silicon, any other material of the corresponding epitaxial source / drain regions 92, or any combination thereof. Similarly, nodules 92P may include silicon germanium, boron-doped silicon germanium, any other material of the corresponding source / drain regions (e.g., silicon may be used for the first semiconductor material layer 92A), or any combination thereof. As shown, each of the epitaxial source / drain regions 92 is formed as a continuous material, while the nodules 92N, 92P are formed as discontinuous clusters or discontinuous nodules. As described above, in some embodiments, some or all of the nodules 92N, 92P may be polycrystalline, amorphous, or a combination thereof.

[0132] The source / drain region 92, the first nanostructure 52, the second nanostructure 54 and / or the substrate 50 may be implanted with dopants to form the source / drain region, similar to the process previously discussed for forming the lightly doped source / drain region, followed by an annealing process. The source / drain region may have a thickness between about 10 19 Atom / cm 3 and about 10 21 Atom / cm 3 The N-type and / or P-type impurities used in the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth. In some embodiments, the epitaxial source / drain regions 92 are implanted with dopants after the cleaning process discussed below (see Figures 13A-13F ).

[0133] Due to the epitaxial process used to form epitaxial source / drain regions 92 in N-type region 50N and P-type region 50P, the upper surface of epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, such as Fig. 12A In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, such as Fig. 12C As shown. Fig. 12A and Fig. 12C In the illustrated embodiment, the first spacer 81 can be formed to the top surface of the STI region 68 to block epitaxial growth. In some other embodiments, the first spacer 81 can cover a portion of the sidewalls of the nanostructure 55, further hindering epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 can be adjusted to remove the spacer material to allow the epitaxial growth region to extend to the surface of the STI region 58.

[0134] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited on the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited on the second semiconductor material layer 92B.

[0135] Fig.12D The embodiment is illustrated in which the sidewalls of the first nanostructure 52 in the N-type region 50N and the sidewalls of the second nanostructure 54 in the P-type region 50P are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Fig.12D As shown, the epitaxial source / drain region 92 may be formed to contact the first inner spacer 90 and may extend through the sidewall of the second nanostructure 54 in the N-type region 50N and through the sidewall of the first nanostructure 52 in the N-type region 50N.

[0136] exist Figures 13A-13F In some embodiments, one or more cleaning processes are performed to remove nodules 92N, 92P. In some embodiments, an NFET cleaning process is performed to remove nodules 92N in N-type region 50N while P-type region 50P is shielded. In addition, a PFET cleaning process is performed to remove nodules 92P in P-type region 50P while N-type region 50N is shielded.

[0137] In some embodiments, the NFET cleaning process includes flowing gaseous precursors of fluorine (F2) and ammonia (NH3)—for example, which may include an inert gas such as argon, nitrogen, etc.—over the structure to react with and remove nodules 92N. Fluorine may have a flow rate in a range from 10 standard cubic centimeters (sccm) to 300 sccm, and ammonia may have a flow rate in a range from 30 sccm to 500 sccm. During the NFET cleaning process, the precursor flow rates may be varied (e.g., increased or decreased) while maintaining a substantially constant ratio between each other. In addition, the NFET cleaning process may be performed at a temperature of 30° C. to 100° C., a pressure of 100 mTorr to 800 mTorr, and for about or less than 10 minutes (e.g., ranging from 10 seconds to 3 minutes). It should be noted that these parameters may be adjusted depending on the number, total volume, individual size, and surface area covered of nodules 92N.

[0138] The NFET cleaning process described above can effectively remove nodules 92N (e.g., silicon in an amorphous form, phosphorus-doped silicon, etc.) without etching or damaging the epitaxial source / drain regions 92 or other exposed components of the structure. The precursor has a higher selectivity for etching nodules 92N (e.g., epitaxial material in an amorphous form) than etching the epitaxial source / drain 92 (e.g., epitaxial material in a crystalline form) and other components in the N-type region 50N. In particular, the precursor does not contain chlorine to prevent unintended etching of the epitaxial source / drain regions 92. In addition, the precursor does not contain hydrogen radicals to prevent damage or change in the chemical composition of the epitaxial source / drain regions 92 or other exposed components of the structure. Therefore, embodiments of the NFET cleaning process can remove nodules 92N more effectively and at a faster rate than using a precursor such as hydrogen chloride.

[0139] In some embodiments, the PFET cleaning process includes flowing gaseous precursors fluorine (F2) and hydrogen fluoride (HF)—for example, which may include inert gases such as argon, nitrogen, etc.—over the structure to react with and remove nodules 92P. Fluorine may have a flow rate in a range from 10 sccm to 300 sccm, and hydrogen fluoride may have a flow rate in a range from 30 sccm to 800 sccm. During the PFET cleaning process, the precursor flow rates may vary (e.g., increase or decrease) while maintaining a substantially constant ratio between each other. In addition, the PFET cleaning process may be performed at a temperature of 30° C. to 100° C., a pressure of 100 mTorr to 800 mTorr, and a duration of about or less than 10 minutes (e.g., ranging from 30 seconds to 10 minutes). It should be noted that these parameters may be adjusted based on the number, total volume, individual size, and coverage surface area of ​​nodules 92P.

[0140] The PFET cleaning process described above can effectively remove nodules 92P (e.g., silicon germanium in a non-crystalline form, boron-doped silicon germanium, etc.) without etching or damaging the epitaxial source / drain region 92 or other exposed parts of the structure. The precursor has a higher selectivity for etching nodules 92N (e.g., epitaxial material in a non-crystalline form) than etching the epitaxial source / drain region 92 (e.g., epitaxial material in a crystalline form) and other parts in the P-type region 50P. In particular, the precursor does not contain chlorine to prevent unintended etching of the epitaxial source / drain region 92. In addition, the precursor does not contain hydrogen radicals that have low selectivity for nodules 92P. In addition, the precursor that does not contain hydrogen radicals also prevents damage or changes in the chemical composition of other exposed parts of the structure. Therefore, an embodiment of the PFET cleaning process can remove nodules 92P more effectively and at a faster rate than using a precursor such as hydrogen chloride.

[0141] refer to Fig.13E and Fig.13F According to some embodiments, the cleaning process may increase the roughness of the surface of certain layers by etching exposed portions of those layers while removing nodules 92N, 92P. Fig.13E Portions of the first and second spacers 81 and 83 are illustrated along the epitaxial source / drain regions 92. The overlying second spacers 83 may be etched, while only the lower portions of the first spacers 81 may be exposed and etched to increase the roughness. Fig.13F The portion of the first spacer 81 along the dummy gate 76 and the mask 78 is illustrated. As shown in the figure, the exposed portions of the first spacer 81 and the second spacer 83 between the nodules 92N and 92P can be etched while etching the nodules 92N and 92P. Specifically, the roughness of the exposed surfaces of the first spacer 81 and the second spacer 83 can be increased. For example, the roughness of the silicon nitride layer (e.g., the first spacer 81) can be increased from Increase to For example, the roughness increases Or increase the previous roughness by two to five times. In addition, the roughness of the silicon oxycarbon nitride layer (e.g., the second spacer 83) can be increased from Increase to For example, the roughness increases by 1-3 Or increase to twice the previous roughness. In addition, the cleaning process can remove up to about 90% of the number and / or volume of nodules 92N and nodules 92P. Similarly, the cleaning process can reduce the surface area coverage of nodules 92N and 92P by up to about 90%.

[0142] exist Figure 14A-Figure 14C In the embodiment, the first interlayer dielectric (ILD) 96 is deposited on Fig. 6A , Fig. 13B and Fig.13AThe structure shown ( Figures 7A-13D The process does not change Fig. 6A ). The first interlayer dielectric 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first interlayer dielectric 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacer 81. The CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has an etching rate different from that of the material of the first interlayer dielectric 96 above. In some embodiments, the increased roughness of the first spacer 81 and the second spacer 83 may improve adhesion to the CESL 94 .

[0143] exist Figure 15A-15B In the process, a planarization process such as CMP may be performed to make the top surface of the first interlayer dielectric 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, and a portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first interlayer dielectric 96 are level within the process variation range. Therefore, the top surface of the dummy gate 72 is exposed through the first interlayer dielectric 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first interlayer dielectric 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0144] exist Fig.16A and Fig. 16BIn the embodiment of the present invention, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps to form a second groove 98. The portion of the dummy gate dielectric 71 in the second groove 98 is also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 76 at a faster rate than the first interlayer dielectric 96 or the first spacer 81. Each second groove 98 exposes and / or covers a portion of the nanostructure 55, which serves as a channel region in a subsequently completed nanoFET. The portion of the nanostructure 55 that serves as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During the removal process, the dummy gate dielectric 71 can be used as an etch stop layer when etching the dummy gate 76. The dummy gate dielectric 71 can then be removed after the dummy gate 76 is removed.

[0145] exist Fig.17A and Fig. 17B , the first nanostructure 52 in the N-type region 50N and the second nanostructure 54 in the P-type region 50P are removed to extend the second recess 98. The first nanostructure 52 can be removed by forming a mask (not illustrated) over the P-type region 50P and performing an isotropic etching process, such as wet etching, etc., using an etchant selective to the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In an embodiment where the first nanostructure 52 includes, for example, SiGe and the second nanostructure 54 includes, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. can be used to remove the first nanostructure 52 in the N-type region 50N.

[0146] The second nanostructure 54 in the P-type region 50P can be removed by forming a mask (not illustrated) over the N-type region 50N and performing an isotropic etching process such as wet etching using an etchant selective to the material, while the first nanostructure 52, the substrate 50, and the STI region 68 remain relatively unetched compared to the second nanostructure 54. In an embodiment where the second nanostructure 54 includes, for example, SiGe and the first nanostructure 52 includes, for example, Si or SiC, another etchant mainly based on fluorine can be used to remove the second nanostructure 54 in the P-type region 50P.

[0147] In other embodiments, the channel regions in the N-type region 50N and the P-type region 50P can be formed simultaneously, for example, by removing the first nanostructure 52 in the N-type region 50N and the P-type region 50P or by removing the second nanostructure 54 in the N-type region 50N and the P-type region 50P. In such embodiments, the channel regions of the N-type nanoFET and the P-type nanoFET can have the same material composition, such as silicon, silicon germanium, etc. Figure 30A-Figure 30C A structure resulting from such an embodiment is illustrated, in which the channel regions in the P-type region 50P and the N-type region 50N are provided by the second nanostructure 54 and contain, for example, silicon.

[0148] exist Fig.18A and Fig.18B In the embodiment of the present invention, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second groove 98. In the N-type region 50N, the gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls and bottom surface of the second nanostructure 54, and in the P-type region 50P, the gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls and bottom surface of the first nanostructure 52. The gate dielectric layer 100 can also be deposited on the top surface of the first interlayer dielectric 96, the CESL 94, the first spacer 81 and the STI region 68.

[0149] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric layer 100 may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high dielectric constant dielectric material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant (k) value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 100 of the N-type region 50N and the P-type region 50P may be the same or different. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0150] The gate electrode 102 is deposited over the gate dielectric layer 100 and fills the remaining portion of the second recess 98. The gate electrode 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although a single-layer gate electrode 102 is illustrated, the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler materials. Any combination of layers constituting the gate electrode 102 may be deposited in the N-type region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and may be deposited in the region 50P between adjacent first nanostructures 52 in the P-type.

[0151] The formation of the gate dielectric layer 100 in the N-type region 50N and the P-type region 50P may occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by different processes, such that the gate dielectric layer 100 may be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region may be formed by different processes, such that the gate electrode 102 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0152] After filling the second groove 98, a planarization process such as CMP may be performed to remove excess portions of the material of the gate dielectric layer 100 and the gate electrode 102, which are above the top surface of the first interlayer dielectric 96. The remaining portions of the material of the gate electrode 102 and the gate dielectric layer 100 thus form a replacement gate structure for the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure".

[0153] exist Figure 19A-Figure 19C In the embodiment of the present invention, the gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed so that a groove is formed directly above the gate structure and between the opposite portions of the first spacer 81. A gate mask 104 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the groove, and a planarization process is then performed to remove excess portions of the dielectric material extending above the first interlayer dielectric 96. A gate contact (e.g., gate contact 110, described below with respect to Fig.21A and Fig. 21B ) penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0154] As further shown, the second interlayer dielectric 106 is deposited over the first interlayer dielectric 96 and over the gate mask 104. In some embodiments, the second interlayer dielectric 106 is a flowable film formed by FCVD. In some embodiments, the second interlayer dielectric 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0155] exist Figure 20A-20C In the embodiment of the present invention, the second interlayer dielectric 106 and the gate mask 104 are etched to form a third recess 108 that exposes the surface of the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process such as RIE, NBE, etc. In some embodiments, the third recess 108 can be etched through the second interlayer dielectric 106 using a first etching process and can be etched through the gate mask 104 using a second etching process. A mask such as a photoresist can be formed and patterned over the second interlayer dielectric 106 to shield portions of the second interlayer dielectric 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch so that the third recess 108 extends into the gate structure, and the bottom of the third recess 108 can be flush with the upper surface of the gate structure (e.g., at the same level as the upper surface of the gate structure or having the same distance to the substrate 50 as the upper surface of the gate structure) or lower than (e.g., closer to the substrate 50 than the upper surface of the gate structure) the upper surface of the gate structure. Although the third recess 108 is illustrated as exposing the gate structure in the same cross-section as the epitaxial source / drain regions 92, in various embodiments, the third recess 108 and the epitaxial source / drain regions 92 may be in different cross-sections, thereby reducing the risk of short circuits between subsequently formed contacts and the source / drain regions 92.

[0156] Then, in Figure 21A-Figure 21C In the third recess 108, a contact 110 (also referred to as a contact plug, a gate contact, or a gate contact plug) is formed. The contacts 110 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the contacts 110 each include a barrier layer and a conductive material, and are electrically coupled to the underlying conductive component (e.g., the gate structure 102 in the illustrated embodiment). The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second interlayer dielectric 106.

[0157] exist Figure 22A-22C, optionally, a third interlayer dielectric 114 is formed over the second interlayer dielectric 106. In addition, the third interlayer dielectric 114, the second interlayer dielectric 106, the first interlayer dielectric 96, the CESL 94, and the fourth recess 116 are etched into the film layer to expose the surface of the epitaxial source / drain region 92. In some embodiments, the third interlayer dielectric 114 is a flowable film formed by FCVD, similar to that described above with respect to the first interlayer dielectric 96 and / or the second interlayer dielectric 106. In some embodiments, the third interlayer dielectric 114 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc. Optionally, a contact etch stop layer (CESL) 112 is disposed between the second interlayer dielectric 106 and the third interlayer dielectric 114. The CESL 112 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having the same or different etch rate as the material of the third interlayer dielectric 114 thereover.

[0158] The fourth recess 116 may be formed by etching using an anisotropic etching process such as RIE, NBE, etc. In some embodiments, the fourth recess 116 may be etched through the third interlayer dielectric 114 (if present), the CESL 112 (if present), the second interlayer dielectric 106, and the first interlayer dielectric 96 using a first etching process, and then a secondary etching process may be used to etch through the CESL 94. A mask such as a photoresist may be formed and patterned over the third interlayer dielectric 114 to shield portions of the third interlayer dielectric 114 from the first etching process and the second etching process. In some embodiments, the etching process may cause over-etching, so that the fourth recess 116 extends into the epitaxial source / drain region 92, and the bottom of the fourth recess 116 may be flush with the upper surface of the epitaxial source / drain region 92 (e.g., at the same level as the upper surface of the epitaxial source / drain region 92 or have the same distance to the substrate as the upper surface of the epitaxial source / drain region 92) or lower than (e.g., closer to the substrate than the upper surface of the epitaxial source / drain region 92) the upper surface of the epitaxial source / drain region 92. Although the fourth recess 116 is illustrated as exposing the epitaxial source / drain region 92 in the same cross-section as the gate contact 110, in various embodiments, the epitaxial source / drain region 92 may expose the contact 110 in a cross-section different from the gate, thereby reducing the risk of shorting between the gate contact 110 and a subsequently formed contact to the epitaxial source / drain region 92.

[0159] exist Figure 23A-23CIn the embodiment of the present invention, a dielectric liner 118 is deposited on the third interlayer dielectric 114 (or on the second interlayer dielectric 106), along the sidewalls of the fourth recess 116, and on the exposed surface of the epitaxial source / drain region 92. In addition, an etching process is performed to remove a portion of the dielectric liner 118 and re-expose the epitaxial source / drain region 92. The dielectric liner 118 may be silicon nitride, etc., and may be deposited by any suitable method, such as CVD, PECVD, ALD, etc. The etching process may be an anisotropic etch that removes a portion of the dielectric liner 118 from the upper surface of the third interlayer dielectric 114 (or the second interlayer dielectric 106) and the upper surface of the epitaxial source / drain region 92.

[0160] exist Figure 24A-24C In the embodiment, epitaxial caps 120 are formed on the exposed epitaxial source / drain regions 92, and nodules 120N may be formed on other surfaces within the N-type region 50N and nodules 120P may be formed on other surfaces within the P-type region 50P. In some embodiments, epitaxial caps 120 are formed in the N-type region 50N while shielding the P-type region 50P, and epitaxial caps 120 are formed in the P-type region 50P while shielding the N-type region 50N. The epitaxial caps 120 may supplement the material of the epitaxial source / drain regions 92, which may be formed during the formation of the fourth recess 116 (see FIG. 1 ). Figure 22A-22C ) and / or during etching of the dielectric liner 118 (see Figure 23A-23C ). Therefore, the epitaxial cap 120 can be considered as a part of the corresponding epitaxial source / drain region 92.

[0161] According to some embodiments, the epitaxial cap 120 formed in the N-type region 50N may be a material that is the same as or similar to the epitaxial source / drain region 92 in the N-type region 50N (eg, the third semiconductor material layer 92C, see Figures 12A-12D ), such as phosphorus-doped silicon. The epitaxial cap 120 formed in the P-type region 50P may be made of the same or similar material as the epitaxial source / drain region 92 in the P-type region 50P (eg, the third semiconductor material layer 92C, see Figures 12A-12D ), such as boron-doped silicon germanium. In some embodiments, epitaxial cap 120 is formed of a similar material having a different composition than the exposed portion of epitaxial source / drain region 92. Epitaxial cap 120 can be used to reduce the resistance between subsequently formed source / drain contacts (e.g., including the silicide portion of the source / drain contacts) and epitaxial source / drain regions 92. Nodules 120N, 120P can be non-crystalline (e.g., amorphous and / or polycrystalline), including the same epitaxial material that forms epitaxial cap 120 in N-type region 50N and P-type region 50P, respectively. For example, epitaxial cap 120 can be formed using a low temperature epitaxial process, such as a temperature of 400° C. or less.

[0162] According to some embodiments, similar to nodules 92N, during the formation of epitaxial cap 120 in N-type region 50N, nodules 120N (e.g., small clusters of epitaxial material) may grow along third interlayer dielectric 114 and fourth recess 116 (e.g., dielectric liner 118) in N-type region 50N. Similarly, during the formation of epitaxial cap 120 in P-type region 50P, nodules 120P (e.g., small clusters of epitaxial material) may grow along the sidewalls of third interlayer dielectric 114 and fourth recess 116 (e.g., dielectric liner 118) in P-type region 50P. For example, nodules 120N may be silicon and / or phosphorus-doped silicon (etc.), and nodules 120P may be silicon germanium and / or boron-doped silicon germanium (etc.). As shown, each epitaxial cap 120 is formed as one continuous material with epitaxial source / drain regions 92, while nodules 120N, 120P form discontinuous clusters or discontinuous nodules. As described above, in some embodiments, some or all of nodules 120N, 120P may be polycrystalline, amorphous, or a combination thereof.

[0163] exist Figure 25A-Figure 25C In the embodiment, one or more cleaning processes are performed to remove the nodules 120N and 120P. Figures 13A-13D Similar to the description, the NFET cleaning process is performed to remove the nodules 120N in the N-type region 50N while shielding the P-type region 50P. In addition, the PFET cleaning process is performed to remove the nodules 120P in the P-type region 50P while shielding the N-type region 50N.

[0164] Similar to the above discussion, the NFET cleaning process includes flowing gaseous precursors fluorine (F2) and ammonia (NH3) to remove nodules 120N, and the PFET cleaning process includes flowing gaseous precursors fluorine (F2) and hydrogen fluoride (HF) to remove nodules 120P. The cleaning process may be performed according to the same other parameters as previously described with respect to the cleaning process for removing nodules 92N, 92P (see Figures 13A-13D In some embodiments, due to the formation of fewer and / or smaller nodules 120N, 120P, as discussed above with respect to nodules 92N, 92P, the cleaning process may be performed for a shorter duration (e.g., a duration of about or less than 3 minutes) compared to nodules 92N, 92P. It should be noted that the process parameters may be adjusted based on the number, total volume, individual size, and covered surface area of ​​nodules 120N, 120P.

[0165] The cleaning process achieves similar benefits as discussed above (e.g., preventing etching or damage to epitaxial source / drain regions 92 and other exposed features) and may also similarly increase the surface roughness of certain layers by etching exposed portions of those layers while removing nodules 120N, 120P. For example, the roughness of an exposed surface of silicon nitride (e.g., dielectric liner 118) may be increased from Increase to For example, the roughness increases Or increase the previous roughness by two to five times. In addition, the cleaning process can remove up to about 90% of the number and / or volume of the nodules 120N, 120P. Similarly, the cleaning process can reduce the surface area coverage of the nodules 120N, 120P by up to about 90%.

[0166] It should be noted that due to the different process conditions and duration for forming epitaxial cap 120 as compared to the formation of epitaxial source / drain regions 92, the number, total volume, individual size, and surface area coverage of nodules 120N, 120P may be smaller than those corresponding metrics of nodules 92N, 92P. Thus, in some embodiments, the roughness of dielectric liner 118 may be determined from Increase to For example, the roughness increases up to about For example, after a cleaning process to remove nodules 120N, 120P, dielectric liner 118 may be less rough (eg, have a smaller increase in roughness) than first and second spacers 81, 83 after a cleaning process to remove nodules 92N, 92P.

[0167] exist Figure 26A-26C In the embodiment of the present invention, the silicide region 124 and the contact 130 (also referred to as a contact plug, a source / drain contact or a source / drain contact plug) are formed in the fourth recess 116. For example, after the epitaxial cap 120 is formed and the nodules 120N, 120P are removed, the silicide region 124 is formed above the epitaxial source / drain region 92 (e.g., above the epitaxial cap 120). In some embodiments, the silicide region 124 is formed by first depositing a metal (not specifically shown) capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial cap 120 to form a silicide and / or germanide, such as depositing nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals or alloys thereof, on the exposed portion of the epitaxial source / drain region 92 (e.g., the epitaxial cap 120), and then performing a thermal annealing process to form the silicide region 124. The unreacted portion of the deposited metal is then removed, such as by an etching process. Although silicide region 124 is referred to as a silicide region, as described above, silicide region 124 may also be a germanide region, or a silicon-germanide region (eg, a region including silicide and germanide). In one embodiment, silicide region 124 includes TiSi.

[0168] The contacts 130 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the contacts 130 each include a barrier layer and a conductive material, and are electrically coupled to the conductive component below (e.g., the silicide region 124 in the illustrated embodiment). The contacts 130 are electrically coupled to the silicide region 124 and may be referred to as source / drain contacts. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the third interlayer dielectric 114.

[0169] Although not specifically shown, in some embodiments, the contact 130 is formed without first forming the third interlayer dielectric 114 and the CESL 112. For example, similar to the third recess 108, the fourth recess 116 can be formed through the second interlayer dielectric 106. Additional steps such as forming the dielectric liner 118, etching the dielectric liner 118, forming the epitaxial cap 120, removing the nodules 120N, 120P, forming the silicide region 124, and forming the contact 130 can be performed similarly to the above.

[0170] According to some embodiments (not specifically illustrated), a front-side interconnect structure is formed over the structure and electrically connected to an active device (e.g., a nanoFET) along the front side of substrate 50. A carrier substrate (not specifically illustrated) can be attached to the front side of the structure, and the structure can be flipped over for back-side processing. For example, back-side contacts can be formed to epitaxial source / drain regions 92, as described below. In addition, although not specifically illustrated, back-side contacts can be formed to gate electrodes 102 or other components of the structure, back-side interconnect structures can be formed and electrically connected to active devices, and / or external connectors can be formed on the back side or front side of the structure.

[0171] Figures 27A-29C Backside processing of the structure according to some embodiments is illustrated. In particular, formation of the backside contacts is similar to that described above with respect to the contacts 130 to the epitaxial source / drain regions 92 unless otherwise noted.

[0172] exist Figure 27A-27CIn the embodiment, the thinning process can be applied to the back side of the substrate 50. In addition, an etching process can be performed to form a fifth groove 144 exposing the back side of the epitaxial source / drain region 92, a dielectric liner 148 can be deposited and partially etched, and an epitaxial cap 150 can be formed on the exposed back side of the epitaxial source / drain region 92. In some embodiments, the thinning process can include a planarization process (e.g., mechanical grinding, CMP, etc.), an etch back process, a combination thereof, etc. In an embodiment where the wafer (e.g., substrate 50) is an SOI substrate, the thinning process can expose the insulating region of the SOI. For example, as described above in conjunction with Figure 2 As discussed, the SOI substrate may include a semiconductor material layer (e.g., labeled as substrate 50) formed on an insulating layer 140. The insulating layer 140 layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. In such an embodiment, a thinning process may be performed until the insulating layer 140 is exposed. In some embodiments, a dielectric layer is formed along the back side of the thinned substrate 50, and the dielectric layer may be referred to as or included together with the insulating layer 140 shown. For example, in an embodiment where the substrate 50 is entirely a semiconductor substrate, the dielectric layer formed along the thinned back side may be the insulating layer 140 shown deposited by any suitable method. In addition, after the thinning process, a portion of the substrate 50 may remain adjacent to the gate structure (e.g., the gate electrode 102 and the gate dielectric layer 100) and the nanostructure 55. In some embodiments (not specifically illustrated), the back surface of the substrate 50, the epitaxial source / drain regions 92, the STI regions 68, and the fins 66 may be flush with each other after the thinning process.

[0173] According to some embodiments, the fifth recess 144 may be formed by etching using an anisotropic etching process such as RIE, NBE, etc. In some embodiments, the fifth recess 144 may be etched through the insulating layer 140, the substrate 50, and the fin 66 using one or more etching processes. A mask such as a photoresist may be formed and patterned over the insulating layer 140 to shield other portions from the etching process. In some embodiments, the etching process may over-etch, so that the fifth recess 144 extends to the back side of the epitaxial source / drain region 92. Fig.27B As shown in FIG. 1 , the fifth groove 144 may have angled sidewalls (eg, non-parallel) that pass through the fin 66 and the substrate 50 . Fig.27C As shown, the fifth groove 144 may have substantially parallel sidewalls that take the shape of the sidewalls of the corresponding fin 66. The subsequently formed dielectric liner 148 and contact 160 (see Fig.29B and Fig.29C )'s side walls can have similar shapes to these.

[0174] After forming the fifth recess 144, a dielectric liner 148 is deposited over the insulating layer 140, along the sidewalls of the fifth recess 144, and over the exposed surface of the epitaxial source / drain region 92, similar to the description above regarding the dielectric liner 118. In addition, an etching process is performed to remove a portion of the dielectric liner 148 and re-expose the back side of the epitaxial source / drain region 92. The dielectric liner 148 may be silicon nitride, etc., and may be deposited by any suitable method, such as CVD, PECVD, ALD, etc. The etching process may be an anisotropic etch that removes a portion of the dielectric liner 148 from the surface of the insulating layer 140 and the surface of the epitaxial source / drain region 92.

[0175] Still reference Figure 27A-27C , a back epitaxial cap 150 is formed on the exposed back side of the epitaxial source / drain region 92, and nodules 150N may be formed on other surfaces within the N-type region 50N and nodules 150P may be formed on other surfaces within the P-type region 50P, similar to the above description of epitaxial cap 120 and nodules 120N, 120P. In some embodiments, the back epitaxial cap 150 is formed in the N-type region 50N while shielding the P-type region 50P, and the back epitaxial cap 150 is formed in the P-type region 50P while the N-type region 50N is shielded. The back epitaxial cap 150 may replenish material on the back side of the epitaxial source / drain region 92 that may have been lost due to over-etching during the formation of the fifth recess 144 and / or during the etching of the dielectric liner 148. Therefore, the back epitaxial cap 150 may be considered as part of the corresponding epitaxial source / drain region 92.

[0176] According to some embodiments, the back epitaxial cap 150 formed in the N-type region 50N may be formed of the same or similar material as the epitaxial source / drain region 92 in the N-type region 50N (eg, the first semiconductor material layer 92A, see Figures 12A-12D ), such as phosphorus-doped silicon. The back epitaxial cap 150 formed in the P-type region 50P may be made of the same or similar material as the epitaxial source / drain region 92 in the P-type region 50P (eg, the first semiconductor material layer 92A, see Figures 12A-12D ), such as boron-doped silicon germanium. In some embodiments, the back epitaxial cap 150 is formed of a similar material having a different composition than the exposed portion of the epitaxial source / drain region 92. The back epitaxial cap 150 can be used to reduce the resistance between subsequently formed source / drain contacts (e.g., including the silicide portion of the source / drain contacts) and the epitaxial source / drain region 92. The nodules 150N, 150P can be non-crystalline (e.g., amorphous and / or polycrystalline), including the same epitaxial material that forms the back epitaxial cap 150 in the N-type region 50N and the P-type region 50P, respectively. For example, the epitaxial cap 150 can be formed using a low temperature epitaxial process, such as a temperature of 400°C or less.

[0177] According to some embodiments, similar to nodules 92N and nodules 120N, nodules 150N (e.g., small clusters of epitaxial material) may grow along the sidewalls of the insulating layer 140 and the fifth recess 144 (e.g., the dielectric liner 148) in the N-type region 50N during the formation of the epitaxial cap 150 in the N-type region 50N. Similarly, nodules 150P (e.g., small clusters of epitaxial material) may grow along the sidewalls of the insulating layer 140 and the fifth recess 144 (e.g., the dielectric liner 148) in the P-type region 50P during the formation of the epitaxial cap 150 in the P-type region 50P. For example, nodules 150N may be silicon and / or phosphorus-doped silicon (or the like), and nodules 150P may be silicon germanium and / or boron-doped silicon germanium (or the like). As shown, each epitaxial cap 150 is formed as a continuous material with the back side of the epitaxial source / drain region 92, while the nodules 150N, 150P are formed as discontinuous clusters or discontinuous nodules. As described above, in some embodiments, some or all of the nodules 150N, 150P may be polycrystalline, amorphous, or a combination thereof.

[0178] exist Figure 28A-28C In the embodiment, one or more cleaning processes are performed to remove nodules 150N, 150P, similar to the above description of removing nodules 92N, 92P (see Figures 13A-13D ) and / or removal of nodules 120N, 120P (see Figure 25A-Figure 25C ). For example, an NFET cleaning process is performed to remove the nodule 150N in the N-type region 50N while shielding the P-type region 50P, and a PFET cleaning process is performed to remove the nodule 150P in the P-type region 50P while shielding the N-type region 50N.

[0179] Similar to the above, the NFET cleaning process includes flowing gaseous precursors fluorine (F2) and ammonia (NH3) to remove nodules 150N, and the PFET cleaning process includes flowing gaseous precursors fluorine (F2) and hydrogen fluoride (HF) to remove nodules 150P. The cleaning process may be performed according to the same other parameters as previously described with respect to the cleaning process for removing nodules 92N, 92P (see Figures 13A-13D In some embodiments, due to the formation of fewer and / or smaller nodules 150N, 150P than nodules 92N, 92P, as discussed above with respect to nodules 92N, 92P, the cleaning process can be performed for a shorter duration (e.g., for a duration of about 3 minutes or less). It should be noted that the process parameters can be adjusted based on the number, total volume, individual size, and covered surface area of ​​nodules 150N, 150P.

[0180] The cleaning process achieves similar benefits as discussed above (e.g., preventing etching or damage to epitaxial source / drain regions 92 and other exposed features) and may also similarly increase the surface roughness of certain layers by etching exposed portions of those layers while removing nodules 150N, 150P. For example, the roughness of an exposed surface of silicon nitride (e.g., dielectric liner 148) may be increased from Increase to For example, the roughness increases Or increase the previous roughness by two to five times. In addition, the cleaning process can remove up to about 90% of the number and / or volume of nodules 150N, 150P. Similarly, the cleaning process can reduce the surface area coverage of nodules 150N, 150P by up to about 90%.

[0181] It should be noted that due to the different process conditions and duration for forming epitaxial cap 150 as compared to the formation of epitaxial source / drain regions 92, the number, total volume, individual size, and surface area coverage of nodules 150N, 150P may be smaller than those corresponding metrics of nodules 92N, 92P. Thus, in some embodiments, the roughness of dielectric liner 148 may be determined from Increase to For example, the roughness increases up to about For example, after a cleaning process to remove nodules 150N, 150P, dielectric liner 148 may be less rough (e.g., have a smaller increase in roughness) than first and second spacers 81, 83 after a cleaning process to remove nodules 92N, 92P. In addition, the roughness of dielectric liner 148 may be increased by approximately the same amount as dielectric liner 118 (and result in a similar roughness to dielectric liner 118).

[0182] exist Figure 29A-29CIn the embodiment of the present invention, the silicide region 154 and the contact 160 (also referred to as a contact plug, a source / drain contact, a source / drain contact plug, or a back contact) are formed in the fifth recess 144. For example, after the epitaxial cap 150 is formed and the nodules 150N, 150P are removed, the silicide region 154 is formed on the epitaxial source / drain region 92 (e.g., on the epitaxial cap 150). In some embodiments, the silicide region 154 is formed by first depositing a metal (not specifically shown) that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial cap 150 to form a silicide and / or germanide, such as depositing nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof on the exposed portion of the epitaxial source / drain region 92 (e.g., the epitaxial cap 150), and then performing a thermal annealing process to form the silicide region 154. The unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide region 154 is referred to as a silicide region, as described above, the silicide region 154 may also be a germanide region, or a silicon-germanide region (e.g., a region including silicide and germanide). In one embodiment, the silicide region 154 includes TiSi.

[0183] The contacts 160 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the contacts 160 each include a barrier layer and a conductive material, and are electrically coupled to the conductive component below (e.g., the silicide region 154 in the illustrated embodiment). The contacts 160 are electrically coupled to the silicide region 154 and may be referred to as source / drain contacts. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the insulating layer 140.

[0184] According to some embodiments (not specifically illustrated), a backside interconnect structure is formed on the structure and is electrically connected to an active device (e.g., a nano FET) through a contact 160. Specifically, although not specifically illustrated, the backside interconnect structure can be formed similarly to the frontside interconnect structure, and an external connector can be formed on the backside interconnect structure and / or the frontside interconnect structure.

[0185] Figure 30A-Figure 30C Cross-sectional views of devices according to some alternative embodiments are illustrated. Fig. 30A Illustrated Figure 1 Reference section AA' is illustrated in FIG. Fig. 30B Illustrated Figure 1 Reference section BB' illustrated in FIG. Fig. 30C Illustrated Figure 1 The reference section C-C' is shown in FIG. Figure 30A-Figure 30C In the drawings, similar reference numerals denote Figure 29A-29C Similar components are formed by similar processes. Figure 30A-Figure 30C In the embodiment, the channel regions in the N-type region 50N and the P-type region 50P include the same material. For example, the second nanostructure 54 including silicon provides a channel region for the P-type nanoFET in the P-type region 50P and the N-type nanoFET in the N-type region 50N. Figure 30A-Figure 30C The structure of can be formed, for example, by removing the first nanostructure 52 from the P-type region 50P and the N-type region 50N at the same time; depositing the gate dielectric layer 100 and the gate electrode 102P (e.g., a gate electrode suitable for a P-type nanoFET) around the second nanostructure 54 in the P-type region 50P; depositing the gate dielectric layer 100 and the gate electrode 102N (e.g., a gate electrode suitable for an N-type nanoFET) around the second nanostructure 54 in the N-type region 50N. In such an embodiment, the material of the epitaxial source / drain region 92 can be different in the N-type region 50N compared to the P-type region 50P, as described above.

[0186] Embodiments of the present disclosure can achieve advantages. For example, epitaxial processes such as the formation of epitaxial source / drain regions 92 and the formation of epitaxial caps 120, 150 may cause non-crystalline nodules of epitaxial material (e.g., nodules 92N, 92P, 120N, 120P, 150N, 150P) to be disposed in unwanted locations. In particular, the embodiment cleaning process can be selected and adjusted based on the epitaxial material, quantity, total volume, individual size, covered surface area, etc. to remove nodules. The cleaning process selectively etches and removes nodules while preventing unexpected damage or etching of exposed portions of the epitaxial source / drain regions 92 and other components. The resulting semiconductor device can be manufactured with higher yield and efficiency and has more robust performance and reliability.

[0187] In one embodiment, a method is provided including forming a first semiconductor fin and a second semiconductor fin over a front surface of a substrate; etching a first groove in the first semiconductor fin and etching a second groove in the second semiconductor fin; forming a first epitaxial region in the first groove and forming a first epitaxial nodule along a sidewall of the first groove; forming a second epitaxial region in the second groove and forming a second epitaxial nodule along a sidewall of the second groove; flowing a first precursor to remove the first epitaxial nodule; depositing an interlayer dielectric over the first epitaxial region and the second epitaxial region; etching a first opening in the interlayer dielectric to expose the first epitaxial region; forming a first epitaxial cap on the first epitaxial region, forming a third epitaxial nodule on the interlayer dielectric; and flowing a second precursor to remove the third epitaxial nodule. In another embodiment, the first epitaxial region includes a first material in a crystalline form, and each of the first epitaxial nodules includes the first material in a non-crystalline form. In another embodiment, the first precursor includes fluorine and ammonia. In another embodiment, the first precursor does not contain chlorine. In another embodiment, the first epitaxial region includes crystalline silicon. In another embodiment, the method further comprises, after depositing the interlayer dielectric: thinning the back side of the substrate; etching a second opening through the back side of the substrate to expose the second epitaxial region; forming a second epitaxial cap in the second epitaxial region and a fourth epitaxial nodule on the back side of the substrate; and flowing a third precursor to remove the fourth epitaxial nodule. In another embodiment, the second epitaxial region comprises silicon germanium, and wherein the second epitaxial cap comprises silicon germanium. In another embodiment, the third precursor comprises fluorine gas and hydrogen fluoride.

[0188] In one embodiment, a method is provided, including forming a source / drain region in a fin; forming a gate structure over the fin; depositing a dielectric layer over the source / drain region and the gate structure; etching an opening in the dielectric layer to expose the source / drain region; forming a dielectric liner over the dielectric layer and over the source / drain region in the opening; etching a portion of the dielectric liner to expose the source / drain region; forming an epitaxial cap over the source / drain region, the epitaxial cap comprising a crystalline form of a first epitaxial material; flowing a first precursor over the epitaxial cap, the first precursor having a higher etch selectivity to an amorphous form of the first epitaxial material than to a crystalline form of the first epitaxial material; converting at least a portion of the epitaxial cap into a silicide region; forming a contact plug over the silicide region in the opening. In another embodiment, the step of forming the epitaxial cap includes forming a first epitaxial nodule in the opening along a remaining portion of the dielectric liner, and wherein the first epitaxial nodule comprises the first epitaxial material in at least one of an amorphous form and a polycrystalline form. In another embodiment, the epitaxial cap comprises silicon, and wherein the first precursor comprises fluorine gas and ammonia gas. In another embodiment, the epitaxial cap comprises silicon germanium, and wherein the first precursor comprises fluorine gas and hydrogen fluoride gas. In another embodiment, the dielectric liner has a first roughness prior to forming the epitaxial cap, wherein the dielectric liner has a second roughness after flowing the first precursor, and wherein the second roughness is greater than the first roughness. In another embodiment, the second roughness is two to five times greater than the first roughness. In another embodiment, the step of forming the source / drain region comprises forming a crystalline form of the second epitaxial material; depositing a second epitaxial nodule along the gate spacer, the second epitaxial nodule comprising the second epitaxial material in an amorphous form. In another embodiment, the method further comprises flowing a second precursor through the source / drain region, the second precursor having a higher etch selectivity to the second epitaxial nodule than to the source / drain region.

[0189] In one embodiment, a structure is provided, including a source / drain region above a semiconductor fin; a gate structure located above the semiconductor fin and adjacent to the source / drain region, the gate structure including a gate spacer layer, the gate spacer layer having a first roughness; a first dielectric layer above the source / drain region; a first contact plug electrically coupled to the source / drain region and extending through the first dielectric layer. A first nitride liner is between the first contact plug and the first dielectric layer, the first nitride liner having a second roughness, the second roughness being less than the first roughness. In another embodiment, the structure further includes a second contact plug electrically coupled to the source / drain region and extending through the semiconductor fin. In another embodiment, the structure further includes a second nitride liner between the second contact plug and the semiconductor fin, wherein the second nitride liner has a third roughness less than the first roughness. In another embodiment, the second nitride liner extends along the semiconductor fin and along an isolation region adjacent to the semiconductor fin.

[0190] The above summarizes the components of several embodiments so that those skilled in the art can more easily understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the concept and scope of the present invention, and they can make various changes, substitutions and replacements without violating the concept and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a source / drain region located on a semiconductor fin; A gate structure located on the semiconductor fin and adjacent to the source / drain region, the gate structure comprising a gate spacer layer having a first roughness; a plurality of first dielectric layers located above the source / drain region; a first contact plug electrically coupled to the source / drain region and extending through the first dielectric layer; as well as A first nitride liner is disposed between the first contact plug and the first dielectric layer. The first nitride liner has a second roughness that is smaller than the first roughness.

2. The semiconductor device according to claim 1, wherein Also included is a second contact plug electrically coupled to the source / drain region and extending through the semiconductor fin.

3. The semiconductor device according to claim 2, wherein: The second contact plug is a single-layer structure.

4. The semiconductor device according to claim 2, wherein: The second contact plug is a multi-layer structure.

5. The semiconductor device according to claim 2, wherein: The invention also includes a second nitride liner between the second contact plug and the semiconductor fin, wherein the second nitride liner has a third roughness smaller than the first roughness.

6. The semiconductor device according to claim 5, wherein: The second nitride liner has a plurality of substantially parallel sidewalls.

7. The semiconductor device according to claim 5, wherein: The second nitride liner extends along the semiconductor fin and along an isolation region adjacent to the semiconductor fin.

8. The semiconductor device according to claim 7, wherein: The isolation region is a shallow trench isolation region.

9. The semiconductor device according to claim 2 or 3, wherein: The invention also includes a silicide region between the source / drain region and the second contact plug.

10. The semiconductor device according to claim 9, wherein: Also included is an epitaxial cap between the source / drain region and the silicide region.

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