Integrated circuit device

Abstract

Some embodiments of the utility model relate to an IC device. The IC device includes a first chip including a plurality of pixel blocks, each including one of a first plurality of conductive pads, the plurality of pixel blocks being arranged in a row extending in a first direction and a column extending in a second direction perpendicular to the first direction; a second chip bonded to the first chip at a bonding interface, wherein the second chip includes a recessed second plurality of conductive pads and the second plurality of conductive pads contacts the first plurality of conductive pads along the bonding interface; and a first corrugated shielding line having an outermost edge retracted in the second direction from an outermost edge of a first row of the plurality of pixel squares, the first corrugated shielding line being disposed within the first dielectric layer and laterally separating adjacent first plurality of conductive pads in the first row of the plurality of pixel squares.

Description

Technical Field

[0001] The utility model relates to an integrated circuit device. Background Art

[0002] Many modern electronic devices include digital image sensors. Digital image sensors can be backside illuminated sensors or frontside illuminated sensors. Digital image sensors can utilize multi-chip packaging to reduce the area per pixel and increase the resolution of the resulting device. Utility Model Content

[0003] The utility model provides an integrated circuit (IC) device, comprising: a first IC chip, comprising a plurality of pixel blocks, wherein the plurality of pixel blocks respectively include one of a first plurality of conductive pads recessed in a first dielectric layer, and the plurality of pixel blocks are arranged in rows extending in a first direction and in columns extending in a second direction perpendicular to the first direction; a second IC chip, bonded to the first IC chip at a bonding interface, wherein the second IC chip includes a second plurality of conductive pads recessed in a second dielectric layer and the second plurality of conductive pads contact the first plurality of conductive pads along the bonding interface; and a first corrugated shielding line, having an outermost edge retracted from an outermost edge of a first row of the plurality of pixel blocks along the second direction, the first corrugated shielding line being arranged in the first dielectric layer and laterally separating adjacent first plurality of conductive pads in the first row of the plurality of pixel blocks.

[0004] The utility model provides another integrated circuit (IC) device, comprising: a first IC chip; a second IC chip bonded to the first IC chip at a bonding interface; and a first pixel arranged across the first IC chip and the second IC chip, the first pixel comprising a first photodetector subarray and a second photodetector subarray, wherein the first IC chip and the second IC chip respectively comprise a first dielectric layer and a second dielectric layer directly contacting at the bonding interface, the first IC chip further comprises a first conductive pad and a first shielding node recessed in the first dielectric layer and at the bonding interface, the first conductive pad being below the first photodetector subarray, the first shielding node being below the second photodetector subarray, and a first section and a second section of a first corrugated shielding line protruding outwardly from opposite sidewalls of the first shielding node to partially surround the first conductive pad.

[0005] The utility model provides a method for forming an integrated circuit (IC) device, comprising: implanting dopants into a first substrate in a first IC chip to form a light detector array having a plurality of pixel blocks arranged in columns and rows; forming a first interconnect structure on the first substrate, the first interconnect structure comprising a first plurality of conductive pads surrounded by a first dielectric layer; forming a first plurality of corrugated shielding lines directly between the conductive pads and in a single row of the plurality of pixel blocks respectively; forming a second interconnect structure on a second IC chip, the second interconnect structure comprising a second plurality of conductive pads surrounded by a second dielectric layer and a second plurality of corrugated shielding lines; flipping the first IC chip and placing the first IC chip on the second IC chip so that the first plurality of conductive pads face the second plurality of conductive pads; and bonding the first IC chip to the second IC chip at a bonding interface, wherein the second plurality of conductive pads are bonded to the first plurality of conductive pads at the bonding interface, and wherein the first plurality of corrugated shielding lines and the second plurality of corrugated shielding lines isolate portions of the first plurality of conductive pads and the second plurality of conductive pads from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noteworthy that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A and Figure 1B Cross-sectional views and top layout views of some embodiments of an integrated circuit (IC) device including metal-metal (MM) and dielectric-dielectric (DD) bonding layers with corrugated shield lines are shown.

[0008] Figure 2A and Figure 2B A cross-sectional view of an alternative embodiment of an IC device including MM and DD bonding layers with corrugated shield lines is shown.

[0009] Figure 2C Cross-sectional views of some embodiments of IC devices with corrugated shield lines and MM and DD bonding layers with additional detail are shown.

[0010] Figure 3A A top layout diagram of some embodiments of an IC device including MM and DD bonding layers with corrugated shield lines and additional details is shown.

[0011] Figure 3B A top layout diagram of an alternative embodiment of an IC device including MM and DD bonding layers with corrugated shield lines and additional details is shown.

[0012] Figure 4 Circuit diagrams of some embodiments of an IC device are shown having a 2×4 array of light detectors in a first IC chip connected to a second IC chip through a bonding interface.

[0013] Figure 5 Cross-sectional views of some embodiments of IC devices including MM and DD bonding layers with corrugated shield lines at the bonding interface are shown.

[0014] Figures 6 to 12 , Fig.13A , Fig. 13B and Figures 14 to 18 A series of cross-sectional views and top layout diagrams of some embodiments of methods for forming an IC device including MM and DD bonding layers with corrugated shield lines at a bonding interface are shown.

[0015] Fig.19 A flow chart illustrating some embodiments of a method for forming an IC device including MM and DD bonding layers with corrugated shield lines. DETAILED DESCRIPTION

[0016] The present disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, forming a first feature on or on a second feature in the following description may include an embodiment in which the first and second features are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, spatially relative terms, such as "below," "beneath," "below," "above," "over," and the like, may be used herein to facilitate describing the relationship of one component or feature to another component or feature, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0018] The image sensor may include a pixel array having a plurality of pixels arranged in rows and columns. The pixels include individual photodetectors in a substrate of a first IC chip. The pixels further include individual transfer transistors that couple the individual photodetectors to individual floating diffusion nodes in the substrate. The floating diffusion nodes may be electrically coupled to an interconnect structure of a second IC chip via metal-metal (MM) and dielectric-dielectric (DD) bonding layers. The MM and DD bonding layers include a plurality of conductive pads surrounded by a dielectric material.

[0019] The second IC chip houses a plurality of transistors, which are individually connected to the pixels. These transistors include a plurality of source follower transistors, a plurality of reset transistors, and a plurality of select transistors, which are configured to read the photodetector and selectively pass the reading of the photodetector to an application specific integrated circuit (ASIC) on a third IC chip. Placing the transistors at the second IC chip instead of at the first IC chip can free up space on the first IC chip, thereby allowing the pixels to be reduced without reducing the size of the photodetector. This thus increases the maximum resolution of the image sensor. A higher maximum resolution is desirable because it increases the quality of the acquired image.

[0020] During operation of the image sensor, charge is transferred from individual photodetectors to the gates of multiple source follower transistors through conductive pads within the MM and DD bonding layer. Due to the proximity of the conductive pads, mutual inductance and mutual capacitance may exist between the conductive pads. The mutual inductance and mutual capacitance between the conductive pads result in crosstalk between the conductive pads. The resulting crosstalk increases as the image sensor shrinks and reduces the accuracy of the captured image. Crosstalk can be avoided by completely surrounding the conductive pads with an electrically grounded shield line. However, completely surrounding each conductive pad with a shield line increases the pattern density of the MM and DD bonding layer, resulting in a higher patterning failure rate, increased dents, and lower bonding interface quality between the first IC chip and the second IC chip.

[0021] The present disclosure relates to an image sensor integrated chip (IC) comprising a plurality of pixel blocks arranged in rows and columns in an array. A plurality of conductive pads are arranged within the plurality of pixel blocks. A corrugated shield line extends between conductive pads in a row of the pixel blocks, but does not extend between the conductive pads in the row and other conductive pads in different rows of the pixel blocks. The corrugated shield line is configured to interrupt the electromagnetic field and reduce the mutual inductance and mutual capacitance between adjacent conductive pads in the row of the pixel blocks. The reduction in mutual inductance reduces the amount of interference, allowing the image sensor IC to produce a higher quality image. Because the pixel blocks can be read on a row-by-row basis, the lack of a shield line between the conductive pad and the other conductive pads does not significantly affect the crosstalk between different rows of the pixel blocks. However, not placing a shield line between the conductive pad and the other conductive pads reduces the pattern density of the MM and DD bonding layers, thereby reducing the number of patterning failures and enhancing the bonding interface quality between the first IC chip and the second IC chip.

[0022] Figure 1A and Figure 1B Some embodiments of an integrated circuit (IC) device including MM and DD bonding layers with corrugated shield lines are shown in cross-sectional view 100a and top layout view 100b, respectively. Figure 1A The cross-sectional view 100a may be, for example, along Figure 1B The line A-A' in the Figure 1B The top layout diagram 100b may be, for example, along the Figure 1A The line A-A' in is intercepted.

[0023] As shown in the cross-sectional view 100a, the IC device includes a first IC chip 101 having a first MM and DD bonding layer 106 and a second IC chip 103 having a second MM and DD bonding layer 115. The first MM and DD bonding layer 106 includes a first plurality of conductive pads 102, which are electrically coupled to the first wiring level 110a through a first plurality of bonding contacts 112a. The second MM and DD bonding layer 115 includes a second plurality of conductive pads 114, which are electrically coupled to the second wiring level 110b through a second plurality of bonding contacts 112b. In addition, the first plurality of conductive pads 102 are electrically coupled to the second wiring level 110b through the second plurality of bonding contacts 112b and the second plurality of conductive pads 114 in the second MM and DD bonding layer 115.

[0024] The first plurality of conductive pads 102 are surrounded by the first dielectric layer 108a, and the second plurality of conductive pads 114 are surrounded by the second dielectric layer 108b. The first dielectric layer 108a and the second dielectric layer 108b are bonded to each other at the first bonding interface 105. In some embodiments, the second plurality of conductive pads 114 are in the second IC chip 103 and bonded to the first plurality of conductive pads 102 at the first bonding interface 105. As such, the first bonding interface 105 has a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface, and thus the first bonding interface 105 is a hybrid or a mix of the two bonding interfaces. The symmetrical bonding of the first plurality of conductive pads 102 and the second plurality of conductive pads 114 allows for a stronger bond between the first IC chip 101 and the second IC chip 103, because the bonding of the first plurality of conductive pads 102 to the second plurality of conductive pads 114 is more effective than the bonding of the first plurality of conductive pads 102 to the second dielectric layer 108b of the second IC chip 103.

[0025] In some embodiments, the first plurality of bonding contacts 112a, the second plurality of bonding contacts 112b, the first plurality of conductive pads 102, the second plurality of conductive pads 114, or any combination thereof are or include metals, such as copper (e.g., Cu), aluminum, silver (e.g., Ag), gold (e.g., Au), and / or the like. In some embodiments, the first dielectric layer 108a and the second dielectric layer 108b each include one or more respective dielectric materials. The first dielectric layer 108a is bonded to the second dielectric layer 108b by van der Waals forces. In some embodiments, the first dielectric layer 108a and the second dielectric layer 108b may be or include one of silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), silicon oxynitride, and / or the like.

[0026] As shown in cross-sectional view 100a and top layout view 100b, the integrated chip includes a plurality of pixel blocks 118, each of which includes one or more photodetectors. For example, one pixel block of the plurality of pixel blocks 118 may include 4 photodetectors (e.g., arranged in a 2×2 array), 8 photodetectors (e.g., arranged in a 2×4 array), or other similar values. The plurality of pixel blocks 118 are arranged in rows extending along a first direction 122 and in columns extending along a second direction 124, the second direction 124 being perpendicular to the first direction 122. The plurality of pixel blocks 118 each include one of the first plurality of conductive pads 102. During a read operation, the first plurality of conductive pads 102 transfer charge from individual photodetectors within the plurality of pixel blocks 118 to the gate of a source follower transistor (e.g., within the second IC chip 103) on a row-by-row basis. For example, during a read operation, a signal may be transferred from the first row 120a in the pixel block while the second row 120b in the pixel block is set to a high voltage (eg, V DD ), the signal can then be transferred from the second row 120b within the pixel block while the first row 120a in the pixel block is set to a high voltage. Because the read operation is performed on a row-by-row basis, minimal noise is generated between conductive pads in adjacent rows (e.g., between conductive pads in the first row 120a and conductive pads in the second row 120b) during the read operation.

[0027] The first corrugated shield line 104 extends in a zigzag pattern that laterally separates adjacent ones of the first plurality of conductive pads 102 within a row of the plurality of pixel blocks 118. For example, a first conductive pad within the first row 120a is laterally separated from a second conductive pad within the first row 120a by the first corrugated shield line 104. The first corrugated shield line 104 has an outermost surface that weaves around adjacent ones of the first plurality of conductive pads 102 within a row. The outermost edges of the first corrugated shield line 104 are located at the top and bottom of the zigzag pattern, as seen in the top layout diagram 100b. In some embodiments, the entirety of the first corrugated shield line 104 is within a corresponding row in the plurality of pixel blocks 118. For example, the first corrugated shield line 104 may have an outermost edge (e.g., the edges of the uppermost and lowermost layers as seen in the top layout diagram 100b) that is retracted a non-zero distance from the outermost edge of the first row 120a (e.g., the edges of the uppermost and lowermost layers as seen in the top layout diagram 100b). In some embodiments, the entire first corrugated shield line 104 within a row is confined between the relative outermost edges of the plurality of conductive pads within the row (e.g., between the top and bottom edges observed in the top layout diagram 100b). In some embodiments, the first corrugated shield line 104 within a row is outside of an adjacent row (e.g., does not extend from within a row into an adjacent row). In some embodiments, the first corrugated shield line 104 is or includes a metal, such as copper (e.g., Cu), silver (e.g., Ag), gold (e.g., Au), aluminum, and / or the like.

[0028] In some embodiments, the first corrugated shield line 104 may include shield line segments 104b, 104c and one or more shield nodes 104a having a width greater than the shield line segments 104b, 104c. In some embodiments, one or more shield nodes 104a may have a top geometry (e.g., a square geometry) identical to the top geometry of the first plurality of conductive pads 102. In some such embodiments, the first plurality of conductive pads 102 are interlaced with the shield nodes 104a in the array so that the placement of the first plurality of conductive pads 102 and the shield nodes 104a alternates on columns and rows. The first plurality of conductive pads 102 have a zig-zag layout along columns and rows. In addition, a plurality of shield line segments 104b, 104c extend along columns and rows in a zig-zag layout and between adjacent shield nodes 104a. In some embodiments, the second corrugated shield line 116 is joined to the first corrugated shield line 104 in the second IC chip 103 and over the length of the first corrugated shield line 104. Furthermore, a shield node of the second corrugated shield line 116 is directly between the first and second conductive pads of the second plurality of conductive pads 114. In some embodiments, the second corrugated shield line 116 may include shield line segments and one or more shield nodes having a greater width than the shield line segments.

[0029] The first corrugated shield line 104 is biased in a manner configured to mitigate crosstalk between adjacent first plurality of conductive pads 102 within a row (e.g., first row 120a or second row 120b) of a plurality of pixel blocks 118. In some embodiments, to avoid coupling between adjacent conductive pads, the first corrugated shield line 104 may be electrically grounded, electrically biased, or electrically floating. Because the first plurality of conductive pads 102 within a row are laterally separated by the first corrugated shield line 104, the mutual inductance and mutual capacitance between the first plurality of conductive pads within the row are reduced. This causes the charge transferred through the first conductive pad of the first plurality of conductive pads to have a weakened effect on other conductive pads of the first plurality of conductive pads, and vice versa. Therefore, interference caused by the proximity of the first plurality of conductive pads to each other is reduced, and the pixel array divided between the first IC chip 101 and the second IC chip 103 can output a higher quality image than would otherwise be possible. Furthermore, since the plurality of pixel blocks 118 are read on a row-by-row basis, no corrugated shield lines are required between adjacent rows to provide noise mitigation, thereby avoiding limiting the MM and DD bonding layer pattern density and resulting in a high quality bonding interface.

[0030] Figure 2A and Figure 2B A cross-sectional view of an alternative embodiment of an IC device including MM and DD bonding layers with corrugated shield lines is shown.

[0031] like Figure 2A As shown in the cross-sectional view 200a of FIG. 1 , in some embodiments, the second IC chip 103 omits the second corrugated shielding line ( Figure 1A 116) and a second plurality of conductive pads ( Figure 1A 114). The second plurality of bonding contacts 112b are bonded to the first plurality of conductive pads 102 along the first bonding interface 105, so that the bonding interface is asymmetric. The omission of the second corrugated shield line 116 and the second plurality of conductive pads 114 may be desirable to reduce production costs, reduce the combined size of the conductive pads, and reduce the amount of mutual capacitance between adjacent conductive features.

[0032] During the bonding process, bubbles of gas may be trapped between the first dielectric layer 108a and the second dielectric layer 108b. The first plurality of corrugated shield wires 104 may help release gas that may be trapped between the first dielectric layer 108a and the second dielectric layer 108b due to different surface conditions at the time of bonding, due to dents, or other effects. The first plurality of corrugated shield wires 104 may provide a path for gas to escape bubbles that would otherwise form between the first dielectric layer 108a and the second dielectric layer 108b.

[0033] In some embodiments, Figure 1AAs shown, the first corrugated shield wire 104 and the second corrugated shield wire 116 are symmetrical and in the first dielectric layer 108a and the second dielectric layer 108b. The symmetry of the first corrugated shield wire 104 and the second corrugated shield wire 116 can result in fewer bubbles of gas remaining between the first dielectric layer 108a and the second dielectric layer 108b, because when the first dielectric layer 108a and the second dielectric layer 108b are bonded, the first corrugated shield wire 104 and the second corrugated shield wire 116 provide a larger path for gas to escape. The first corrugated shield wire 104 and the second corrugated shield wire 116 are further bonded together during a later process, wherein the enhanced bonding of the first plurality of corrugated shield wires 104 to the second corrugated shield wire 116 results in fewer bubbles.

[0034] like Figure 2B As shown in the cross-sectional view 200b of FIG. 1 , in some embodiments, the third MM and DD bonding layer 203 is directly below the first MM and DD bonding layer 106 and includes a third plurality of conductive pads 204. In some embodiments, the thickness of the first MM and DD bonding layer 106 is greater than or equal to the thickness of the third MM and DD bonding layer 203. In other embodiments (not shown), the thickness of the first MM and DD bonding layer 106 is less than the thickness of the third MM and DD bonding layer 203.

[0035] The third plurality of conductive pads 204 are directly and respectively located below the first plurality of conductive pads 102. The third plurality of conductive pads 204 are respectively bonded to the second plurality of bonding points 112b at the first bonding interface 105. The first corrugated shield line 104 is separated from the first bonding interface 105 by the third dielectric layer 108c in the third MM and DD bonding layer 203. In some embodiments, the bottom surface of the first corrugated shield line 104 is flush with the top surface of the third MM and DD bonding layer 203.

[0036] The third dielectric layer 108c bonds more effectively to the second dielectric layer 108b than the third dielectric layer 108c bonds to the first corrugated shield line 104. Therefore, because the third MM to DD bonding layer 203 separates the first plurality of corrugated shield lines 104 from the first bonding interface 105, a better bond is created between the first IC chip 101 and the second IC chip 103.

[0037] Figure 2C Cross-sectional views of some embodiments of IC devices with corrugated shield lines and MM and DD bonding layers with additional detail are shown.

[0038] like Figure 2CAs shown in the cross-sectional view 200c of , in some embodiments, there are a first dielectric material 208a and a second dielectric material 208b at the first bonding interface 105. The first dielectric material 208a is a part of the first dielectric layer 108a, and the second dielectric material 208b is a part of the second dielectric layer 108b. In some embodiments, the first dielectric material 208a and the second dielectric material 208b can be or include silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), silicon oxynitride, another insulating material, the like, or any combination of the foregoing. In some further embodiments, other portions of the first dielectric layer 108a and the second dielectric layer 108b constitute a dielectric material different from the first dielectric material 208a and the second dielectric material 208b. The addition of the first dielectric material 208a and the second dielectric material 208b can provide a greater bonding strength between the first IC chip 101 and the second IC chip 103.

[0039] Figure 3A A top layout diagram of some embodiments of an IC device with corrugated shield lines and MM and DD bonding layers with additional details is shown.

[0040] like Figure 3A As shown in top layout diagram 300a of FIG. 1 , an array of photodetectors 302 (dashed lines) covers first plurality of conductive pads 102a-102e. The array of photodetectors 302 is such that four photodetectors are in a 2×2 sub-array and directly above each individual conductive pad of first plurality of conductive pads 102, and four photodetectors are in a 2×2 sub-array and directly above each individual shielding node of shielding node 104a. In some embodiments, one or more photodetectors within the array of photodetectors 302 extend continuously from directly below first corrugated shield line 104 to laterally past the outermost sidewall of first corrugated shield line 104.

[0041] Eight photodetectors form one pixel in one pixel block. The eight photodetectors overlie and couple to one conductive pad and further overlie one shielding node. For example, first pixel 304 (including the first plurality of photodetectors) overlie and couple to first conductive pad 102a and further overlie shielding node 104a. The eight photodetectors are coupled to first conductive pad 102a via two floating diffusion nodes (not shown) located directly above first conductive pad 102a and shielding node 104a, respectively. Additional pixels 306, 308 are in first row 310 with first pixel 304. For example, second pixel 306 (including the second plurality of photodetectors) is directly over third conductive pad 102c and electrically coupled to third conductive pad 102c. In some embodiments, the first plurality of photodetectors and the second plurality of photodetectors are adjacent. The first plurality of conductive pads 102 in the first row 310 are offset from each other in the zigzag line 309 below the pixels 304 , 306 , and 308 .

[0042] In some embodiments, the first shielding line segment 104b of the first corrugated shielding line 104 is a portion extending from the first conductive pad 102a to the third conductive pad 102c substantially perpendicular to the sawtooth line 309, and the second shielding line segment 104c of the first corrugated shielding line 104 is a portion extending from the first conductive pad 102a to the third conductive pad 102c substantially parallel to the sawtooth line 309. The first shielding line segment 104b and the second shielding line segment 104c are coupled to a shielding node 104a equidistant from the first conductive pad 102a and the second conductive pad 102b, and wherein the shielding node 104a is offset from the first conductive pad 102a in a first direction and offset from the third conductive pad 102c in a second direction perpendicular to the first direction. The portion of the sawtooth line 309 extending between the third conductive pad 102c and the second conductive pad 102b is at a 45 degree angle to the line 318 extending between the second conductive pad 102b and the first conductive pad 102a. A line 318 extending between the first conductive pad 102a and the second conductive pad 102b extends through the shielding node 104a.

[0043] In some embodiments, the second pixel 306 of the additional pixels 306, 308 covers and is coupled to the third conductive pad 102c, and further covers the additional shielding node 104a, which is close to the first conductive pad 102a and connected to the shielding node 104a below the first pixel 304 through the first shielding line segment 104b. In further embodiments, the first pixel 304 and the second pixel 306 are periodically and alternately repeated along an axis extending parallel to the first row 310 and the second row 312, and wherein the shielding nodes 104a of the repeated first pixel 304 and the second pixel 306 are electrically coupled through the repeated first shielding line segments 104b and the second shielding line segments 104c of the first corrugated shielding line 104. In some embodiments, the first row 310 and the second row 312 are periodically and alternately repeated along a second axis extending perpendicular to the first row 310 and the second row 312, and the first corrugated shielding line 104 is periodically repeated in the repeated first row 310 and the second row 312.

[0044] During operation, pixels 304, 306, and 308 in the first row 310 are read in parallel, and the light detectors in pixels 304, 306, and 308 are read row by row within the pixel. The first plurality of conductive pads 102 in other rows of pixels (e.g., the second row 312) maintain a constant voltage throughout the process, limiting the amount of interference that may come from other rows. Based on this pattern of readout operations, the first plurality of conductive pads 102 in the first row 310 are simultaneously sending light to the second IC chip ( Figure 1A 103) transfers charge. The sawtooth pattern of the first plurality of conductive pads 102 increases the distance between the first plurality of conductive pads 102. Since the electric field strength caused by the charge is inversely proportional to the square of the distance from the charge, increasing the distance reduces the strength of the electromagnetic field effect and the interference caused by the charge transfer. The first corrugated shield line 104 also reduces the mutual inductance and mutual capacitance between the first plurality of conductive pads 102 in the first row 310. The combination of the increased distance and the first corrugated shield line 104 allows the first MM to reduce interference between the first plurality of conductive pads 102 without reducing the resolution of the pixel array.

[0045] In some embodiments, the third conductive pad 102c of the first plurality of conductive pads 102 is separated from the fourth conductive pad 102d and the fifth conductive pad 102e. The third conductive pad 102c is separated from the fourth conductive pad 102d by the third corrugated shield line 316, and a line extending between the fifth conductive pad 102e and the third conductive pad 102c is parallel to a section of the third corrugated shield line 316. In further embodiments, the first shielding node 316a of the third corrugated shield line 316 is directly located between the third conductive pad 102c and the fourth conductive pad 102d. In further embodiments, the third conductive pad 102c, the fourth conductive pad 102d, and the fifth conductive pad 102e are substantially the same distance away from the first shielding node 316a of the third corrugated shield line 316.

[0046] like Figure 3B As shown in the top layout diagram 300b of FIG. 1 , in some embodiments, the first plurality of conductive pads 102 and the shielding node 104a are square in top view. The first shielding line segment 104b and the second shielding line segment 104c connecting the shielding node 104a of the first corrugated shielding line 104 extend to a line extending in the direction of the corresponding row at an angle θ' of 135 degrees and an angle θ of 45 degrees. In some embodiments, the first shielding line segment 104b and the second shielding line segment 104c may have a first width w1 between about 1000 angstroms and 200 angstroms, between about 800 angstroms and 1800 angstroms, between 1200 angstroms and 2200 angstroms, or within another suitable range. In some embodiments, the shielding node 104a may have a second width w2 that is larger than the first width w1.

[0047] Figure 4 Circuit diagrams of some embodiments of an IC device are shown having a 2×4 array of light detectors in a first IC chip connected to a second IC chip through a bonding interface.

[0048] like Figure 4As shown in the circuit diagram 400 of FIG. 1 , eight photodetectors 402 are electrically coupled to a floating diffusion node 405 through eight transfer transistors 404. The floating diffusion node 405 in the first IC chip 101 is coupled to a source follower transistor 408 in the second IC chip 103 through the first bonding interface 105. In some embodiments, each source follower transistor 408 has two floating diffusion nodes 405, and the eight photodetectors 402 are evenly distributed between the two floating diffusion nodes 405. For example, the eight photodetectors 402 can be divided into two 2×2 sub-arrays corresponding to the floating diffusion nodes 405. The reset transistor 406 selectively couples the floating diffusion node 405 to a reset voltage Vrst to reset the floating diffusion node 405 so as to perform other measurements. The source follower transistor 408 is coupled to a select transistor 410, which controls the transfer of a signal corresponding to the measured photocurrent of the photodetector 402 to an application specific integrated circuit (ASIC) 412 on the third IC chip 418. The third IC chip 418 is bonded to the second IC chip 103 via the second bonding interface 414 .

[0049] Figure 5 Cross-sectional views of some embodiments of IC devices including MM and DD bonding layers with corrugated shield lines at the bonding interface are shown.

[0050] like Figure 5 As shown in cross-sectional view 500 of FIG. 1 , first IC chip 101, second IC chip 103, and third IC chip 418 are bonded together at first bonding interface 105 and second bonding interface 414. The figure shows that the pixel has components that are independent of the pixel in first IC chip 101 and second IC chip 103. Transfer transistor 404 couples photodetector 402 to floating diffusion node 405. Transfer transistor 404 includes a respective gate 502 and a respective gate dielectric layer 504 stacked with gate 502 to form a gate stack. In addition, transfer transistor 404 includes a respective source / drain region in substrate 503. In some embodiments, substrate 503 is or includes one of a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like, which can be doped (e.g., with p-type or n-type dopants) or undoped. The source / drain region includes a collector region of photodetector 402 and floating diffusion node 405. The source / drain region may be referred to individually or collectively as a source or a drain, depending on the context.

[0051] A bias voltage is applied to the gate 502 of the transfer transistor 404 to form a channel between the photodetector 402 and the floating diffusion node 405 , providing a path for the photocurrent to flow. The photocurrent flows from the floating diffusion node 405 to the second IC chip 103 through the first interconnect structure 506 .

[0052] The first interconnect structure 506 includes a contact 508 extending from the floating diffusion node 405. The first interconnect structure 506 also includes a plurality of conductor levels 110a, 110c and a plurality of vias 512, which are alternately stacked from the contact 508 to a first plurality of bonding contacts 112a (only one of which is shown). The plurality of conductor levels 110a, 110c and the plurality of vias 512 are alternately stacked to form a conductive path. The plurality of conductor levels 110a, 110c provide lateral wiring between the plurality of vias 512. The plurality of vias 512 provide vertical wiring between the plurality of conductor levels 110a, 110c.

[0053] In some embodiments, one or more additional conductor levels are located between the first conductor level 110a and the third conductor level 110c. In some embodiments, the contacts 508, the plurality of conductor levels 110a, 110c, the plurality of vias 512, or any combination thereof are or include polysilicon, copper (e.g., Cu), titanium nitride (e.g., TiN), tungsten (e.g., W), aluminum (e.g., Al), tantalum nitride (e.g., TaN), the like, or any combination thereof. In some embodiments, the first plurality of bonding contacts 112a, the first plurality of conductive pads 102, or any combination thereof are or include copper (e.g., Cu), silver (e.g., Ag), gold (e.g., Au), another metal, the like, or any combination thereof. The first corrugated shield line 104 is laterally spaced from the first plurality of conductive pads 102.

[0054] The second plurality of bonding contacts 112b extend from the second plurality of conductive pads 114 to the second interconnect structure 513. In addition, the second interconnect structure 513 extends from the second plurality of bonding contacts 112b to the reset transistor 406, the source follower transistor 408, and the select transistor 410. The second plurality of bonding contacts 112b can, for example, be as described for the first plurality of bonding contacts 112a. In addition, the second interconnect structure 513 can, for example, be as described for the first interconnect structure 506, except for the layout and / or number of conductive features.

[0055] The second interconnect structure 513 is electrically coupled to the ASIC 412 on the third IC chip 418 through through substrate vias (TSVs) 514. The TSVs 514 are coupled to the third IC chip 418 through additional MM and DD bonding layers 516 at the second bonding interface 414. In some embodiments, the second interconnect structure 513 may be or include the same material as the first interconnect structure 506. The additional MM and DD bonding layers 516 may be, for example, as described for the first MM and DD bonding layers 106, except for the layout and / or number of conductive pads.

[0056] In some embodiments, photodetectors 402 are separated from each other by backside deep trench isolation (BDTI) structures 520. Backside metal grid (BSMG) 522 covers BDTI structures 520 and is surrounded by a grid of dielectric material 524. In some embodiments, a barrier layer 523 is provided between BSMG 522 and BDTI structures 520. A plurality of color filters 526 are disposed within the grid of dielectric material 524 and cover photodetectors 402. In other embodiments, a plurality of microlenses 528 are disposed above color filters 526. Color filters 526 and microlenses 528 are arranged in a plurality of columns and a plurality of rows, respectively covering photodetectors 402 of the pixel array.

[0057] Although Figures 1A to 5 The invention is described with respect to an image sensor integrated chip, but it should be understood that the disclosed corrugated shield line is not limited to such an embodiment. Instead, the disclosed corrugated shield line can be applied to any integrated chip structure including an array of conductive bonding pads operated in a column-by-column or row-by-row manner.

[0058] Figures 6 to 12 , Fig.13A , Fig. 13B and Figures 14 to 18 A series of cross-sectional views 600-1200, 1300a, 1400-1800 and a top layout view 1300b of some embodiments of a method for forming an IC device including an MM and DD bonding layer with a corrugated shield line at a bonding interface are shown. For example, the method can be used to form Figure 5 integrated chip or the like. Although Figures 6 to 12 , Fig.13A , Fig. 13B and Figures 14 to 18 Described as a series of actions, it should be understood that these actions are not limiting, because the order of actions can be changed in other embodiments and methods and are also applicable to other structures. In other embodiments, some actions illustrated and / or described can be omitted in whole or in part.

[0059] like Figure 6 As shown in cross-sectional view 600 of FIG. 5 , a plurality of light detectors 402 are formed in substrate 503 of an integrated chip. In some embodiments, light detectors 402 are formed by an implantation process. In further embodiments, a first mask layer (not shown) is formed on substrate 503 before the implantation process to protect portions of substrate 503 outside of light detectors 402 from being affected by dopants.

[0060] like Figure 7As shown in the cross-sectional view 700 of , a plurality of transfer transistors 404 and floating diffusion nodes 405 are formed on the substrate 503. In some embodiments, the transfer transistors 404 are formed using one or more deposition steps to form layers corresponding to the plurality of gate dielectric layers 504 and the plurality of gates 502. In further embodiments, one or more etching processes are performed to pattern the layers into the plurality of gate dielectric layers 504 and the plurality of gates 502. In some embodiments, the plurality of floating diffusion nodes 405 are formed by an implantation process.

[0061] like Figure 8 As shown in the cross-sectional view 800 of the first IC chip 101, the first interconnect structure 506, the first conductor level 110a and the first plurality of bonding contacts 112a are formed in the first dielectric layer 108a. In some embodiments, the first interconnect structure 506, the first conductor level 110a and the first plurality of bonding contacts 112a are formed by first depositing a portion of the first dielectric layer 108a. A mask (not shown) is formed on the uppermost surface of the first dielectric layer 108a, and the pattern of the mask corresponds to the features of the through hole or line to be formed. Then an etching step is performed to remove a portion of the first dielectric layer 108a to form an opening (not shown) corresponding to the pattern of the mask. The mask is then stripped and the resulting opening is filled with a conductive material. In some embodiments, the conductive material is formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, electrochemical plating, electroless plating, some other suitable deposition process or a combination of the foregoing. In a further embodiment, a planarization process is performed to remove excess conductive material from above the uppermost surface of the first dielectric layer 108a. The formation process is then repeated for the remaining layers of the first interconnect structure 506, the first conductive layer 110a, and the first plurality of bonding contacts 112a. Additional portions of the first dielectric layer 108a are formed over the first plurality of bonding contacts 112a to form conductive pads for the first MM to DD bonding layer 106 below.

[0062] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , a second mask 902 is formed on the first dielectric layer 108a. The second mask 902 has a first plurality of conductive pads 102 ( Figure 1A 106) and a first plurality of corrugated shielded wires ( Figure 1B In some embodiments, the second mask 902 is or includes silicon oxynitride and / or other suitable materials. In some embodiments, the second mask 902 is or includes photoresist or other suitable materials, and / or is formed by lithography or some other suitable process.

[0063] like Fig.10As shown in the cross-sectional view 1000 of , etching 1002 is performed to remove the portion of the first dielectric layer 108a corresponding to the opening in the second mask 902. The etching forms an opening 1004 in the first dielectric layer 108a. The opening 1004 exposes the first plurality of bonding contacts 112a (only one of which is shown). In some embodiments, etching 1002 is a dry etching process (e.g., plasma dry etching).

[0064] like Fig.11 As shown in the cross-sectional view 1100, the second mask ( Fig.10 902) is removed to expose the uppermost surface of the first dielectric layer 108a. In some embodiments, the second mask ( Fig.10 902).

[0065] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , a conformal conductive layer 1202 is deposited on the uppermost surface of the first dielectric layer 108 a. The conformal conductive layer 1202 fills the opening 1004 (shown in dashed lines). In some embodiments, the conformal conductive layer 1202 is deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other process, or a combination of the foregoing.

[0066] like Fig.13A and Fig. 13B As shown in the cross-sectional view 1300a and the top layout view 1300b, in the conformal conductive layer ( Fig.12 A planarization process (e.g., a chemical mechanical planarization (CMP) process) is performed on the first dielectric layer 108a to remove the portion of the conformal conductive layer 1202 that extends above the first dielectric layer 108a, so that the first plurality of conductive pads 102 and the first plurality of corrugated shield lines 104 remain on the first dielectric layer 108a. The first plurality of conductive pads 102 are electrically coupled to the first conductor level 110a through the first plurality of bonding contacts 112a and are electrically isolated from the first plurality of corrugated shield lines 104. In some embodiments, the recess causes the upper surfaces of the first plurality of conductive pads 102 and the corrugated shield lines 104 to bend and extend below the uppermost surface of the first dielectric layer 108a. The planarization process separates the first plurality of corrugated shield lines 104 from the first plurality of conductive pads 102, wherein the shielding nodes 104a are directly between individual conductive pads of the first plurality of conductive pads 102 in the first direction 122 and the second direction 124. Fig.13A The cross-sectional view 1300a may be, for example, along Fig. 13B The line B-B' in Fig. 13B The top layout diagram 1300b may be, for example, along the Fig.13A The line BB' in is intercepted.

[0067] like Fig.14 As shown in the cross-sectional view 1400 of , the first IC chip 101 is bonded to the second IC chip 103 and the third IC chip 418. The bonding process includes turning the first IC chip 101 over, aligning the first IC chip 101 with the second IC chip 103, and then applying pressure to the center of the first IC chip 101 or the third IC chip 418, so that the first dielectric layer 108a is bonded to the second dielectric layer 108b through van der Waals force.

[0068] like Fig.15 As shown in the cross-sectional view 1500 of , annealing is performed to expand the first plurality of conductive pads 102 and the first plurality of corrugated shield lines 104 and contact the second IC chip 103. The expansion and higher temperature of the first plurality of conductive pads 102 cause the first plurality of conductive pads 102 to bond with the second plurality of conductive pads 114 of the second IC chip 103. The first plurality of corrugated shield lines 104 also bond with the second corrugated shield lines 116 to strengthen the bond between the first IC chip 101 and the second IC chip 103.

[0069] like Fig.16 As shown in cross-sectional view 1600 of FIG. 1 , BDTI structure 520 is formed on a side of substrate 503 opposite transfer transistor 404. BDTI structure 520 extends to substrate 503 and separates photodetectors 402 from each other. BDTI structure 520 is formed by etching one or more openings (not shown) into the substrate and then performing one or more deposition processes to fill the openings. BDTI structure 520 is or includes a high dielectric constant (high-k) dielectric and / or some other suitable dielectric.

[0070] like Fig.17 As shown in the cross-sectional view 1700 of BSMG 522, a grid of dielectric material 524 is formed on the exposed surface of BDTI structure 520. In some embodiments, a barrier layer 523 is formed between BSMG 522 and BDTI structure 520. BSMG 522 and barrier layer 523 are formed by depositing barrier layer 523 and a metal layer (not shown) on substrate 503, and then patterning barrier layer 523 and metal layer to form a grid shape. The grid of dielectric material 524 is then formed by depositing a conformal layer of dielectric material (not shown), and then patterning the conformal layer into a grid around BSMG 522.

[0071] like Fig.18 As shown in cross-sectional view 1800 of FIG. 1 , a plurality of color filters 526 are formed in a grid of dielectric material 524 and cover light detectors 402 . In some embodiments, a plurality of microlenses 528 are formed on color filters 526 .

[0072] Fig.19Flowchart 1900 illustrates some embodiments of a method for forming an IC device including MM and DD bonding layers with corrugated shield lines.

[0073] Although the method icons and descriptions are hereinafter described as a series of actions or events, it should be understood that the icon order of such actions or events should not be interpreted as a limiting meaning. For example, except those shown and / or described herein, some actions may occur in different orders and / or occur simultaneously with other behaviors or events. In addition, all illustrated actions may not be required to realize one or more aspects or embodiments described herein. In addition, one or more actions described herein can be performed in one or more separated actions and / or stages.

[0074] At block 1902, dopants are implanted into a first substrate in a first IC chip to form a photodetector array having a plurality of pixel blocks arranged in columns and rows. Figure 6 .

[0075] At block 1904, a first interconnect structure is formed over a first substrate, the first interconnect structure comprising a first plurality of conductive pads surrounded by a first dielectric layer. Figures 8 to 13B .

[0076] At block 1906, a first plurality of corrugated shield lines are formed directly between the conductive pads and within the individual rows of the plurality of pixel blocks. Fig. 13B .

[0077] At block 1908, a second interconnect structure is formed on the second IC chip, the second interconnect structure comprising a second plurality of conductive pads and a second plurality of corrugated shield lines surrounded by a second dielectric layer. Fig.14 .

[0078] At block 1910, the first IC chip is flipped over and placed on the second chip such that the first plurality of conductive pads face the second plurality of conductive pads. Fig.14 .

[0079] At a block 1912, the first IC chip is bonded to the second IC chip at a bonding interface, wherein the second plurality of conductive pads are bonded to the first plurality of conductive pads at the bonding interface, and wherein the first plurality of corrugated shielding wires and the second plurality of corrugated shielding wires isolate portions of the first plurality of conductive pads and the second plurality of conductive pads from each other. For example, see Figure 14 to Figure 15 .

[0080] Thus, the present disclosure is directed to a method of forming an IC device including MM and DD bonding layers with corrugated shield lines.

[0081] Some embodiments relate to an IC device, which includes a first IC chip, a second IC chip, and a first corrugated shield line. The first IC chip includes a plurality of pixel blocks, each of which includes one of a first plurality of conductive pads recessed into a first dielectric layer. The plurality of pixel blocks are arranged in rows extending in a first direction and in columns extending in a second direction perpendicular to the first direction. The second IC chip is bonded to the first IC chip at a bonding interface, wherein the second IC chip includes a second plurality of conductive pads recessed into a second dielectric layer and the second plurality of conductive pads contact the first plurality of conductive pads along the bonding interface. The first corrugated shield line has an outermost edge retracted along the second direction from an outermost edge of a first row of the plurality of pixel blocks, and the first corrugated shield line is arranged in the first dielectric layer and laterally separates adjacent first plurality of conductive pads in the first row of the plurality of pixel blocks.

[0082] In some embodiments, the first plurality of conductive pads includes a first conductive pad and a second conductive pad, and wherein the first shielding line segment of the first corrugated shielding line is substantially perpendicular to a line extending from the first conductive pad to the second conductive pad, and the second shielding line segment of the first corrugated shielding line is substantially parallel to a line extending from the first conductive pad to the second conductive pad. In some embodiments, the first shielding line segment and the second shielding line segment are coupled to a shielding node equidistant from the first conductive pad and the second conductive pad, and wherein the shielding node is offset from the first conductive pad in a first direction and offset from the second conductive pad in a second direction. In some embodiments, the IC device also includes a third conductive pad separated from the first conductive pad and the second conductive pad, wherein the line between the third conductive pad and the second conductive pad is at a 45 degree angle to the line between the third conductive pad and the first conductive pad, and wherein the line between the third conductive pad and the first conductive pad extends through the shielding node. In some embodiments, the second IC chip also includes a second corrugated shielding line recessed in the second dielectric layer and the second corrugated shielding line has a surface flush with the surface of the second dielectric layer at the bonding interface, and wherein the second corrugated shielding line directly contacts the first corrugated shielding line. In some embodiments, the first corrugated shield line has a surface facing the bonding interface and spaced apart from the bonding interface, wherein the first IC chip further includes a third conductive pad and a fourth conductive pad respectively covering and directly contacting the first conductive pad and the second conductive pad of the first plurality of conductive pads, and the third conductive pad and the fourth conductive pad are further flush with the first corrugated shield line. In some embodiments, the IC device further includes a first plurality of light detectors of the light detector array directly located above and electrically coupled to the first conductive pad of the first plurality of conductive pads; and a second plurality of light detectors of the light detector array directly located above and electrically coupled to the second conductive pad of the first plurality of conductive pads, wherein the first plurality of light detectors and the second plurality of light detectors are adjacent to each other. In some embodiments, the plurality of pixel blocks respectively include a plurality of light detectors, and the plurality of light detectors continuously extend from directly below the first corrugated shield line to laterally pass the outermost wall of the first corrugated shield line.

[0083] In other embodiments, the disclosure is directed to an IC device including a first IC chip; a second IC chip bonded to the first IC chip at a bonding interface; and a first pixel arranged across the first IC chip and the second IC chip, the first pixel including a first photodetector subarray and a second photodetector subarray, wherein the first IC chip and the second IC chip respectively include a first dielectric layer and a second dielectric layer that are in direct contact at the bonding interface. The first IC chip also includes a first conductive pad and a first shielding node recessed into the first dielectric layer and at the bonding interface, the first conductive pad being located below the first photodetector subarray, the first shielding node being located below the second photodetector subarray, and a first segment and a second segment of a first corrugated shield line protruding outwardly from opposite sidewalls of the first shielding node to partially surround the first conductive pad.

[0084] In some embodiments, the IC device further comprises a second pixel arranged across the first IC chip and the second IC chip, the second pixel comprising a third photodetector subarray and a fourth photodetector subarray; wherein the first IC chip further comprises a second shielding node and a second conductive pad recessed in the first dielectric layer and at the bonding interface, the second shielding node and the second conductive pad being respectively located below the third photodetector subarray and the fourth photodetector subarray, and wherein the first photodetector subarray and the third photodetector subarray are in a first row and the second photodetector subarray and the fourth photodetector subarray are in a second row. In some embodiments, the first pixel and the second pixel repeat periodically and alternately along an axis extending parallel to the first row and the second row, and wherein the shielding nodes of the repeated first pixel and the second pixel are electrically coupled by repeated first and second segments of the first corrugated shielding line. In some embodiments, the first row and the second row repeat periodically and alternately along a second axis extending perpendicular to the first row and the second row, and the first corrugated shielding line repeats periodically in the repeated first row and the second row. In some embodiments, the IC device further comprises a second corrugated shield line partially surrounding the first conductive pad, wherein the first corrugated shield line and the second corrugated shield line are separated from each other by a first dielectric layer. In some embodiments, the first shield node has a top geometry that is the same as a top geometry of the first conductive pad. In some embodiments, the second photodetector subarray is electrically coupled to the first conductive pad. In some embodiments, the first shield node is metal.

[0085] In yet another embodiment, the present disclosure is directed to a method of forming an integrated circuit (IC) device, comprising implanting dopants into a first substrate in a first IC chip to form a photodetector array; forming a first interconnect structure over the first substrate, the first interconnect structure comprising a first plurality of conductive pads surrounded by a first dielectric layer; forming a first plurality of corrugated shield lines directly between the conductive pads; forming a second interconnect structure over a second IC chip, the second interconnect structure comprising a second plurality of conductive pads surrounded by a second dielectric layer and a second plurality of corrugated shield lines; flipping the first IC chip and placing the first IC chip on the second IC chip with the first plurality of conductive pads facing the second plurality of conductive pads; bonding the first IC chip to the second IC chip at a bonding interface, wherein the second plurality of conductive pads are bonded to the first plurality of conductive pads at the bonding interface, and wherein the first plurality of corrugated shield lines and the second plurality of corrugated shield lines isolate portions of the first plurality of conductive pads and the second plurality of conductive pads from each other.

[0086] In some embodiments, the first dielectric layer is bonded to the second dielectric layer using van der Waals forces, and wherein bonding the first IC chip to the second IC chip further comprises performing an anneal to bond the second plurality of conductive pads to the first plurality of conductive pads. In some embodiments, eight photodetectors of the photodetector array are electrically coupled to one conductive pad, wherein the eight photodetectors are within two 2×2 photodetector subarrays, the two 2×2 photodetector subarrays are respectively coupled to a first floating diffusion node and a second floating diffusion node, and wherein the first floating diffusion node and the second floating diffusion node are respectively directly over one conductive pad and directly over a corrugated shield line of the first plurality of corrugated shield lines. In some embodiments, the first plurality of corrugated shield lines are formed adjacent to the first plurality of conductive pads.

[0087] It should be understood that in this written description and the appended claims, the terms "first", "second", "second", "third", etc. are merely general identifiers used to facilitate the description to distinguish components of different figures or series of figures. By themselves, these terms do not imply any temporal order or structural proximity of these components, and are not intended to describe corresponding components in different illustrated embodiments and / or non-illustrated embodiments. For example, the "first dielectric layer" described in conjunction with the first figure does not necessarily correspond to the "first dielectric layer" described in conjunction with another figure, and does not necessarily correspond to the "first dielectric layer" in non-illustrated embodiments.

[0088] The above summarizes the features in several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications to it without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, characterized in that: include: A first integrated circuit chip, comprising a plurality of pixel blocks, each of the plurality of pixel blocks comprising one of a first plurality of conductive pads recessed in a first dielectric layer, the plurality of pixel blocks being arranged in rows extending in a first direction and in columns extending in a second direction perpendicular to the first direction; a second integrated circuit chip bonded to the first integrated circuit chip at a bonding interface, wherein the second integrated circuit chip includes a second plurality of conductive pads recessed in the second dielectric layer and the second plurality of conductive pads contact the first plurality of conductive pads along the bonding interface; as well as A first corrugated shielding line having an outermost edge retracted along the second direction from an outermost edge of a first row of the plurality of pixel blocks, the first corrugated shielding line being arranged in the first dielectric layer and laterally separating adjacent first plurality of conductive pads in the first row of the plurality of pixel blocks.

2. The integrated circuit device according to claim 1, characterized in that The first plurality of conductive pads includes a first conductive pad and a second conductive pad; and The first shielding line segment of the first corrugated shielding line is substantially perpendicular to the line extending from the first conductive pad to the second conductive pad, and the second shielding line segment of the first corrugated shielding line is substantially parallel to the line extending from the first conductive pad to the second conductive pad.

3. The integrated circuit device according to claim 2, characterized in that The first and second shielding line segments are coupled to a shielding node equidistant from the first and second conductive pads, and wherein the shielding node is offset from the first conductive pad in the first direction and offset from the second conductive pad in the second direction.

4. The integrated circuit device according to claim 3, characterized in that Also included is a third conductive pad separated from the first conductive pad and the second conductive pad, wherein a line between the third conductive pad and the second conductive pad is at a 45 degree angle to a line between the third conductive pad and the first conductive pad, and wherein the line between the third conductive pad and the first conductive pad extends through the shielding node.

5. The integrated circuit device according to claim 1, wherein: The first corrugated shielding line has a surface facing the bonding interface and spaced apart from the bonding interface, wherein the first integrated circuit chip further includes a third conductive pad and a fourth conductive pad respectively covering and directly contacting the first conductive pad and the second conductive pad of the first plurality of conductive pads, and the third conductive pad and the fourth conductive pad are further flush with the first corrugated shielding line.

6. An integrated circuit device, characterized in that: include: a first integrated circuit chip; a second integrated circuit chip bonded to the first integrated circuit chip at a bonding interface; as well as a first pixel arranged across the first integrated circuit chip and the second integrated circuit chip, the first pixel comprising a first light detector sub-array and a second light detector sub-array, wherein the first integrated circuit chip and the second integrated circuit chip respectively include a first dielectric layer and a second dielectric layer directly contacting at the bonding interface, The first integrated circuit chip further includes a first conductive pad and a first shielding node recessed in the first dielectric layer and at the bonding interface, The first conductive pad is below the first light detector sub-array, The first shielding node is below the second photodetector subarray, and A first section and a second section of the first corrugated shield line protrude outward from opposite side walls of the first shield node to partially surround the first conductive pad.

7. The integrated circuit device according to claim 6, characterized in that Also includes: a second pixel arranged across the first integrated circuit chip and the second integrated circuit chip, the second pixel comprising a third photodetector subarray and a fourth photodetector subarray; The first integrated circuit chip further includes a second shielding node and a second conductive pad recessed in the first dielectric layer at the bonding interface, the second shielding node and the second conductive pad being respectively located below the third photodetector subarray and the fourth photodetector subarray, and wherein the first photodetector subarray and the third photodetector subarray are in a first row, and the second photodetector subarray and the fourth photodetector subarray are in a second row.

8. The integrated circuit device according to claim 6, characterized in that Also included is a second corrugated shield wire partially surrounding the first conductive pad, wherein the first corrugated shield wire and the second corrugated shield wire are spaced apart from each other by the first dielectric layer.

9. The integrated circuit device according to claim 6, characterized in that The first shielding node has a top geometry that is the same as a top geometry of the first conductive pad.

10. The integrated circuit device according to claim 6, characterized in that The second photodetector sub-array is electrically coupled to the first conductive pad.

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