Image sensor device

Abstract

An image sensor device includes a pixel sensor array and a black level correction (BLC) region. The black level correction region includes a sensing region in the substrate and a light blocking layer on the sensing region. The anti-reflective array is formed in the light blocking layer. The anti-reflective array includes holes, trenches, and / or other structural features such that the light blocking layer includes two or more regions, where the top surfaces of the light blocking layer are different heights in the image sensor device. Different heights of the top surface of the light blocking layer reduce the likelihood that light is reflected from the light blocking layer to the pixel sensor array. The anti-reflection array can reduce the possibility that flare or hot spots occur in an image generated by the image sensor device, and the image quality of the image generated by the image sensor device can be improved.

Description

Technical Field

[0001] The present disclosure relates to an image sensor device, and more particularly to an image sensor device including a black level correction area. Background Art

[0002] Complementary metal oxide semiconductor (CMOS) image sensor (CIS) devices utilize light-sensitive CMOS circuits to convert light energy into electrical energy. The light-sensitive CMOS circuits may include photodiodes formed in a silicon substrate. When the photodiode is exposed to light, an electric charge is induced in the photodiode (called photocurrent). The photodiode may be coupled to a switching transistor, which is used to sample the charge of the photodiode. Color can be determined by placing a filter on the light-sensitive CMOS circuit.

[0003] The light received by the pixel sensors of a CIS device is generally based on the three primary colors: red, green, and blue (R, G, B). The pixel sensors that sense each color of light can be defined by the use of color filters, which allow wavelengths of light of a specific color to pass through to the photodiode. Some pixel sensors may include near infrared (NIR) filters, which block visible light and allow near infrared light to pass through to the photodiode. Utility Model Content

[0004] One aspect of the present disclosure is to provide an image sensor device. The image sensor device includes a pixel sensor array. The image sensor device includes a black level correction region adjacent to the pixel sensor array. The black level correction region includes a sensing region, a light blocking layer on the sensing region, and an anti-reflection array in the light blocking layer. The anti-reflection array includes a plurality of recessed portions in the light blocking layer.

[0005] Another aspect of the present disclosure is to provide an image sensor device. The image sensor device includes a pixel sensor array. The image sensor device includes a black level correction region adjacent to the pixel sensor array. The black level correction region includes a sensing region, a light blocking layer on the sensing region, an anti-reflection film on the light blocking layer, and an anti-reflection array in the anti-reflection film and the light blocking layer. The anti-reflection array includes a plurality of recessed portions extending through the anti-reflection film and into the light blocking layer.

[0006] Another aspect of the present disclosure is to provide an image sensor device. The image sensor device includes a pixel sensor array, a metal layer, and a black level correction region. The metal layer includes a metal grid on the pixel sensor array. The black level correction region is adjacent to the pixel sensor array. The black level correction region includes a sensing region, wherein at least a portion of the metal layer is in the black level correction region, and at least a portion of the metal layer in the black level correction region is on the sensing region and has a plurality of recessed portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is better understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[0008] Figure 1 is a schematic diagram illustrating an exemplary environment in which the system and / or method described in the present disclosure may be implemented;

[0009] Figure 2 is a top view illustrating an exemplary image sensor device described in the present disclosure;

[0010] Figure 3 is a cross-sectional view illustrating an exemplary embodiment of an image sensor device described in the present disclosure;

[0011] Figure 4 is a schematic diagram illustrating an exemplary embodiment of an anti-reflection array described in the present disclosure;

[0012] FIG. 5A to FIG. 5O is a schematic diagram illustrating an exemplary embodiment of the present disclosure;

[0013] Figure 6 is a cross-sectional view illustrating an exemplary embodiment of an image sensor device described in the present disclosure;

[0014] Fig. 7A and Figure 7B is a schematic diagram illustrating an exemplary embodiment of the anti-reflection film disclosed herein;

[0015] FIG. 8A to FIG. 8D is a schematic diagram illustrating an exemplary embodiment of the present disclosure;

[0016] Fig. 9 is a schematic diagram illustrating an exemplary embodiment of the gas ratio for forming an anti-reflection film according to the present disclosure;

[0017] Fig. 10A and Fig. 10B is a schematic diagram illustrating an exemplary embodiment of an anti-reflection array described in the present disclosure;

[0018] Fig.11is a schematic diagram illustrating exemplary components of an apparatus described in the present disclosure;

[0019] Fig.12 is a flow chart illustrating an exemplary process associated with forming an image sensor device.

[0020]

Explanation of symbols

[0021] 100: Environment

[0022] 102:Semiconductor process tools / deposition tools

[0023] 104:Semiconductor process tools / exposure tools

[0024] 106:Semiconductor process tools / development tools

[0025] 108:Semiconductor process tools / etching tools

[0026] 110:Semiconductor process tools / planarization tools

[0027] 112:Semiconductor process tools / electroplating tools

[0028] 114:Semiconductor process tools / ion implantation tools

[0029] 116: Wafer / die transfer tool

[0030] 200: Image sensor device

[0031] 202: Pixel sensor array

[0032] 204: Pixel sensor

[0033] 206: Black level correction area

[0034] 208: Bonding pad area

[0035] 300: Example

[0036] 302: Intermetallic dielectric layer

[0037] 304: Interlayer dielectric layer

[0038] 306: Base material

[0039] 308: Photodiode

[0040] 310: Deep Trench Isolation Structure

[0041] 312: Anti-reflective coating

[0042] 314: Oxide layer

[0043] 316: Adhesive layer

[0044] 318:Metal layer

[0045] 320:Metal Grid

[0046] 322: Color filter area

[0047] 324: Oxide layer

[0048] 326: Microlens layer

[0049] 328: Metallization layer

[0050] 330: Shallow trench isolation area

[0051] 332: Groove

[0052] 334: Buffer oxide layer

[0053] 336: Bonding pad

[0054] 338: Sensing area

[0055] 340: Anti-reflection array

[0056] 342: Non-depressed part

[0057] 344: Depression

[0058] 400: Example

[0059] 402: bottom surface

[0060] 404: Side wall

[0061] 406: Top surface

[0062] 500: Example

[0063] 502: Groove

[0064] 506: Opening

[0065] 508: Opening

[0066] 600: Example

[0067] 602: Anti-reflective film

[0068] 700: Example embodiment

[0069] 702: Environment

[0070] 704: Incident light

[0071] 706: Reflected Light

[0072] 708: Refracted Light

[0073] 710: Reflectance ratio

[0074] 712: Refractive index

[0075] 714: Example Embodiment

[0076] 716: First floor

[0077] 718: Second floor

[0078] 720: Reflected light

[0079] 722: Refracted Light

[0080] 724: Reflected Light

[0081] 726: Refracted Light

[0082] 728: Reflected Light

[0083] 730: Refracted Light

[0084] 732: Reflected Light

[0085] 734: Proportion

[0086] 800: Example 900: Example

[0087] 902: Refractive index

[0088] 904: Gas ratio

[0089] 1000, 1010, 1020, 1030, 1040, 1050: Example embodiments

[0090] 1100: Device

[0091] 1110: Bus

[0092] 1120: Processor

[0093] 1130:Memory

[0094] 1140: Input component

[0095] 1150: Output component

[0096] 1160: Communication components

[0097] 1200: Craftsmanship

[0098] 1210,1220,1230,1240: Blocks

[0099] AA:Line

[0100] A1, A2, A3, A4: Angle

[0101] D1: Depth

[0102] H1,H2: Height

[0103] n1,n2,n3,n4: refractive index

[0104] S: Spacing

[0105] W1,W2: Width DETAILED DESCRIPTION

[0106] The following disclosure provides many different embodiments or illustrations to implement different features of the utility model. The specific examples of components and configurations described below are intended to simplify the disclosure. These are of course only for illustration and are not intended to be limiting. For example, the description of a first feature formed on or above a second feature includes an embodiment in which the first feature and the second feature are in direct contact, and also includes an embodiment in which other features are formed between the first feature and the second feature, so that the first feature and the second feature are not in direct contact. In addition, the disclosure repeats component symbols and / or letters in various specific examples. The purpose of this repetition is to simplify and clarify the description, and does not indicate a relationship between the various discussed embodiments and / or configurations.

[0107] Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., are used to facilitate description of the relationship of parts or features illustrated in the drawings to other parts or features. Spatially relative terms encompass different orientations of the elements in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in the present disclosure may be interpreted so.

[0108] In some examples, an image sensor device (e.g., a complementary metal oxide semiconductor (CMOS) image sensor (CIS) device) may include a black level correction (BLC) region adjacent to and / or surrounding a pixel sensor array of the image sensor device. The black level correction region includes one or more layers of light blocking material that prevent light from entering a sensing region beneath the one or more layers. Because the one or more layers prevent incident light from entering the sensing region, the sensing region is "dark." This causes the sensing region to produce a dark current measurement of the black level correction (or black level standard) of the pixel sensor array. Dark current is a current that occurs in the image sensor device due to an energy source other than incident light. For example, dark current may be caused by heat generated by the image sensor device and / or one or more other devices in proximity to the image sensor device. Dark current may cause noise and other defects in images and / or videos captured by the image sensor device. For example, dark current may artificially increase the photocurrent generated by pixel sensors in a pixel sensor array, which may result in an elevated level and / or may cause some pixels in an image or video to appear as white pixels or hot pixels.

[0109] Light blocking materials commonly used in black level correction areas may be metallic and reflective. While high reflectivity may result in increased light blocking effects, the reflectivity of the light blocking material may cause light to be reflected to pixel sensors in the pixel sensor array. Light reflected to pixel sensors in the pixel sensor array may cause flares or hot spots (e.g., areas of elevated height) in images and / or movies generated by the image sensor device and / or may otherwise degrade the image quality of the images and / or movies generated by the image sensor device.

[0110] In some embodiments described in the present disclosure, an image sensor device includes a pixel sensor array and a black level correction region adjacent to the pixel sensor array. The black level correction region may include a sensing region in a substrate and a light blocking layer on the sensing region. An anti-reflection array may be formed in the light blocking layer. The anti-reflection array may include holes, trenches and / or other structural features so that the light blocking layer includes two or more regions, wherein the top surface of the light blocking layer is at different heights in the image sensor device. The different heights of the top surface of the light blocking layer reduce the possibility of light being reflected from the light blocking layer to the pixel sensor array. In this way, the anti-reflection array can reduce the possibility of glare or hot spots occurring in images and / or videos generated by the image sensor device, which can increase the image quality of the images and / or videos generated by the image sensor device.

[0111] Figure 1 1 is a schematic diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, the environment 100 may include a plurality of semiconductor process tools 102 to 114 and a wafer / die transfer tool 116. The plurality of semiconductor process tools 102 to 114 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, an ion implantation tool 114 and / or other types of semiconductor process tools. The tools included in the exemplary environment 100 may be included in a semiconductor cleaning chamber, a semiconductor wafer foundry, a semiconductor process facility and / or a manufacturing facility, among other examples.

[0112] Deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices that can be used to deposit various materials on a substrate. In some embodiments, deposition tool 102 includes a spin coating tool that can be used to deposit a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma enhanced atomic layer deposition (PEALD) tool, or other types of chemical vapor deposition tools. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other types of PVD tools. In some embodiments, the exemplary environment 100 includes a plurality of deposition tools 102 .

[0113] The exposure tool 104 is a semiconductor processing tool that can expose the photoresist layer to a radiation source, such as an ultraviolet (UV) light source [e.g., a deep UV light source, an extreme UV (EUV) light source, and / or the like], an X-ray light source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns used to form one or more semiconductor devices, can include patterns used to form one or more structures of a semiconductor device, can include patterns used to etch various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, an exposure machine, or a similar type of exposure tool.

[0114] The developing tool 106 is a semiconductor process tool that can develop the photoresist layer that has been exposed to the radiation source to develop the pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portion of the photoresist layer. In some embodiments, the developing tool 106 dissolves the exposed portion or the unexposed portion of the photoresist layer through the use of a chemical developer to develop the pattern.

[0115] The etching tool 108 is a semiconductor processing tool that can etch various types of substrates, wafers, or materials of semiconductor devices. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 can utilize plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which includes utilizing an ionized gas to etch the one or more portions isotropically or directionally.

[0116] The planarization tool 110 is a semiconductor process tool that can grind or planarize the layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or other types of planarization tools that can grind or planarize layers or surfaces of deposited or plated materials. The planarization tool 110 can combine chemical and mechanical forces (such as chemical etching and abrasive-free grinding) to grind or planarize the surface of the semiconductor device. The planarization tool 110 can use abrasives and corrosive chemical polishing liquids in combination with a polishing pad and a retaining ring (e.g., typically having a diameter larger than the semiconductor device). The polishing pad and the semiconductor device can be pressed together by a powered polishing head and held in place by a retaining ring. The powered polishing head can rotate on different rotation axes to remove material and equalize the irregular surface morphology of the semiconductor device to flatten or planarize the semiconductor device.

[0117] The electroplating tool 112 is a semiconductor processing tool that can electroplate a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the electroplating tool 112 can include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0118] The ion implantation tool 114 is a semiconductor processing tool that can implant ions into a substrate. The ion implantation tool 114 can generate ions from a source material (e.g., a gas or solid) in an arc chamber. The source material can be provided to the arc chamber, and an arc voltage is released between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward the substrate to implant the ions below the surface of the substrate.

[0119] The wafer / die transfer tool 116 may be included in a cluster tool or other type of tool including multiple process chambers, and is configured to transfer substrates and / or semiconductor devices between multiple process chambers, between a process chamber and a buffer area, between a process chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or between a process chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some embodiments, the wafer / die transfer tool 116 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-clean process tool (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations).

[0120] In some embodiments, one or more of the semiconductor process tools 102 to the semiconductor process tools 114 and / or the wafer / die transfer tool 116 may perform one or more semiconductor process operations described herein. For example, the semiconductor process tools 102 to the semiconductor process tools 114 and / or the wafer / die transfer tool 116 may form one or more photodiodes in a pixel sensor array of the image sensor device in a substrate of the image sensor device; may form a metal layer on the one or more photodiodes of the image sensor device and on a sensing region in a black level correction region; may remove a first portion of the metal layer in the pixel sensor array to form a metal grid over the one or more photodiodes; and / or remove a second portion of the metal layer in the black level correction region to form an anti-reflection array in the metal layer in the black level correction region, wherein the metal layer in the black level correction region corresponds to a light blocking layer and the light blocking layer is on the sensing region in the black level correction region, and other examples in addition thereto. One or more of the semiconductor process tools 102 to 114 and / or the wafer / die transfer tool 116 may perform semiconductor process operations described herein, such as those related to FIG. 5A to FIG. 5O , FIG. 8A to FIG. 8D and / or Fig.12 , and other examples besides these.

[0121] Figure 1 The number and arrangement of devices shown are provided as one or more specific examples. In practice, there may be additional devices, fewer devices, different devices, or different Figure 1 The device configuration shown. Furthermore, Figure 1Two or more of the devices shown may be used in a single device, or Figure 1 The single device shown may be used in a variety of distributed devices. In addition or alternatively, one or more devices of the exemplary environment 100 may perform one or more functions performed by another set of devices of the exemplary environment 100.

[0122] Figure 2 2 is a top view of an exemplary image sensor device 200 described in the present disclosure. The image sensor device 200 may include a CMOS image sensor, a backside illuminated (BSI) CMOS image sensor, and / or other types of image sensors. The image sensor device 200 is configured to be deployed in various embodiments, such as digital cameras, video recorders, night-vision cameras, automotive sensors and cameras, and / or other types of light-sensitive embodiments.

[0123] Image sensor device 200 may include pixel sensor array 202. Figure 2 As shown, the pixel sensor array 202 may include a plurality of pixel sensors 204. Figure 2 As shown, the pixel sensors 204 may be arranged in a grid. In some embodiments, the pixel sensors 204 are square (e.g., Figure 2 In some embodiments, the pixel sensor 204 includes other shapes, such as a circle, an octagon, a diamond, and / or other shapes.

[0124] The pixel sensor 204 may be configured to sense and / or accumulate incident light (e.g., light directed toward the pixel sensor array 202). For example, the pixel sensor 204 may absorb and accumulate incident light photons in a photodiode. The photons accumulated in the photodiode may generate a charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a greater intensity or brightness, while a smaller amount of charge may correspond to a lower intensity or brightness).

[0125] The pixel sensor array 202 may be electrically connected to a back-end-of-line (BEOL) metal stack (not shown) of the image sensor. The BEOL metal stack may electrically connect the pixel sensor array 202 to a control circuit that may be used to measure the amount of incident light accumulated in the pixel sensor 204 and convert the measured value into an electrical signal.

[0126] Further Figure 2As shown, the image sensor device 200 may include a black level correction region 206 adjacent to and / or surrounding the pixel sensor array 202. The black level correction region 206 includes one or more layers of light blocking material that prevent light from entering the sensing region below the one or more layers. Because the one or more layers prevent incident light from entering the sensing region, the sensing region is "dark." This causes the sensing region to produce a dark current measurement of the black level correction (or black level standard) of the pixel sensor array 202. The black level correction region 206 is about 25 microns to about 200 microns from the edge of the image sensor device 200. However, other ranges of values ​​are still within the scope of the present disclosure.

[0127] Further Figure 2 As shown, image sensor device 200 may include a bonding pad region 208 (which may also be referred to as an E-pad region) adjacent to black level correction region 206. Bonding pad region 208 may include one or more metallization layers (e.g., conductive bonding pads, e-pads, metallization layers, vias) that establish electrical connections through image sensor device 200 and external devices and / or external packages.

[0128] In some embodiments, image sensor device 200 includes one or more other regions, such as scribeline regions that separate a semiconductor die or portion of a semiconductor die including image sensor device 200 from adjacent semiconductor dies or portions of semiconductor dies including other image sensor devices and / or other integrated circuits.

[0129] As mentioned above, Figure 2 is provided as a specific example. Figure 2 Other specific examples may be different from those described.

[0130] Figure 3 The image sensor device 200 described in the present disclosure is shown along Figure 2 2 is a cross-sectional view of the exemplary embodiment 300 taken along line AA in FIG. Figure 3 The cross-sectional structure and / or layer arrangement of the image sensor device 200 is shown, which includes the pixel sensor array 202 , the black level correction region 206 , and the bonding pad region 208 .

[0131] like Figure 3As shown, image sensor device 200 may include various layers and / or various structures. In some embodiments, during one or more process operations to form image sensor device 200, image sensor device 200 may be disposed and / or fabricated on a carrier substrate (not shown). Image sensor device 200 may include an inter-metal dielectric (IMD) layer 302, an interlayer dielectric (ILD) layer 304 on and / or over IMD layer 302, and a substrate 306 on and / or over ILD layer 304. Each of IMD layer 302 and ILD layer 304 may include one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide and / or other dielectric materials. The substrate 306 may be composed of silicon (Si), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon on insulator (SOI), or other types of semiconductor materials that can generate charges from incident light photons.

[0132] Various metallization layers may be formed in IMD layer 302 and / or between layers of IMD layer 302. Metallization layers may include bonding pads, conductive lines, and / or other types of conductive structures that electrically connect various regions of image sensor device 200 and / or electrically connect various regions of image sensor device 200 to one or more external devices and / or external packages. Metallization layers may be referred to as BEOL metallization stacks and may include conductive materials such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys, and / or combinations thereof, among other examples. The BEOL metallization stack may electrically connect pixel sensor array 202, black level correction region 206, and / or bonding pad region 208 to a device die on an integrated process circuit included in an embodiment of image sensor device 200, wherein the embodiment of image sensor device 200 includes a plurality of stacked and bonded semiconductor dies.

[0133] The photodiode 308 of the pixel sensor 204 in the pixel sensor array 202 may be included in the substrate 306. The photodiode 308 may include a region of the substrate 306 doped with various types of ions to form a pn junction or a PIN junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) portion, and an n-type portion). For example, the substrate 306 is doped with an n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 308, and is doped with a p-type dopant to form a second portion (e.g., a p-type portion) of the photodiode 308. The photodiode 308 is configured to absorb photons of incident light. The absorption of the photons causes the photodiode 308 to accumulate a charge (referred to as a photocurrent) due to the photoelectric effect. Thereby, the photons strike the photodiode 308, which causes the photodiode 308 to emit electrons. The emission of electrons causes the generation of electron-hole pairs, wherein the electrons migrate toward the cathode of the photodiode 308 and the holes migrate toward the anode, thereby generating a photocurrent.

[0134] A deep trench isolation (DTI) structure 310 may be included in substrate 306. Deep trench isolation structure 310 may be included in substrate 306 extending from a top surface of substrate 306 to around photodiode 308 of pixel sensor 204. Thus, photodiode 308 is surrounded by a trench of deep trench isolation structure 310. In some embodiments, deep trench isolation structure 310 may be a backside deep trench isolation (BDTI) structure that is formed as part of a backside process of image sensor device 200.

[0135] The trenches of the deep trench isolation structure 310 may provide optical isolation between the pixel sensors 204 of the pixel sensor array 202, which may reduce the amount of optical crosstalk between adjacent pixel sensors 204. In particular, the trenches of the deep trench isolation structure 310 may absorb, refract, and / or reflect incident light, which may reduce the amount of incident light that penetrates a pixel sensor 204 into an adjacent pixel sensor 204 and is absorbed by the adjacent pixel sensor 204.

[0136] The top surface of the substrate 306 and the surface of the deep trench isolation structure 310 may be coated with an antireflective coating (ARC) 312 to reduce reflection of incident light from the photodiode 308 and increase transmission of incident light into the substrate 306. The antireflective coating 312 may include a suitable material for reducing reflection of incident light projected toward the photodiode 308, such as a nitrogen-containing material or other examples.

[0137] The deep trench isolation structure 310 may include an oxide layer 314 on the substrate 306 and on and / or over the anti-reflective coating 312. Furthermore, the material of the oxide layer 314 may fill the trenches of the deep trench isolation structure 310. The oxide layer 314 may be combined with an adhesion layer 316 between the substrate 306 and the upper layers of the pixel sensor array 202. The adhesion layer 316 may extend through the black level correction region 206 to improve the adhesion between the silicon of the substrate 306 and the metal material of the metal layer 318 on the substrate 306. In some embodiments, the oxide layer 314 and the adhesion layer 316 may be a single structure including an oxide material, such as silicon oxide (SiO x In some embodiments, silicon nitride (SiN x ), Silicon Carbide (SiC x ) or a mixture thereof, such as silicon carbonitride (SiCN), silicon oxynitride (SiON) or other dielectric materials are used to replace the oxide layer 314 and serve as the adhesion layer 316.

[0138] Metal layer 318 may be located on and / or over adhesion layer 316. Metal layer 318 may extend laterally across other areas of pixel sensor array 202, black level correction region 206, and / or bonding pad region 208. Metal grid 320 may be formed within metal layer 318 in pixel sensor array 202 to provide optical isolation between pixel sensors 204 in pixel sensor array 202. Metal grid 320 may include columns or pillars surrounding pixel sensors 204. The columns or pillars of metal grid 320 may be located over trenches of deep trench isolation structure 310. Metal layer 318 may be formed of a metal material, such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys (such as aluminum copper (AlCu)), and / or combinations thereof, among other examples.

[0139] The color filter regions 322 of the pixel sensor 204 may be included between the metal grids 320. In other words, the color filter regions 322 may be included to replace the removed portions of the metal layer 318 on the photodiode 308. Each color filter region 322 may be configured to filter incident light so that incident light of a specific wavelength passes through the photodiode 308 of the associated pixel sensor 204. For example, the color filter regions 322 included in the pixel sensor 204 may filter red light (thus, the pixel sensor 204 may be a red pixel sensor). In another specific example, the color filter regions 322 included in the pixel sensor 204 may filter green light (thus, the pixel sensor 204 may be a green pixel sensor). In another specific example, the color filter regions 322 included in the pixel sensor 204 may filter blue light (thus, the pixel sensor 204 may be a blue pixel sensor).

[0140] The blue filter region allows incident light components with a wavelength of about 450 nanometers to pass through the color filter region 322 and blocks other wavelengths from passing through. The green filter region allows incident light components with a wavelength of about 550 nanometers to pass through the color filter region 322 and blocks other wavelengths from passing through. The red filter region allows incident light components with a wavelength of about 650 nanometers to pass through the color filter region 322 and blocks other wavelengths from passing through. The yellow filter region allows incident light components with a wavelength of about 580 nanometers to pass through the color filter region 322 and blocks other wavelengths from passing through.

[0141] In some embodiments, color filter region 322 may be indifferent or non-filtering, which may define a white pixel sensor. Indifferent or non-filtering color filter region 322 may include a material that allows all wavelengths of light to pass into associated photodiode 308 (e.g., to determine overall brightness to increase the light sensitivity of the image sensor). In some embodiments, color filter region 322 may be a near infrared (NIR) bandpass color filter region, which may define an NIR pixel sensor. NIR bandpass color filter region 322 may include a material that allows a portion of incident light in the near infrared wavelength range to pass through associated photodiode 308 while blocking visible light from passing through.

[0142] One or more passivation layers may be formed on and / or over metal layer 318. For example, oxide layer 324 may be located on and / or over a portion of metal layer 318. In some embodiments, oxide layer 324 may also be included on and / or over a portion of adhesion layer 316 exposed through metal layer 318. Thus, oxide layer 324 is included between color filter region 322 and adhesion layer 316, and between color filter region 322 and metal layer 318. Oxide layer 324 may include an oxide material, such as silicon oxide (SiO x In addition and / or in lieu thereof, silicon nitride (SiN x ), Silicon Carbide (SiC x ) or a mixture thereof, such as silicon carbonitride (SiCN), silicon oxynitride (SiON) or other dielectric materials are used to replace the oxide layer 324.

[0143] Microlens layer 326 may be included on color filter region 322 and on and / or over metal grid 320. Microlens layer 326 may include a respective microlens for each pixel sensor 204. Microlenses may be formed to focus incident light toward photodiode 308 of pixel sensor 204.

[0144] As shown in the bonding pad region 208 of the image sensor device 200, a metallization layer 328 may be formed that is electrically connected to the intermetal dielectric layer 302. A shallow trench isolation (STI) region 330 may be located on and / or over the metallization layer 328. The shallow trench isolation region 330 may provide electrical isolation in the bonding pad region 208. The shallow trench isolation region 330 may be located under and / or under a recess 332 in the bonding pad region 208. Above the shallow trench isolation region 330, a buffer oxide layer 334 may be included in the recess 332 and on the sidewalls and bottom surface of the recess 332. A bonding pad 336 may be located on the shallow trench isolation region 330 and / or in the bonding pad region 208 on and / or over the buffer oxide layer 334. The bonding pad 336 may extend through the buffer oxide layer 334, through the shallow trench isolation region 330, and through the interlayer dielectric layer 304 to the intermetallic dielectric layer 302, and may contact the metallization layer 328 in the intermetallic dielectric layer 302. The bonding pad 336 may include a conductive material, such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), a metal alloy (such as aluminum copper (AlCu)) and / or a combination thereof, and other examples in addition to the foregoing.

[0145] As shown in the black level correction region 206, the sensing region 338 can be included in the substrate 306. The sensing region 338 can include the portion of the substrate 306 below the metal layer 318. The metal layer 318 in the black level correction region 206 can act as a light blocking material, which can prevent light from entering the sensing region 338. This can enable the sensing region to produce a dark current measurement for black level correction (or black level standard) of the pixel sensor array 202.

[0146] Further Figure 3 As shown, the anti-reflection array 340 can be included in the metal layer 318 in the black level correction region 206. In particular, the anti-reflection array 340 can be included on the sensing region 338. The anti-reflection array 340 includes holes, trenches and / or other structural features that are configured to reduce the possibility of light being reflected from the metal layer 318 to the pixel sensor array 202. As such, the anti-reflection array 340 is configured to prevent incident light from being reflected from the black level correction region 206 to the pixel sensor array 202, which can reduce the possibility of glare or hot spots occurring in the images and / or videos generated by the image sensor device 200. This can increase the image quality of the images and / or videos generated by the image sensor device 200.

[0147] The anti-reflection array 340 may include a plurality of non-recessed portions 342 that define a plurality of recessed portions 344 in the metal layer 318 (e.g., in the light blocking layer of the black level correction region 206). The top surface of the metal layer 318 (e.g., the light blocking layer) in the non-recessed portions 342 may be at a first height H1 in the image sensor device 200. The top surface of the metal layer 318 in the recessed portions 344 may be at a second height H2 in the image sensor device 200. The different heights of the anti-reflection array 340 in the metal layer 318 (e.g., the first height H1 and the second height H2) cause the incident light to be scattered in an omnidirectional manner relative to being primarily redirected toward the pixel sensor array 202. In a specific example, and as Figure 3 As shown, light may enter and may be reflected by the recessed portion 344 of the anti-reflective array 340. The light may then be reflected by the sidewalls of the non-recessed portion 342, which causes the light to move away from the pixel sensor array 202.

[0148] As mentioned above, Figure 3 is provided as a specific example. Figure 3 Other specific examples may be different from those described.

[0149] Figure 4 FIG. 4 is a schematic diagram illustrating an exemplary embodiment 400 of an anti-reflection array 340 according to the present disclosure. The anti-reflection array 340 may be included in a metal layer 318 (eg, a light blocking layer) in a black level correction region 206 of an image sensor device 200 according to the present disclosure.

[0150] like Figure 4 As shown, the recessed portion 344 of the anti-reflection array 340 may include a bottom surface 402 (corresponding to the top surface of the metal layer 318) and a sidewall 404. The non-recessed portion 342 may also include a sidewall 404 (which may correspond to the sidewall 404 of the recessed portion 344) and a top surface 406 (corresponding to the top surface of the metal layer 318).

[0151] Further Figure 4 As shown, exemplary dimensions of the anti-reflection array 340 may include an angle A1 between the bottom surface 402 of the recessed portion 344 and the adjacent sidewalls of the recessed portion 344. In some embodiments, the angle A1 may be included in the range of approximately 90 degrees to 96 degrees. However, other ranges of values ​​are still within the scope of the present disclosure. The angle A1 may be selected based on the use example of the image sensor device 200, the application purpose of the image sensor device 200, the estimated angle of incidence of the incident light in the use example of the image sensor device 200, and / or based on other parameters. In general, the angle A1 may be selected to reduce the likelihood and / or amount of incident light reflected to the pixel sensor array 202 of the image sensor device 200.

[0152] Another exemplary dimension of the anti-reflection array 340 may include a width W1 of the opening of the recessed portion 344. The width W1 may correspond to a cross-sectional width of the recessed portion 344 at the top of the recessed portion 344, such as Figure 4 In some embodiments, the width W1 is within a range of about 0.5 micrometers to about 1 micrometer so that light is reflected from the pixel sensor array 202 and the recessed portion 344 is formed to have a sufficient depth. However, other numerical ranges are still within the scope of the present disclosure.

[0153] Another exemplary dimension of the anti-reflection array 340 may include a width W2 of the bottom surface 402 of the recessed portion 344 between the sidewalls 404 of the recessed portion 344. In some embodiments, the width W2 is included in the range of about 0.25 microns to about 0.5 microns so that light is reflected from the pixel sensor array 202 and the recessed portion 344 is formed with a sufficient depth. However, other numerical ranges are still within the scope of the present disclosure. In some embodiments, the ratio of the width W1 to the width W2 is in the range of about 1:1 to about 2:1 so that light is reflected from the pixel sensor array 202 and the recessed portion 344 is formed with a sufficient depth. However, other numerical ranges are still within the scope of the present disclosure.

[0154] Another exemplary dimension of the anti-reflection array 340 may include a depth D1 of the recessed portion 344. The depth D1 is the difference between a height H1 corresponding to the top surface of the metal layer 318 in the non-recessed portion 342 and a height H2 of the top surface of the metal layer 318 in the recessed portion 344. In other words, the depth D1 is the height difference between the bottom surface 402 corresponding to the recessed portion 344 and the top surface 406 of the non-recessed portion 342. In some embodiments, the depth D1 is included in the range of about 0.1 microns to about 0.18 microns so that light can be reflected from the pixel sensor array 202 while providing sufficient residual thickness of the metal layer 318 in the recessed portion 344 to still block light from propagating through the metal layer 318 and to the sensing region 338 below. However, other numerical ranges are still within the scope of the present disclosure. In some embodiments, the ratio of the depth D1 to the thickness of the metal layer 318 is within a range of about 0.5:1 to about 0.9:1, so that light is reflected from the pixel sensor array 202 while providing sufficient residual thickness of the metal layer 318 in the recessed portion 344 to still block light from propagating through the metal layer 318 and to the underlying sensing region 338. However, other numerical ranges are still within the scope of the present disclosure.

[0155] Another exemplary dimension of the anti-reflection array 340 may include a spacing S between adjacent recessed portions 344. The spacing S may correspond to the width of the top surface of the non-recessed portion 342 between adjacent recessed portions 344. In some embodiments, the spacing S is included in the range of 0.5 microns to 1 micron so that light is reflected from the pixel sensor array 202 and the recessed portions 344 are formed with sufficient depth. However, other numerical ranges are still within the scope of the present disclosure.

[0156] As mentioned above, Figure 4 is provided as a specific example. Figure 4 Other specific examples may be different from those described.

[0157] FIG. 5A to FIG. 5O is a schematic diagram of an exemplary embodiment 500 of the present disclosure. The exemplary embodiment 500 may be an exemplary process for the image sensor device 200 of the present disclosure. The image sensor device 200 may include a pixel sensor array 202, wherein the pixel sensor array 202 includes a plurality of pixel sensors 204, a black level correction region 206 including an anti-reflection array 340, and a bonding pad region 208, among other examples.

[0158] like Figure 5A As shown, image sensor device 200 may include multiple layers, including intermetallic dielectric layer 302, interlayer dielectric layer 304, and substrate 306, among other examples. In some embodiments, substrate 306 is provided as a semiconductor wafer or other type of semiconductor workpiece. In some embodiments, deposition tool 102 may be used in a physical vapor deposition operation, an atomic layer deposition operation, a chemical vapor deposition operation, an epitaxial operation, an oxidation operation, a reference operation, a substrate 306, and a substrate 306. Figure 1 The IMD layer 302 and / or the ILD layer 304 may be deposited by the deposition tool 102 in other types of deposition operations and / or other suitable deposition operations. In some embodiments, after the deposition tool 102 deposits the IMD layer 302 and / or the ILD layer 304, the planarization tool 110 planarizes the IMD layer 302 and / or the ILD layer 304.

[0159] Further Figure 5A As shown, shallow trench isolation region 330 is formed in substrate 306 (e.g., before IMD layer 302 and / or ILD layer 304 are formed). Shallow trench isolation region 330 is formed in bonding pad region 208 of image sensor device 200. In some embodiments, deposition tool 102 can be used in a physical vapor deposition operation, an atomic layer deposition operation, a chemical vapor deposition operation, an epitaxial operation, an oxidation operation, a reference operation, or a substrate 306. Figure 1The STI regions 330 may be deposited in other types of deposition operations and / or other suitable deposition operations as described above. In some embodiments, after the STI regions 330 are deposited by the deposition tool 102, the planarization tool 110 planarizes the STI regions 330. In some embodiments, the etching tool 108 may form a recess in the substrate 306, and the STI regions 330 may be formed in the recess.

[0160] Further Figure 5A As shown, metallization layer 328 may be formed in IMD layer 302. IMD layer 302 may be formed in bonding pad region 208 of image sensor device 200. In some embodiments, etching tool 108 may form a recess in IMD layer 302, and metallization layer 328 may be formed in the recess. Deposition tool 102 and / or plating tool 112 may be used in a chemical vapor deposition operation, a physical vapor deposition operation, an atomic layer deposition operation, an electroplating operation, a reference Figure 1 The metallization layer 328 is deposited in other types of deposition operations and / or other suitable deposition operations as described above. In some embodiments, the seed layer is deposited first, and the metallization layer 328 is deposited on the seed layer. In some embodiments, after the metallization layer 328 is deposited by the deposition tool 102 and / or the electroplating tool 112, the planarization tool 110 planarizes the metallization layer 328.

[0161] like Figure 5B As shown, one or more semiconductor processing tools may form a plurality of photodiodes 308 in a substrate 306. For example, an ion implantation tool 114 may utilize ion implantation techniques to dope portions of the substrate 306 to form respective photodiodes 308 for the plurality of pixel sensors 204. The substrate 306 is doped with various types of ions to form a pn junction for each of the photodiodes 308. For example, the substrate 306 is doped with n-type dopants to form a first portion (e.g., an n-type portion) of the photodiode 308, and with p-type dopants to form a second portion (e.g., a p-type portion) of the photodiode 308. In some embodiments, other techniques are used to form the photodiodes 308, such as diffusion.

[0162] Further Figure 5B As shown, sensing region 338 can be included in substrate 306 in black level correction region 206 adjacent to pixel sensor 204 of pixel sensor array 202. In some embodiments, sensing region 338 includes an undoped portion of substrate 306 in black level correction region 206. In some embodiments, ion implantation tool 114 can dope a portion of substrate 306 using ion implantation techniques to form sensing region 338.

[0163] like Figure 5CAs shown, recess 502 may be formed in substrate 306 around photodiode 308 in pixel sensor array 202. Recess 502 may be formed in a portion of substrate 306 around photodiode 308 in pixel sensor array 202 to form deep trench isolation structure 310. In some embodiments, one or more semiconductor process tools may be used to form recess 502 of deep trench isolation structure 310 in substrate 306. For example, deposition tool 102 may form a photoresist layer on substrate 306, exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, development tool 106 may develop and remove a portion of the photoresist layer to expose a pattern, and etching tool 108 may etch a portion of substrate 306 to form recess 502 of deep trench isolation structure 310 in substrate 306. In some embodiments, after etching tool 108 etches substrate 306, a photoresist removal tool removes remaining portions of the photoresist layer (e.g., using a chemical stripper and / or other techniques).

[0164] like Figure 5D As shown, anti-reflective coating 312 may be formed on and / or over substrate 306 and may be formed in recess 502. Anti-reflective coating 312 may be conformally deposited so that anti-reflective coating 312 includes a thin film that conforms to the shape and / or contour of recess 502. Anti-reflective coating 312 may be included in pixel sensor array 202, in black level correction region 206, and / or on the surface of bonding pad region 208, among other exemplary substrates 306. Deposition tool 102 may deposit anti-reflective coating 312 using chemical vapor deposition techniques, physical vapor deposition techniques, atomic layer deposition techniques, or other types of deposition techniques. In some embodiments, deposition tool 102 may form anti-reflective coating 312 with a thickness in a range of about 200 angstroms to about 1000 angstroms. However, other ranges of values ​​are still within the scope of the present disclosure.

[0165] like Figure 5E As shown, recess 502 is filled with oxide layer 314. Additional oxide material may be deposited to extend adhesion layer 316 along the surface of substrate 306 in pixel sensor array 202, in black level correction region 206, and in bond pad region 208, among other examples. Deposition tool 102 may deposit oxide layer 314 using chemical vapor deposition techniques and / or atomic layer deposition techniques, such as plasma assisted chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, and / or plasma assisted atomic layer deposition, among other examples.

[0166] like Fig. 5FAs shown, metal layer 318 can be formed on and / or over adhesion layer 316. Metal layer 318 can be formed in pixel sensor array 202, in black level correction region 206, and in bonding pad region 208, among other examples. The portion of metal layer 318 in black level correction region 206 can correspond to the light blocking layer of sensing region 338. In some embodiments, metal layer 318 can be formed to have a thickness in the range of about 0.22 microns to about 0.24 microns. However, other ranges of values ​​are still within the scope of the present disclosure. Deposition tool 102 and / or electroplating tool 112 can be in a chemical vapor deposition operation, a physical vapor deposition operation, an atomic layer deposition operation, an electroplating operation, a reference Figure 1 The metal layer 318 is deposited by the other types of deposition operations described above and / or other suitable deposition operations. In some embodiments, the seed layer is deposited first, and the metal layer 318 is deposited on the seed layer. In some embodiments, after the metal layer 318 is deposited by the deposition tool 102 and / or the electroplating tool 112, the planarization tool 110 planarizes the metal layer 318.

[0167] like Figure 5G As shown, opening 506 is formed through metal layer 318 in pixel sensor array 202. Opening 506 is formed over photodiode 308 of pixel sensor 204 in pixel sensor array 202. Opening 506 is formed by removing a first portion of metal layer 318 to form metal grid 320 over deep trench isolation structure 310. Opening 506 and metal grid 320 may be formed when black level correction region 206 and bonding pad region 208 are masked (e.g., by a photoresist layer or hard mask). This allows metal layer 318 in pixel sensor array 202 to be fabricated to be separate from metal layer 318 in black level correction region 206 and bonding pad region 208. As such, opening 506 and metal grid 320 are formed before anti-reflection array 340 is formed in black level correction region 206. Alternatively, the pixel sensor array 202 may be shielded and the anti-reflection array 340 may be formed in the black level correction region 206 before the metal grid 320 is formed.

[0168] In some embodiments, one or more semiconductor process tools may be used to form openings 506 in metal layer 318 to form metal grid 320. For example, deposition tool 102 may form a photoresist layer on metal layer 318, exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, development tool 106 may develop and remove portions of the photoresist layer to expose the pattern, and etching tool 108 may etch through portions of metal layer 318 to form openings 506. In some embodiments, etching tool 108 etches into portions of underlying adhesion layer 316 to ensure that metal layer 318 is completely etched through. The portions of underlying adhesion layer 316 that are removed may be referred to as over-etched regions. In some embodiments, after etching tool 108 etches metal layer 318, a photoresist removal tool removes remaining portions of the photoresist layer (e.g., using chemical strippers and / or other techniques).

[0169] like Figure 5H As shown, oxide layer 324 is formed on and / or over metal grid 320 in pixel sensor array 202. Oxide layer 324 may also be formed in openings 506 on exposed portions of adhesion layer 316. Furthermore, oxide layer 324 may be formed on metal layer 318 in black level correction region 206 and bond pad region 208. Deposition tool 102 may conformally deposit oxide layer 324 using chemical vapor deposition techniques, physical vapor deposition techniques, atomic layer deposition techniques, or other types of deposition techniques.

[0170] like Fig.5I As shown, the anti-reflection array 340 is formed in the metal layer 318 in the black level correction area 206 of the image sensor device 200. The recessed portion 344 is formed in the metal layer 318 on the sensing area 338 of the black level correction area 206 to form the anti-reflection array 340. The recessed portion 344 can be formed by removing the second portion of the metal layer 318. The recessed portion 344 and the anti-reflection array 340 can be formed when the pixel sensor array 202 and the bonding pad area 208 are masked (e.g., by a photoresist layer or a hard mask). This allows the metal layer 318 in the black level correction area 206 to be made separate from the metal layer 318 in the pixel sensor array 202 and the bonding pad area 208. As such, the recessed portion 344 and the anti-reflection array 340 are formed after the opening 506 and the metal grid 320 are formed. Alternatively, the pixel sensor array 202 may be shielded and the anti-reflection array 340 may be formed in the black level correction region 206 before the metal grid 320 is formed.

[0171] In some embodiments, one or more semiconductor process tools may be used to form recessed portions 344 in metal layer 318 to form anti-reflective array 340. For example, deposition tool 102 may form a photoresist layer on oxide layer 324 in black level correction region 206, exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, development tool 106 may develop and remove portions of the photoresist layer to expose the pattern, and etching tool 108 may etch through portions of oxide layer 324 into portions of metal layer 318 to form recessed portions 344. In some embodiments, after etching tool 108 etches metal layer 318, a photoresist removal tool removes remaining portions of the photoresist layer (e.g., using chemical strippers and / or other techniques).

[0172] like Figure 5J As shown, a separate color filter region 322 may be formed in the opening 506 of each of the pixel sensors 204 in the pixel sensor array 202. Each color filter region 322 may be formed between the metal grids 320 to provide color mixing between adjacent pixel sensors 204. Alternatively, the area between the metal grids 320 is filled with a passivation layer, and the color filter layer including the color filter regions 322 may be formed over the passivation layer on the metal grids 320. In some embodiments, the deposition tool 102 may be used in a physical vapor deposition operation, an atomic layer deposition operation, a chemical vapor deposition operation, an epitaxial operation, an oxidation operation, a reference operation, or a combination thereof. Figure 1 The color filter regions 322 may be deposited by the other types of deposition operations described above and / or other suitable deposition operations. In some embodiments, after the deposition tool 102 deposits the color filter regions 322 , the planarization tool 110 planarizes the color filter regions 322 .

[0173] like Figure 5K As shown, recesses 332 are formed in the bond pad region 208. In particular, recesses 332 may be formed through the oxide layer 324, through the metal layer 318, through the adhesion layer 316, through the anti-reflective coating 312, into the substrate 306 to the shallow trench isolation region 330. The shallow trench isolation region 330 may be exposed through recesses 332. Recesses 332 may be formed by coating the oxide layer 324 with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing exposed or unexposed portions of the photoresist (e.g., using a development tool 106), and etching recesses 332 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0174] like Figure 5LAs shown, buffer oxide layer 334 is formed on STI region 330 and on the sidewalls of recess 332 in bond pad region 208. Deposition tool 102 may conformally deposit buffer oxide layer 334 using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other types of deposition techniques.

[0175] like Figure 5M As shown, opening 508 is formed in recess 332 of bond pad region 208. In particular, opening 508 is formed through buffer oxide layer 334, through shallow trench isolation region 330, through interlayer dielectric layer 304 to metallization layer 328 in intermetal dielectric layer 302. Opening 508 may be formed by coating buffer oxide layer 334 with photoresist (e.g., using deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using exposure tool 104), removing exposed or unexposed portions of the photoresist (e.g., using development tool 106), and etching opening 508 based on the pattern in the photoresist (e.g., using etching tool 108).

[0176] like Figure 5N As shown, bond pad 336 may be formed in opening 508. For example, a semiconductor process tool (e.g., deposition tool or plating tool 112) may form a metal layer (e.g., aluminum layer, copper layer, tungsten layer, gold layer, silver layer, metal alloy layer, or other type of metal layer) on buffer oxide layer 334, on shallow trench isolation region 330, and in opening 508 such that a portion of bond pad 336 is located on metallization layer 328. In some embodiments, removal of a portion of bond pad 336 may be performed by coating bond pad 336 with photoresist (e.g., using deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using exposure tool 104), removing the exposed or unexposed portions of the photoresist (e.g., using development tool 106), and etching a portion of bond pad 336 based on the pattern in the photoresist (e.g., using etching tool 108).

[0177] like Fig.5O As shown, microlens layer 326 including a plurality of microlenses is formed on and / or over color filter region 322. Microlens layer 326 may include a respective microlens for each of pixel sensors 204 in pixel sensor array 202.

[0178] As mentioned above, FIG. 5A to FIG. 5O is provided as a specific example. FIG. 5A to FIG. 5O Other specific examples may be different from those described.

[0179] Figure 6 The image sensor device 200 described in the present disclosure is shown along Figure 2 2 is a cross-sectional view of the exemplary embodiment 600 taken along line AA in FIG. Figure 6 FIG. 6 is a diagram illustrating a cross-sectional structure and / or layer combination of an image sensor device 200 included in a pixel sensor array 202, a black level correction region 206, and a bonding pad region 208. In exemplary embodiment 600, the image sensor device 200 includes the following Figure 3 The illustrated and described exemplary embodiment 300 of the image sensor device 200 has similarly configured layers and / or structures (i.e., IMD layer 302 to recessed portion 344). However, in exemplary embodiment 600, the image sensor device 200 includes an anti-reflection film 602 on the anti-reflection array 340 in the black level correction region 206 to further reduce the likelihood and amount of incident light being reflected to the pixel sensor array 202.

[0180] like Figure 6 As shown, the anti-reflection film 602 is included on the non-recessed portion 342 of the anti-reflection array 340. Thus, the anti-reflection film 602 is included on the oxide layer 324, wherein the oxide layer 324 is included on the non-recessed portion 342. The anti-reflection film 602 may include titanium nitride (TiN), silicon oxide (SiO x , such as SiO2), silicon oxynitride (SiON), and / or other suitable materials that can make the reflectivity of the anti-reflection array 340 reach about 1% or less. In some embodiments, the anti-reflection film 602 includes a single-layer structure, wherein the single-layer material is included on the non-recessed portion 342. In some embodiments, the anti-reflection film 602 includes a multi-layer structure, which includes a plurality of stacked layers, wherein at least two or more of the plurality of stacked layers have different refractive indices to further reduce the reflectivity of the anti-reflection array 340. In some embodiments, the multi-layer structure includes alternating material layers with different refractive indices.

[0181] The thickness of the anti-reflection film 602 may be selected to achieve a relatively low (e.g., less than about 1%) reflectivity of the anti-reflection array 340. For example, for visible light having a wavelength in the range of about 300 nanometers to about 700 nanometers, in an embodiment where the anti-reflection film 602 comprises titanium nitride, the thickness of the anti-reflection film 602 may be selected to be in the range of about 80 nanometers to about 140 nanometers. For another specific example, for visible light having a wavelength in the range of about 300 nanometers to about 700 nanometers, in an embodiment where the anti-reflection film 602 comprises silicon dioxide, the thickness of the anti-reflection film 602 may be selected to be in the range of about 70 nanometers to about 120 nanometers. However, other numerical ranges are still within the scope of the present disclosure.

[0182] As mentioned above, Figure 6 is provided as a specific example. Figure 6 Other specific examples may be different from those described.

[0183] Fig. 7A and Figure 7B is a schematic diagram illustrating an exemplary embodiment of the anti-reflection film 602 described in the present disclosure. Fig. 7A and Figure 7B The illustrated and described exemplary embodiment of anti-reflective film 602 may be implemented in anti-reflective array 340 in black level correction region 206 of image sensor device 200 .

[0184] Fig. 7A 700 is an exemplary embodiment of a single-layer structure of the anti-reflection film 602. The anti-reflection film 602 is included on the oxide layer 324, wherein the oxide layer 324 is included on the metal layer 318 (e.g., a light blocking layer) in the black level correction region 206. The interface between the anti-reflection film 602 and the surrounding environment 702 is composed of air or other types of gases.

[0185] like Fig. 7A As shown, incident light 704 may propagate into the anti-reflective film 602 and be partially reflected by the interface between the anti-reflective film 602 and the oxide layer 324. The remaining portion of the incident light 704 is refracted into the oxide layer 324. The ratio of the incident light reflected as reflected light 706 and the ratio of the incident light refracted as refracted light 708 are based on the angle of incidence A2, the refractive index (n1) of the anti-reflective film 602, and the refractive index (n2) of the oxide layer 324.

[0186] like Fig. 7A As further shown, the reflectivity 710 of the anti-reflection array 340 can be a function of the refractive index 712. In particular, the material of the anti-reflection film 602 can be selected such that the refractive index (n1) of the anti-reflection film 602 promotes a relatively low reflectivity 710. In one specific example, the material of the anti-reflection film 602 can be selected such that the anti-reflection film 602 achieves a reflectivity 710 of the anti-reflection array 340 of less than about 1%. In some embodiments, the refractive index (n1) of the anti-reflection film 602 is included in the range of about 1.14 to about 1.48 to make the reflectivity 710 of the anti-reflection array 340 less than about 1%. However, other numerical ranges are still within the scope of the present disclosure.

[0187] Figure 7B714 is an exemplary embodiment of an anti-reflection film 602 including a multilayer structure having a plurality of stacked layers. The anti-reflection film 602 is included on an oxide layer 324, wherein the oxide layer 324 is included on a metal layer 318 (e.g., a light blocking layer) in a black level correction region 206. The anti-reflection film 602 includes a first layer 716 having a refractive index (n1) and a second layer 718 having a second refractive index (n2). The refractive index (n1) and the refractive index (n2) may be different refractive indices. The first layer 716 is included on and / or above the second layer 718, and the interface between the first layer 716 and the surrounding environment 702 is composed of air or other types of gases. The second layer 718 is included on and / or above the oxide layer 324 and is connected to the oxide layer 324.

[0188] like Figure 7B As shown, part of the incident light 704 may be reflected by the first layer 716 as reflected light 720, and another part of the incident light 704 may propagate into the first layer 716 as refracted light 722 based on the refractive index (n1) of the first layer 716 and the refractive index (n3) of the surrounding environment 702. Part of the refracted light 722 is reflected by the interface between the first layer 716 and the second layer 718 as reflected light 724, and another part of the refracted light 722 is refracted light 726 propagating into the second layer 718. The ratio of the refracted light 722 being reflected as the reflected light 724 and the ratio of the refracted light 722 being refracted as the refracted light 726 are based on the incident angle A3 of the refracted light 722, the refractive index (n1) of the first layer 716, and the refractive index (n2) of the second layer 718.

[0189] Further Figure 7B As shown, part of the refracted light 726 is reflected by the interface between the second layer 718 and the oxide layer 324 as reflected light 728, and another part of the refracted light 726 is refracted light 730 that propagates into the oxide layer 324. The ratio of the refracted light 726 being reflected as reflected light 728 and the ratio of the refracted light 726 being refracted as refracted light 730 are based on the incident angle A4 of the refracted light 726, the refractive index (n2) of the second layer 718, and the refractive index (n4) of the oxide layer 324. At least a portion of the refracted light 730 may be reflected by the oxide layer 324 as reflected light 732.

[0190] Reflected light 724, reflected light 728, and reflected light 732 may continue to be reflected and / or refracted internally in the layers of the anti-reflective film 602. The additional reflections and refractions cause the rate at which incident light 704 is absorbed by the anti-reflective film 602 to reduce the reflectivity 710 of the anti-reflective array 340.

[0191] Further Figure 7BAs shown, the reflectivity 710 of the anti-reflection array 340 can be a function of a ratio 734 of the refractive index (n1) of the first layer 716 to the refractive index (n2) of the second layer 718 and other parameters. In particular, the materials of the first layer 716 and the second layer 718 are selected so that the ratio 734 of the refractive index (n1) of the first layer 716 to the refractive index (n2) of the second layer 718 promotes a relatively low reflectivity 710. In a specific example, the materials of the first layer 716 and the second layer 718 are selected so that the ratio 734 of the refractive index (n1) of the first layer 716 to the refractive index (n2) of the second layer 718 achieves a reflectivity 710 of the anti-reflection array 340 of less than about 1%. In some embodiments, the ratio 734 of the refractive index (n1) of the first layer 716 to the refractive index (n2) of the second layer 718 is within a range of about 1:1 to about 1.3:1 to achieve a reflectivity 710 of the anti-reflective array 340 of less than about 1%. However, other numerical ranges are still within the scope of the present disclosure.

[0192] As mentioned above, Fig. 7A and Figure 7B is provided as a specific example. Fig. 7A and Figure 7B Other specific examples may be different from those described.

[0193] FIG. 8A to FIG. 8D FIG. 8 is a schematic diagram of an exemplary embodiment 800 of the present disclosure. The exemplary embodiment 800 may be an exemplary process for an image sensor device 200 including an anti-reflection film 602 of the present disclosure.

[0194] like Fig. 8A As shown, you can refer to FIG. 5A to FIG. 5H One or more process operations are depicted and described to form a photodiode 308 of the pixel sensor 204 , to form a deep trench isolation structure 310 , and to form a metal grid 320 in a metal layer 318 , among other examples.

[0195] like Figure 8BAs shown, the anti-reflective film 602 is formed on and / or over the oxide layer 324 of the pixel sensor 204, on the oxide layer 324 in the black level correction area 206, and / or on the oxide layer 324 in the bonding pad area 208, among other examples. The deposition tool 102 may deposit the anti-reflective film 602 using a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, or other types of deposition techniques. In some embodiments, the anti-reflective film 602 includes silicon oxynitride (SiON). In the aforementioned embodiments, the deposition tool 102 may be provided by providing a nitrogen (N) gas flow to a process chamber where the image sensor device 200 of the deposition tool 102 is located, and by providing an oxygen (O) gas flow to the process chamber, wherein the ratio of oxygen to nitrogen is precisely controlled to achieve a specific refractive index of the anti-reflective film 602. As such, the refractive index of the anti-reflective film 602 may be selected to achieve a relatively low reflectivity of the anti-reflective film 602, such as less than about 1%, among other examples.

[0196] like Figure 8C As shown, a portion of the anti-reflective film 602 is removed so that the anti-reflective film 602 remains only in the black level correction region 206. In some embodiments, the etching tool 108 may etch the anti-reflective film 602 to remove a portion of the anti-reflective film 602.

[0197] like Fig.8D As shown, the anti-reflection array 340 is formed in the metal layer 318 in the black level correction area 206 of the image sensor device 200. The recessed portion 344 is formed in the metal layer 318 on the sensing area 338 of the black level correction area 206 to form the anti-reflection array 340. The recessed portion 344 is formed by removing the second portion of the metal layer 318. The recessed portion 344 and the anti-reflection array 340 can be formed when the pixel sensor array 202 and the bonding pad area 208 are masked (e.g., by a photoresist layer or a hard mask). This allows the metal layer 318 in the black level correction area 206 to be made separate from the metal layer 318 in the pixel sensor array 202 and the bonding pad area 208. In this way, the recessed portion 344 and the anti-reflection array 340 can be formed after the metal grid 320 in the pixel sensor array 202 is formed. Instead, the pixel sensor array 202 is shielded and the anti-reflection array 340 is formed in the black level correction region 206 before the metal grid 320 is formed.

[0198] In some embodiments, one or more semiconductor process tools may be used to form the recessed portion 344 in the metal layer 318 to form the anti-reflective array 340. For example, the deposition tool 102 may form a photoresist layer on the anti-reflective film 602 in the black level correction region 206, the exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, the development tool 106 may develop and remove a portion of the photoresist layer to expose the pattern, and the etching tool 108 may etch through a portion of the anti-reflective film 602, through a portion of the oxide layer 324, into a portion of the metal layer 318 to form the recessed portion 344. In this way, the recessed portion 344 extends through the anti-reflective film 602, through the oxide layer 324, and into the metal layer 318. In some embodiments, after the etching tool 108 etches the metal layer 318, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper and / or other techniques).

[0199] In some embodiments, reference may be made to FIG. 8A to FIG. 8D The above operation is followed by additional process operations, such as FIG. 5J to FIG. 5O As shown and described.

[0200] As mentioned above, FIG. 8A to FIG. 8D is provided as a specific example. FIG. 8A to FIG. 8D Other specific examples may be different from those described.

[0201] Fig. 9 FIG. 9 is a diagram illustrating an exemplary embodiment 900 of the present disclosure of gas ratios for forming an anti-reflection film 602. The anti-reflection film 602 is included on an oxide layer 324, wherein the oxide layer 324 is included on a metal layer 318 (eg, a light blocking layer) in the black level correction region 206.

[0202] like Fig. 9 As shown, the refractive index 902 of the anti-reflective film 602 is based on the gas ratio 904 of oxygen to the combination of oxygen and nitrogen used to form the anti-reflective film 602. In particular, the refractive index 902 may decrease as the gas ratio 904 decreases. In some embodiments, a gas ratio 904 of about 0.9:1 may be used to achieve a refractive index of the anti-reflective film 602 in the range of about 1.06 to about 1.50. The refractive index of the anti-reflective film 602 may be selected from the aforementioned range to achieve a relatively low reflectivity (e.g., less than about 1%) for the anti-reflective film 602. However, other numerical ranges are still within the scope of the present disclosure.

[0203] As mentioned above, Fig. 9 is provided as a specific example. Fig. 9 Other specific examples may be different from those described.

[0204] Fig. 10A and Fig. 10Bis a schematic diagram illustrating an exemplary embodiment of the anti-reflection array 340 described in the present disclosure. Fig. 10A and Fig. 10B The illustrated and described exemplary embodiment of the anti-reflection array 340 may be implemented in the black level correction region 206 of the image sensor device 200 described herein. The exemplary embodiment of the anti-reflection array 340 is illustrated in a top view of the metal layer 318 in which the anti-reflection array 340 is formed.

[0205] like Fig. 10A As shown, the exemplary embodiment 1000 of the anti-reflective array 340 may include a plurality of recessed portions 344 arranged in a grid pattern in the anti-reflective array 340. The recessed portions 344 may include grooves that are approximately circular in a top view of the anti-reflective array 340.

[0206] like Fig. 10A As shown, the exemplary embodiment 1010 of the anti-reflective array 340 can include a plurality of recessed portions 344 arranged in an offset pattern in the anti-reflective array 340. In other words, the recessed portions 344 can be arranged in columns, and the recessed portions 344 of adjacent columns in the anti-reflective array 340 are offset or staggered from each other. The recessed portions 344 can include grooves that are approximately circular in a top view of the anti-reflective array 340.

[0207] Further Fig. 10A As shown, the exemplary embodiment 1020 of the anti-reflective array 340 may include a plurality of recessed portions 344 arranged in a grid pattern in the anti-reflective array 340. The recessed portions 344 may include grooves that are approximately square in a top view of the anti-reflective array 340.

[0208] like Fig. 10B As shown, the exemplary embodiment 1030 of the anti-reflective array 340 may include a plurality of recessed portions 344 arranged in a grid pattern in the anti-reflective array 340. The recessed portions 344 may include grooves that are approximately rectangular in a top view of the anti-reflective array 340.

[0209] like Fig. 10B As shown, the exemplary embodiment 1040 of the anti-reflection array 340 may include a plurality of recessed portions 344 arranged in a row in the anti-reflection array 340. The recessed portions 344 may include elongated rectangular grooves in a top view of the anti-reflection array 340.

[0210] Further Fig. 10BAs shown, an exemplary embodiment 1050 of the anti-reflection array 340 may include a plurality of recessed portions 344 arranged in crossed columns in the anti-reflection array 340. The recessed portions 344 may include elongated rectangular grooves in a top view of the anti-reflection array 340. Each recessed portion 344 in the anti-reflection array 340 may intersect with at least one other recessed portion 344.

[0211] In some embodiments, the specific arrangement and / or shape of recessed portions 344 in anti-reflection array 340 is selected based on one or more parameters of image sensor device 200 including anti-reflection array 340. For example, in an example of an intended use of image sensor device 200, the specific arrangement and / or shape of recessed portions 344 in anti-reflection array 340 is selected based on an estimated direction of incident light received by image sensor device 200. In one specific example, if image sensor device 200 including anti-reflection array 340 is expected to receive incident light from one or more independent directions, square grooves and / or rectangular grooves may be selected as recessed portions 344 in anti-reflection array 340. In another specific example, if image sensor device 200 including anti-reflection array 340 is expected to receive incident light from omnidirectional directions, circular grooves may be selected as recessed portions 344 in anti-reflection array 340.

[0212] In another embodiment, in an example of an intended use of image sensor device 200, a particular arrangement and / or shape of recessed portions 344 in anti-reflection array 340 is selected based on an estimated wavelength (or wavelength composition) of incident light received by image sensor device 200. In one embodiment, if image sensor device 200 including anti-reflection array 340 is expected to receive incident light having a longer wavelength (e.g., infrared, IR light), larger recessed portions may be selected as recessed portions 344 in anti-reflection array 340. In another embodiment, if image sensor device 200 including anti-reflection array 340 is expected to receive incident light having a shorter wavelength (e.g., infrared, IR light), smaller recessed portions may be selected as recessed portions 344 in anti-reflection array 340.

[0213] As mentioned above, Fig. 10A and Fig. 10B is provided as a specific example. Fig. 10A and Fig. 10B Other specific examples may be different from those described.

[0214] Fig.11 1 is a schematic diagram illustrating exemplary components of the apparatus 1100 described herein. In some embodiments, one or more of the semiconductor process tool 102 to the semiconductor process tool 114 and the wafer / die transfer tool 116 may include one or more apparatuses 1100 and / or one or more components of the apparatus 1100. Fig.11 As shown, device 1100 may include a bus 1110 , a processor 1120 , a memory 1130 , an input component 1140 , an output component 1150 , and / or a communication component 1160 .

[0215] The bus 1110 includes one or more components that enable wired and / or wireless communication between components of the device 1100. The bus 1110 may be connected to Fig.11 Two or more components of a computer system are coupled together, such as by operational coupling, communication coupling, electrical coupling, and / or electrical coupling. For example, bus 1110 may include electrical connections (such as wires, traces, and / or leads) and / or wireless buses. Processor 1120 includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable logic gate array, a special application integrated circuit, and / or other types of process elements. Processor 1120 is implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1120 includes one or more processors that can be programmed to perform one or more operations or processes described elsewhere in the present disclosure.

[0216] The memory 1130 may include volatile and / or non-volatile memory. For example, the memory 1130 may include random access memory (RAM), read only memory (ROM), and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 1130 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 1130 may be a non-transitory computer-readable medium. The memory 1130 may store information related to the operation of the device 1100, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, the memory 1130 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 1120), for example, via a bus 1110. The communicative coupling between the processor 1120 and the memory 1130 allows the processor 1120 to read and / or process information stored in the memory 1130 and / or store information in the memory 1130 .

[0217] Input components 1140 enable device 1100 to receive input, such as user input and / or sensor input. For example, input components 1140 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a converter, a sensor, a global positioning system component, an accelerometer, a gyroscope, and / or a brake. Output components 1150 enable device 1100 to provide output, such as through a screen, a loudspeaker, and / or a light emitting diode. Communication components 1160 enable device 1100 to communicate with other devices via wired connections and / or wireless connections. For example, communication components 1160 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0218] Device 1100 may perform one or more operations or processes described above. For example, a non-transitory computer-readable medium (e.g., memory 1130) may store a set of instructions (e.g., one or more instructions or program codes) executed by processor 1120. Processor 1120 may perform one or more operations or processes described in the present disclosure. In some embodiments, a set of instructions executed by one or more processors 1120 causes one or more processors 1120 and / or device 1100 to perform one or more operations or processes described in the present disclosure. In some embodiments, fixed-wire circuits may replace or be combined with instructions to perform one or more operations or processes described in the present disclosure. In addition or alternatively, processor 1120 is configured to perform one or more operations or processes described in the present disclosure. Therefore, the embodiments described in the present disclosure are not limited to any particular combination of fixed-wire circuits and software.

[0219] Fig.11 The number and configuration of components shown are provided for illustration only. Device 1100 may include additional components, fewer components, different components, or different Fig.11 Additionally or alternatively, one set of components (eg, one or more components) of device 1100 may perform one or more functions described as being performed by another set of components of device 1100.

[0220] Fig.12 is a flow chart of an exemplary process 1200 associated with forming an image sensor device. In some embodiments, Fig.12 One or more process blocks are performed by one or more semiconductor process tools (e.g., semiconductor process tools 102 to semiconductor process tools 114). In addition or alternatively, Fig.12 One or more process blocks may be performed by one or more components of the apparatus 1100 , such as the processor 1120 , the memory 1130 , the input component 1140 , the output component 1150 , and / or the communication component 1160 .

[0221] like Fig.12As shown, process 1200 may include forming one or more photodiodes in a substrate of an image sensor device in an array of pixel sensors of the image sensor device (block 1210). For example, one or more of semiconductor process tools 102 to semiconductor process tools 114 may form one or more photodiodes 308 in substrate 306 of image sensor device 200 in array of pixel sensors of image sensor device 200, as described herein.

[0222] Further Fig.12 As shown, process 1200 may include forming a metal layer on one or more photodiodes of the image sensor device and on a sensing region in the black level correction region (block 1220). For example, one or more of semiconductor process tools 102 to semiconductor process tools 114 may form metal layer 318 on one or more photodiodes 308 of image sensor device 200 and on sensing region 338 in the black level correction region 206, as described herein.

[0223] Further Fig.12 As shown, process 1200 may include removing a first portion of a metal layer in the pixel sensor array to form a metal grid over one or more photodiodes (block 1230). For example, one or more of semiconductor process tools 102 to semiconductor process tools 114 may remove a first portion of metal layer 318 in pixel sensor array 202 to form metal grid 320 over one or more photodiodes 308, as described herein.

[0224] Further Fig.12 As shown, the process 1200 may include removing a second portion of the metal layer in the black level correction region to form an anti-reflection array in the metal layer in the black level correction region (block 1240). For example, one or more of the semiconductor process tools 102 to the semiconductor process tools 114 may remove a second portion of the metal layer 318 in the black level correction region 206 to form an anti-reflection array 340 in the metal layer 318 in the black level correction region 206, as described in the present disclosure. In some embodiments, the metal layer 318 in the black level correction region 206 corresponds to a light blocking layer on the sensing region 338 in the black level correction region 206.

[0225] The process 1200 may include additional embodiments, such as any single embodiment or any combination of the embodiments described below and / or in combination with one or more other processes described elsewhere in this disclosure.

[0226] In a first embodiment, removing the second portion of the metal layer 318 in the black level correction region 206 includes removing the second portion of the metal layer 318 in the black level correction region 206 after removing the first portion of the metal layer 318 in the pixel sensor array 202. In a second embodiment, either alone or in combination with the first embodiment, removing the first portion of the metal layer 318 in the pixel sensor array 202 includes removing the first portion of the metal layer 318 in the pixel sensor array 202 when the metal layer 318 in the black level correction region 206 is masked. In a third embodiment, either alone or in combination with one or more of the first and second embodiments, the process 1200 includes forming an oxide layer 324 on the metal layer 318 after removing the first portion of the metal layer 318 in the pixel sensor array 202 and before removing the second portion of the metal layer 318 in the black level correction region 206.

[0227] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the process 1200 includes removing a portion of the oxide layer 324 in the black level correction region 206 to form the anti-reflection array 340. In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the process 1200 includes forming an anti-reflection film 602 on the metal layer 318 after removing a first portion of the metal layer 318 in the pixel sensor array 202 and before removing a second portion of the metal layer 318 in the black level correction region 206.

[0228] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the anti-reflective film 602 includes silicon oxynitride (SiON), and forming the anti-reflective film 602 includes providing a nitrogen flow into a process chamber where the image sensor device 200 is located, and providing an oxygen flow into the process chamber, wherein the ratio of the oxygen flow to the nitrogen flow is about 0.9:1 to about 9:1.

[0229] Although Fig.12 Example blocks of process 1200 are shown. In some embodiments, process 1200 may include additional blocks, fewer blocks, different blocks, or blocks different from those in the process 1200. Fig.12 The block configuration is depicted. Additionally or alternatively, two or more blocks of process 1200 can be performed simultaneously.

[0230] In this way, the image sensor device includes a pixel sensor array and a black level correction area adjacent to the pixel sensor array. The black level correction area may include a sensing area in the substrate and a light blocking layer on the sensing area. An anti-reflection array is formed in the light blocking layer. The anti-reflection array includes holes, trenches and / or other structural features so that the light blocking layer includes two or more areas, wherein the top surface of the light blocking layer is at different heights in the image sensor device. The different heights of the top surface of the light blocking layer reduce the possibility of light being reflected from the light blocking layer to the pixel sensor array. In this way, the anti-reflection array can reduce the possibility of glare or hot spots occurring in the images and / or videos generated by the image sensor device, which can increase the image quality of the images generated by the image sensor device.

[0231] As described in detail above, some embodiments of the present disclosure provide an image sensor device. The image sensor device includes a pixel sensor array. The image sensor device includes a black level correction region adjacent to the pixel sensor array. The black level correction region includes a sensing region, a light blocking layer on the sensing region, and an anti-reflection array in the light blocking layer. The anti-reflection array includes a plurality of recessed portions in the light blocking layer.

[0232] As described in detail above, some embodiments of the present disclosure provide an image sensor device. The image sensor device includes a pixel sensor array. The image sensor device includes a black level correction region adjacent to the pixel sensor array. The black level correction region includes a sensing region, a light blocking layer on the sensing region, an anti-reflection film on the light blocking layer, and an anti-reflection array in the anti-reflection film and the light blocking layer. The anti-reflection array includes a plurality of recessed portions extending through the anti-reflection film and into the light blocking layer.

[0233] As described in detail above, some embodiments of the present disclosure provide a method for manufacturing an image sensor device. The method includes forming one or more photodiodes in a pixel sensor array of the image sensor device in a substrate of the image sensor device. The method includes forming a metal layer on the one or more photodiodes of the image sensor device and on a sensing area in a black level correction area. The method includes removing a first portion of the metal layer in the pixel sensor array to form a metal grid on the one or more photodiodes. The method includes removing a second portion of the metal layer in the black level correction area to form an anti-reflection array in the metal layer in the black level correction area, wherein the metal layer in the black level correction area corresponds to a light blocking layer on the sensing area in the black level correction area.

[0234] In some embodiments of the present disclosure, an image sensor device is provided. The image sensor device includes a pixel sensor array. The image sensor device includes a black level correction region adjacent to the pixel sensor array. The black level correction region includes a sensing region, a light blocking layer on the sensing region, and an anti-reflection array in the light blocking layer. The anti-reflection array includes a plurality of recessed portions in the light blocking layer.

[0235] In the above embodiment, the top surface of the light blocking layer in the non-recessed portion of the light blocking layer is at a first height in the image sensor device, and the first height is greater than a second height of the top surface of the light blocking layer in the recessed portion of the recessed portion. In the above embodiment, the recessed portions are arranged in a grid pattern in the anti-reflection array. In the above embodiment, the recessed portions are arranged in an offset pattern in the anti-reflection array. In the above embodiment, the recessed portions are arranged in a row in the anti-reflection array. In the above embodiment, the anti-reflection array is configured to prevent an incident light from being reflected from the black level correction area to the pixel sensor array.

[0236] In some embodiments of the present disclosure, an image sensor device is provided. The image sensor device includes a pixel sensor array. The image sensor device includes a black level correction region adjacent to the pixel sensor array. The black level correction region includes a sensing region, a light blocking layer on the sensing region, an anti-reflection film on the light blocking layer, and an anti-reflection array in the anti-reflection film and the light blocking layer. The anti-reflection array includes a plurality of recessed portions extending through the anti-reflection film and into the light blocking layer.

[0237] In the above embodiment, the anti-reflection film comprises a single-layer structure. In the above embodiment, the anti-reflection film comprises a plurality of stacked layers. In the above embodiment, the stacked layers comprise a first layer having a first refractive index and a second layer having a second refractive index, and the first refractive index and the second refractive index are different refractive indices. In the above embodiment, the ratio of the second refractive index to the first refractive index is about 1:1 to about 1.3:1. In the above embodiment, the anti-reflection film comprises at least one of the following: titanium nitride (TiN), silicon oxide (SiO x ) or silicon oxynitride (SiON). In the above embodiment, the refractive index of the anti-reflection film is about 1.14 to about 1.48.

[0238] In some embodiments of the present disclosure, a method for manufacturing an image sensor device is provided. The method includes forming one or more photodiodes in a pixel sensor array of the image sensor device in a substrate of the image sensor device. The method includes forming a metal layer on the one or more photodiodes of the image sensor device and on a sensing area in a black level correction region. The method includes removing a first portion of the metal layer in the pixel sensor array to form a metal grid on the one or more photodiodes. The method includes removing a second portion of the metal layer in the black level correction region to form an anti-reflection array in the metal layer in the black level correction region, wherein the metal layer in the black level correction region corresponds to a light blocking layer on the sensing area in the black level correction region.

[0239] In the above embodiment, removing the second portion of the metal layer in the black level correction area includes removing the second portion of the metal layer in the black level correction area after removing the first portion of the metal layer in the pixel sensor array. In the above embodiment, the step of removing the first portion of the metal layer in the pixel sensor array includes removing the first portion of the metal layer in the pixel sensor array when the metal layer in the black level correction area is shielded. In the above embodiment, the method further includes forming an oxide layer on the metal layer after removing the first portion of the metal layer in the pixel sensor array and before removing the second portion of the metal layer in the black level correction area. In the above embodiment, the method further includes removing a portion of the oxide layer in the black level correction area to form an anti-reflection array. In the above embodiment, the method further includes forming an anti-reflection film on the metal layer after removing the first portion of the metal layer in the pixel sensor array and before removing the second portion of the metal layer in the black level correction area. In the above embodiment, the anti-reflective film includes silicon oxynitride (SiON), and the above formation of the anti-reflective film includes providing a nitrogen flow into a process chamber, wherein the image sensor device is located in the process chamber; and providing an oxygen flow into the process chamber, wherein the ratio of the oxygen flow to the nitrogen flow is substantially 0.9:1 to 9:1.

[0240] In some embodiments of the present disclosure, an image sensor device is provided. The image sensor device includes a pixel sensor array, a metal layer, and a black level correction region. The metal layer includes a metal grid on the pixel sensor array. The black level correction region is adjacent to the pixel sensor array. The black level correction region includes a sensing region, wherein at least a portion of the metal layer is in the black level correction region, and at least a portion of the metal layer in the black level correction region is on the sensing region and has a plurality of recessed portions.

[0241] In the above embodiment, the black level correction region further includes an anti-reflection array in the metal layer on the sensing region and in the black level correction region.

[0242] The above summarizes the features of many embodiments, so that those with ordinary knowledge in the art can better understand the aspects of the present disclosure. Those with ordinary knowledge in the art should understand that other processes and structures can be designed or modified based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments described. Those with ordinary knowledge in the art should also understand that equivalent structures do not deviate from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor device, characterized in that: Include: a pixel sensor array; and A black level correction (BLC) region adjacent to the pixel sensor array, wherein the black level correction region comprises: a sensing area; a light blocking layer on the sensing area; and An anti-reflection array is in the light blocking layer, wherein the anti-reflection array comprises a plurality of recessed portions in the light blocking layer.

2. The image sensor device according to claim 1, wherein: A top surface of the light blocking layer in a non-recessed portion of the light blocking layer is at a first height in the image sensor device, and the first height is greater than a second height of the top surface of the light blocking layer in a recessed portion of the plurality of recessed portions.

3. The image sensor device according to claim 1, wherein: The plurality of recessed portions are arranged in a grid pattern in the anti-reflection array.

4. The image sensor device according to claim 1, wherein: The plurality of recessed portions are arranged in an offset pattern in the anti-reflection array.

5. The image sensor device according to claim 1, wherein: The plurality of recessed portions are arranged in a row in the anti-reflection array.

6. An image sensor device, characterized in that: Include: a pixel sensor array; and A black level correction region adjacent to the pixel sensor array, wherein the black level correction region comprises: a sensing area; a light blocking layer on the sensing area; an anti-reflection film on the light blocking layer; and An anti-reflection array is provided in the anti-reflection film and the light blocking layer, wherein the anti-reflection array comprises a plurality of recessed portions, and the plurality of recessed portions extend through the anti-reflection film and extend into the light blocking layer.

7. The image sensor device according to claim 6, wherein: The anti-reflection film comprises a single-layer structure.

8. The image sensor device according to claim 6, wherein: The anti-reflection film comprises a plurality of stacked layers.

9. An image sensor device, characterized in that: Include: a pixel sensor array; a metal layer including a metal grid on the pixel sensor array; and A black level correction region adjacent to the pixel sensor array, wherein the black level correction region comprises: A sensing region, wherein at least a portion of the metal layer is in the black level correction region, and the at least a portion of the metal layer in the black level correction region is on the sensing region and has a plurality of concave portions.

10. The image sensor device according to claim 9, wherein: The black level correction area also includes: An anti-reflection array is on the sensing area and in the metal layer in the black level correction area.

Images