Integrated chip

Abstract

The utility model provides an integrated chip which comprises a semiconductor substrate. The semiconductor substrate includes a first region having a first doping type, a second region having a second doping type different from the first doping type, and a third region having the second doping type. The photodetector is located in the semiconductor substrate. The photodetector is at least partially formed by a first region and a second region. A first capacitor electrode is over the third region of the semiconductor substrate. The first capacitor electrode includes a semiconductor. The first insulator layer is between the first capacitor electrode and the third region. The capacitor is along the semiconductor substrate. The capacitor is at least partially formed by the first capacitor electrode, the third region, and the first insulator layer.

Description

Technical Field

[0001] The embodiment of the utility model relates to an integrated chip. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) image sensors are widely used in modern electronic devices such as cameras, tablets, smartphones, etc. CMOS image sensors can be front-side illuminated (FSI) or back-side illuminated (BSI). Compared with FSI image sensors, BSI image sensors have better sensitivity, better angle response, and greater metal routing flexibility.

[0003] Many modern integrated chips include transistors and passive components. Some examples of passive components include capacitors, resistors, inductors, varactor diodes, etc. Passive components are widely used to control integrated chip characteristics, such as gain, time constant, etc. Some passive components include integrated passive components (IPDs). An IPD is a collection of one or more passive components that are embedded into a single monolithic component and packaged as an integrated circuit (IC). Utility Model Content

[0004] An embodiment of the utility model provides an integrated chip including: a semiconductor substrate, a photodetector, a first capacitor electrode and a first insulator layer. The semiconductor substrate includes a first region having a first doping type, a second region having a second doping type different from the first doping type, and a third region having the second doping type. The photodetector is located in the semiconductor substrate. The photodetector is at least partially formed by the first region and the second region. The first capacitor electrode is located above the third region of the semiconductor substrate. The first capacitor electrode includes a semiconductor. The first insulator layer is located between the first capacitor electrode and the third region. The integrated chip also includes a capacitor along the semiconductor substrate. The capacitor is at least partially formed by the first capacitor electrode, the third region and the first insulator layer, and the capacitor extends directly above the photodetector.

[0005] In some embodiments, the first capacitor electrode forms a first electrode of the capacitor, and wherein the third region forms a second electrode of the capacitor. In some embodiments, the integrated chip further comprises: a second capacitor electrode located above the first capacitor electrode; and a second insulator layer located between the first capacitor electrode and the second capacitor electrode, wherein the capacitor is further formed by the second capacitor electrode and the second insulator layer. In some embodiments, the first capacitor electrode forms a first electrode of the capacitor, wherein the second capacitor electrode is coupled to the third region, and wherein the second capacitor electrode and the third region form a second electrode of the capacitor. In some embodiments, the sidewalls of the semiconductor substrate define a trench in the third region of the semiconductor substrate, and wherein the first capacitor electrode and the first insulator layer extend below the top surface of the semiconductor substrate and between the sidewalls of the semiconductor substrate. In some embodiments, the photodetector is buried in the semiconductor substrate below the first side of the semiconductor substrate, and wherein the capacitor is arranged along the first side of the semiconductor substrate. In some embodiments, the sidewalls of the semiconductor substrate define a trench in the third region of the semiconductor substrate, and wherein the first capacitor electrode and the first insulator layer extend below the top surface of the semiconductor substrate and between the sidewalls of the semiconductor substrate. In some embodiments, the semiconductor substrate further comprises a fourth region having a first doping type, the fourth region extending along the sidewalls of the semiconductor substrate between the sidewalls of the semiconductor substrate and the third region. In some embodiments, the semiconductor substrate further includes a fourth region adjacent to the third region, the fourth region having the second doping type. In some embodiments, the semiconductor substrate further includes a fifth region adjacent to the third region, the fifth region having the second doping type, wherein the fourth region and the fifth region are located on opposite sides of the third region, and wherein the fourth region forms a first source / drain of the transistor, the fifth region forms a second source / drain of the transistor, the third region forms a channel of the transistor, and the first capacitor electrode forms a gate of the transistor.

[0006] The utility model embodiment provides an integrated chip including: a semiconductor substrate, a photodetector, a transfer transistor, a first capacitor electrode and a first insulator layer. The semiconductor substrate includes a bulk region having a first doping type and a capacitor injection region having a second doping type different from the first doping type. The photodetector is located in the semiconductor substrate. The transfer transistor is arranged along the semiconductor substrate. The first source / drain of the transfer transistor is coupled to the photodetector, and the second source / drain of the transfer transistor is coupled to the capacitor injection region. The first capacitor electrode is located above the capacitor injection region. The first capacitor electrode includes a semiconductor. The first insulator layer is located between the first capacitor electrode and the capacitor injection region. The integrated chip also includes a capacitor along the semiconductor substrate. The capacitor is at least partially formed by the first capacitor electrode, the capacitor injection region and the first insulator layer. The semiconductor substrate has a pair of sidewalls defining a groove in the capacitor injection region of the semiconductor substrate, and wherein the first capacitor electrode and the first insulator layer extend below the top surface of the semiconductor substrate and between the opposite sidewalls of the semiconductor substrate.

[0007] In other embodiments, the integrated chip further includes: a second capacitor electrode overlying the first capacitor electrode; and a second insulator layer located between the second capacitor electrode and the first capacitor electrode, wherein the first capacitor electrode forms a first electrode of the capacitor, and wherein the second capacitor electrode and the capacitor injection region form a second electrode of the capacitor. In other embodiments, the semiconductor substrate further includes a protection injection region having a first doping type, the protection injection region extending along a trench between the semiconductor substrate and the opposite sidewalls of the capacitor injection region. In other embodiments, the photodetector is buried in the semiconductor substrate below the first side of the semiconductor substrate, and wherein the capacitor is arranged along the first side of the semiconductor substrate and extends directly above the photodetector. In other embodiments, the integrated chip further includes: a shallow trench isolation layer located on the opposite side of the semiconductor substrate to the first capacitor electrode, wherein the bottom surface of the first capacitor electrode is located between the opposite sidewalls of the semiconductor substrate and below the bottom surface of the shallow trench isolation layer. In other embodiments, the integrated chip further includes: a shallow trench isolation layer located in the semiconductor substrate and on the opposite side of the first capacitor electrode, wherein the bottom surface of the first capacitor electrode is located above the bottom surface of the shallow trench isolation layer.

[0008] Based on the above, the present invention relates to an integrated chip including a semiconductor capacitor and a method for forming the same. In various embodiments of the present invention, the capacitance of the semiconductor capacitor can be increased without reducing the fill factor of the pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0010] Figure 1 Cross-sectional views of some embodiments of an integrated chip including a pixel along a semiconductor substrate and a semiconductor capacitor along the pixel are shown.

[0011] Figure 2 Shows Figure 1 Circuit diagrams of some embodiments of an integrated chip.

[0012] Figure 3 Cross-sectional views of some other embodiments of integrated chips including pixels along a semiconductor substrate and semiconductor capacitors along the pixels are shown.

[0013] Figure 4 and Figure 5 Cross-sectional views of various other embodiments of an integrated chip including a pixel along a semiconductor substrate and a semiconductor capacitor along the pixel are shown.

[0014] Figure 6 Shows Figure 4 and Figure 5 Top view of some embodiments of an integrated chip.

[0015] Figure 7 and Figure 8 Cross-sectional views of various other embodiments of an integrated chip including a pixel along a semiconductor substrate and a semiconductor capacitor along the pixel are shown.

[0016] Fig. 9 Shows Figure 1 A cross-sectional view of some embodiments of an integrated chip in which a transistor is arranged between a pass transistor and a semiconductor capacitor.

[0017] Fig.10 Shows Figure 3 A cross-sectional view of some embodiments of an integrated chip in which a transistor is arranged between a pass transistor and a semiconductor capacitor.

[0018] Fig.11A and Fig. 11B Shows Fig. 9 and / or Fig.10 Circuit diagrams of some embodiments of an integrated chip.

[0019] Fig.12 Shows Fig. 9 Cross-sectional views of some other embodiments of integrated chips.

[0020] Fig.13 Shows Fig.10 Cross-sectional views of some other embodiments of integrated chips.

[0021] Fig.14 Shows Figure 1 Cross-sectional views of some embodiments of an integrated chip wherein the semiconductor capacitor is a capacitor and a transistor.

[0022] Fig.15 Shows Figure 3 Cross-sectional views of some embodiments of an integrated chip wherein the semiconductor capacitor is a capacitor and a transistor.

[0023] Fig.16A Shows Fig.14 and / or Fig.15 Circuit diagrams of some embodiments of an integrated chip.

[0024] Fig. 16B Shows Fig.16A and Fig. 11B Circuit diagrams of some other embodiments of circuits.

[0025] Figure 17-Figure 31 Cross-sectional views of some embodiments of methods for forming an integrated chip including a pixel along a semiconductor substrate and a semiconductor capacitor along the pixel are shown.

[0026] Fig.32 A flow chart of some embodiments of a method for forming an integrated chip including a pixel along a semiconductor substrate and a semiconductor capacitor along the pixel is shown. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. The following describes specific examples of components and arrangements to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse component numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0028] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature illustrated in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0029] An integrated chip includes an image sensor. The image sensor includes a pixel along a semiconductor substrate. The pixel includes a photodetector in the substrate. The pixel also includes a semiconductor capacitor arranged along the substrate. For example, the substrate includes a bulk region having a first doping type and a capacitor injection region having a second doping type. A first capacitor electrode is located above the capacitor injection region, and a first insulator layer is directly between the first capacitor electrode and the capacitor injection region. The first capacitor electrode forms a first electrode of the semiconductor capacitor, and the capacitor injection region forms a second electrode of the semiconductor capacitor.

[0030] Increasing the capacitance of a semiconductor capacitor can be challenging. For example, increasing the total capacitance of a semiconductor capacitor can be achieved by increasing the lateral area of ​​the semiconductor capacitor. However, increasing the lateral area of ​​the semiconductor capacitor may reduce the available area along the substrate for the photodetector. Reducing the available area of ​​the photodetector may reduce the fill factor of the pixel (e.g., the ratio of the photosensitive area of ​​the pixel to the total area of ​​the pixel).

[0031] In various embodiments of the present invention, the capacitance of the semiconductor capacitor can be increased without reducing the fill factor of the pixel. For example, in some embodiments, the photodetector is embedded in the semiconductor substrate and the semiconductor capacitor is arranged directly above the photodetector. Therefore, the lateral area of ​​the semiconductor capacitor can be increased without reducing the area of ​​the semiconductor photodetector. In this way, the capacitance of the semiconductor capacitor can be increased without reducing the fill factor of the pixel.

[0032] In some embodiments, the first capacitor electrode extends into a trench in the semiconductor substrate. Thus, the area between the first electrode and the second electrode of the semiconductor capacitor increases in the vertical direction without increasing the lateral area of ​​the semiconductor capacitor. In this way, the capacitance of the semiconductor capacitor can be increased without reducing the fill factor of the pixel.

[0033] In some embodiments, the second capacitor electrode is located above the first capacitor electrode and the second insulator layer is directly between the second capacitor electrode and the first capacitor electrode. The capacitor injection region of the substrate is coupled to the second capacitor electrode, so that the second capacitor electrode and the capacitor injection region together form a second electrode of the semiconductor capacitor. By including the second capacitor electrode above the first capacitor electrode and coupling the second capacitor electrode to the capacitor injection region, the area between the first electrode and the second electrode of the semiconductor capacitor can be increased without increasing the lateral area of ​​the semiconductor capacitor. In this way, the capacitance of the semiconductor capacitor can be increased without reducing the fill factor of the pixel.

[0034] Figure 1 A cross-sectional view 100 of some embodiments of an integrated chip including a pixel 102 along a semiconductor substrate 104 and a semiconductor capacitor 128 along the pixel 102 is shown.

[0035] The semiconductor substrate 104 includes a bulk region 108 and a photodiode implant region 110. The bulk region 108 has a first doping type (e.g., p-type doping) and the photodiode implant region 110 has a second doping type different from the first doping type (e.g., n-type doping). The photodetector 106 is located in the substrate 104. For example, the photodetector 106 is formed by a pn junction between the photodiode implant region 110 of the substrate 104 and the bulk region 108 of the substrate 104. In some embodiments, the photodiode implant region 110 is buried in the substrate 104 (e.g., disposed below the first side 104a of the substrate 104). Although the region 108 is referred to as a bulk region, in some embodiments, the region 108 may alternatively be referred to as a well implant region having a first doping type.

[0036] The deep trench isolation layer 112 extends into the substrate 104 and surrounds the photodetector 106 along the boundary of the pixel 102. The deep trench isolation layer 112 isolates (eg, electrically and / or optically) the pixel 102 from adjacent pixels (not shown).

[0037] The first gate 114 is located on the first side 104a of the substrate 104. In some embodiments, the first gate 114 extends from the first side 104a of the substrate 104 into the substrate 104 and to the photodiode implant region 110 of the substrate 104. A first insulator layer 116 (eg, a gate dielectric layer) is directly between the first gate 114 and the substrate 104.

[0038] The substrate 104 also includes a first floating diffusion region 118 having a second doping type. The first floating diffusion region 118 is arranged along the first side 104a of the substrate 104 and is laterally spaced apart from the first gate 114. The bulk region 108 of the substrate 104 extends between the photodiode implant region 110 and the first floating diffusion region 118. In some embodiments, the first floating diffusion region 118 is located directly above the photodiode implant region 110.

[0039] The photodiode implant region 110, the first floating diffusion region 118, the bulk region 108, the first gate 114, and the first insulator layer 116 form a transfer transistor 120. For example, the photodiode implant region 110 forms a first source / drain region, the first floating diffusion region 118 forms a second source / drain region, the bulk region 108 forms a channel region, the first gate 114 forms a transfer gate, and the first insulator layer 116 forms a gate dielectric layer. Depending on the context, the source / drain regions may be referred to individually or collectively as a source or a drain.

[0040] The color filter 122 and the microlens 124 are arranged along a second side 104b of the substrate 104 opposite the first side 104a. Photons (not shown) may pass through the microlens 124 and the color filter 122 and impinge on the photodetector 106.

[0041] The substrate 104 further includes a capacitor implant region 125 along the first side 104a of the substrate 104. The capacitor implant region 125 has the second doping type. In some embodiments, the capacitor implant region 125 is adjacent to the first floating diffusion region 118.

[0042] The first capacitor electrode 126 is located directly above the capacitor implant region 125 of the substrate 104. The first insulator layer 116 is directly between the first capacitor electrode 126 and the capacitor implant region 125 of the substrate 104. The first capacitor electrode 126, the capacitor implant region 125, and the first insulator layer 116 form a semiconductor capacitor 128. For example, the first capacitor electrode 126 forms a first electrode (e.g., Figure 2 The capacitor injection region 125 forms a second electrode of the semiconductor capacitor 128 (eg, Figure 2 The second electrode 204 is formed, and the first insulator layer 116 forms an insulator between the first electrode and the second electrode of the semiconductor capacitor 128.

[0043] The shallow trench isolation layer 132 is located on opposite sides of the capacitor implant region 125. In some embodiments, the shallow trench isolation layer 132 surrounds the capacitor implant region 125 to isolate the capacitor implant region 125 (eg, the second electrode of the semiconductor capacitor 128) from adjacent elements.

[0044] The dielectric structure 140 is located on the first side 104a of the substrate 104. The dielectric structure 140 includes a plurality of dielectric layers (not shown). The conductive contacts 144, 146, 148 and the conductive lines 150, 152 are disposed within the dielectric structure 140.

[0045] In some embodiments, the first capacitor electrode 126 (e.g., the first electrode of the semiconductor capacitor 128) is coupled to a bias voltage supply 154. For example, in some embodiments, the conductive contact 146 is coupled to the first capacitor electrode 126, the wire 152 is coupled to the conductive contact 146, and the wire 152 is coupled to the bias voltage supply 154.

[0046] The capacitor injection region 125 (e.g., the second electrode of the semiconductor capacitor 128) is selectively coupled to the first floating diffusion region 118. For example, by controlling the bias voltage applied to the first capacitor electrode 126, the capacitor injection region 125 (e.g., the second electrode of the semiconductor capacitor 128) can be selectively coupled to the first floating diffusion region 118.

[0047] In some embodiments, the semiconductor capacitor 128 is located directly above the photodetector 106 (e.g., directly above the photodiode implant region 110). Therefore, the lateral area of ​​the semiconductor capacitor 128 can be increased without reducing the area of ​​the photodetector 106. Therefore, the total capacitance of the semiconductor capacitor 128 can be increased without reducing the fill factor of the semiconductor pixel 102. In this embodiment, the substrate 104 further includes an isolation implant region 111 directly between the photodiode implant region 110 and the capacitor implant region 125 to isolate the photodiode implant region 110 from the capacitor implant region 125. The isolation implant region 111 has a first doping type.

[0048] In some embodiments, the first capacitor electrode 126 extends to one or more capacitor trenches 134 in the semiconductor substrate 104. For example, the first capacitor electrode 126 extends between the sidewalls of the substrate 104 defining the trenches 134 in the substrate 104 and below the first side 104a of the substrate 104. The first insulator layer 116 extends between the first capacitor electrode 126 and the sidewalls and upper surface of the substrate 104 defining the capacitor trenches 134. Thus, the area between the first capacitor electrode 126 and the capacitor implant region 125 (e.g., the area between the first electrode and the second electrode of the semiconductor capacitor 128) is increased in the vertical direction without increasing the lateral area (e.g., width) of the semiconductor capacitor 128. Thus, the capacitance of the semiconductor capacitor 128 can be increased without reducing the area of ​​the photodetector 106 and, therefore, the fill factor of the pixel 102. In some such embodiments, because the vertical area between the electrodes of the semiconductor capacitor 128 is increased, the lateral area of ​​the semiconductor capacitor 128 can even be reduced, so that the area of ​​the photodetector 106 (and therefore the fill factor of the pixel 102) can be increased without reducing the capacitance of the semiconductor capacitor 128.

[0049] In some embodiments, the capacitor implant region 125 extends along the sidewalls and upper surface of the substrate 104 that define the capacitor trench 134. In some other embodiments, the substrate 104 further includes a protection implant region 127 that extends along the sidewalls and upper surface of the substrate 104 that define the capacitor trench 134 (between the capacitor implant region 125 and the sidewalls and upper surface of the substrate 104 that define the capacitor trench 134). In some embodiments, the protection implant region 127 has a first doping type. The protection implant region 127 can isolate (e.g., protect) the capacitor implant region 125 from damage along the sidewalls and upper surface of the substrate 104 that define the capacitor trench 134.

[0050] In some embodiments, the depth of the capacitor trench 134 (e.g., the distance between the first side 104a of the substrate 104 and the upper surface of the substrate 104 defining the bottom of the trench 134) is approximately equal to or less than the depth of the shallow trench isolation layer 132 (e.g., the distance between the first side 104a of the substrate 104 and the bottom surface of the shallow trench isolation layer 132). Therefore, the bottom surface of the first capacitor electrode 126 is located above the bottom surface of the shallow trench isolation layer 132.

[0051] In some embodiments, the second capacitor electrode 136 is located above the first capacitor electrode 126 and the second insulator layer 138 is directly between the second capacitor electrode 136 and the first capacitor electrode 126. The second capacitor electrode 136 is coupled to the capacitor implant region 125 (e.g., the second electrode of the semiconductor capacitor 128). For example, the conductive contact 148 is coupled to the second capacitor electrode 136 and the conductive line 150. Therefore, the second capacitor electrode 136 further forms the second electrode of the semiconductor capacitor 128 (e.g., Figure 2 By including the second capacitor electrode 136 above the first capacitor electrode 126 and coupling the second capacitor electrode 136 to the capacitor injection region 125, the area between the first electrode and the second electrode of the semiconductor capacitor 128 can be increased without increasing the lateral area (e.g., width) of the semiconductor capacitor 128. For example, the area between the second capacitor electrode 136 and the first capacitor electrode 126 increases the total area between the first electrode and the second electrode of the semiconductor capacitor 128. Therefore, the capacitance of the semiconductor capacitor 128 can be increased without reducing the area of ​​the photodetector 106 and thus the fill factor of the pixel 102. In some such embodiments, the lateral area of ​​the semiconductor capacitor 128 can even be reduced, so that the area of ​​the photodetector 106 can be increased (and thus the fill factor of the pixel 102 can be increased) without reducing the capacitance of the semiconductor capacitor 128.

[0052] In some embodiments, the semiconductor substrate 104 includes silicon, germanium, silicon germanium, gallium arsenide, or some other suitable material. In some embodiments, the shallow trench isolation layer 132, the deep trench isolation layer 112, and the dielectric layer of the dielectric structure 140 include silicon dioxide, silicon nitride, or some other suitable material. In some embodiments, the conductive contacts 144, 146, 148 and the conductive interconnects 150, 152 include copper, tungsten, aluminum, or some other suitable material. In some embodiments, the first insulator layer 116 and the second insulator layer 138 include silicon dioxide, silicon nitride, some high-k dielectric (e.g., a dielectric with a greater dielectric constant than silicon dioxide), or some other suitable material. In some embodiments, the first gate 114, the first capacitor electrode 126, and the second capacitor electrode 136 include polysilicon or some other suitable material.

[0053] Figure 2 Shows Figure 1 Circuit diagram 200 of some embodiments of an integrated chip.

[0054] The transfer transistor 120 selectively couples the photodetector 106 to the first floating diffusion region 118. The first electrode 202 of the semiconductor capacitor 128 is coupled to the bias power supply 154. The second electrode 204 of the semiconductor capacitor 128 is coupled to the first floating diffusion region 118. An additional circuit 206 is coupled to the first floating diffusion region 118. In some embodiments, the additional circuit 206 includes an additional transistor such as a pixel transistor (e.g., a reset transistor, a source follower transistor, a select transistor, etc.), an additional capacitor, or some other suitable circuit.

[0055] Figure 3 A cross-sectional view 300 of some other embodiments of an integrated chip including a pixel 102 along a semiconductor substrate 104 and a semiconductor capacitor 128 along the pixel 102 is shown.

[0056] In some embodiments, the photodiode implant region 110 is arranged along the first side 104a of the substrate 104 and does not extend directly under the semiconductor capacitor 128. In addition, the bottom surface of the first gate 114 is located above the first side 104a of the substrate 104 and is spaced apart from the first side 104a of the substrate 104.

[0057] In some embodiments, the depth of the capacitor trench 134 is greater than the depth of the shallow trench isolation layer 132. Therefore, the bottom surface of the first capacitor electrode 126 is lower than the bottom surface of the shallow trench isolation layer 132. By increasing the depth of the capacitor trench 134, the area between the capacitor injection region 125 (e.g., the second electrode of the semiconductor capacitor 128) and the first capacitor electrode 126 (e.g., the first electrode of the semiconductor capacitor 128) can be further increased, so the capacitance of the semiconductor capacitor 128 can be further increased without increasing the lateral area of ​​the semiconductor capacitor 128.

[0058] Figure 4 A cross-sectional view 400 showing various other embodiments of an integrated chip and Figure 5 A cross-sectional view 500 of an integrated chip including a pixel 102 along a semiconductor substrate 104 and a semiconductor capacitor 128 along the pixel 102 is shown.

[0059] In some embodiments, semiconductor capacitor 128 does not have a second insulator layer (eg, Figure 1 and Figure 3 a second insulator layer 138 and a second capacitor electrode (eg, Figure 1 and Figure 3 The dielectric structure 140 (eg, a dielectric layer of the dielectric structure 140 ) covers a top surface of the first capacitor electrode 126 .

[0060] In some embodiments, the substrate 104 further includes another implant region 402 along the first side 104a of the substrate 104 and adjacent to the capacitor implant region 125. The implant region 402 has a second doping type. In some embodiments, the shallow trench isolation layer 132 is directly between the implant region 402 and the first floating diffusion region 118.

[0061] The implant region 402 is coupled to the first floating diffusion region 118. For example, the conductive contact 404 is located on the implant region 402 and is coupled to the implant region 402. In addition, the contact 144 and the contact 404 are coupled together through the conductive line 150.

[0062] Figure 6 Shows Figure 4 and Figure 5 A top view 600 of some embodiments of the first capacitor electrode 126 is shown.

[0063] The first capacitor electrode 126 has a lateral area (e.g., a planar area) extending above the first side 104a of the substrate 104. The first capacitor electrode 126 also has one or more vertical areas extending from the lateral area to below the first side 104a of the substrate 104 and into the capacitor trench 134. In some embodiments, the capacitor trench 134 and the vertical areas of the first capacitor electrode 126 have an elongated trench shape, as shown by the dashed line 602. In some other embodiments, the capacitor trench 134 and the vertical areas of the first capacitor electrode 126 have a square-like shape, as shown by the dashed line 604. In some other embodiments, the capacitor trench 134 and the vertical areas of the first capacitor electrode 126 have a circular shape, as shown by the dashed line 606.

[0064] Figure 7 A cross-sectional view 700 is shown and Figure 8 A cross-sectional view 800 of various other embodiments of an integrated chip including a pixel 102 along a semiconductor substrate 104 and a semiconductor capacitor 128 along the pixel 102 is shown.

[0065] In some embodiments, the first capacitor electrode 126 does not extend below the first side 104a of the substrate 104. For example, a bottommost surface of the first capacitor electrode 126 is above and spaced apart from the first side 104a of the substrate 104. In some embodiments, the bottommost surface of the first capacitor electrode 126 is substantially flat between the outermost sidewalls of the first capacitor electrode 126.

[0066] The first gate 114 and the first floating diffusion region 118 are not shown. Figure 8 Because in some embodiments, the transfer gate and the first floating diffusion region 118 are spaced apart from the semiconductor capacitor 128 (eg, in a direction into the page).

[0067] Fig. 9 and Fig.10 They are Figure 1 and Figure 3 Cross-sectional views 900 and 1000 of some embodiments of an integrated chip of the present invention are shown, wherein transistor 906 is disposed between pass transistor 120 and semiconductor capacitor 128 .

[0068] The second gate 902 is located on the first side 104a of the substrate 104 and is laterally spaced apart from the first gate 114. The first insulator layer 116 is directly between the second gate 902 and the substrate 104.

[0069] The substrate 104 also includes a second floating diffusion region 904 along the first side 104a of the substrate 104 and laterally spaced apart from the first floating diffusion region 118. The second floating diffusion region 904 has a second doping type. The second gate 902 is interposed between the first floating diffusion region 118 and the second floating diffusion region 904. The contact 144 is located on the second floating diffusion region 904 and couples the second electrode (e.g., capacitor injection region 125) of the semiconductor capacitor 128 to the second floating diffusion region 904.

[0070] The first floating diffusion region 118, the second floating diffusion region 904, the bulk region 108, the second gate 902, and the first insulator layer 116 form a transistor 906. For example, the first floating diffusion region 118 forms a first source / drain region, the second floating diffusion region 904 forms a second source / drain region, the bulk region 108 forms a channel region, the second gate 902 forms a capacitor gate, and the first insulator layer 116 forms a gate dielectric layer.

[0071] The third gate 908 is located over the first side 104a of the substrate 104 and is laterally spaced apart from the second gate 902. The first insulator layer 116 is directly between the third gate 908 and the substrate 104.

[0072] The substrate 104 further includes another implant region 910 along the first side 104a of the substrate 104 and laterally spaced apart from the second floating diffusion region 904. The implant region 910 has a second doping type. The third gate 908 is located between the second floating diffusion region 904 and the implant region 910. In some embodiments, the implant region 910 is coupled to a voltage source (e.g., Fig.11A voltage power supply 1108).

[0073] The second floating diffusion region 904, the implant region 910, the bulk region 108, the third gate 908, and the first insulator layer 116 form a first pixel transistor 912 (e.g., a reset transistor). For example, the second floating diffusion region 904 forms a first source / drain region, the implant region 910 forms a second source / drain region, the bulk region 108 forms a channel region, the third gate 908 forms a gate, and the first insulator layer 116 forms a gate dielectric layer.

[0074] In some embodiments, the substrate 104 further includes a body implant region (not shown) for biasing the bulk region 108. The body implant region has a first doping type. In some embodiments, the body implant region is coupled to ground.

[0075] In some embodiments, additional pixel transistors (not shown) are disposed along substrate 104. For example, a source follower transistor (e.g., Fig.11A and Fig. 11B 1102) and a selection transistor (eg, Fig.11A and Fig. 11B 1104) is disposed along the substrate 104. In some embodiments, the second semiconductor capacitor (eg, Fig.11A and 11B The second semiconductor capacitor 1110) is arranged along the substrate 104.

[0076] Fig.11A Shows Fig. 9 and / or Fig.10 Circuit diagram 1100a of some embodiments of an integrated chip. Fig. 11B Shows Fig. 9 and / or Fig.10 Circuit diagram 1100b of some other embodiments of the integrated chip.

[0077] 1. Transistor 906 selectively couples second floating diffusion region 904 and second electrode 204 of semiconductor capacitor 128 to first floating diffusion region 118. A gate of a second pixel transistor 1102 (e.g., a source follower transistor) is coupled to first floating diffusion region 118. A third pixel transistor 1104 (e.g., a select transistor) is coupled to second pixel transistor 1102. In some embodiments, second semiconductor capacitor 1110 is coupled to first floating diffusion region 118. In some embodiments, additional circuitry 1106 (e.g., an application specific integrated circuit (ASIC), etc.) is coupled to third pixel transistor 1104.

[0078] In some embodiments (e.g., Fig.11A ), the first pixel transistor 912 selectively couples the second floating diffusion region 904 to the voltage source 1108. In some embodiments (e.g., as Fig. 11BAs shown in FIG. 1 , the integrated chip further includes a third floating diffusion region 1112, a transistor 1114, and a third semiconductor capacitor 1116. The injection region 910 and an electrode of the third semiconductor capacitor 1116 are coupled to the third floating diffusion region 1112. The transistor 1114 selectively couples the third floating diffusion region 1112 to the voltage source 1108.

[0079] In some embodiments, the circuit may be referred to as a multiple conversion gain (MCG) circuit, a dual conversion gain (DCG) circuit, or a lateral overflow integrated capacitor (LOFIC) circuit, or a combination of the foregoing. The second gate 902 may be referred to as a DCG gate, an MCG gate, or a LOBIC gate. The semiconductor capacitor 128 may be referred to as a DCG capacitor, an MCG capacitor, or a LOBIC capacitor. In some embodiments, the semiconductor capacitor 128 may be used to adjust the gain in the MCG or DCG circuit. In some other embodiments, the semiconductor capacitor 128 may be used as a voltage domain storage in the LOBIC circuit.

[0080] Fig.12 They are shown respectively Fig. 9 and Fig.10 The cross-sectional view 1200 and the cross-sectional view 1300 of some embodiments of the integrated chip, wherein the first capacitor electrode 126 is disposed directly above the second floating diffusion region 904 .

[0081] The second floating diffusion region 904 and the second capacitor electrode 136 form a second electrode of the semiconductor capacitor 128. The first capacitor electrode 126 is located directly between the second gate 902 and the third gate 908. The contact 144 is coupled to the second floating diffusion region 904 in addition to the first capacitor electrode 126.

[0082] Fig.14 and Fig.15 They are Figure 1 and Figure 3 Cross-sectional view 1400 and cross-sectional view 1500 of some embodiments of an integrated chip, wherein semiconductor capacitor 128 is a capacitor and a transistor. Fig.16A Shows Fig.14 and / or Fig.15 Circuit diagram 1600a of some embodiments of an integrated chip.

[0083] The substrate 104 includes another implant region 1402 along the first side 104a of the substrate 104 and adjacent to the capacitor implant region 125. The first capacitor electrode 126 forms a gate, the first insulator layer 116 forms a gate dielectric, the first floating diffusion region 118 forms a first source / drain, the implant region 1402 forms a second source / drain, and the capacitor implant region 125 forms a channel. By controlling the bias voltage at the first capacitor electrode 126, the first floating diffusion region 118 can be selectively coupled to the implant region 1402 through the capacitor implant region 125.

[0084] In some embodiments, semiconductor capacitor / transistor 128 is coupled between first floating diffusion region 118 and second floating diffusion region 904. For example, implant region 1402 is coupled to second floating diffusion region 904. Furthermore, capacitor 1602 is coupled to implant region 1402 and second floating diffusion region 904.

[0085] Fig. 16B Shows Fig.16A and Fig. 11B Circuit diagram 1600b of some other embodiments of the circuit.

[0086] Transistor 906 is coupled between first floating diffusion 118 and second floating diffusion 904. Capacitor 1602 is coupled to second floating diffusion 904. Semiconductor capacitor / transistor 128 is coupled between second floating diffusion 904 and third floating diffusion 1112. Capacitor 1116 is coupled to third floating diffusion 1112. Transistor 1114 is coupled between third floating diffusion 1112 and voltage supply 1108.

[0087] Figure 17-Figure 31 Cross-sectional views 1700-3100 of some embodiments of a method for forming an integrated chip including a pixel 102 along a semiconductor substrate 104 and a semiconductor capacitor 128 along the pixel 102 are shown. Figure 17-Figure 31 is described relative to a method, but it should be understood that Figure 17-Figure 31 The structure disclosed in is not limited to this method, but can exist independently as a structure independent of the method.

[0088] like Fig.17 As shown in cross-sectional view 1700 of , a photodetector 106 is formed in a semiconductor substrate 104. For example, the substrate 104 includes a bulk region 108 having a first doping type (e.g., p-type). A photodiode implant region 110 having a second doping type (e.g., n-type) different from the first doping type is formed in the substrate 104. The photodetector 106 is formed by a pn junction between the photodiode implant region 110 and the bulk region 108. In some embodiments, the bulk region 108 may alternatively be referred to as a well implant region.

[0089] In some embodiments, the photodiode implant region 110 is formed below the first side 104a of the substrate 104. In some other embodiments (e.g., Figure 3 ), a photodiode implant region 110 is formed along the first side 104a of the substrate 104. In some embodiments, an isolation implant region 111 having a first doping type is formed on the photodiode implant region 110.

[0090] In some embodiments, the implanted regions 110 and 111 are formed by an ion implantation process or some other suitable process. In some embodiments, the semiconductor substrate 104 includes silicon, germanium, silicon germanium, gallium arsenide, or some other suitable material.

[0091] like Fig.18 As shown in the cross-sectional view 1800 of , the substrate 104 is etched to form one or more shallow trenches 1802 in the substrate 104 along the first side 104a of the substrate 104. In some embodiments, a mask layer 1804 is formed on the first side 104a of the substrate 104, and etching is performed according to the mask layer 1804. In some embodiments, the mask layer 1804 includes a photoresist layer, a hard mask layer, or some other suitable layer. In some embodiments, the mask layer 1804 is removed during and / or after etching. In some embodiments, the etching includes a dry etching process (e.g., a plasma etching process, a reactive ion etching process, an ion beam etching process, etc.) or some other suitable process.

[0092] like Fig.19 As shown in the cross-sectional view 1900 of FIG. 1 , a shallow trench isolation layer 132 is deposited in the shallow trench (eg, Fig.18 1802). In some embodiments, the shallow trench isolation layer 132 includes silicon dioxide, silicon nitride, or some other suitable material. In some embodiments, the shallow trench isolation layer 132 is deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable process. In some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP) or some other suitable process) is subsequently performed on the shallow trench isolation layer 132 to remove the shallow trench isolation layer 132 from above the first side 104a of the substrate 104.

[0093] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 1 , a capacitor implant region 125 having a second doping type is formed along the first side 104a of the substrate 104. In some embodiments, the capacitor implant region 125 is formed by an ion implantation process or some other suitable process.

[0094] like Fig.21As shown in the cross-sectional view 2100 of FIG. 1 , in some embodiments, the substrate 104 is etched to form one or more capacitor trenches 134 in the capacitor implant region 125 of the substrate 104. In some embodiments, a mask layer 2102 is formed on the first side 104a of the substrate 104, and etching is performed according to the mask layer 2102. In some embodiments, etching includes a dry etching process or some other suitable process.

[0095] In some embodiments, the depth of the capacitor trench 134 (e.g., the distance between the first side 104a of the substrate 104 and the bottom of the capacitor trench 134) is approximately equal to or less than the depth of the shallow trench isolation layer 132. In other words, the upper surface of the substrate 104 that defines the bottom of the capacitor trench 134 is located above or at the same depth as the bottommost surface of the shallow trench isolation layer 132. In some other embodiments, the depth of the capacitor trench 134 is greater than the depth of the shallow trench isolation layer 132. In other words, the upper surface of the substrate 104 that defines the bottom of the capacitor trench 134 is located below the bottommost surface of the shallow trench isolation layer 132.

[0096] In some cases, the etching causes damage (e.g., creates defects) along the surface (e.g., sidewalls and upper surface) of the substrate 104 that defines the capacitor trench 134. Therefore, in some embodiments, a protective layer implant region 127 having a first doping type is formed in the capacitor implant region 125 along the capacitor trench 134. The protective implant region 127 can isolate (e.g., protect) the capacitor implant region 125 from the damaged surface to reduce negative effects that may be caused by the damaged surface. In some embodiments, the protective implant region 127 is formed by an ion implantation process or some other suitable process.

[0097] like Fig. 22 As shown in the cross-sectional view 2200 of , the first insulator layer 116 is deposited on the first side 104a of the substrate 104, so that the first insulator layer 116 lines the capacitor trench 134 and the first side 104a of the substrate 104. In some embodiments, the first insulator layer 116 includes silicon dioxide, silicon nitride, some high-k dielectric (e.g., some dielectric with a greater dielectric constant than silicon dioxide), or some other suitable material. In some embodiments, the first insulator layer 116 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0098] like Fig.23 As shown in the cross-sectional view 2300 of FIG. 1 , a first semiconductor layer 2302 is deposited on the first side 104a of the substrate 104 so that the first semiconductor layer 2302 fills the capacitor trench (eg, Fig. 22In some embodiments, the first semiconductor layer 2302 includes polysilicon or some other suitable material. In some embodiments, the first semiconductor layer 2302 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0099] In some embodiments, the second insulator layer 138 is deposited on the first semiconductor layer 2302 and the second semiconductor layer 2304 is deposited on the second insulator layer 138. In some embodiments, the second insulator layer 138 includes silicon dioxide, silicon nitride, some high-k dielectric, or some other suitable material. In some embodiments, the second semiconductor layer 2304 includes polysilicon or some other suitable material. In some embodiments, the second insulator layer 138 and / or the second semiconductor layer 2304 are deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0100] like Fig.24 As shown in the cross-sectional view 2400 of FIG. 24 , the first semiconductor layer 2302, the second insulator layer 138, and the second semiconductor layer 2304 are patterned. The patterning forms the first capacitor electrode 126 from the first semiconductor layer 2302 and the second capacitor electrode 136 from the second semiconductor layer 2304. The second capacitor electrode 136, the second insulator layer 138, the first capacitor electrode 126, the first insulator layer 116, and the capacitor injection region 125 form a semiconductor capacitor 128.

[0101] In some embodiments, a mask layer 2402 is formed on the second semiconductor layer 2304, and etching is performed according to the mask layer 2402. In some embodiments, the etching includes a dry etching process or some other suitable process.

[0102] like Fig.25 As shown in the cross-sectional view 2500 of , the second capacitor electrode 136 is patterned to remove the second capacitor electrode 136 from a portion of the second insulator layer 138 and a portion of the first capacitor electrode 126. In some embodiments, a mask layer 2502 is formed on the second capacitor electrode 136 and etching is performed according to the mask layer 2502. In some embodiments, the etching includes a dry etching process or some other suitable process.

[0103] like Fig.26 As shown in the cross-sectional view 2600 of FIG. 1 , an implantation region 402 having a second doping type is formed in the substrate 104, wherein the implantation region 402 is along the first side 104a of the substrate 104 and adjacent to the capacitor implantation region 125. In some embodiments, the implantation region 402 is formed by an ion implantation process or some other suitable process. In some embodiments, another implantation region (e.g., Fig.14 and Fig.15An implant region 1402) is formed in the substrate 104 to be adjacent to the capacitor implant region 125 on an opposite side of the capacitor implant region 125.

[0104] like Fig. 27 As shown in the cross-sectional view 2700 of , a dielectric structure 140 including one or more dielectric layers is deposited on the first side 104a of the substrate 104. In some embodiments, the one or more dielectric layers of the dielectric structure 140 include silicon dioxide, silicon nitride, or some other suitable material. In some embodiments, the dielectric structure 140 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0105] like Fig.28 As shown in cross-sectional view 2800 of , a plurality of conductive interconnects (e.g., contacts 144, 146, 148 and lines 150, 152) are formed within dielectric structure 140. In some embodiments, the interconnects (e.g., contacts 144, 146, 148 and lines 150, 152) are formed by etching a dielectric layer of dielectric structure 140 and depositing copper, tungsten, aluminum, or some other suitable material on the etched dielectric layer by one or more CVD processes, PVD processes, ALD processes, or some other suitable processes.

[0106] like Fig.29 As shown in the cross-sectional view 2900 of FIG. 1 , a second side 104b of the substrate 104 opposite to the first side 104a is etched to form a deep trench 2902 surrounding the photodetector 106. The deep trench 2902 establishes a boundary of the pixel 102. In some embodiments, the deep trench 2902 extends through the substrate 104 from the second side 104b to the first side 104a. In some other embodiments, the deep trench 2902 extends into the substrate 104 but does not reach the first side 104a. In some embodiments, a mask layer 2904 is formed on the second side 104b of the substrate 104 and etching is performed based on the mask layer 2904. In some embodiments, the etching includes a dry etching process or some other suitable process.

[0107] like Fig.30 As shown in the cross-sectional view 3000 of FIG. 1 , the deep trench isolation layer 112 is deposited on the second side 104 b of the substrate 104 so that the deep trench isolation layer 112 fills the deep trench (eg, Fig.29 2902). In some embodiments, the deep trench isolation layer 112 includes silicon dioxide, silicon nitride, or some other suitable material. In some embodiments, the deep trench isolation layer 112 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0108] In some embodiments, a planarization process (e.g., CMP or some other suitable process) is subsequently performed on the deep trench isolation layer 112 to remove the deep trench isolation layer 112 from above the second side 104b of the substrate 104. In some other embodiments (not shown), the deep trench isolation layer 112 covers the second side 104b of the substrate 104.

[0109] like Fig.31 As shown in the cross-sectional view 3100 of , a color filter 122 and a microlens 124 are formed on the second side 104 b of the substrate 104 .

[0110] Fig.32 A flow chart of some embodiments of a method 3200 for forming an integrated chip including pixels along a semiconductor substrate and semiconductor capacitors along the pixels is shown. Although method 3200 is shown and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be interpreted as limiting. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, all of the illustrated actions may not be required to implement one or more aspects or embodiments described herein. In addition, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0111] At block 3202, a photodetector is formed in a semiconductor substrate. Fig.17 A cross-sectional view 1700 corresponding to some embodiments of block 3202 is shown.

[0112] At block 3204, a shallow trench isolation layer extending into the substrate is formed. Fig.18 and Fig.19 Cross-sectional view 1800 and cross-sectional view 1900 are shown corresponding to some embodiments of block 3204 .

[0113] At block 3206 , a capacitor implant region is formed in the substrate between sidewalls of the shallow trench isolation layer. Fig. 20 A cross-sectional view 2000 corresponding to some embodiments of block 3206 is shown.

[0114] At block 3208, the substrate is etched to form one or more trenches in the capacitor implant region of the substrate. Fig.21 A cross-sectional view 2100 corresponding to some embodiments of block 3208 is shown.

[0115] At block 3210, a first insulator layer is deposited over the substrate and in the trenches. Fig. 22 A cross-sectional view 2200 corresponding to some embodiments of block 3210 is shown.

[0116] At block 3212, a first semiconductor layer is deposited over the first insulator layer and in the trench. Fig.23 A cross-sectional view 2300 corresponding to some embodiments of block 3212 is shown.

[0117] At block 3214, a second insulator layer is deposited over the first semiconductor layer. Fig.23 A cross-sectional view 2300 corresponding to some embodiments of block 3214 is shown.

[0118] At block 3216, a second semiconductor layer is deposited over the second insulator layer. Fig.23 A cross-sectional view 2300 corresponding to some embodiments of block 3216 is shown.

[0119] At block 3218, the first semiconductor layer is patterned to form a first capacitor electrode from the first semiconductor layer. Fig.24 A cross-sectional view 2400 corresponding to some embodiments of block 3218 is shown.

[0120] At block 3220 , the second semiconductor layer is patterned to form a second capacitor electrode from the second semiconductor layer. Fig.25 A cross-sectional view 2500 corresponding to some embodiments of block 3220 is shown.

[0121] At block 3222, a deep trench isolation layer is formed surrounding the photodetector. Fig.29 and Fig.30 Cross-sectional view 2900 and cross-sectional view 3000 are shown corresponding to some embodiments of block 3222 .

[0122] At block 3224, color filters and microlenses are formed along the substrate. Fig.31 A cross-sectional view 3100 corresponding to some embodiments of block 3224 is shown.

[0123] Therefore, the present invention relates to an integrated chip and a method of forming the integrated chip, the integrated chip including a semiconductor capacitor with increased capacitance.

[0124] Therefore, in some embodiments, the utility model relates to an integrated chip, including a semiconductor substrate, the semiconductor substrate including a first region having a first doping type, a second region having a second doping type different from the first doping type, and a third region having the second doping type. A photodetector is located in the semiconductor substrate. The photodetector is at least partially formed by the first region and the second region. A first capacitor electrode is located above the third region of the semiconductor substrate. The first capacitor electrode includes a semiconductor. A first insulator layer is located between the first capacitor electrode and the third region. The capacitor is along the semiconductor substrate. The capacitor is at least partially formed by the first capacitor electrode, the third region, and the first insulator layer. The capacitor extends directly above the photodetector.

[0125] In some embodiments, the first capacitor electrode forms a first electrode of the capacitor, and wherein the third region forms a second electrode of the capacitor. In some embodiments, the integrated chip further comprises: a second capacitor electrode located above the first capacitor electrode; and a second insulator layer located between the first capacitor electrode and the second capacitor electrode, wherein the capacitor is further formed by the second capacitor electrode and the second insulator layer. In some embodiments, the first capacitor electrode forms a first electrode of the capacitor, wherein the second capacitor electrode is coupled to the third region, and wherein the second capacitor electrode and the third region form a second electrode of the capacitor. In some embodiments, the sidewalls of the semiconductor substrate define a trench in the third region of the semiconductor substrate, and wherein the first capacitor electrode and the first insulator layer extend below the top surface of the semiconductor substrate and between the sidewalls of the semiconductor substrate. In some embodiments, the photodetector is buried in the semiconductor substrate below the first side of the semiconductor substrate, and wherein the capacitor is arranged along the first side of the semiconductor substrate. In some embodiments, the sidewalls of the semiconductor substrate define a trench in the third region of the semiconductor substrate, and wherein the first capacitor electrode and the first insulator layer extend below the top surface of the semiconductor substrate and between the sidewalls of the semiconductor substrate. In some embodiments, the semiconductor substrate further includes a fourth region having the first doping type, the fourth region extending along the sidewall of the semiconductor substrate between the sidewall of the semiconductor substrate and the third region. In some embodiments, the semiconductor substrate further includes a fourth region adjacent to the third region, the fourth region having the second doping type. In some embodiments, the semiconductor substrate further includes a fifth region adjacent to the third region, the fifth region having the second doping type, wherein the fourth region and the fifth region are located on opposite sides of the third region, and wherein the fourth region forms a first source / drain of a transistor, the fifth region forms a second source / drain of the transistor, the third region forms a channel of the transistor, and the first capacitor electrode forms a gate of the transistor.

[0126] In other embodiments, the utility model relates to an integrated chip including a semiconductor substrate including a bulk region having a first doping type and a capacitor injection region having a second doping type different from the first doping type. A photodetector is located in the semiconductor substrate. A transfer transistor is arranged along the semiconductor substrate. A first source / drain of the transfer transistor is coupled to the photodetector, and a second source / drain of the transfer transistor is coupled to the capacitor injection region. A first capacitor electrode is located above the capacitor injection region. The first capacitor electrode includes a semiconductor. A first insulator layer is located between the first capacitor electrode and the capacitor injection region. The capacitor is arranged along the semiconductor substrate. The capacitor is at least partially formed by the first capacitor electrode, the capacitor injection region, and the first insulator layer. The semiconductor substrate has a pair of sidewalls that define a trench in the capacitor injection region of the semiconductor substrate. The first capacitor electrode and the first insulator layer extend below the top surface of the semiconductor substrate and between the pair of sidewalls of the semiconductor substrate.

[0127] In other embodiments, the integrated chip further comprises: a second capacitor electrode overlying the first capacitor electrode; and a second insulator layer located between the second capacitor electrode and the first capacitor electrode, wherein the first capacitor electrode forms the first electrode of the capacitor, and wherein the second capacitor electrode and the capacitor injection region form the second electrode of the capacitor. In other embodiments, the semiconductor substrate further comprises a protection injection region having the first doping type, the protection injection region extending along the trench between the pair of sidewalls of the semiconductor substrate and the capacitor injection region. In other embodiments, the photodetector is buried in the semiconductor substrate below the first side of the semiconductor substrate, and wherein the capacitor is arranged along the first side of the semiconductor substrate and extends directly above the photodetector. In other embodiments, the integrated chip further comprises: a shallow trench isolation layer located on the side opposite to the first capacitor electrode in the semiconductor substrate, wherein the bottom surface of the first capacitor electrode is located between the pair of sidewalls of the semiconductor substrate and below the bottom surface of the shallow trench isolation layer. In other embodiments, the integrated chip further comprises: a shallow trench isolation layer located in the semiconductor substrate and on the side opposite to the first capacitor electrode, wherein the bottom surface of the first capacitor electrode is located above the bottom surface of the shallow trench isolation layer.

[0128] In some other embodiments, the utility model relates to a method for forming an integrated chip. The method includes forming a photodetector and a capacitor injection region in a semiconductor substrate. Etching the semiconductor substrate to form a groove in the capacitor injection region of the semiconductor substrate. Depositing a first insulator layer on the semiconductor substrate and in the groove. Depositing a first semiconductor layer on the first insulator layer and in the groove. Depositing a second insulator layer on the first semiconductor layer. Depositing the second semiconductor layer on the second insulator layer. Etching the first semiconductor layer to form a first capacitor electrode from the first semiconductor layer. Etching the second semiconductor layer to form a second capacitor electrode from the second semiconductor layer. The second capacitor electrode is located on the first capacitor electrode. The first capacitor electrode is located on the capacitor injection region and extends into the groove.

[0129] In some further embodiments, the photodetector is formed to be buried in the semiconductor substrate and the first capacitor electrode is formed directly above the photodetector. In some further embodiments, the method further includes: forming a trench isolation layer on the opposite side of the semiconductor substrate from the first capacitor electrode. In some further embodiments, the method further includes: forming a first conductive contact coupled to the capacitor injection region and adjacent to the first capacitor electrode; forming a second conductive contact on the first capacitor electrode; forming a third conductive contact on the second capacitor electrode; forming a first conductive wire on the first conductive contact and the third conductive contact; and forming a second conductive wire on the second conductive contact.

[0130] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present invention, and various modifications, substitutions, and changes can be made to the present invention without departing from the spirit and scope of the present invention.

Claims

1. An integrated chip, characterized in that: include: The semiconductor substrate includes a first region having a first doping type, a second region having a second doping type different from the first doping type, and a third region having the second doping type; A photodetector is located in the semiconductor substrate, and the photodetector is at least partially formed by the first region and the second region; A first capacitor electrode is located on the third region of the semiconductor substrate, the first capacitor electrode comprising a semiconductor; a first insulator layer between the first capacitor electrode and the third region; as well as A capacitor is along the semiconductor substrate, the capacitor is at least partially formed by the first capacitor electrode, the third region, and the first insulator layer, and the capacitor extends directly above the photodetector.

2. The integrated chip according to claim 1, characterized in that: Also includes: a second capacitor electrode disposed on the first capacitor electrode; as well as a second insulator layer is located between the first capacitor electrode and the second capacitor electrode, Wherein the capacitor is further formed by the second capacitor electrode and the second insulator layer.

3. The integrated chip according to claim 1, characterized in that: Sidewalls of the semiconductor substrate define a trench in the third region of the semiconductor substrate, and wherein the first capacitor electrode and the first insulator layer extend below a top surface of the semiconductor substrate and between the sidewalls of the semiconductor substrate.

4. The integrated chip according to claim 3, characterized in that: The semiconductor substrate further includes a fourth region having the first doping type, the fourth region extending along the sidewall of the semiconductor substrate between the sidewall of the semiconductor substrate and the third region.

5. The integrated chip according to claim 1, characterized in that: The semiconductor substrate further includes a fourth region adjacent to the third region, the fourth region having the second doping type.

6. The integrated chip according to claim 5, characterized in that: The semiconductor substrate also includes a fifth region adjacent to the third region, the fifth region having the second doping type, wherein the fourth region and the fifth region are located on opposite sides of the third region, and wherein the fourth region forms a first source / drain of the transistor, the fifth region forms a second source / drain of the transistor, the third region forms a channel of the transistor, and the first capacitor electrode forms a gate of the transistor.

7. An integrated chip, characterized in that: include: A semiconductor substrate including a bulk region having a first doping type and a capacitor implant region having a second doping type different from the first doping type; A photodetector is located in the semiconductor substrate; A transfer transistor is disposed along the semiconductor substrate, wherein a first source / drain of the transfer transistor is coupled to the photodetector, and a second source / drain of the transfer transistor is coupled to the capacitor injection region; a first capacitor electrode located above the capacitor implant region, the first capacitor electrode comprising a semiconductor; as well as a first insulator layer between the first capacitor electrode and the capacitor injection region; as well as a capacitor along the semiconductor substrate, the capacitor being at least partially formed by the first capacitor electrode, the capacitor implant region, and the first insulator layer, wherein the semiconductor substrate has a pair of sidewalls defining a trench in the capacitor implant region of the semiconductor substrate, and wherein the first capacitor electrode and the first insulator layer extend below a top surface of the semiconductor substrate and between the pair of sidewalls of the semiconductor substrate.

8. The integrated chip according to claim 7, characterized in that: Also includes: A second capacitor electrode overlies the first capacitor electrode; as well as a second insulator layer is located between the second capacitor electrode and the first capacitor electrode, The first capacitor electrode forms a first electrode of the capacitor, and the second capacitor electrode and the capacitor injection region form a second electrode of the capacitor.

9. The integrated chip according to claim 7, characterized in that: The semiconductor substrate also includes a protection implant region having the first doping type, the protection implant region extending along the trench between the semiconductor substrate and the pair of sidewalls of the capacitor implant region.

10. The integrated chip according to claim 7, characterized in that: The photodetector is buried in the semiconductor substrate below a first side of the semiconductor substrate, and wherein the capacitor is arranged along the first side of the semiconductor substrate and extends directly above the photodetector.

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