Novel 4K decoding processor

Abstract

The utility model discloses a novel 4K decoding processor comprising a housing, an RJ45 network interface, four HDMI ports, a 4K decoding processing assembly, a video conversion assembly and a video output assembly. The RJ45 network interface and the four HDMI ports are respectively and externally arranged on a panel of the shell; the 4K decoding processing assembly, the video conversion assembly and the video output assembly are all installed in the shell; the RJ45 network interface is internally connected with the 4K decoding processing assembly, and the output end of the 4K decoding processing assembly is connected with the input end of the video conversion assembly; the video conversion assembly outputs to the video output assembly, and four output ends of the video output assembly are respectively connected with the four HDMI ports. The novel 4K decoding processor is compact in structure, different function modules for decoding processing, video conversion and video output are installed in the shell, and cooperation is tight and efficient; the multi-channel high-definition video output device can receive multiple channels of video streams and output multiple channels of high-definition video signals at the same time, the multi-screen display requirement is met, and a more flexible and high-performance video output function is provided.

Description

Technical Field

[0001] The utility model relates to the technical field of video signal processing equipment, and more specifically to a novel 4K decoding processor for decoding and distributing 4K video signals. Background Art

[0002] Currently, 4K decoding processors have made significant progress in processing high-definition video signals, but there are still some limitations. Typically, these decoding processors only have limited HDMI output channels, usually one or two, which limits their application in multi-screen display or video processing. In particular, when it is necessary to decode and output a single 4K network signal or multiple 1080P network signals to multiple independent display devices, the current decoding processors are not competent. In addition, existing decoding processors often lack functions such as image stitching, zooming in, zooming out, and superimposing, which are crucial in the fields of large-screen video display, monitoring systems, conference room equipment, etc.

[0003] Therefore, in view of the limitations of these existing technologies, a new type of 4K decoding processor is urgently needed to solve the above technical problems. Utility Model Content

[0004] In view of this, the utility model provides a new 4K decoding processor with a simple and compact structure, which can solve the limitations of existing 4K decoding processors in multi-screen display, and help to output the decoded 4K video signal to four display devices for synchronous display.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] A new 4K decoding processor, comprising: a housing, an RJ45 network interface, four HDMI ports, a 4K decoding processing component, a video conversion component and a video output component;

[0007] Wherein, the RJ45 network interface and four HDMI ports are respectively externally mounted on the panel of the housing;

[0008] The 4K decoding processing component, the video conversion component and the video output component are all installed inside the housing;

[0009] The RJ45 network interface is internally connected to the 4K decoding processing component, and the output end of the 4K decoding processing component is connected to the input end of the video conversion component; the video conversion component outputs to the video output component, and the 4 output ends of the video output component are respectively connected to the four HDMI ports.

[0010] Furthermore, the 4K decoding processing component is composed of an ASIC chip, the input end receives video stream data through the RJ45 network port, converts the output video signal into a format that complies with the HDMI2.0 standard, and sends it to the video conversion component.

[0011] Furthermore, the video conversion component is composed of an HDMI2.0 receiving chip and an FPGA;

[0012] The HDMI2.0 receiving chip receives the video signal from the 4K decoding processing component, converts it into a 60-bit LVTTL data interface, and connects it to the FPGA;

[0013] The FPGA converts into 4-way BT1120 parallel data and connects with the video output component.

[0014] Furthermore, the video output component is composed of 4 sets of HDMI 1.4 receiving chips;

[0015] The four groups of HDMI 1.4 receiving chips respectively receive four channels of BT1120 parallel data and convert them into HDMI signals for corresponding connection to display devices.

[0016] Furthermore, the shell is made of engineering plastic or metal.

[0017] Furthermore, the side surface of the shell has heat dissipation holes.

[0018] Furthermore, fixing members are provided at both ends of the shell, and the fixing members are provided with through holes.

[0019] Furthermore, convex points are provided at the four corners of the bottom of the shell.

[0020] Through the above technical solutions, it can be known that compared with the prior art, the utility model discloses a new 4K decoding processor with a compact structure. Different functional modules of decoding processing, video conversion, and video output are installed inside the shell, and the cooperation is close and efficient; it can receive multiple video streams and output multiple high-definition video signals at the same time, meet the needs of multi-screen display, and provide more flexible and high-performance video output functions. The 4K decoding processor of the utility model has more HDMI output channels, supports higher quality video signal display, and effectively reduces application costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0022] Figure 1 This is a schematic diagram of the overall structure of the new 4K decoding processor provided by the utility model.

[0023] Figure 2 This is an internal connection schematic diagram of a novel 4K decoding processor provided by the utility model.

[0024] Figure 3 This is a structural schematic diagram of the 4K decoding processing component provided by the utility model.

[0025] Figure 4 This is a structural schematic diagram of the video conversion component provided by the utility model.

[0026] Figure 5 This is a schematic diagram of the structure of the video output component provided by the utility model. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0028] The utility model embodiment discloses a novel 4K decoding processor, referring to Figure 1-2 As shown, it includes: a housing 1, an RJ45 network interface 2, four HDMI ports 3, a 4K decoding processing component 4, a video conversion component 5 and a video output component 6;

[0029] Among them, the RJ45 network interface 2 and the four HDMI ports 3 are respectively externally arranged on the panel of the shell 1; the 4K decoding processing component 4, the video conversion component 5 and the video output component 6 are all installed inside the shell 1; the RJ45 network interface 2 is internally connected to the 4K decoding processing component 4, and the output end of the 4K decoding processing component 4 is connected to the input end of the video conversion component 5; the video conversion component 5 outputs to the video output component 6, and the 4 output ends of the video output group 6 are respectively connected to the four HDMI ports.

[0030] It has an RJ45 Gigabit network interface, which can be used to collect 4K network video signals or multi-channel 1080P network video signals in the external network and transmit them to the 4K decoding processing component; it has four HDMI output channels, which are used to distribute the decoded and converted video signals to four different 1080P display devices.

[0031] The new 4K decoding processor provided in this embodiment can support multiple HDMI output channels to meet the needs of multi-screen display; can process single-channel 4K network signals or multiple-channel 1080P network signals to achieve high-definition video decoding; has image splicing, zooming in, zooming out, superimposing and other functions to meet the needs of different scenarios; in addition, it has flexible configuration options to adapt to various application scenarios and layout requirements. The utility model aims to provide users with a 4K decoding processor with more comprehensive functions and superior performance to meet the growing needs of multi-screen display and video processing.

[0032] Specifically, refer to Figure 3 As shown, the 4K decoding processing component 4 is used, for example, to receive multiple ultra-high-definition network video streams with a resolution of up to 3840x2160 and to zoom in, zoom out, crop and overlay the video streams; it can support H.265 and H.264 decoding.

[0033] The structure of the 4K decoding processing component is: accessing the local area network through a network port, decoding the video stream in the local area network, using an ASIC chip, can decode up to 4 ultra-clear video streams with a resolution of up to 3840x2160, and performing a variety of display processing on the decoded video signal, including zooming in, zooming out, cropping and superimposing, and sending it to the post-stage video conversion module through an HDMI interface after processing. Among them, the ASIC chip decoding function is realized by hardware circuits, and no additional software support is required. ASIC chips are generally more suitable for application scenarios with high requirements for performance and efficiency, such as video processing, image processing, etc. The advantages of hardware decoding are fast speed, high stability, low power consumption, etc. Among them, if the ASIC chip is connected to the RJ45 interface, middleware, such as an Ethernet controller chip or a PHY chip, is required to transmit data between the ASIC chip and the network interface. These Ethernet controller chips or PHY chips are responsible for transmitting data from the RJ45 interface to the ASIC chip, transmitting or receiving data from the network through the network, and transmitting it to the ASIC chip. The specific pin connection is equivalent to the known technology on the market, does not belong to the innovation of the utility model, and can be fully implemented by those skilled in the art.

[0034] Reference Figure 4 As shown, the video conversion component 5 can be used to process 3840x2160 video into 4 channels of 1920x1080 video, for example; the structure of the video conversion component 5 is: connecting 1 channel of 4Kx2K@60 / 50Hz video signal to 1 HDMI2.0 receiving chip respectively, converting them into 60-bit LVTTL data interface respectively, connecting the LVTTL data to 1 FPGA, converting them into 4 channels of BT1120 parallel data through the FPGA, each channel of BT1120 parallel data is 1080P@60 / 50Hz, and then connecting to the video output component 6.

[0035] Reference Figure 5 As shown, the video output component 6 can be used to output 4 channels of 1920x1080 videos through 4 HDMI interfaces. The structure of the video output component 6 is as follows: 4 channels of BT1120 parallel data are respectively sent to 4 HDMI1.4 receiving chips, and each HDMI1.4 receiving chip is responsible for converting 1 channel of BT1120 parallel data into HDMI signal, supporting 1080P@60Hz display.

[0036] The 4K decoding processor of this utility model can receive multiple ultra-clear network video streams with a resolution of up to 3840x2160 and perform processing such as amplification, reduction, cropping and superposition on the video streams; it has four HDMI output channels, and can output the decoded 4K video signal to four 1080P display devices for synchronous display at the same time, achieving a point-to-point high-definition display effect. It can also decode and output multiple 1080P network signals to the 2X2 splicing screen connected to the HDMI, achieving functions such as amplification, reduction, cropping and superposition.

[0037] The 4K decoding processor of the utility model realizes the decoding of multiple 4K ultra-clear videos, and realizes the diversified display processing of multiple 4K ultra-clear videos, and finally sends them to the subsequent display device in the form of four-channel output after conversion and output. It can support the display of higher-intelligence video signals and effectively reduce the application cost.

[0038] In addition, the shell of the 4K decoding processor of the present invention is made of engineering plastic or metal, which can provide good structural strength and durability, and can also effectively prevent external interference and electromagnetic interference, and protect internal components from damage.

[0039] Reference Figure 1 As shown, there are heat dissipation holes 7 on the side of the shell, which can promote air circulation, improve heat dissipation efficiency, effectively reduce the operating temperature of internal components, and maintain the stability and reliability of the equipment. Fixings 8 are provided at both ends of the shell, and through holes are provided on them. Through the design of the fixings and through holes, the equipment can be easily installed and fixed, and the installation efficiency and reliability of the equipment can be improved. Bumps 9 are provided at the four corners of the bottom of the shell. By providing bumps at the bottom of the shell, the space between the equipment and the supporting surface can be effectively increased, the ventilation space can be increased, the heat dissipation efficiency can be further improved, and the stability and reliability of the equipment can be improved.

[0040] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0041] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A new 4K decoding processor, characterized in that: include: Housing, RJ45 network interface, four HDMI ports, 4K decoding processing component, video conversion component and video output component; Wherein, the RJ45 network interface and four HDMI ports are respectively externally mounted on the panel of the housing; The 4K decoding processing component, the video conversion component and the video output component are all installed inside the housing; The RJ45 network interface is internally connected to the 4K decoding processing component, and the output end of the 4K decoding processing component is connected to the input end of the video conversion component; the video conversion component outputs to the video output component, and the 4 output ends of the video output component are respectively connected to the four HDMI ports.

2. A novel 4K decoding processor according to claim 1, characterized in that: The 4K decoding processing component is composed of an ASIC chip. The input end receives video stream data through an RJ45 network port, converts the output video signal into a format that complies with the HDMI2.0 standard, and sends it to the video conversion component.

3. A novel 4K decoding processor according to claim 2, characterized in that: The video conversion component is composed of an HDMI2.0 receiving chip and an FPGA; The HDMI2.0 receiving chip receives the video signal from the 4K decoding processing component, converts it into a 60-bit LVTTL data interface, and connects it to the FPGA; The FPGA converts into 4-way BT1120 parallel data and connects with the video output component.

4. A novel 4K decoding processor according to claim 3, characterized in that: The video output component is composed of 4 sets of HDMI 1.4 receiving chips; The four groups of HDMI 1.4 receiving chips respectively receive four channels of BT1120 parallel data and convert them into HDMI signals for corresponding connection to display devices.

5. A novel 4K decoding processor according to any one of claims 1 to 4, characterized in that: The shell is made of engineering plastic or metal.

6. A novel 4K decoding processor according to any one of claims 1 to 4, characterized in that: The side surface of the shell is provided with heat dissipation holes.

7. A novel 4K decoding processor according to any one of claims 1 to 4, characterized in that: Two ends of the shell are provided with fixing pieces, and the fixing pieces are provided with through holes.

8. A novel 4K decoding processor according to any one of claims 1 to 4, characterized in that: The four corners of the bottom of the shell are provided with convex points.

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