SPI switching circuit and SPI equipment

Abstract

The utility model provides an SPI (Serial Peripheral Interface) switching circuit and SPI equipment, and relates to the field of SPI circuit design, the SPI switching circuit comprises an SPI switching chip, a DSP (Digital Signal Processor), an SOC (System on Chip) chip and an MCU (Microprogrammed Control Unit) chip; when the MCU detects that the SOC is started, the SPI switching chip is actively controlled through the GPIO interface to change a channel, and the SPI interface is switched to SOC end control, so that time-sharing control of different master devices on one slave device is realized, and the development cost can be effectively reduced.

Description

Technical Field

[0001] The utility model relates to the field of SPI circuit design, in particular to a SPI switching circuit and a SPI device. Background Art

[0002] SPI is a common data interface on microcontrollers. It adopts a master-slave architecture and usually uses an application mode in which one master device corresponds to one or more slave devices. This application mode may be difficult to meet the needs in some scenarios. For example, when making a quick sound on an in-vehicle multimedia device, the SOC needs to drive the DSP chip to make a quick sound through the SPI interface, but the startup of the SOC takes a certain amount of time and it is difficult to reach the specified time range. Therefore, it is necessary to start a faster MCU to drive the DSP chip to make a sound. If all the functions of driving the DSP are given to the MCU to implement, the functions that have been implemented on the SOC must be redeveloped on the MCU side, which will undoubtedly increase the development cost. Utility Model Content

[0003] In view of this, the purpose of the utility model is to provide an SPI switching circuit and an SPI device, through which the time-sharing control of a slave device by different master devices is realized, which can effectively reduce the development cost.

[0004] In the first aspect, the embodiment of the utility model provides an SPI switching circuit including: an SPI switching chip, a DSP digital signal processor, a SOC system-on-chip chip and an MCU microcontroller chip; the first interface of the SPI switching chip is connected to the first SPI interface of the SOC system-on-chip chip; the second interface of the SPI switching chip is connected to the second SPI interface of the MCU microcontroller chip; the third SPI interface of the DSP digital signal processor is connected to the SPI port of the SPI switching chip;

[0005] The first interface and the second interface are connected to the SPI port through a mutually exclusive switch; the SEL input end of the SPI switching chip is connected to the GPIO end of the MCU microcontroller unit chip.

[0006] In one embodiment, the SPI switching chip is a model SN3257 chip; the first interface of the SPI switching chip includes the first, S2A, S3A, and S4A ports of the SN3257 chip; the second interface of the SPI switching chip includes the second, S2B, S3B, and S4B ports of the SN3257 chip; the SPI port of the SPI switching chip includes the D1, D2, D3, and D4 ports of the SN3257 chip.

[0007] In one implementation, the DSP digital signal processor is a chip of model AK7765; the third SPI interface of the DSP digital signal processor includes a CSN pin, a SO pin, a SCLK pin, and a SI pin of the AK7765 chip.

[0008] In one implementation, the SOC system-on-chip chip is a model MT8666 chip; the second SPI interface of the SOC system-on-chip chip includes a MISO pin, a MOSI pin, a SCLK pin, and a CSN pin of the MT8666 chip.

[0009] In one implementation, the MCU microcontroller chip is a FS32K146HAT0 chip; the first SPI interface of the MCU microcontroller chip includes a CS pin, a MOSI pin, a MISO pin, and a CLK pin of the FS32K146HAT0 chip.

[0010] In one implementation, the SPI switching circuit further includes: a first resistor; one end of the first resistor is connected to the SEL input end of the SPI switching chip; and the other end of the first resistor inputs the first voltage.

[0011] In one implementation, the resistance of the first resistor is 10K ohms; the first voltage is 1.8V.

[0012] In one embodiment, when the GPIO pin of the MCU microcontroller chip is in a suspended state, the SPI port of the SPI switching chip is connected to the first interface;

[0013] When the GPIO pin of the MCU microcontroller chip is at a high level, the SPI port of the SPI switch chip is connected to the third SPI interface of the DSP digital signal processor;

[0014] When the GPIO pin of the MCU microcontroller chip is at a low level, the SPI port of the SPI switching chip is connected to the second interface;

[0015] The voltage value of the high level is greater than the voltage value of the low level.

[0016] In one embodiment, the voltage value of the high level is 1.8V; the voltage value of the low level is 0.3V;

[0017] The input voltage of the SPI switch chip is 5V;

[0018] The input voltage of DSP digital signal processor is 3.3V or 1.8V;

[0019] The input voltage of the SOC system-on-chip chip is 4V;

[0020] The input voltage of the MCU microcontroller chip is 3.3V.

[0021] In a second aspect, an embodiment of the present utility model provides an SPI device, the SPI device comprising a slave device, a master device and the SPI switching circuit mentioned in the first aspect above;

[0022] Wherein, the slave device is connected to a plurality of master devices respectively through the SPI switching circuit.

[0023] The utility model provides a SPI switching circuit and SPI device, the SPI switching circuit includes: an SPI switching chip, a DSP digital signal processor, a SOC chip and an MCU microcontroller chip; the first interface of the SPI switching chip is connected to the first SPI interface of the SOC chip; the second interface of the SPI switching chip is connected to the second SPI interface of the MCU microcontroller chip; the third SPI interface of the DSP digital signal processor is connected to the SPI port of the SPI switching chip; wherein the first interface and the second interface are connected to the SPI port through a mutually exclusive switch; the SEL input end of the SPI switching chip is connected to the GPIO end of the MCU microcontroller chip. The SPI switching circuit can make the SPI interface of the DSP controlled by the MCU when the SPI device is started; when the MCU detects that the SOC has been started and has successfully shaken hands with it, it actively controls the SPI switching chip to change the channel through the GPIO interface, and switches the SPI interface to the SOC end control; thereby realizing the time-sharing control of a slave device by different master devices, which can effectively reduce the development cost, thereby solving the problems existing in the prior art.

[0024] Other features and advantages of the utility model will be described in the following description, and partly become apparent from the description, or understood by practicing the utility model. The purpose and other advantages of the utility model are realized and obtained by the structures specifically pointed out in the description, claims and drawings.

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1A schematic diagram of the structure of an SPI switching circuit provided by an embodiment of the utility model;

[0028] Figure 2 A schematic diagram of the structure of another SPI switching circuit provided in an embodiment of the utility model.

[0029] icon:

[0030] 10-SPI switching chip; 20-DSP digital signal processor; 30-SOC system-on-chip chip; 40-MCU microcontroller unit chip; 50-first resistor. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the utility model clearer, the technical solution of the utility model will be clearly and completely described in combination with the embodiments below. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0032] SPI (Serial Peripheral Interface) is a common data interface on microcontrollers. It adopts a master-slave architecture and usually uses an application method in which one master device corresponds to one or more slave devices. This application method may be difficult to meet the needs in some scenarios. For example, when making fast sounds on an in-vehicle multimedia device, the SOC (System on Chip) needs to drive the DSP (Digital Signal Process) chip to make sounds quickly through the SPI interface, but the startup of the SOC takes a certain amount of time and it is difficult to reach the specified time range. Therefore, it is necessary to start a faster MCU (Microcontroller Unit) to drive the DSP chip to make sounds. If all the functions of driving the DSP are given to the MCU for implementation, the functions that have been implemented on the SOC must be redeveloped on the MCU side, which will undoubtedly increase the development cost.

[0033] Based on this, an embodiment of the utility model provides an SPI switching circuit and an SPI device, through which time-sharing control of a slave device by different master devices is realized, which can effectively reduce development costs.

[0034] To facilitate understanding of this embodiment, a SPI switching circuit disclosed in the embodiment of the utility model is first introduced in detail. Figure 1As shown, the SPI switching circuit includes: a SPI switching chip 10, a DSP digital signal processor 20, a SOC system-on-chip chip 30 and an MCU microcontroller unit chip 40.

[0035] The first interface of the SPI switching chip 10 is connected to the first SPI interface of the SOC system-on-chip chip 30; the second interface of the SPI switching chip 10 is connected to the second SPI interface of the MCU microcontroller chip 40; and the third SPI interface of the DSP digital signal processor 20 is connected to the SPI port of the SPI switching chip 10.

[0036] Among them, the first interface and the second interface of the SPI switch chip 10 are connected to the SPI port through a mutually exclusive switch; the SEL input terminal in the SPI switch chip 10 is connected to the GPIO terminal of the MCU micro control unit chip 40.

[0037] Specifically, on the communication link of the SPI interface, there is only one master device according to the communication protocol requirements, and there can be multiple slave devices. This embodiment can realize the time-sharing control of one slave device by different master devices through an SPI switching circuit. The SPI interface of the DSP is first controlled by the MCU. When the MCU detects that the SOC has been started and the handshake with it is successful, it actively controls the SPI switching chip to change the channel through the GPIO interface and switches the SPI interface to the SOC end control. Through this SPI switching circuit, the software development investment and cycle can be effectively reduced, and a faster delivery plan can be achieved.

[0038] like Figure 2 It can be seen from another SPI switching circuit structure that in one embodiment, the SPI switching chip 10 is a model SN3257 chip; the first interface of the SPI switching chip 10 includes the first, S2A, S3A, and S4A ports of the SN3257 chip; the second interface of the SPI switching chip 10 includes the second, S2B, S3B, and S4B ports of the SN3257 chip; the SPI port of the SPI switching chip 10 includes the D1, D2, D3, and D4 ports of the SN3257 chip.

[0039] In one implementation, the DSP digital signal processor 20 is a chip of model AK7765; the third SPI interface of the DSP digital signal processor 20 includes a CSN pin, a SO pin, a SCLK pin, and a SI pin of the AK7765 chip.

[0040] In one implementation, the SOC chip 30 is a MT8666 chip; the second SPI interface of the SOC chip 30 includes a MISO pin, a MOSI pin, a SCLK pin, and a CSN pin of the MT8666 chip.

[0041] In one implementation, the MCU microcontroller chip 40 is a FS32K146HAT0 chip; the first SPI interface of the MCU microcontroller chip 40 includes a CS pin, a MOSI pin, a MISO pin, and a CLK pin of the FS32K146HAT0 chip.

[0042] In one implementation, the SPI switching circuit further includes: a first resistor 50; one end of the first resistor 50 is connected to the SEL input end of the SPI switching chip 10; and the other end of the first resistor 50 inputs the first voltage.

[0043] In one implementation, the resistance of the first resistor 50 is 10K ohms; the first voltage is 1.8V.

[0044] In one embodiment, when the GPIO pin of the MCU microcontroller chip 40 is in a suspended state, the SPI port of the SPI switch chip 10 is connected to the first interface;

[0045] When the GPIO pin of the MCU microcontroller chip 40 is at a high level, the SPI port of the SPI switch chip is connected to the third SPI interface of the DSP digital signal processor;

[0046] When the GPIO pin of the MCU microcontroller chip 40 is at a low level, the SPI port of the SPI switching chip is connected to the second interface;

[0047] The voltage value of the high level is greater than the voltage value of the low level.

[0048] In one embodiment, the voltage value of the high level is 1.8V; the voltage value of the low level is 0.3V;

[0049] The input voltage of the SPI switch chip is 5V;

[0050] The input voltage of DSP digital signal processor is 3.3V or 1.8V;

[0051] The input voltage of the SOC system-on-chip chip is 4V;

[0052] The input voltage of the MCU microcontroller chip is 3.3V.

[0053] Specifically, the SPI switching circuit in this embodiment is switched through the SPI switching chip, the SPI interface of the DSP digital signal processor is connected to the SPI switching chip, the S1A interface of the SPI switching chip is connected to the SPI interface of the MCU microcontroller chip, and the S1B interface of the SPI switching chip is connected to the SPI interface of the SOC system-on-chip chip.

[0054] In actual scenarios, when the 17-pin GPIO of the MCU is in a floating state and does not output voltage, the SEL pin of the SPI switching chip is affected by the 10K resistor and the voltage is pulled up to 1.8V. At this time, the D1, D2, D3, D4 and S1A interfaces of the SPI switching chip are turned on, so that the DSP and MCU are connected through the switching chip.

[0055] When the 17-pin GPIO of the MCU is at a high level, the connection status of each chip remains the same as when it is suspended, that is, the DSP and the MCU are connected through the switching chip.

[0056] When the 17-pin GPIO of the MCU outputs a low level, that is, a voltage below 0.3V, the SEL pin voltage of the SPI switch chip also drops below 0.3V. At this time, the D1, D2, D3, D4 and S1B interfaces of the SPI switch chip are turned on, so that the DSP and MCU are disconnected, and the DSP and SOC are connected through the switch chip. Through the above operations, the purpose of switching the SPI interface device is achieved, and both the MCU and the SOC can control the DSP chip separately.

[0057] It can be seen from the SPI switching circuit provided in the embodiment of the utility model that the SPI switching circuit can make the SPI interface of the DSP controlled by the MCU when the SPI device is started; when the MCU detects that the SOC has been started and has successfully shaken hands with it, it actively controls the SPI switching chip to change the channel through the GPIO interface, and switches the SPI interface to the SOC end control; thereby realizing time-sharing control of a slave device by different master devices, which can effectively reduce development costs and solve the problems existing in the prior art.

[0058] The utility model provides an SPI device, which comprises a slave device, a master device and the SPI switching circuit mentioned in the above embodiment; wherein the slave device is connected to a plurality of master devices respectively through the SPI switching circuit.

[0059] The SPI switching circuit in the SPI device provided in the embodiment of the utility model has the same implementation principle and technical effects as those of the aforementioned SPI switching circuit embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the aforementioned embodiment.

[0060] In the several embodiments provided in the present application, it should be understood that the disclosed systems and devices can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0061] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0062] In addition, each functional unit in each embodiment of the present utility model may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0063] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the utility model can essentially or in other words, the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of each embodiment method of the utility model. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0064] Finally, it should be noted that the above embodiments are only specific implementation methods of the utility model, which are used to illustrate the technical solution of the utility model, rather than to limit it. The protection scope of the utility model is not limited thereto. Although the utility model is described in detail with reference to the above embodiments, ordinary technicians in this field should understand that any technician familiar with the technical field can still modify the technical solution recorded in the above embodiments within the technical scope disclosed by the utility model, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solution of the embodiment of the utility model, and should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model shall be based on the protection scope of the claims.

Claims

1. An SPI switching circuit, characterized in that: The SPI switching circuit comprises: an SPI switching chip, a DSP digital signal processor, a SOC system-on-chip chip and an MCU microcontroller chip; the first interface of the SPI switching chip is connected to the first SPI interface of the SOC system-on-chip chip; the second interface of the SPI switching chip is connected to the second SPI interface of the MCU microcontroller chip; the third SPI interface of the DSP digital signal processor is connected to the SPI port of the SPI switching chip; Among them, the first interface and the second interface are connected to the SPI port through a mutually exclusive switch; the SEL input end of the SPI switching chip is connected to the GPIO end of the MCU micro control unit chip.

2. The SPI switching circuit according to claim 1, characterized in that: The SPI switching chip is a model SN3257 chip; the first interface of the SPI switching chip includes the S1A, S2A, S3A, and S4A ports of the SN3257 chip; the second interface of the SPI switching chip includes the S1B, S2B, S3B, and S4B ports of the SN3257 chip; the SPI port of the SPI switching chip includes the D1, D2, D3, and D4 ports of the SN3257 chip.

3. The SPI switching circuit according to claim 1, characterized in that: The DSP digital signal processor is a chip of model AK7765; the third SPI interface of the DSP digital signal processor includes a CSN pin, a SO pin, a SCLK pin, and a SI pin of the AK7765 chip.

4. The SPI switching circuit according to claim 1, characterized in that: The SOC system-on-chip chip is a model MT8666 chip; the second SPI interface of the SOC system-on-chip chip includes the MISO pin, MOSI pin, SCLK pin, and CSN pin of the MT8666 chip.

5. The SPI switching circuit according to claim 1, characterized in that: The MCU microcontroller chip is a FS32K146HAT0 chip; the first SPI interface of the MCU microcontroller chip includes a CS pin, a MOSI pin, a MISO pin, and a CLK pin of the FS32K146HAT0 chip.

6. The SPI switching circuit according to claim 1, characterized in that: The SPI switching circuit also includes: a first resistor; one end of the first resistor is connected to the SEL input end of the SPI switching chip; and the other end of the first resistor inputs a first voltage.

7. The SPI switching circuit according to claim 6, characterized in that: The resistance of the first resistor is 10K ohms; the first voltage is 1.8V.

8. The SPI switching circuit according to any one of claims 1 to 7, characterized in that: When the GPIO pin of the MCU microcontroller chip is in a suspended state, the SPI port of the SPI switching chip is connected to the first interface; When the GPIO pin of the MCU microcontroller chip is at a high level, the SPI port of the SPI switch chip is connected to the third SPI interface of the DSP digital signal processor; When the GPIO pin of the MCU microcontroller chip is at a low level, the SPI port of the SPI switching chip is connected to the second interface; The voltage value of the high level is greater than the voltage value of the low level.

9. The SPI switching circuit according to claim 8, characterized in that: The voltage value of the high level is 1.8V; the voltage value of the low level is 0.3V; The input voltage of the SPI switching chip is 5V; The input voltage of the DSP digital signal processor is 3.3V or 1.8V; The input voltage of the SOC chip is 4V; The input voltage of the MCU microcontroller chip is 3.3V.

10. An SPI device, characterized in that: The SPI device comprises a slave device, a master device and the SPI switching circuit according to any one of claims 1 to 9; Wherein, the slave device is connected to the plurality of master devices respectively through the SPI switching circuit.

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