Semiconductor device

Abstract

A semiconductor device includes an array of a plurality of pixel sensors and a deep trench isolation structure. The array of pixel sensors includes photodiodes that are physically partitioned by at least one isolation structure wherein incident light to the photodiodes is separated by the at least one isolation structure. And a deep trench isolation structure at least partially surrounding the pixel sensors of the array. The intra-pixel separation structure may separate a photodiode of the pixel array into a plurality of regions. As a result, a lens of the image sensor device may be focused by using a combined signal associated with different portions of the photodiode. As a result, the lens can focus faster and the pixel array has fewer pixels, which saves power, processing resources, and raw materials.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] A complementary metal oxide semiconductor (CMOS) image sensor may include a plurality of pixel sensors. A pixel sensor of a CMOS image sensor may include a transfer transistor, which may include a photodiode for converting incident light photons into a photocurrent of electrons and a transfer gate for controlling the flow of the photocurrent between the photodiode and a drain region. The drain region may be used to receive the photocurrent so that the photocurrent may be measured and / or transferred to other areas of the CMOS image sensor. Utility Model Content

[0003] Some embodiments of the present disclosure provide a semiconductor device including an array of a plurality of pixel sensors and a deep trench isolation structure. The array of pixel sensors includes a photodiode physically partitioned by at least one isolation structure, wherein incident light to the photodiode is separated by the at least one isolation structure. The deep trench isolation structure at least partially surrounds the pixel sensors of the array.

[0004] Some embodiments of the present disclosure provide a semiconductor device including an array of a plurality of pixel sensors and a deep trench isolation structure. The array of pixel sensors includes a photodiode physically partitioned by at least one isolation structure, wherein incident light to the photodiode is separated by the at least one isolation structure, wherein the at least one isolation structure has an angle ranging from 0 degrees to 75 degrees relative to an axis of the photodiode. A deep trench isolation structure at least partially surrounds the pixel sensors of the array.

[0005] Some embodiments of the present disclosure provide a semiconductor device including an array of a plurality of pixel sensors and a deep trench isolation structure. The array of pixel sensors includes a photodiode physically partitioned by at least one isolation structure, wherein incident light to the photodiode is separated by at least one isolation structure, wherein at least one isolation structure includes a single isolation structure that divides the photodiode approximately into one-third and two-thirds. A deep trench isolation structure at least partially surrounds the pixel sensors of the array. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of this disclosure are in the attached Figure 1 The following detailed description is best understood when read together. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of an example environment in which the systems and / or methods described herein may be implemented;

[0008] Figure 2 is a schematic diagram of an example pixel array described herein;

[0009] Figures 3A to 3G is a schematic diagram of an example pixel sensor described herein;

[0010] FIG. 4A to FIG. 4B is a schematic diagram of an example implementation described herein;

[0011] FIG. 5A to FIG. 5H is a schematic diagram of an example pixel array described herein;

[0012] 6A to 6F is a schematic diagram of an example implementation described herein;

[0013] FIG. 7A to FIG. 7G is a schematic diagram of an example implementation described herein;

[0014] FIG. 8A to FIG. 8G is a schematic diagram of an example implementation described herein;

[0015] 9A to 9D is a schematic diagram of an example pixel array described herein;

[0016] Fig.10 This article describes Figure 1 schematic diagrams of example components of one or more devices;

[0017] Fig.11 is a flow chart of an example process associated with forming the semiconductor structure described herein;

[0018] Fig.12 is a flow chart of an example process associated with using the semiconductor structure described herein.

[0019]

Explanation of symbols

[0020] 100: Environment

[0021] 102:Deposition tools / semiconductor processing tools

[0022] 104: Exposure tools / semiconductor processing tools

[0023] 106: Development tools / semiconductor processing tools

[0024] 108: Etching tools / semiconductor processing tools

[0025] 110: Planarization tools / semiconductor processing tools

[0026] 112:Electroplating tools / semiconductor processing tools

[0027] 114: Photoresist removal tool / semiconductor processing tool

[0028] 116: Annealing tools / semiconductor processing tools

[0029] 118: Wafer / die transfer tool

[0030] 200: Pixel array

[0031] 202: Pixel sensor

[0032] 300: Pixel sensor

[0033] 302:Substrate

[0034] 304: Photodiode

[0035] 304-1, 304-2, 304-3, 304-4: Photodiode

[0036] 306: Lining layer

[0037] 308:DTI structure

[0038] 310: Isolation structure / HA structure

[0039] 310-1, 310-2, 310-3, 310-4, 310-5, 310-6, 310-7, 310-8: Isolation structure

[0040] 310a, 310b, 310c: HA structure

[0041] 312: Buffer layer

[0042] 314: Color filter layer

[0043] 316: Microlens layer

[0044] 320, 330, 340, 350: Pixel sensor

[0045] 400:Pixel sensor

[0046] 450: Pixel Array

[0047] 452, 454: Reference numbers

[0048] 500, 510, 520, 530, 540, 550, 530, 570: pixel array

[0049] 600: Example Implementation

[0050] 602, 604: groove / groove

[0051] 700, 800: Example implementation

[0052] 900: Pixel Array

[0053] 902, 904: Pixel sensor

[0054] 910, 920, 930: Pixel array

[0055] 1000: Installation

[0056] 1010: Bus

[0057] 1020: Processor

[0058] 1030: Memory

[0059] 1040: Input component

[0060] 1050: Output component

[0061] 1060: Communication components

[0062] 1100: Craftsmanship

[0063] 1110, 1120, 1130: Blocks

[0064] 1200: Craftsmanship

[0065] 1210, 1220, 1230, 1240: Blocks

[0066] W: Width

[0067] θ: angle DETAILED DESCRIPTION

[0068] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0069] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0070] An image sensor device (e.g., a complementary metal oxide semiconductor (CMOS) image sensor device or another type of image sensor device) is a type of electronic semiconductor device that uses a pixel sensor to generate a photocurrent based on light received at the pixel sensor. The measure of the photocurrent can be based on the intensity of the light, based on the wavelength of the light, and / or based on another property of the light. The photocurrent is then processed to generate an electronic image, an electronic video, and / or another type of electronic signal.

[0071] Typically, a camera device that includes an image sensor device may also include an independent phase detector auto focus (PDAF) device. A portion of the incident light received through the lens of the camera device is directed to the PDAF device for the purpose of performing the auto focus function of the camera device to focus the field of view onto the image sensor device. Generally speaking, the PDAF device combines signals from pixels in different positions in the array in order to determine the focus position of the lens of the image sensor device. This process generally uses signals from a large number of pixels and multiple calculations to estimate the phase difference between these pixels.

[0072] Some implementations described herein provide a technique and device for forming an intra-pixel separation structure that separates the photodiode of a pixel into multiple regions. The intra-pixel separation structure may be a shallow deep trench isolation (DTI) structure. Alternatively, a high absorption (HA) structure formed in a line may be used as the intra-pixel separation structure. Each pixel may be divided into two or three by one or more intra-pixel separation structures. As a result, the lens of the image sensor device can be focused by using the combined signals associated with different parts of the photodiode. Because the phase difference can be determined using only a few photodiodes that are physically partitioned, the lens can focus faster and with fewer pixels, which saves power, processing resources, and raw materials.

[0073] Figure 11 is a schematic diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown in the example environment 100, the environment 100 may include a plurality of semiconductor processing tools 102-116 and a wafer / die transfer tool 118. The plurality of semiconductor processing tools 102-116 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, a photoresist removal tool 114, an annealing tool 116, and / or another semiconductor processing tool. The tools included in the example environment 100 may be included in a semiconductor cleaning chamber, a semiconductor wafer fab, a semiconductor processing and / or manufacturing facility, or another location.

[0074] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some implementations, the deposition tool 102 includes a spin-on coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some implementations, the deposition tool 102 includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, an epitaxy tool, or another type of CVD tool. In some implementations, the deposition tool 102 includes a physical vapor deposition (PVD) tool such as a sputtering tool or another type of PVD tool. In some implementations, the example environment 100 includes multiple types of deposition tools 102 .

[0075] The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV light source, an extreme UV light (EUV) source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include patterns for forming one or more structures of a semiconductor device, can include patterns for etching various portions of a semiconductor device, and / or the like. In some implementations, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0076] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some implementations, the developing tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some implementations, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some implementations, the developing tool 106 develops the pattern by dissolving the exposed or unexposed portions of the photoresist layer using a chemical developer.

[0077] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or the like. In some implementations, the etching tool 108 includes a chamber filled with an etchant in which a substrate is placed for a specific period of time to remove a specific amount of one or more portions of the substrate. In some implementations, the etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0078] The planarization tool 110 is a semiconductor processing tool capable of grinding or planarizing individual layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that grinds or planarizes a layer or surface of a deposited or plated material. The planarization tool 110 can grind or planarize the surface of a semiconductor device using a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive grinding). The planarization tool 110 can utilize abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device can be pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head can rotate on different rotation axes to remove material and even out any irregular topography of the semiconductor device, making the semiconductor device flat or planar.

[0079] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a composite material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0080] The photoresist removal tool 114 is a semiconductor processing tool capable of removing remaining portions of a photoresist layer from a substrate after the etching tool 108 removes portions of the substrate. For example, the photoresist removal tool 114 may remove the photoresist layer from the substrate using chemical stripping and / or another technique.

[0081] The annealing tool 116 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of heating a semiconductor substrate or a semiconductor device. For example, the annealing tool 116 may include a rapid thermal annealing (RTA) tool or another type of annealing tool that can heat a semiconductor substrate to cause a reaction between two or more materials or gases to cause material decomposition. As another example, the annealing tool 116 can be used to heat a structure or layer (or a portion thereof) (e.g., increase or raise its temperature) to cause the structure or layer to reflow, or to crystallize the structure or layer to remove defects such as voids or seams. As another example, the annealing tool 116 can be used to heat a layer (or a portion thereof) (e.g., increase or raise its temperature) to enable bonding of two or more semiconductor devices.

[0082] The wafer / die transfer tool 118 may be included in a cluster tool or another type of tool including multiple processing chambers and may be used to transfer substrates and / or semiconductor devices between multiple processing chambers, between a processing chamber and a buffer, between a processing chamber and an interface tool such as an equipment front end module (EFEM), and / or between a processing chamber and a transfer carrier (e.g., a front opening unified pod (FOUP)), among other things. In some implementations, the wafer / die transfer tool 118 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-clean process chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations).

[0083] In some implementations, one or more of the semiconductor processing tools 102-116 and / or the wafer / die transfer tool 118 can perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-116 and / or the wafer / die transfer tool 118 can form a plurality of photodiodes in a substrate; form a DTI structure at least partially surrounding the plurality of photodiodes; and / or form at least one isolation structure in at least one photodiode of the plurality of photodiodes to phase separate light entering the at least one photodiode, among other examples.

[0084] Figure 1 The number and configuration of tools shown in the figure are provided as one or more examples. Figure 1 There may be additional tools, fewer tools, different tools, or different configurations of tools than those shown in . Figure 1 Two or more of the tools shown in may be implemented in a single tool, or Figure 1 The single tool shown in can be implemented as multiple distributed tools. Additionally or alternatively, a tool set (eg, one or more tools) of environment 100 can perform one or more functions described as being performed by another tool set of environment 100.

[0085] Figure 2 2 is a schematic diagram of an example pixel array 200 (or a portion thereof) described herein. Pixel array 200 may be included in an image sensor, such as a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0086] Figure 2 A top view of the pixel array 200 is shown. Figure 2 As shown in , the pixel array 200 may include a plurality of pixel sensors 202. Figure 2 As further shown in FIG. 1 , the pixel sensors 202 may be arranged in a grid. In some implementations, the pixel sensors 202 are square shaped (e.g., Figure 2 ). In some implementations, the pixel sensor 202 includes other shapes, such as a circular shape, an octagonal shape, a diamond shape, and / or other shapes.

[0087] Pixel sensor 202 may be used to sense and / or accumulate incident light (e.g., direct light toward pixel array 200). For example, pixel sensor 202 may absorb and accumulate photons of incident light in a photodiode. Accumulation of photons in the photodiode may generate a charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a higher intensity or brightness, while a smaller amount of charge may correspond to a lower intensity or brightness).

[0088] Pixel array 200 may be electrically connected to a back-end-of-line (BEOL) metallization stack (not shown) of an image sensor. The BEOL metallization stack may electrically connect pixel array 200 to a control circuit system that may be used to measure the accumulation of incident light in pixel sensor 202 and convert the measurement into an electrical signal.

[0089] As mentioned above, Figure 2 are provided as examples. Other examples may differ from those described in Figure 2 described.

[0090] Figures 3A to 3G is a schematic diagram of an example pixel sensor described herein. Each pixel sensor includes at least one isolation structure that physically partitions a photodiode of the pixel sensor. The isolation structure separates incident light by phase such that the output from the photodiode is based on including photons having a phase that constructively interacts with the isolation structure and excluding photons having a phase that destructively interacts with the isolation structure.

[0091] Figure 3A A cross-sectional view of a pixel sensor 300 is shown. In some implementations, the pixel sensor 300 can be included in the pixel array 200 (or a portion thereof). In some implementations, the pixel sensor 300 can be included in an image sensor. The image sensor can be a CMOS image sensor, a backside illuminated (BSI) CMOS image sensor, or another type of image sensor.

[0092] like Figure 3AAs shown in , pixel sensor 300 may include substrate 302. Substrate 302 may include a semiconductor die substrate, a semiconductor wafer, or another type of substrate in which semiconductor pixels may be formed. In some implementations, substrate 302 is formed of silicon (Si), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon on insulator (SOI), or another type of semiconductor material capable of generating charge from photons of incident light. In some implementations, substrate 302 is formed of a doped material (e.g., a p-type doped material or an n-type doped material) such as doped silicon.

[0093] Pixel sensor 300 may include a photodiode 304 included in substrate 302 (e.g., below the top surface of substrate 302). Photodiode 304 may include a region of substrate 302 doped with multiple types of ions to form a pn junction or a PIN junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) type portion, and an n-type portion). For example, substrate 302 may be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of photodiode 304 and doped with a p-type dopant to form a second portion (e.g., a p-type portion) of photodiode 304. Photodiode 304 may be configured to absorb photons of incident light. The absorption of photons causes photodiode 304 to accumulate charge (referred to as photocurrent) due to the photoelectric effect. Here, photons bombard photodiode 304, which causes the emission of electrons of photodiode 304. The emission of electrons causes the formation of electron-hole pairs, where the electrons migrate toward the cathode of photodiode 304 and the holes migrate toward the anode, thereby generating photocurrent.

[0094] DTI structure 308 may be included in substrate 302 and at least partially surround photodiode 304. DTI structure 308 may provide optical isolation by blocking or preventing light from diffusing or overflowing from photodiode 304 to adjacent photodiodes, thereby reducing crosstalk between adjacent pixel sensors. Figure 3A As further shown in , DTI structure 308 may include trenches coated or lined with a liner layer 306 (e.g., an antireflective coating (ARC)) and filled with a dielectric layer (e.g., above liner layer 306). DTI structure 308 may be formed in a grid layout, where DTI structure 308 extends around the perimeter of pixel sensors (including pixel sensor 300) in a pixel array and intersects at various locations in the pixel array. In some implementations, DTI structure 308 is formed in the back side of substrate 302 to provide optical isolation between pixel sensors, and thus may be referred to as a backside DTI (BDTI) structure.

[0095] The dielectric layer filling the DTI structure 308 may include, for example, silicon oxide (SiO x ) (e.g., oxide materials such as silicon dioxide (SiO2)), silicon nitride (SiN x ), Silicon Carbide (SiC x ), titanium nitride (TiN x ), Tantalum Nitride (TaN x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ), or aluminum oxide (AlO x ), or another dielectric material capable of providing optical isolation between pixel sensors. A liner layer 306 may be included within the DTI structure 308 and above the photodiode 304 on the substrate 302. The liner layer 306 may include a suitable material for reducing reflection of incident light projected toward the photodiode 304. For example, the liner layer 306 may include a nitrogen-containing material.

[0096] The pixel sensor 300 may include at least one isolation structure 310 (eg, Figure 3A 308). The isolation structure 310 is located within the perimeter (or inner boundary) of the DTI structure 308 and is generally physically smaller than the DTI structure 308. For example, the isolation structure 310 may have a width at the top surface of the substrate 302 that is less than the width of the DTI structure 308 at the top surface of the substrate 302. For example, the isolation structure 310 may have a width ranging from about 0.2 micrometers (μm) to about 1.0 μm. Selecting a width of at least 0.2 μm enables the isolation structure 310 to separate incident light in phase. Selecting a width of no more than 1.0 μm reduces the blocking effect on the photodiode 304 (e.g., fewer incident photons, causing the sensitivity of the photodiode 304 to decrease). Similarly, the isolation structure 310 may have a width at the bottom of the isolation structure 310 that is less than the width of the DTI structure 308 at the bottom of the DTI structure 308. Additionally, isolation structure 310 may have a depth into substrate 302 that is less than a depth of DTI structure 308 into substrate 302 .

[0097] As combined Figure 3B As described above, the isolation structure 310 may include a shallow DTI structure. Figure 3C As described above, the isolation structure 310 may include a plurality of high absorption (HA) structures. Each HA structure may include a structure having an oblique wall, so that the structure has an approximately pyramid shape (for example, an approximately triangular shape in a cross-sectional view, such as Fig. 6F , Figure 7G ,and Figure 8G As shown in , it appears in a polygonal shape in a top view, such as an approximately rectangular shape, as shown in Figure 3C As used herein, "pyramid shape" refers to a structure having a polygonal base connected to a point or to a smaller polygon serving as a vertex.

[0098] The isolation structure 310 may be additionally coated or lined with a liner layer. In some implementations, the liner layer of the isolation structure 310 includes the same material as the liner layer 306 that coats or lines the DTI structure 308. In some implementations, the liner layer of the isolation structure 310 includes a different material than the liner layer 306 that coats or lines the DTI structure 308. In addition, the isolation structure 310 may be filled with a dielectric layer (e.g., above the liner layer 306). In some implementations, the dielectric layer of the isolation structure 310 includes the same material as the dielectric layer that fills the DTI structure 308. In some implementations, the dielectric layer of the isolation structure 310 includes a different material than the dielectric layer that fills the DTI structure 308.

[0099] like Figure 3A As further shown in FIG. 1 , a buffer layer 312 may be included above and / or on the top surface of the substrate 302. The buffer layer 312 may include a dielectric material to provide protection to layers below the buffer layer 312 from layers and structures formed above the buffer layer 312. Thus, the buffer layer 312 may include a dielectric material such as silicon oxide (SiO x ) (e.g., oxide materials such as silicon dioxide (SiO2)), silicon nitride (SiN x ), Silicon Carbide (SiC x ), titanium nitride (TiN x ), Tantalum Nitride (TaN x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ), or aluminum oxide (AlO x ), or another dielectric material capable of providing protection.

[0100] Color filter layer 314 may be included on and / or above buffer layer 312. In some implementations, color filter layer 314 includes a visible light filter for filtering visible light of a particular wavelength or a particular range of wavelengths (e.g., red light, blue light, or green light). In some implementations, color filter layer 314 includes a NIR filter (e.g., a NIR bandpass filter) for allowing wavelengths associated with near infrared (NIR) light to pass through color filter layer 314 and blocking light of other wavelengths. In some implementations, color filter layer 314 includes a NIR cutoff filter for blocking NIR light from passing through color filter layer 314. In some implementations, color filter layer 314 is omitted from pixel sensor 300 to allow all wavelengths of light to pass through photodiode 304. In these examples, pixel sensor 300 may be configured as a white pixel sensor.

[0101] Microlens layer 316 may be included above and / or on color filter layer 314. Microlens layer 316 may include microlenses of pixel sensor 300 to focus incident light toward photodiode 304 and / or reduce optical crosstalk between pixel sensor 300 and adjacent pixel sensors.

[0102] Because photodiode 304 is separated by isolation structure 310, the signal from photodiode 304 can be combined with signals from similar photodiodes to determine the horizontal phase and / or vertical phase of incident light, such as with respect to Figure 4B As a result, microlens layer 316 and / or a larger lens included in an image sensor having pixel sensor 300 can use the signal from photodiode 304 to focus. Using the signal from a physically partitioned photodiode is faster and less computationally intensive than other PDAF techniques.

[0103] Figure 3B A top view of pixel sensor 320 is shown. Pixel sensor 320 is similar to pixel sensor 300 and includes isolation structure 310 that separates a photodiode (not shown) of pixel sensor 320. Figure 3B As shown in FIG, the isolation structure 310 includes a shallow DTI extending from the upper left corner of the pixel sensor 320 to the lower right corner of the pixel sensor 320. Thus, the isolation structure 310 approximately divides the photodiode of the pixel sensor 320 into two.

[0104] Figure 3C A top view of pixel sensor 330 is shown. Pixel sensor 330 is similar to pixel sensor 300 and includes isolation structure 310 that separates a photodiode (not shown) of pixel sensor 330. Figure 3C As shown in FIG. 3 , the isolation structure 310 includes a plurality of HA structures (e.g., HA structure 310a, HA structure 310b, HA structure 310c, etc.) extending from the upper left corner of the pixel sensor 330 to the lower right corner of the pixel sensor 330. For example, each HA structure may partially overlap with adjacent HA structures on two sides (e.g., two sides forming the upper left corner or two sides forming the lower right corner). Therefore, the isolation structure 310 divides the photodiode of the pixel sensor 330 approximately into two.

[0105] like Figure 3C As further shown in FIG. 1 , each HA structure may have a cross-section that is approximately square (e.g., in a top view). As used herein, "square" refers to a polygon having four approximately equal sides (e.g., within a 1%, 10%, or similar error margin). Thus, the width W of the HA structure (given by Figure 3CThe width of the HA structure (denoted by W in FIG. 1 ) (e.g., at the top surface of a substrate (not shown) supporting pixel sensor 330) may be in a range of about 0.2 μm to about 1.0 μm. Selecting a width of at least 0.2 μm enables the HA structure to phase separate incident light. Selecting a width of no more than 1.0 μm reduces blocking effects on pixel sensor 330 (e.g., fewer incident photons, resulting in reduced sensitivity of pixel sensor 330).

[0106] Figure 3D A top view of pixel sensor 340 is shown. Pixel sensor 340 is similar to pixel sensor 300 and includes isolation structure 310 that separates the photodiode of pixel sensor 340 (under microlens layer 316 and color filter layer 314). Figure 3D As shown in FIG. 3 , isolation structure 310 extends from (approximately) the top center of pixel sensor 340 to (approximately) the bottom center of pixel sensor 340. Thus, isolation structure 310 approximately bisects the photodiode of pixel sensor 340 along the vertical axis. Figure 3E A cross-sectional view of a pixel sensor 340 is shown. Figure 3E An isolation structure 310 is shown in the substrate 302 that physically partitions the photodiode 304 .

[0107] Figure 3F A top view of pixel sensor 350 is shown. Pixel sensor 350 is similar to pixel sensor 300 and includes isolation structure 310 that separates the photodiode of pixel sensor 350 (under microlens layer 316 and color filter layer 314). Figure 3F As shown in , the isolation structure 310 extends across the surface of the pixel sensor 340 at an angle to the vertical axis. Figure 3F As shown in , the angle may be greater than 0° but less than 45°, and isolation structure 310 approximately bisects the photodiode of pixel sensor 350 along the vertical axis. Figure 3G A cross-sectional view of a pixel sensor 350 is shown. Figure 3G An isolation structure 310 is shown in the substrate 302 that physically partitions the photodiode 304 .

[0108] As mentioned above, Figures 3A to 3G are provided as examples. Other examples may differ from those described in Figures 3A to 3G described.

[0109] Figure 4Ais a schematic diagram of a pixel sensor 400. The pixel sensor 400 includes an isolation structure 310 that physically partitions the photodiode 304 of the pixel sensor 400. The isolation structure 310 separates incident light by phase such that the output from the photodiode 304 is based on including photons having a phase that constructively interacts with the isolation structure 310 and excluding photons having a phase that destructively interacts with the isolation structure 310.

[0110] like Figure 4A As further shown in FIG. 1 , the isolation structure 310 may form an angle with the vertical axis of the pixel sensor 400 (eg, by Figure 4A θ in θ). Angle θ may be in the range of about 0° to about 75°. This range allows phase separation around polarization along the vertical axis. Other implementations may include isolation structure 310 forming an angle θ with the horizontal axis of pixel sensor 400 ranging from about 0° to about 75°. This range allows phase separation around polarization along the horizontal axis.

[0111] Figure 4B 4 is a top view of pixel array 450. In some implementations, pixel array 450 can be configured as or included in pixel array 200 (or a portion thereof). In some implementations, pixel array 450 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0112] like Figure 4B As shown in FIG. , the pixel array 450 includes a plurality of photodiodes (eg, Figure 4B 4), each photodiode having a corresponding isolation structure (e.g., isolation structures 310-1, 310-2, 310-3, and 310-4) that separates the photodiodes. Some photodiodes (e.g., Figure 4B The other photodiodes (eg, Figure 4B The photodiodes 304-3 and 304-4 in FIG.

[0113] like Figure 4B As further shown in FIG. 4 , signals from different photodiodes may be combined to estimate a phase along a vertical direction or a horizontal direction. As shown at reference numeral 452, signals from photodiode 304-1 and / or photodiode 304-2 may be combined with signals from photodiode 304-3 and / or photodiode 304-4 to estimate a phase along a first direction (e.g., Figure 4BFor example, a signal associated with the upper left portion of photodiode 304-1 and / or photodiode 304-2 may be combined with a signal associated with the lower left portion of photodiode 304-3 and / or photodiode 304-4 to estimate the phase along the first direction. Additionally or alternatively, a signal associated with the lower right portion of photodiode 304-1 and / or photodiode 304-2 may be combined with a signal associated with the upper right portion of photodiode 304-3 and / or photodiode 304-4 to estimate the phase along the first direction. Similarly, as shown by reference numeral 454, signals from photodiode 304-1 and / or photodiode 304-2 may be combined with signals from photodiode 304-3 and / or photodiode 304-4 to estimate the phase along a second direction perpendicular to the first direction (e.g., Figure 4B 4. In some embodiments, the phase of the pixel array 450 may be estimated by measuring the phase of the pixel array 450 (e.g., a microlens layer as described herein and / or a larger lens covering multiple pixels of the pixel array 450). For example, a signal associated with the upper left portion of the photodiode 304-1 and / or the photodiode 304-2 may be combined with a signal associated with the upper right portion of the photodiode 304-3 and / or the photodiode 304-4 to estimate the phase along the second direction. Additionally or alternatively, a signal associated with the lower right portion of the photodiode 304-1 and / or the photodiode 304-2 may be combined with a signal associated with the lower left portion of the photodiode 304-3 and / or the photodiode 304-4 to estimate the phase along the second direction. Thus, a lens associated with the pixel array 450 (e.g., a microlens layer as described herein and / or a larger lens covering multiple pixels of the pixel array 450) may be adjusted based on the estimated phase. For example, a controller (e.g., a processor) associated with the pixel array 450 may generate (and send) a command to adjust the lens to reduce differences between signals associated with different portions of the photodiodes 304-1, 304-2, 304-3, and 304-4. As a result, the lens adjusts faster and with less power and processing resources than using other PDAF techniques.

[0114] In some implementations, the above adjustments may be performed iteratively. For example, after generating (and sending) a command to adjust the lens, the controller may receive a combined update signal from the photodiodes to estimate an updated phase. Thus, the controller may generate (and send) additional commands to adjust the lens based on the updated phase. This process may continue until the estimated phase meets a threshold (e.g., until the difference between the signals associated with different portions of the photodiodes 304-1, 304-2, 304-3, and 304-4 meets a threshold).

[0115] As mentioned above, FIG. 4A to FIG. 4B are provided as examples. Other examples may differ from those described in FIG. 4A to FIG. 4B described.

[0116] FIG. 5A to FIG. 5H is a schematic diagram of an example pixel array described herein. Figure 5A A top view of pixel array 500 is shown. In some implementations, pixel array 500 can be configured as or included in pixel array 200 (or a portion thereof). In some implementations, pixel array 500 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSICMOS image sensor, or another type of image sensor.

[0117] like Figure 5A As shown in FIG. , the pixel array 500 includes a plurality of photodiodes (eg, Figure 5A 4), each photodiode having a corresponding isolation structure (e.g., isolation structures 310-1, 310-2, 310-3, and 310-4) that separates the photodiodes. The photodiodes within a column (e.g., Figure 5A The photodiodes 304-1 and 304-4 in the same column are separated by an isolation structure that forms a positive acute angle with the horizontal axis of the pixel array 500 to separate the photodiodes in another column (eg, Figure 5A 304-2 and 304-3 in FIG.

[0118] Figure 5B A top view of pixel array 510 is shown. Pixel array 510 is similar to pixel array 500, except that all photodiodes are separated by isolation structures that form a positive acute angle with a vertical axis of pixel array 510. Figure 5C A top view of pixel array 520 is shown. Pixel array 520 is similar to pixel array 500, except that all photodiodes are separated by isolation structures that form a positive acute angle with the horizontal axis of pixel array 520.

[0119] Figure 5D Pixel array 530 is shown in a top view. Pixel array 530 is similar to pixel array 500, except that the photodiodes within a row are separated by isolation structures that form a positive acute angle with the vertical axis of pixel array 530 (e.g., Figure 5D 304-1 and 304-2 in the same row), and the photodiodes in another row are separated by an isolation structure that forms a positive acute angle with the horizontal axis of the pixel array 530 (e.g., Figure 5D The photodiodes 304-3 and 304-4 in FIG.

[0120] Figure 5EPixel array 540 is shown in a top view. Pixel array 540 is similar to pixel array 500, except that the photodiodes along a diagonal line (e.g., Figure 5E 304-1 and 304-3 in the pixel array 500), and the photodiodes along another diagonal line (eg, Figure 5E 304-2 and 304-4 in FIG.

[0121] Fig. 5F A top view of pixel array 550 is shown. Pixel array 550 is similar to pixel array 520, except that the isolation structures divide the photodiodes approximately into one-third and two-thirds. For example, each isolation structure can divide the photodiode into a top first portion (e.g., ranging from about 30% to about 40% of the total surface area of ​​the top surface of the photodiode) and a bottom second portion (e.g., ranging from about 60% to about 70% of the total surface area of ​​the top surface of the photodiode).

[0122] Figure 5G A top view of pixel array 560 is shown. Pixel array 560 is similar to pixel array 550, except that the isolation structures divide the photodiodes into approximately two-thirds and one-third. For example, each isolation structure can divide the photodiode into a top first portion (e.g., ranging from about 60% to about 70% of the total surface area of ​​the top surface of the photodiode) and a bottom second portion (e.g., ranging from about 30% to about 40% of the total surface area of ​​the top surface of the photodiode).

[0123] Figure 5H FIG. 5 is a top view of the pixel array 570. Figure 5H As shown in FIG. , the pixel array 570 includes a plurality of photodiodes (eg, Figure 5H 4). The photodiodes 304-1, 304-2, 304-3, and 304-4 in the photodiode array are each provided with two corresponding isolation structures that separate the photodiodes (e.g., isolation structures 310-1 and 310-2 for photodiode 304-1, isolation structures 310-3 and 310-4 for photodiode 304-2, isolation structures 310-5 and 310-6 for photodiode 304-3, and isolation structures 310-7 and 310-8 for photodiode 304-4).

[0124] Each pair of isolation structures can divide the photodiode into three. For example, each photodiode can include two isolation structures that separate the photodiode into a first portion ranging from about 30% to about 40% of the total surface area of ​​the top surface of the photodiode, a second portion ranging from about 30% to about 40% of the total surface area of ​​the top surface of the photodiode, and a third portion ranging from about 30% to about 40% of the total surface area of ​​the top surface of the photodiode.

[0125] The above pixel array can be used to adjust the lens, such as in combination with Figure 4B A controller (e.g., a processor) associated with the pixel array may estimate a phase and perform adjustments based on the estimated phase. The controller combines the signals from the photodiodes, such as by combining Figure 4B The method of claim 1, wherein the signals associated with different portions of the photodiode are determined based on a data structure indicating a pattern of isolation structures in the photodiode. The above pixel array may be selected as a design choice. In some implementations, the pixel array may include a single array (e.g., having a combination of Figure 5A The first part and the combination Figure 5B The array of the second portion described, as well as other examples) has multiple isolation structures with different orientations.

[0126] As mentioned above, FIG. 5A to FIG. 5H are provided as examples. Other examples may differ from FIG. 5A to FIG. 5H described.

[0127] 6A to 6F 600 is a schematic diagram of an example implementation 600 described herein. Example implementation 600 may be an example process for forming pixel sensor 300 having an isolation structure with a physically partitioned photodiode. A pixel sensor formed using example implementation 600 may be included in a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0128] like Fig. 6A As shown in , an example process for forming a pixel sensor can be performed in conjunction with a substrate 302. As described above, the substrate 302 can include a semiconductor die substrate, a semiconductor wafer, a stacked semiconductor wafer, or another type of substrate in which a semiconductor pixel can be formed. For example, the substrate 302 can be formed of silicon (Si) (e.g., a silicon substrate), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), SOI, or another type of semiconductor material capable of generating charge from photons of incident light. In some implementations, the substrate 302 is formed of a doped material such as doped silicon (e.g., a p-type doped material or an n-type doped material).

[0129] like Figure 6B, a photodiode 304 can be formed in a substrate 302. For example, an ion implantation tool can dope one or more portions of the substrate 302 using ion implantation techniques to form an n-type region and / or a p-type region of the photodiode 304, thereby forming a pn junction of the photodiode 304. For example, the ion implantation tool can dope the substrate 302 with an n-type dopant to form an n-type region, and can dope the substrate 302 with a p-type dopant to form a p-type portion of the pn junction. In some implementations, the photodiode 304 is formed using another technique such as diffusion.

[0130] like Figure 6C , the etching tool 108 can form a recess 602 in the substrate 302 and at least partially surround the photodiode 304. In some implementations, the deposition tool 102 can form a photoresist layer above and / or on the front side surface of the substrate 302, the exposure tool 104 can expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and the development tool 106 can develop and remove a portion of the photoresist layer to expose the pattern. Thus, the etching tool 108 can etch a portion of the substrate 302 adjacent to the photodiode 304. For example, the etching tool 108 can use a wet etching technique, a dry etching technique, a plasma enhanced etching technique, and / or another type of etching technique to etch the portion of the substrate 302. After the etching tool 108 etches the substrate 302, the photoresist removal tool 114 can remove the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique).

[0131] In addition, if Figure 6C As shown in FIG. 1 , the etching tool 108 may form a recess 604 in the substrate 302 and extend at least partially into the photodiode 304. The recess 604 may include a shallow trench (e.g., for a shallow DTI structure, such as a combination of Figure 3B described) or a series of approximately pyramidal grooves (e.g., for multiple HA structures, such as combined Figure 3C In some implementations, the pattern exposed by the developer tool 106 may also allow the etch tool 108 to form the recess 604 in addition to the recess 602 .

[0132] like Fig.6D , liner layer 306 can be formed over substrate 302. For example, deposition tool 102 can form liner layer 306 over and / or on the front side surface of substrate 302 (and thus on the bottom surface and sidewalls of recess 602 and recess 604). In some implementations, deposition tool 102 can use a spin-on coating technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique to form liner layer 306. Some implementations may include a different material deposited in recess 602 compared to recess 604.

[0133] like Fig. 6E As shown in , recess 602 and recess 604 may be filled with a dielectric material to form DTI structure 308 and isolation structure 310, respectively. Deposition tool 102 may deposit the dielectric material using a spin-on coating technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique. In some implementations, the dielectric material may overflow recess 602 and recess 604, so that planarization tool 110 uses a CMP technique to remove the dielectric material outside recess 602 and recess 604. Some implementations may include a different material for forming DTI structure 308 compared to isolation structure 310.

[0134] like Fig. 6F As shown in FIG. 1 , a buffer layer 312 may be formed on the top surface of the substrate 302 above the DTI structure 308 and the isolation structure 310. The deposition tool 102 may use a CVD technique, a PVD technique, an ALD technique, or another type of deposition technique to deposit the buffer layer 312. The planarization tool 110 may planarize the buffer layer 312 after depositing the buffer layer 312. Fig. 6F As shown in , the color filter layer 314 can be formed on the top surface of the substrate 302 above the buffer layer 312. The deposition tool 102 can use CVD technology, PVD technology, ALD technology, or another type of deposition technology to deposit the color filter layer 314. The planarization tool 110 can planarize the color filter layer 314 after depositing the color filter layer 314. In addition, as shown in FIG. Fig. 6F As shown in FIG, microlens layer 316 may be formed on a top surface of substrate 302 above color filter layer 314. Deposition tool 102 may deposit microlens layer 316 using a CVD technique, a PVD technique, an ALD technique, or another type of deposition technique.

[0135] As mentioned above, 6A to 6F are provided as examples. Other examples may differ from those described in 6A to 6F described.

[0136] FIG. 7A to FIG. 7G is a schematic diagram of an example implementation 700 described herein. Example implementation 700 may be an example process for forming a pixel sensor 300 having an isolation structure of a physically partitioned photodiode. A pixel sensor formed using example implementation 700 may be included in a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor. In example implementation 700, a DTI structure is formed before the isolation structure of the physically partitioned photodiode.

[0137] like Fig. 7A As shown in FIG. , example implementation 700 may include combining FIG. 6A to FIG. 6B The process described. Fig. 7AAs further shown in FIG. 1 , the etching tool 108 can form a recess 602 in the substrate 302 and at least partially surround the photodiode 304. In some implementations, the deposition tool 102 can form a photoresist layer above and / or on the front side surface of the substrate 302, the exposure tool 104 can expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and the development tool 106 can develop and remove a portion of the photoresist layer to expose the pattern. Thus, the etching tool 108 can etch a portion of the substrate 302 adjacent to the photodiode 304. For example, the etching tool 108 can use a wet etching technique, a dry etching technique, a plasma enhanced etching technique, and / or another type of etching technique to etch the portion of the substrate 302. After the etching tool 108 etches the substrate 302, the photoresist removal tool 114 can remove the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique).

[0138] like Figure 7B , a liner layer 306 can be formed over the substrate 302. For example, the deposition tool 102 can form the liner layer 306 over and / or on the front side surface of the substrate 302 (and thus on the bottom surface and sidewalls of the recess 602). In some implementations, the deposition tool 102 can form the liner layer 306 using a spin-on coating technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique.

[0139] like Figure 7C As shown in FIG. 3 , the recess 602 may be filled with a dielectric material to form the DTI structure 308. The deposition tool 102 may deposit the dielectric material using a spin-on coating technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique. In some implementations, the dielectric material may overflow the recess 602, so that the planarization tool 110 removes the dielectric material outside the recess 602 using a CMP technique.

[0140] like Fig.7D As shown in FIG. 1 , the etching tool 108 may form a recess 604 in the substrate 302 and extend at least partially into the photodiode 304. The recess 604 may include a shallow trench (e.g., for a shallow DTI structure, such as a combination of Figure 3B described) or a series of approximately pyramidal grooves (e.g., for multiple HA structures, such as combined Figure 3C304). In some implementations, deposition tool 102 may form a photoresist layer over and / or on the front side surface of substrate 302, exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and development tool 106 may develop and remove portions of the photoresist layer to expose the pattern. Thus, etching tool 108 may etch a portion of substrate 302 over photodiode 304. For example, etching tool 108 may use a wet etching technique, a dry etching technique, a plasma enhanced etching technique, and / or another type of etching technique to etch a portion of substrate 302. After etching tool 108 etches substrate 302, photoresist removal tool 114 may remove the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique).

[0141] like Fig. 7E As shown in FIG. 6 , a liner layer 306 can be formed in the recess 604. In some implementations, the deposition tool 102 can use a spin-on coating technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique to form the liner layer 306. In some implementations, the planarization tool 110 uses a CMP technique to remove a portion of the liner layer 306 formed outside the recess 604.

[0142] like Figure 7F As shown in , the recess 604 may be filled with a dielectric material to form the isolation structure 310. The deposition tool 102 may deposit the dielectric material using a spin-on coating technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique. In some implementations, the dielectric material may overflow the recess 604, so that the planarization tool 110 uses a CMP technique to remove the dielectric material outside the recess 604.

[0143] like Figure 7G As shown in FIG. 1 , a buffer layer 312 may be formed on the top surface of the substrate 302 above the DTI structure 308 and the isolation structure 310. The deposition tool 102 may use a CVD technique, a PVD technique, an ALD technique, or another type of deposition technique to deposit the buffer layer 312. The planarization tool 110 may planarize the buffer layer 312 after depositing the buffer layer 312. Figure 7G As shown in , the color filter layer 314 can be formed on the top surface of the substrate 302 above the buffer layer 312. The deposition tool 102 can use CVD technology, PVD technology, ALD technology, or another type of deposition technology to deposit the color filter layer 314. The planarization tool 110 can planarize the color filter layer 314 after depositing the color filter layer 314. In addition, as shown in FIG. Figure 7GAs shown in FIG, microlens layer 316 may be formed on a top surface of substrate 302 above color filter layer 314. Deposition tool 102 may deposit microlens layer 316 using a CVD technique, a PVD technique, an ALD technique, or another type of deposition technique.

[0144] As mentioned above, FIG. 7A to FIG. 7G are provided as examples. Other examples may differ from those described in FIG. 7A to FIG. 7G described.

[0145] FIG. 8A to FIG. 8G 8 is a schematic diagram of an example implementation 800 described herein. Example implementation 800 may be an example process for forming a pixel sensor 300 having an isolation structure of a physically partitioned photodiode. A pixel sensor formed using example implementation 800 may be included in a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor. In example implementation 800, a DTI structure is formed after the isolation structure of the physically partitioned photodiode.

[0146] like Fig. 8A As shown in FIG. 8 , an example implementation 800 may include combining FIG. 6A to FIG. 6B The process described. Fig. 8A As further shown in FIG. 1 , the etching tool 108 may form a recess 604 in the substrate 302 and extend at least partially into the photodiode 304. The recess 604 may include a shallow trench (e.g., for a shallow DTI structure, such as in combination with Figure 3B described) or a series of approximately pyramidal grooves (e.g., for multiple HA structures, such as combined Figure 3C 304). In some implementations, deposition tool 102 may form a photoresist layer over and / or on the front side surface of substrate 302, exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and development tool 106 may develop and remove a portion of the photoresist layer to expose the pattern. Thus, etching tool 108 may etch a portion of substrate 302 over photodiode 304. For example, etching tool 108 may use a wet etching technique, a dry etching technique, a plasma enhanced etching technique, and / or another type of etching technique to etch a portion of substrate 302. After etching tool 108 etches substrate 302, photoresist removal tool 114 may remove the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or other techniques).

[0147] like Figure 8B, a liner layer 306 can be formed over the substrate 302. For example, the deposition tool 102 can form the liner layer 306 over and / or on the front side surface of the substrate 302 (and thus on the bottom surface and sidewalls of the recess 604). In some implementations, the deposition tool 102 can form the liner layer 306 using a spin-on coating technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique.

[0148] like Figure 8C As shown in , the recess 604 may be filled with a dielectric material to form the isolation structure 310. The deposition tool 102 may deposit the dielectric material using a spin-on coating technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique. In some implementations, the dielectric material may overflow the recess 604, so that the planarization tool 110 uses a CMP technique to remove the dielectric material outside the recess 604.

[0149] like Fig.8D , the etching tool 108 can form a recess 602 in the substrate 302 and at least partially surround the photodiode 304. In some implementations, the deposition tool 102 can form a photoresist layer above and / or on the front side surface of the substrate 302, the exposure tool 104 can expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and the development tool 106 can develop and remove a portion of the photoresist layer to expose the pattern. Thus, the etching tool 108 can etch a portion of the substrate 302 adjacent to the photodiode 304. For example, the etching tool 108 can use a wet etching technique, a dry etching technique, a plasma enhanced etching technique, and / or another type of etching technique to etch the portion of the substrate 302. After the etching tool 108 etches the substrate 302, the photoresist removal tool 114 can remove the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or another technique).

[0150] like Fig. 8E As shown in FIG. 6 , a liner layer 306 can be formed in the recess 602. In some implementations, the deposition tool 102 can use a spin-on coating technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique to form the liner layer 306. In some implementations, the planarization tool 110 uses a CMP technique to remove a portion of the liner layer 306 formed outside the recess 602.

[0151] like Figure 8F As shown in , the recess 604 may be filled with a dielectric material to form the isolation structure 310. The deposition tool 102 may deposit the dielectric material using a spin-on coating technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique. In some implementations, the dielectric material may overflow the recess 604, so that the planarization tool 110 uses a CMP technique to remove the dielectric material outside the recess 604.

[0152] like Figure 8G As shown in FIG. 1 , a buffer layer 312 may be formed on the top surface of the substrate 302 above the DTI structure 308 and the isolation structure 310. The deposition tool 102 may use a CVD technique, a PVD technique, an ALD technique, or another type of deposition technique to deposit the buffer layer 312. The planarization tool 110 may planarize the buffer layer 312 after depositing the buffer layer 312. Figure 8G As shown in , the color filter layer 314 can be formed on the top surface of the substrate 302 above the buffer layer 312. The deposition tool 102 can use CVD technology, PVD technology, ALD technology, or another type of deposition technology to deposit the color filter layer 314. The planarization tool 110 can planarize the color filter layer 314 after depositing the color filter layer 314. In addition, as shown in FIG. Figure 8G As shown in FIG, microlens layer 316 may be formed on a top surface of substrate 302 above color filter layer 314. Deposition tool 102 may deposit microlens layer 316 using a CVD technique, a PVD technique, an ALD technique, or another type of deposition technique.

[0153] As mentioned above, FIG. 8A to FIG. 8G are provided as examples. Other examples may differ from those described in FIG. 8A to FIG. 8G described.

[0154] 9A to 9D is a schematic diagram of an example pixel array described herein. Fig.9A A top view of pixel array 900 is shown. In some implementations, pixel array 900 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0155] like Fig.9A As shown in FIG. 1 , pixel array 900 includes a plurality of pixel sensors having an isolation structure (e.g., pixel sensor 902) and a plurality of pixel sensors not having an isolation structure (e.g., pixel sensor 904). The pixel sensors having the isolation structure are grouped into four (e.g., as combined with FIG. 5A to FIG. 5H Distributing clusters throughout pixel array 900 can improve the accuracy of phase estimation. Pixel array 900 is shown with six clusters of pixel sensors having isolation structures, but additional or fewer clusters may be used. Sensors without isolation structures may exhibit slightly improved sensitivity relative to pixel sensors with isolation structures.

[0156] Fig. 9BA top view of pixel array 910 is shown. In some implementations, pixel array 910 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0157] like Fig. 9B As shown in , pixel array 910 includes a plurality of pixel sensors with isolation structures (e.g., pixel sensor 902) and a plurality of pixel sensors without isolation structures (e.g., pixel sensor 904). The pixel sensors with isolation structures are clustered in columns on the top and bottom of pixel array 910. Pixel array 910 is shown with five columns of pixel sensors with isolation structures, but additional or fewer columns may be used. As a result, pixel sensors with isolation structures may be formed separately from image sensors without isolation structures and combined in a single image sensor, which may reduce manufacturing time compared to forming pixel sensors with isolation structures and without isolation structures together.

[0158] Fig. 9C A top view of pixel array 920 is shown. In some implementations, pixel array 920 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0159] like Fig. 9C As shown in , pixel array 920 includes a plurality of pixel sensors with isolation structures (e.g., pixel sensor 902) and a plurality of pixel sensors without isolation structures (e.g., pixel sensor 904). The pixel sensors with isolation structures are clustered in rows on both sides of pixel array 920. Pixel array 920 is shown with five rows of pixel sensors with isolation structures, but additional or fewer rows may be used. As a result, pixel sensors with isolation structures may be formed separately from image sensors without isolation structures and combined into a single image sensor, which may reduce manufacturing time compared to forming pixel sensors with isolation structures and without isolation structures together.

[0160] Fig.9D A top view of the pixel array 930 is shown. In some implementations, the pixel array 930 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor. Fig.9DAs shown in , pixel array 900 includes all pixel sensors having isolation structures (e.g., pixel sensor 902) and no pixel sensors having no isolation structures (e.g., no pixel sensor 904). As a result, pixel array 900 can be formed on a single wafer and / or using a single process, which reduces manufacturing time compared to using separate processes to form pixel sensors having isolation structures and pixel sensors having no isolation structures.

[0161] As mentioned above, 9A to 9D are provided as examples. Other examples may differ from those described in 9A to 9D described.

[0162] Fig.10 1 is a schematic diagram of example components of the apparatus 1000 described herein. In some implementations, one or more of the semiconductor processing tools 102-116 and / or the wafer / die transport tool 118 may include one or more apparatuses 1000 and / or one or more components of the apparatus 1000. Fig.10 As shown in , the device 1000 may include a bus 1010 , a processor 1020 , a memory 1030 , an input component 1040 , an output component 1050 , and a communication component 1060 .

[0163] The bus 1010 may include one or more components that enable wired and / or wireless communications between components of the device 1000. The bus 1010 may include: Fig.10 Two or more components of an apparatus 1020 are coupled together, such as by operational coupling, communication coupling, electronic coupling, and / or electrical coupling. Processor 1020 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application specific integrated circuit, and / or another type of processing component. Processor 1020 is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 1020 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0164] The memory 1030 may include volatile and / or non-volatile memory. For example, the memory 1030 may include random access memory (RAM), read only memory (ROM), a hard drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 1030 may include internal memory (e.g., RAM, ROM, or hard drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 1030 may be a non-transitory computer-readable medium. The memory 1030 stores information, instructions, and / or software (e.g., one or more software applications) related to the operation of the device 1000. In some implementations, the memory 1030 may include one or more memories coupled to one or more processors (e.g., processor 1020), such as via the bus 1010.

[0165] Input components 1040 enable device 1000 to receive inputs, such as user inputs and / or sensory inputs. For example, input components 1040 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, an accelerometer, a gyroscope, and / or an actuator. Output components 1050 enable device 1000 to provide outputs, such as through a display, a speaker, and / or a light emitting diode. Communication components 1060 enable device 1000 to communicate with other devices through wired connections and / or wireless connections. For example, communication components 1060 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0166] The device 1000 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1030) may store an instruction set (e.g., one or more instructions or codes) for execution by the processor 1020. The processor 1020 may execute the instruction set to perform one or more operations or processes described herein. In some implementations, execution of the instruction set by one or more processors 1020 causes one or more processors 1020 and / or the device 1000 to perform one or more operations or processes described herein. In some implementations, fixed-line circuitry is used instead of instructions or in combination with instructions to perform one or more operations or processes described herein. Additionally or otherwise, the processor 1020 may be used to perform one or more operations or processes described herein. Therefore, the implementations described herein are not limited to any specific combination of hardware circuitry and software.

[0167] Fig.10 The number and configuration of components shown in the drawings are provided as examples. Device 1000 may include additional components, fewer components, different components, or different components. Fig.10 Additionally or alternatively, a set of components (eg, one or more components) of device 1000 may perform one or more functions described as being performed by another set of components of device 1000.

[0168] Fig.11 is a flow chart of an example process 1100 associated with forming a structure for phase detection autofocus. In some implementations, Fig.11 One or more process blocks of are performed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-116). Additionally or alternatively, Fig.11 One or more process blocks may be executed by one or more components of the apparatus 1000 , such as the processor 1020 , the memory 1030 , the input component 1040 , the output component 1050 , and / or the communication component 1060 .

[0169] like Fig.11 As shown in FIG. 1 , process 1100 may include forming a plurality of photodiodes in a substrate (block 1110 ). For example, one or more of semiconductor processing tools 102 - 116 may form a plurality of photodiodes 304 in substrate 302 , as described herein.

[0170] like Fig.11 As further shown in FIG. 1 , process 1100 may include forming a DTI structure at least partially surrounding the plurality of photodiodes (block 1120). For example, one or more of semiconductor processing tools 102 - 116 may form DTI structure 308 at least partially surrounding the plurality of photodiodes 304, as described herein.

[0171] like Fig.11 As further shown in FIG. 1 , process 1100 may include forming at least one isolation structure in at least one photodiode of the plurality of photodiodes to separate light entering the at least one photodiode in phase (block 1130). For example, one or more of semiconductor processing tools 102-116 may form at least one isolation structure 310 in at least one photodiode of the plurality of photodiodes 304 to separate light entering the at least one photodiode in phase, as described herein.

[0172] Process 1100 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0173] In a first implementation, forming the DTI structure 308 includes forming a trench 602 at least partially surrounding the plurality of photodiodes 304 , forming a liner layer 306 on sidewalls of the trench 602 , and filling the trench 602 with a dielectric material to form the DTI structure 308 .

[0174] In a second embodiment, alone or in combination with the first embodiment, forming at least one isolation structure 310 includes forming at least one trench 604 in at least one photodiode, forming a liner layer 306 on a sidewall of the at least one trench 604, and filling the at least one trench 604 with a dielectric material to form at least one isolation structure 310.

[0175] In a third implementation, alone or in combination with one or more of the first and second implementations, forming at least one isolation structure includes forming a plurality of trenches 604 in at least one photodiode, and forming a plurality of HA structures 310 arranged along at least one line in the plurality of trenches 604 .

[0176] In a fourth implementation, alone or in combination with one or more of the first to third implementations, the process 1100 includes forming the trenches 602 and 604 for the DTI structure 308 and the at least one isolation structure 310 in the same etch cycle.

[0177] In a fifth implementation, alone or in combination with one or more of the first to fourth implementations, the process 1100 includes forming at least one first trench 602 for the DTI structure 308 in a first etch cycle and forming at least one second trench 604 for at least one isolation structure 310 in a second etch cycle.

[0178] although Fig.11 Example blocks of process 1100 are shown, but in some implementations, process 1100 includes additional blocks, fewer blocks, different blocks, or blocks that are different from the blocks described above. Fig.11 Additionally or alternatively, two or more of the blocks of process 1100 may be performed in parallel.

[0179] Fig.12 is a flow chart of an example process 1200 associated with using the phase detection autofocus structure described herein. In some implementations, Fig.12 One or more process blocks in are performed by an image sensor device (e.g., including one or more pixels described herein). Additionally or alternatively, Fig.12 One or more process blocks in the process may be executed by one or more components of the apparatus 1000 , such as the processor 1020 , the memory 1030 , the input component 1040 , the output component 1050 , and / or the communication component 1060 .

[0180] like Fig.12As shown in FIG. 1 , process 1200 may include receiving a first signal from a first photodiode physically partitioned by at least one isolation structure (block 1210). For example, an image sensor device may receive a first signal from a first photodiode 304-1 physically partitioned by at least one isolation structure 310-1, as described herein.

[0181] like Fig.12 As further shown in FIG. 1 , process 1200 may include receiving a second signal at a second photodiode physically partitioned by at least one isolation structure (block 1220). For example, an image sensor device may receive a second signal at a second photodiode 304-2 physically partitioned by at least one isolation structure 310-2, as described herein.

[0182] like Fig.12 As further shown in , process 1200 may include combining the first signal with the second signal to estimate the phase along the first direction (block 1230). For example, the image sensor device may combine the first signal with the second signal to estimate the phase along the first direction as described herein.

[0183] like Fig.12 As further shown in , process 1200 may include generating a command for adjusting the lens based on the phase along the first direction (block 1240). For example, the image sensor device may generate a command for adjusting the lens based on the phase along the first direction, as described herein.

[0184] Process 1200 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0185] In some implementations, process 1200 includes receiving a third signal by a third photodiode 304-3 physically partitioned by at least one isolation structure 310-3, and combining the first signal or the second signal with the third signal to estimate a phase along a second direction perpendicular to the first direction, whereby a command for adjusting the lens is further based on the phase along the second direction.

[0186] although Fig.12 Example blocks of process 1200 are shown, but in some implementations, process 1200 includes additional blocks, fewer blocks, different blocks, or blocks that are different from the blocks described above. Fig.12 1200. Additionally or alternatively, two or more of the processes 1200 may be performed in parallel.

[0187] In this manner, the intra-pixel separation structure can separate the photodiodes of the pixel array into multiple regions. As a result, the lens of the image sensor device can be focused by using the combined signals associated with different portions of the photodiodes. As a result, the lens can be focused faster and with fewer pixels in the pixel array, which saves power, processing resources, and raw materials.

[0188] As described in more detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes an array of a plurality of pixel sensors, the array of pixel sensors including photodiodes physically partitioned by at least one isolation structure, wherein incident light to the photodiodes is separated by at least one isolation structure. The semiconductor device includes a deep trench isolation (DTI) structure at least partially surrounding the pixel sensors of the array.

[0189] In some embodiments, at least one isolation structure comprises a plurality of highly absorbent structures.

[0190] In some embodiments, each of the highly absorbent structures has a width ranging from about 0.2 microns to about 1.0 microns.

[0191] In some embodiments, at least one isolation structure comprises a shallow deep trench isolation structure.

[0192] In some embodiments, at least one isolation structure has an angle ranging from about 0 degrees to about 75 degrees relative to an axis of the photodiode.

[0193] In some embodiments, the axis of the photodiode is the vertical axis of the array.

[0194] In some embodiments, the axis of the photodiodes is the horizontal axis of the array.

[0195] In some implementations, the at least one isolation structure comprises a single isolation structure that approximately bisects the photodiode.

[0196] In some implementations, the at least one isolation structure includes a single isolation structure that divides the photodiode into approximately one-third and two-thirds.

[0197] In some embodiments, the at least one isolation structure includes two isolation structures that approximately divide the photodiode into thirds.

[0198] In some embodiments, the array includes additional photodiodes that lack at least one isolation structure.

[0199] In some implementations, the array includes one or more additional photodiodes that are physically partitioned.

[0200] As described in more detail above, some implementations described herein provide a semiconductor device including an array of a plurality of pixel sensors and a deep trench isolation structure. The array of pixel sensors includes a photodiode physically partitioned by at least one isolation structure, wherein incident light to the photodiode is separated by the at least one isolation structure, wherein the at least one isolation structure has an angle ranging from about 0 degrees to about 75 degrees relative to an axis of the photodiode. A deep trench isolation structure at least partially surrounds the pixel sensors of the array.

[0201] In some embodiments, the axis of the photodiode is the vertical axis of the array.

[0202] In some embodiments, the axis of the photodiodes is the horizontal axis of the array.

[0203] In some implementations, the at least one isolation structure comprises a single isolation structure that approximately bisects the photodiode.

[0204] As described in more detail above, some implementations described herein provide a semiconductor device including an array of a plurality of pixel sensors and a deep trench isolation structure. The array of pixel sensors includes a photodiode physically partitioned by at least one isolation structure, wherein incident light to the photodiode is separated by the at least one isolation structure, wherein the at least one isolation structure includes a single isolation structure that divides the photodiode approximately into one-third and two-thirds. A deep trench isolation structure at least partially surrounds the pixel sensors of the array.

[0205] In some embodiments, the array includes additional photodiodes that lack at least one isolation structure.

[0206] As described in more detail above, some implementations described herein provide a method. The method includes forming a plurality of photodiodes in a substrate. The method includes forming a deep trench isolation (DTI) structure at least partially surrounding the plurality of photodiodes. The method includes forming at least one isolation structure in at least one photodiode of the plurality of photodiodes to phase separate light entering the at least one photodiode.

[0207] In some embodiments, the step of forming a deep trench isolation structure includes the steps of: forming a trench at least partially surrounding the photodiodes; forming a liner layer on multiple sidewalls of the trench; and filling the trench with a dielectric material to form a deep trench isolation structure.

[0208] In some embodiments, the step of forming at least one isolation structure includes the following steps: forming at least one trench in at least one photodiode; forming a liner layer on multiple sidewalls of the at least one trench; and filling the at least one trench with a dielectric material to form at least one isolation structure.

[0209] In some embodiments, the step of forming at least one isolation structure includes the steps of: forming a plurality of trenches in at least one photodiode; and forming a plurality of high absorption structures in the trenches, wherein the high absorption structures are arranged along at least one line.

[0210] In some embodiments, the method further comprises the step of forming a plurality of trenches for the deep trench isolation structure and the at least one isolation structure in the same etching cycle.

[0211] In some embodiments, the method further comprises the steps of: forming at least one first trench for a deep trench isolation structure in a first etching cycle; and forming at least one second trench for at least one isolation structure in a second etching cycle.

[0212] As described in more detail above, some implementations described herein provide a method. The method includes receiving a first signal from a first photodiode physically partitioned by at least one isolation structure. The method includes receiving a second signal from a second photodiode physically partitioned by at least one isolation structure. The method includes combining the first signal with the second signal to estimate a phase along a first direction. The method includes generating a command to adjust a lens based on the phase along the first direction.

[0213] In some embodiments, the method further includes the following steps: receiving a plurality of third signals by a third photodiode physically partitioned by at least one isolation structure; and combining these first signals or these second signals with these third signals to estimate a phase along a second direction perpendicular to the first direction, wherein the command for adjusting the lens is further based on the phase along the second direction.

[0214] As used herein, "satisfying a threshold value" may refer to a value greater than a threshold value, greater than or equal to a threshold value, less than a threshold value, less than or equal to a threshold value, equal to a threshold value, not equal to a threshold value, or the like, depending on the context.

[0215] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: An array of a plurality of pixel sensors comprising: a photodiode physically partitioned by at least one isolation structure, wherein incident light to the photodiode is separated by the at least one isolation structure; and A deep trench isolation structure at least partially surrounds the plurality of pixel sensors of the array.

2. The semiconductor device according to claim 1, wherein The at least one isolation structure comprises a plurality of high absorption structures.

3. The semiconductor device according to claim 2, wherein: Each of the plurality of highly absorbent structures has a width ranging from 0.2 micrometers to 1.0 micrometers.

4. The semiconductor device according to claim 1, wherein: The at least one isolation structure includes a shallow deep trench isolation structure.

5. A semiconductor device, characterized in that: Include: An array of a plurality of pixel sensors comprising: a photodiode physically partitioned by at least one isolation structure, wherein incident light to the photodiode is separated by the at least one isolation structure, wherein The at least one isolation structure has an angle ranging from 0 degrees to 75 degrees relative to an axis of the photodiode; and A deep trench isolation structure at least partially surrounds the plurality of pixel sensors of the array.

6. The semiconductor device according to claim 5, wherein: The axis of the photodiode is a vertical axis of the array.

7. The semiconductor device according to claim 5, wherein: The axis of the photodiode is a horizontal axis of the array.

8. The semiconductor device according to claim 5, wherein: The at least one isolation structure includes a single isolation structure that approximately divides the photodiode into two.

9. A semiconductor device, characterized in that: Include: An array of a plurality of pixel sensors comprising: a photodiode physically partitioned by at least one isolation structure, wherein incident light to the photodiode is separated by the at least one isolation structure, wherein The at least one isolation structure includes a single isolation structure that divides the photodiode into approximately one-third and two-thirds; and A deep trench isolation structure at least partially surrounds the plurality of pixel sensors of the array.

10. The semiconductor device according to claim 9, wherein: The array includes an additional photodiode lacking at least one isolation structure.

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