Image sensing device

Abstract

An image sensing device includes a pixel sensor array including a plurality of pixel sensors. The plurality of transistors may be electrically connected to a back-end process region of the image sensing device. The image sensing device may also include a bonding pad region including a bonding pad. A dielectric plug may surround a portion of the bond pad and may extend completely through the semiconductor device region to provide electrical, thermal, and / or optical isolation for pixel sensors of the pixel sensor array. Additionally and / or alternatively, one or more capacitors in a BEOL region of an image sensing device. The one or more capacitors may enable photocurrent generated by the one or more pixel sensors to be transferred directly from the one or more source follower transistors to the one or more capacitors for storage.

Description

Technical Field

[0001] The embodiments of the present disclosure are generally directed to an image sensing device. Background Art

[0002] A complementary metal oxide semiconductor (CMOS) image sensor may include a plurality of pixel sensors. A pixel sensor of a CMOS image sensor may include a transfer gate transistor, which may include a photodiode and a transfer gate, wherein the photodiode is configured to convert photons of incident light into a photocurrent of electrons, and the transfer gate is configured to control the flow of the photocurrent between the photodiode and a drain region. The drain region may be configured to receive the photocurrent so that the photocurrent may be measured and / or transferred to other regions of the CMOS image sensor. Utility Model Content

[0003] An image sensing device includes a sensing die and a circuit die. The circuit die is bonded to the sensing die at a bonding interface, and the sensing die includes a pixel sensor, and the pixel sensor includes a sensing region and a control circuit region. The sensing region includes a photodiode located in the device region of the sensing die. The control circuit region is located below the device region and includes a transfer gate transistor, a reset gate transistor, a plurality of source follower transistors, a capacitor, and a column selection transistor. The reset gate transistor is electrically connected to the transfer gate transistor, the plurality of source follower transistors are electrically connected to the transfer gate transistor and the reset gate transistor, the capacitor is electrically connected to these source follower transistors, and the column selection transistor is electrically connected to the capacitor.

[0004] An image sensing device includes a sensing die, a circuit die, and a capacitor. The sensing die includes a photodiode in a sensing region of a pixel sensor, wherein the pixel sensor is included in a pixel sensor array; a transfer gate transistor, included in a first control circuit region of the sensing die and electrically connected to the photodiode; a reset gate transistor, included in the first control circuit region and electrically connected to the transfer gate transistor; and a column selection transistor, included in the first control circuit region. The circuit die includes a plurality of source follower transistors, included in a second control circuit region associated with the pixel sensor. A capacitor is included in at least one of the sensing die or the circuit die, wherein the capacitor is electrically connected to the column selection transistor and the source follower transistors.

[0005] An image sensing device includes a sensing die and a circuit die. The sensing die includes a pixel sensor. The pixel sensor includes a sensing region and a first control circuit region. The sensing region includes a photodiode in a device region of the sensing die. The first control circuit region is located below the sensing region and includes a transfer gate transistor, a reset gate transistor, a plurality of source follower transistors, and a column selection transistor. The reset gate transistor is electrically connected to the transfer gate transistor. A plurality of source follower transistors are electrically connected to the transfer gate transistor and the reset gate transistor. The circuit die is bonded to the sensing die at a bonding interface and includes a second control circuit region. The second control circuit region includes a capacitor, which is electrically connected to the source follower transistors and the column selection transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be better understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased to make the discussion clearer.

[0007] Figure 1 is a schematic diagram of an example environment in which the systems and / or methods described herein may be implemented;

[0008] Figure 2 is a schematic diagram of an example of a pixel sensor as described herein;

[0009] FIG. 3A to FIG. 3C is a schematic diagram of an example of a stacked image sensing device as described herein;

[0010] Figure 4 is a schematic diagram of an example of an image sensing device described herein;

[0011] Figure 5 is a schematic diagram of an implementation example of a capacitor described in this article;

[0012] FIG. 6A to FIG. 6R is a schematic diagram of an implementation example described in this article;

[0013] Figure 7 is a schematic diagram of an implementation example of the image sensing device described herein;

[0014] Figure 8 is a schematic diagram of an implementation example of the image sensing device described herein;

[0015] Fig. 9 is a schematic diagram of an implementation example of the image sensing device described herein;

[0016] Fig.10 is a schematic diagram of an implementation example of the image sensing device described herein;

[0017] Fig.11 is a schematic diagram of example elements of an apparatus described herein;

[0018] Fig.12 is a flow chart of an example process associated with forming an image sensing device.

[0019]

Explanation of symbols

[0020] 100: Environment

[0021] 102:Deposition tools

[0022] 104:Exposure Tools

[0023] 106: Development Tools

[0024] 108: Etching tools

[0025] 110: Flattening tool

[0026] 112:Electroplating tools

[0027] 114:Ion implantation tools

[0028] 116:Joining tool

[0029] 118: Wafer / die transport tool

[0030] 200: Pixel sensor

[0031] 202: Supply voltage

[0032] 204: Electrical ground

[0033] 206: Sensing area

[0034] 208: Control circuit area

[0035] 210: Photocurrent

[0036] 212: Photodiode

[0037] 214: Transfer gate transistor

[0038] 216: Transfer voltage

[0039] 218: Reset gate transistor

[0040] 220: Reset voltage

[0041] 222: Floating diffusion node

[0042] 224,224a,224b: Source follower transistor

[0043] 226: Column selection transistor

[0044] 228: Select voltage

[0045] 230: Output

[0046] 232: Capacitor

[0047] 300: Example

[0048] 302: Sensing Wafer

[0049] 304: Circuit Wafer

[0050] 306: Sensing Die

[0051] 308: Circuit Die

[0052] 310: Image sensing device

[0053] 312a,312b:BEOL area

[0054] 314:Joint interface

[0055] 316: Pixel sensor array

[0056] 400: Embodiment

[0057] 402: Installation area

[0058] 404:Logic Circuit

[0059] 406: Dielectric region

[0060] 408: Metallization layer

[0061] 410: Dielectric region

[0062] 412,412a,412b,412c: metallization layer

[0063] 414: Engagement contact

[0064] 416: BLC District

[0065] 418: Bonding pad area

[0066] 420: Installation area

[0067] 422: p-type implant region

[0068] 424:DTI Structure

[0069] 426,428,430,432: Oxide layer

[0070] 434: Grid structure

[0071] 436: Ceramic layer

[0072] 438:Metal layer

[0073] 440: Oxide layer

[0074] 442: Buffer oxide layer

[0075] 444: Light blocking structure

[0076] 446: Bonding pad

[0077] 448: Dielectric plug

[0078] 450: Etching stop layer

[0079] 452: Dielectric layer

[0080] 500: Embodiment

[0081] 502: first conductive layer

[0082] 504: Insulation layer

[0083] 506: second conductive layer

[0084] 508: Bottom metal contact

[0085] 510: Dielectric layer

[0086] 512: Top metal contact

[0087] 514,516,518: Covering layer

[0088] 600: Embodiment

[0089] 602,604,606: Grooves

[0090] 700, 800, 900, 1000: Example

[0091] 1100: Device

[0092] 1110: Bus

[0093] 1120: Processor

[0094] 1130:Memory

[0095] 1140: Input component

[0096] 1150: Output component

[0097] 1160: Communication Component

[0098] 1200: Craftsmanship

[0099] 1210: Block

[0100] 1220: Block

[0101] 1230: Block

[0102] 1240: Block DETAILED DESCRIPTION

[0103] The following disclosure provides many different embodiments or examples to implement different features of the subject matter provided. The specific examples of components and arrangements described below are intended to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature is formed on or above a second feature, which may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in each embodiment. Such repetition is for the purpose of simplicity and clarity, and is not itself intended to limit the relationship between the various embodiments and / or configurations discussed.

[0104] Additionally, spatially relative terms such as "under," "beneath," "below," "above," "over" and the like may be used herein to describe the relationship of one element or component to another element(s) or component(s) as illustrated in the accompanying drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device / apparatus may be oriented in various ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0105] In some cases, an image sensing device (e.g., a complementary metal oxide semiconductor (CMOS) image sensor) may include a pixel sensor array including one or more pixel sensors. The pixel sensor may include a plurality of transistors configured to transfer photocurrent generated by the pixel sensor to a circuit of the image sensing device for measurement, so that an image and / or a movie can be generated based on the measurement results. The transistors may include, for example, a transfer gate transistor, a source follower transistor, and / or a column select transistor. The transfer gate transistor may transfer the photocurrent generated by the pixel sensor to a source follower transistor that amplifies the photocurrent. The column select transistor may control the photocurrent to flow to an external circuit of the image sensing device.

[0106] Pixel sensors in image sensing devices may be susceptible to electrical, thermal and / or optical noise, which may degrade the quality of images and / or videos generated based on photocurrents generated by the pixel sensors. For example, electrical, thermal and / or optical noise (e.g., dark current, optical and / or electrical crosstalk, optical flare) may cause visual artifacts (e.g., white / hot pixels, inaccurate color representation, low-light noise) to degrade the quality of images and / or videos generated based on photocurrents generated by the pixel sensors.

[0107] In some cases, one or more regions of an image sensing device may include isolation structures to reduce the exposure of a pixel sensor to electrical, thermal, and / or optical noise. For example, a silicon (Si) substrate of an image sensing device may include a shallow trench isolation (STI) region. The STI region may be included in a bonding pad region of the image sensing device to isolate the bonding pad region of the image sensing device, thereby reducing and / or preventing electrical and / or optical noise from the bonding pad from invading and affecting the performance of the pixel sensor.

[0108] However, the STI regions may occupy a significant amount of lateral area in the silicon substrate of the image sensing device. This reduces the area of ​​the transistors in the image sensing device that are available for the pixel sensors of the image sensing device. Therefore, it may be necessary to reduce the size of one or more transistors to accommodate all transistors in the pixel sensor array. However, reducing the size of one or more transistors may result in reduced performance of one or more transistors. For example, reducing the size of the source follower transistor may result in reduced signal amplification of the source follower transistor, thereby increasing the level of noise in the photocurrent and / or dark current, etc.

[0109] In some embodiments described herein, an image sensing device may include a pixel sensor array including a plurality of pixel sensors. A plurality of transistors may be included below the pixel sensors and electrically connected to a back-end-of-line (BEOL) region of the image sensing device. Those transistors may include transfer gate transistors, reset gate transistors, source follower transistors, column select transistors, and / or other transistors that may be used to control the operation of the pixel sensors.

[0110] The image sensing device may further include a bonding pad region including a bonding pad. Instead of including an STI region to electrically and / or optically isolate the bonding pad, a dielectric plug may be included, wherein the dielectric plug surrounds a portion of the bonding pad and extends completely through a semiconductor device region (e.g., a silicon substrate (Si) and / or other type of semiconductor device region) to provide electrical isolation, thermal isolation, and / or optical isolation for pixel sensors of a pixel sensor array. Relative to the STI region, the inclusion of the dielectric plug may provide enhanced electrical, thermal, and / or optical isolation while occupying a smaller lateral area (relative to the STI region). The smaller lateral area of ​​the dielectric plug enables more lateral area in the semiconductor device to be used for transistors of the pixel sensors of the image sensing device. This enables one or more transistors to be formed to a larger size, which enables one or more transistors to achieve better performance. For example, the smaller lateral area of ​​the dielectric plug enables more lateral area in the semiconductor device to be used for a source follower transistor, which enables the size of the source follower transistor to be increased, and / or enables multiple source follower transistors to be included in the image sensing device. Increasing the size and / or increasing the number of source follower transistors may result in increased amplification of the photocurrent, thereby reducing noise and increasing image quality in photographs and / or videos produced by the image sensing device.

[0111] Additionally and / or alternatively, in some embodiments described herein, one or more capacitors are in the BEOL region of the image sensing device. The capacitors may perform and / or support one or more functions in the image sensing device, such as photocurrent storage, shutter operation, increasing the capacitance per unit area of ​​the pixel sensor of the image sensing device, and / or other functions. One or more capacitors may be included in the BEOL region and may be electrically connected to one or more transistors. For example, one or more capacitors may be electrically connected to one or more source-follower transistors such that photocurrent generated by one or more pixel sensors can be directly transferred from the one or more source-follower transistors to the one or more capacitors for storage.

[0112] In some embodiments, one or more capacitors may be configured in an image sensing device to support shutter operations associated with the image sensing device. A shutter is a component that enables pixel sensors in a pixel sensor array of an image sensing device to be selectively exposed to light. Shutters are often included in digital cameras to capture individual images or photographs. Capacitors can enable "global shutter" techniques or "total shutter" techniques, in which the entire pixel sensor array is exposed synchronously. At the beginning of a global exposure operation, each pixel sensor in the pixel sensor array may begin to accumulate charge due to exposure to light. The charge can be stored in the capacitor and transferred to a readout circuit at the end of the global exposure operation.

[0113] Thus, one or more capacitors in the BEOL region of the image sensing device can facilitate the use of advanced shutter techniques in the image sensing device, can reduce the delay in the image sensing device generating an image and / or a movie, can increase the low-light performance of the image sensing device. In addition, by facilitating the direct transfer of photocurrent from the source-follower transistor(s) to the capacitor(s), the amount of noise in the movie generated by the image sensing device can be reduced, thereby increasing the quality of the image and / or movie generated by the image sensing device.

[0114] Figure 1 1 is a schematic diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, environment 100 may include multiple semiconductor process tools 102 to 116, and a wafer / die transport tool 118. Semiconductor process tools 102 to 116 may include deposition tools 102, exposure tools 104, development tools 106, etching tools 108, planarization tools 110, plating tools 112, ion implantation tools 114, bonding tools 116, and / or other types of semiconductor process tools. The tools included in the example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor process plant, and / or a manufacturing plant, etc.

[0115] Deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer onto a substrate (e.g., a wafer). In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or other types of CVD tools. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other type of PVD tool. In some embodiments, the example environment 100 includes multiple types of deposition tools 102 .

[0116] The exposure tool 104 is a semiconductor process tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., a deep ultraviolet light source, an extreme ultraviolet (EUV) light source, etc.), an X-ray source, an electron beam (e-beam) source, and / or a similar radiation source. The exposure tool 104 is capable of exposing the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for etching various portions of a semiconductor device, and / or similar patterns, etc. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0117] The developing tool 106 is a semiconductor process tool capable of developing the photoresist layer that has been exposed to the radiation source to develop the pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving the exposed portion or the unexposed portion of the photoresist layer using a chemical developer.

[0118] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etch tool, a dry etch tool, and / or similar etching tools. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may include using an ionized gas to etch the one or more portions isotropically or directionally.

[0119] The planarization tool 110 is a semiconductor process tool capable of grinding or flattening individual layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or other types of planarization tools to grind or flatten a layer or surface of a deposited material or a plated material. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to grind or flatten the surface of a semiconductor device. The planarization tool 110 may use an abrasive and corrosive chemical polishing slurry in conjunction with a polishing pad and a support ring (e.g., typically having a diameter greater than the diameter of the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a movable polishing head and held in place by a support ring. The movable polishing head may rotate with different rotation axes to remove material and flatten any irregular topography of the semiconductor device so that the semiconductor device is flat or planar.

[0120] The electroplating tool 112 is a semiconductor process tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, etc.) or a portion of a substrate with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a composite material or alloy (e.g., tin-silver, tin-lead, etc.) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0121] The ion implantation tool 114 is a semiconductor process tool capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a source material such as a gas or a solid in an arc chamber. The source material can be provided to the arc chamber, and an arc voltage is discharged between a cathode and an anode to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward the substrate so that the ions are implanted below the surface of the substrate.

[0122] The bonding tool 116 is a semiconductor process tool capable of bonding two or more wafers (or two or more semiconductor substrates, or two or more semiconductor devices) together. For example, the bonding tool 116 may include a eutectic bonding tool capable of forming a eutectic bond between two or more wafers. In these examples, the bonding tool 116 may heat the two or more wafers to form a eutectic system between the materials of the two or more wafers. As another embodiment, the bonding tool 116 may include a hybrid bonding tool, a direct bonding tool, and / or another type of bonding tool.

[0123] The wafer / die handling tool 118 may be included in a cluster tool or another type of tool including multiple process chambers, and may be configured to transport substrates and / or semiconductor devices between multiple process chambers, to transport substrates and / or semiconductor devices between a process chamber and a buffer, to transport substrates and / or semiconductor devices between a process chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or to transport substrates and / or semiconductor devices between a process chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), etc. In some embodiments, the wafer / die handling tool 118 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts on substrates and / or semiconductor devices), and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations).

[0124] In some embodiments, one or more semiconductor process tools 102 to 116 and / or wafer / die handling tool 118 may perform one or more semiconductor process operations described herein. For example, one or more semiconductor process tools 102 to 116 and / or wafer / die handling tool 118 may form a pixel sensor in a sensing die; may form a sensing region including a photodiode in a device region of the sensing die; may form a control circuit region below the device region including a transfer gate transistor; may form a reset gate transistor electrically connected to the transfer gate transistor; may form a plurality of source follower transistors electrically connected to the transfer gate transistor and the reset gate transistor; may form a capacitor electrically connected to the plurality of source follower transistors; may form a column select transistor electrically connected to the capacitor; may form a circuit die; and / or may join a sensing die and a circuit die, etc.

[0125] As another example, one or more semiconductor process tools 102 to 116 and / or wafer / die transport tool 118 can form a photodiode in a sensing die, which is in a sensing area of ​​a pixel sensor included in a pixel sensor array; a transfer gate transistor can be formed in a first control circuit area included in the sensing die and electrically connected to the photodiode; a reset gate transistor can be formed in the first control area and electrically connected to the transfer gate transistor; a column selection transistor can be formed in the first control circuit area; a plurality of source follower transistors can be formed in a circuit die, those source follower transistors are included in a second control circuit area associated with the pixel sensor; a capacitor can be formed in at least one of the sensing die or the circuit die, wherein the capacitor is electrically connected to the column selection transistor and those source follower transistors; and / or the sensing die and the circuit die can be joined, etc.

[0126] As another example, one or more semiconductor process tools 102 to 116 and / or wafer / die transport tool 118 can form a sensing die, a pixel sensor including a sensing region, the sensing region including a photodiode in a device region of the sensing die; a first control circuit region located below the sensing region, a transfer gate transistor, a reset gate transistor electrically connected to the transfer gate transistor, a plurality of source follower transistors electrically connected to the transfer gate transistor and the reset gate transistor, and a column selection transistor can be formed; a second control circuit region can be formed, which includes: a capacitor electrically connected to those source follower transistors and the column selection transistor, wherein the capacitor is configured to store photocurrent received from those source follower transistors; and / or the sensing die and the circuit die can be joined, etc.

[0127] In some embodiments, one or more of the semiconductor process tools 102 to 116 and / or the wafer / die handling tool 118 may be combined with FIG. 6A to FIG. 6R and / or Fig.12 and other examples describing one or more semiconductor process operations.

[0128] supply Figure 1 The number and arrangement of devices shown are provided as one or more examples. Figure 1 There may be more devices, fewer devices, different devices, or devices arranged differently than those shown. Figure 1 One or more of the devices shown in the figure may be implemented in a single device, or Figure 1 The single device shown in the example environment 100 may be implemented in multiple distributed devices. Additionally and / or alternatively, one or more functions described by another group of devices in the example environment 100 may be performed by a group of devices in the example environment 100.

[0129] Figure 2 2 is a schematic diagram of an example of a pixel sensor 200 described herein. The pixel sensor 200 may include a front-side pixel sensor (e.g., a pixel sensor configured to receive photons of light from a front end of a sensing die), a back-side pixel sensor (e.g., a pixel sensor configured to receive photons of light from a back end of a sensing die), and / or another type of pixel sensor. The pixel sensor 200 may be electrically connected to a supply voltage (V dd )202 and an electrical ground terminal 204.

[0130] The pixel sensor 200 includes a sensing region 206 that can be configured to sense and / or accumulate incident light (e.g., light directed toward the pixel sensor 200). The pixel sensor 200 also includes a control circuit region 208. The control circuit region 208 is electrically connected to the sensing region 206 and configured to receive a photocurrent 210 generated by the sensing region 206. In addition, the control circuit region 208 is configured to transfer the photocurrent 210 from the sensing region 206 to a downstream circuit, such as an amplifier or an analog-to-digital (AD) converter.

[0131] The sensing region 206 includes a photodiode 212. The photodiode 212 is capable of absorbing and accumulating photons of incident light, and is capable of generating a photocurrent 210 based on the absorbed photons. The magnitude of the photocurrent 210 depends on the amount of light collected in the photodiode 212. Therefore, the accumulation of photons in the photodiode 212 generates an accumulation of charge, which represents the intensity or brightness of the incident light (e.g., a greater amount of charge may correspond to a greater intensity or brightness, and a lesser amount of charge may correspond to a lesser intensity or brightness).

[0132] The photodiode 212 is electrically connected to the source of a transfer gate transistor 214 in the control circuit area 208. The transfer gate transistor 214 is configured to control the discharge of the photocurrent 210 from the photodiode 212. Based on the selective switching of the gate of the transfer gate transistor 214, the photocurrent 210 is supplied from the source of the transfer gate transistor 214 to the drain of the transfer gate transistor 214. By applying a transfer voltage (V tx ) 216 to the gate of transfer gate transistor 214, the gate of transfer gate transistor 214 can be selectively switched. In some embodiments, applying transfer voltage 216 to the gate of transfer gate transistor 214 causes a conductive channel to be formed between the source and drain of transfer gate transistor 214, so that photocurrent 210 can flow from the source to the drain along the conductive channel. In some embodiments, removing transfer voltage 216 from the gate (or the absence of transfer voltage 216) causes the conductive channel to be removed, so that photocurrent 210 cannot flow from the source to the drain.

[0133] The control circuit area 208 also includes a reset gate transistor 218. The reset gate transistor 218 is electrically connected to the supply voltage 202 and the drain of the transfer gate transistor 214. Before the transfer gate transistor 214 is enabled to read the photocurrent 210 from the photodiode 212, the reset gate transistor 218 is configured to pull the drain of the transfer gate transistor 214 to a high voltage (e.g., the supply voltage 202) to “reset” the control circuit area 208. The reset gate transistor 218 can be controlled by a reset voltage (V rst )220.

[0134] The output from the drain of the transfer gate transistor 214 is electrically connected to the gate of the source follower transistor 224 through a floating diffusion node 222. The output from the transfer gate transistor 214 is provided to the gate of the source follower transistor 224 by the floating diffusion node 222. The floating diffusion node 222 provides the floating diffusion voltage (V fd ) is applied to the gate of source follower transistor 224. This allows the photocurrent 210 to be observed without removing or releasing the photocurrent 210 from floating diffusion node 222. Instead, a reset gate transistor 218 is used to remove or release the photocurrent 210 from floating diffusion node 222.

[0135] The source follower transistor 224 is used as a high impedance amplifier for the pixel sensor 200. The source follower transistor 224 provides a voltage-to-current conversion of the floating diffusion voltage. The output of the source follower transistor 224 is electrically connected to the column select transistor 226, which is configured to control the photocurrent 210 to flow to an external circuit. The column select transistor 226 is controlled by selectively applying a select voltage (V di ) 228 to the gate of column select transistor 226. This allows photocurrent 210 to flow to output 230 of pixel sensor 200.

[0136] like Figure 2 As further shown, capacitor 232 can store photocurrent 210 output from source follower transistor 224. Capacitor 232 can store photocurrent 210 before enabling column select transistor 226. Enabling column select transistor 226 can cause photocurrent 210 stored in capacitor 232 to discharge to output 230.

[0137] As described herein, one or more transistors 214, 218, 224, and / or 226, and / or capacitor 232 of control circuit area 208 of pixel sensor 200 may be included in separate dies of a stacked image sensing device (e.g., a 3D CMOS image sensor (3DCIS) device). This may allow the size of source follower transistor 224 to be increased and / or may allow a greater number of source follower transistors 224 to be included in pixel sensor 200. The increased size and / or increased number of source follower transistors 224 may improve the amplification of photocurrent 210, among other things, by reducing noise in the amplified photocurrent 210 and / or by increasing the amplitude of the amplified photocurrent 210.

[0138] As shown above, provide Figure 2 As an example. Other examples may be related to Figure 2 Different than described.

[0139] FIG. 3A to FIG. 3C is a schematic diagram of an example 300 of a stacked image sensing device as described herein. Figure 3A As shown in , a stacked image sensing device can be formed by bonding a sensing wafer 302 and a circuit wafer 304. For example, the bonding tool 116 can perform a bonding operation using a hybrid bonding technique, a direct bonding technique, a eutectic bonding technique, and / or another bonding technique to bond the sensing wafer 302 and the circuit wafer 304. In the bonding operation, the sensing die 306 on the sensing wafer 302 is bonded with the associated circuit die 308 on the circuit wafer 304 to form a stacked image sensing device 310. The image sensing device 310 is then cut and packaged. Other process steps may be performed to form the image sensing device 310.

[0140] Each image sensor device 310 includes a sensing die 306 and a circuit die 308. The sensing die 306 includes a pixel sensor array, which includes a plurality of pixel sensors 200, or portions of a plurality of pixel sensors 200. Specifically, the pixel sensor array includes at least the sensing region 206 (and therefore the photodiode 212) of the pixel sensor 200. Therefore, the sensing die 306 is primarily configured to sense photons of incident light and convert the photons into photocurrent 210.

[0141] The circuit die 308 includes circuitry configured to measure, manipulate, and / or otherwise use the photocurrent 210. Among other things, the circuit die 308 includes at least a subset of transistors of the control circuit region 208 of the pixel sensor 200. For example, the circuit die 308 may include a column select transistor 226 of the pixel sensor 200, a source follower transistor 224 of the pixel sensor 200, and / or a combination of the foregoing. This provides a larger area for the photodiode 212 on the sensing die 306, allowing the size of the photodiode 212 to be increased to increase the sensitivity and / or overall performance of the light sensing performance of the pixel sensor, and / or allowing the size of the pixel sensor 200 to be reduced while maintaining the same size photodiode 212.

[0142] like Figure 3A As further shown in FIG. 1 , the sensing die 306 may include a back end of line (BEOL) region 312a, and the circuit die 308 may include a BEOL region 312b. The BEOL region 312a and the BEOL region 312b may each include one or more metallization layers insulated by one or more dielectric layers. In other examples, the BEOL region 312a and the BEOL region 312b may electrically connect the sensing die 306 and the circuit die 308, and may electrically connect one or more components of the sensing die 306 and the circuit die 308 to a package and / or other structures. The sensing die 306 and the circuit die 308 may be bonded at a bonding interface 314, which may be included between the BEOL region 312a and the BEOL region 312b, or may be included in a portion of the BEOL region 312a and / or a portion of the BEOL region 312b.

[0143] Figure 3B FIG. 3 is a top view of an exemplary pixel sensor array 316 included on the sensing die 306. The sensing die 306 of the image sensing device 310 may include the pixel sensor array 316. Figure 3B As shown, the pixel sensor array 316 may include a plurality of pixel sensors 200 (or portions of a plurality of pixel sensors 200). Figure 3B As further shown, the pixel sensors 200 can be arranged in a grid. In some embodiments, the pixel sensors 200 are square (e.g., Figure 3B In some embodiments, the pixel sensor 200 includes other shapes, such as a rectangle, a circle, an octagon, a diamond, and / or other shapes.

[0144] In some embodiments, the dimension (e.g., width or diameter) of the pixel sensor 200 is approximately 1 micron. In some embodiments, the dimension (e.g., width or diameter) of the pixel sensor 200 is less than approximately 1 micron. For example, the width of one or more pixel sensors 200 may be included in the range of approximately 0.6 microns to approximately 0.7 microns. In these examples, the pixel sensor 200 may be referred to as a sub-micron pixel sensor. Sub-micron pixel sensors may reduce the pitch of pixel sensors in the pixel sensor array 316 (e.g., the distance between adjacent pixel sensors), which may increase the density of pixel sensors in the pixel sensor array 316 (which may improve the performance of the pixel sensor array 316). However, other ranges of values ​​for the dimension of the pixel sensor 200 are also within the scope of the present disclosure.

[0145] Figure 3C A detailed top view of pixel sensor 200 included in pixel sensor array 316 is shown. Figure 3C As shown, the pixel sensor 200 may include a transfer gate transistor 214, a reset gate transistor 218, and a column select transistor 226. In addition, the pixel sensor 200 may include a plurality of source follower transistors 224, including a source follower transistor 224a and a source follower transistor 224b, etc. The source follower transistor 224b may be included to replace the STI region (e.g., the STI region may be omitted and the source follower transistor 224 may be included to replace the STI region). As described herein, the bonding pad region for the image sensing device 310 may include a dielectric plug that provides electrical and / or optical isolation instead of the STI region, which enables the source follower transistor 224b to be included in a location that may have originally included the STI region. In some embodiments, the size (e.g., gate length, gate width, channel length, channel width) of the source follower transistor 224a and / or the source follower transistor 224b may be increased due to the omission of the STI region. For example, relative to the gate length of a source follower transistor in an image sensor device including an STI region (which may be in the range of about 100 nanometers to about 600 nanometers), the gate length of source follower transistor 224a and / or source follower transistor 224b may be in the range of about 200 nanometers to about 5000 nanometers to achieve increased amplification and reduced signal noise. However, other numerical ranges are also within the scope of the present disclosure.

[0146] As mentioned above, providing FIG. 3A to FIG. 3C As an example. Other examples may differ from FIG. 3A to FIG. 3C The content described in .

[0147] Figure 4 is a schematic diagram of an embodiment 400 of the image sensing device 310 described herein. Figure 4 A cross-sectional view of an embodiment 400 of an image sensing device 310 is depicted.

[0148] like Figure 4 As shown in , the image sensing device 310 may include a sensing die 306 and a circuit die 308. The sensing die 306 may include a BEOL region 312a, and the circuit die 308 may include a BEOL region 312b. The sensing die 306 and the circuit die 308 may be bonded at a bonding interface 314. Specifically, the BEOL region 312a of the sensing die 306 and the BEOL region 312b of the circuit die 308 may be bonded at the bonding interface 314.

[0149] Circuit die 308 may include a device region 402 including logic circuit 404. Device region 402 may include a substrate, such as a semiconductor die substrate, a semiconductor wafer, a stacked semiconductor wafer, or another type of substrate. In some embodiments, device region 402 is formed of silicon (Si) (e.g., a silicon substrate), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon on insulator (SOI), or other types of semiconductor materials.

[0150] The logic circuit 404 may include one or more application-specific integrated circuit (ASIC) devices, one or more system-on-chip (SOC) devices, one or more transistors, and / or one or more other components configured to measure the magnitude of the photocurrent 210 generated by the pixel sensor 200 to determine the light intensity of the incident light and / or generate an image and / or video (e.g., a digital photograph, a digital video).

[0151] The BEOL region 312b may include a dielectric region 406 and a plurality of metallization layers 408. The dielectric region 406 may include one or more interlayer dielectric (ILD) layers, one or more intermetal dielectric (IMD) layers, and / or one or more etch stop layers (ESL), etc. The dielectric region 406 may include one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (silicon nitride; Si x N y), silicon oxynitride (SiON), tetraethyl orthosilicate oxide (tetraethyl orthosilicate oxide), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinatedsilicate glass (FSG), and / or carbon doped silicon oxide (carbon doped silicon oxide), etc.

[0152] The metallization layer 408 may include bonding pads, conductive lines, trenches, vias, interconnects, and / or other types of conductive structures to electrically connect the logic circuit 404 to one or more other regions of the circuit die 308 and / or to one or more regions of the sensing die 306. The metallization layer 408 may include one or more conductive materials, such as conductive metals, conductive metal alloys, conductive ceramics, tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), among other examples of conductive materials.

[0153] The BEOL region 312a may include a dielectric region 410 and a plurality of metallization layers 412. The dielectric region 410 may include one or more ILD layers, one or more IMD layers, and / or one or more ESL layers. The dielectric region 410 may include one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (silicon nitride; Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide (tetraethyl orthosilicate Oxide), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon doped silicon oxide (carbon doped silicon oxide), etc.

[0154] The metallization layer 412 may include bonding pads, conductive lines, trenches, vias, interconnects, and / or other types of conductive structures to electrically connect the semiconductor device of the sensing die 306 to one or more other regions of the sensing die 306 and / or to one or more regions of the circuit die 308. The metallization layer 412 may include one or more conductive materials, such as conductive metals, conductive metal alloys, conductive ceramics, tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), among other examples of conductive materials.

[0155] The sensing die 306 and the circuit die 308 may be bonded at the bonding interface 314 by dielectric-to-dielectric bonding (e.g., where the dielectric region 406 and the dielectric region 410 are bonded), by metal-to-metal bonding (e.g., where the metallization layer 408 and the metallization layer 412 are bonded), and / or by another bonding configuration. In some embodiments, bonding contacts 414 may be included in the BEOL regions 312a and 312b and may be used to bond the sensing die 306 and the circuit die 308 at the bonding interface 314. The bonding contacts 414 may include one or more conductive materials, such as conductive metals, conductive metal alloys, conductive ceramics, tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), among other examples of conductive materials. Signals may be routed and / or transmitted between the sensing die 306 and the circuit die 308 through the bonding contacts 414.

[0156] like Figure 4 As further shown, the image sensing device 310 (particularly the sensing die 306) can include multiple lateral regions, including a pixel sensor array 316, a black level correction (BLC) region 416 adjacent to (e.g., horizontally adjacent to) the pixel sensor array 316, and a bonding pad region 418 adjacent to (e.g., horizontally adjacent to) the BLC region 416. The pixel sensor array 316 can include one or more pixel sensors 200. The pixel sensor 200 can include a photodiode 212 located in a device region 420 of the sensing die 306. The device region 420 can include a substrate, such as a semiconductor die substrate, a semiconductor wafer, a stacked semiconductor wafer, or another type of substrate. In some embodiments, the device region 420 is formed of silicon (Si) (e.g., a silicon substrate), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon on insulator (SOI), or other types of semiconductor materials.

[0157] The photodiode 212 may include one or more doped regions of a device region 420. The device region 420 may be doped with multiple types of ions to form a pn junction or a PIN junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) type portion, and an n-type portion) corresponding to the photodiode 212. For example, the device region 420 may be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 212, and doped with a p-type dopant to form a second portion (e.g., a p-type portion) of the photodiode 212. The photodiode 212 may be configured to absorb photons of incident light. The absorption of the photons causes the photodiode 212 to accumulate charge (referred to as a photocurrent 210) due to the photoelectric effect. Here, the photons bombard the photodiode 212, thus causing electron emission from the photodiode 212. The emission of the electrons causes the formation of electron-hole pairs, wherein the electrons migrate toward the cathode of the photodiode 212 and the holes migrate toward the anode, thereby generating the photocurrent 210.

[0158] The photodiode 212 may be electrically and / or optically isolated from other photodiodes and / or other regions of the device region 420 by the p-type implant region 422 and the deep trench isolation (DTI) structure 424 above the p-type implant region 422. The p-type implant region 422 and the DTI structure 424 may form a grid around the photodiode 212 of the pixel sensor 200 included in the pixel sensor array 316. The p-type implant region 422 may include a portion of the device region 420 doped with p-type ions. The p-type ions may include a p-type material (e.g., boron (B) or germanium (Ge), etc.). The DTI structure 424 may include a dielectric structure (e.g., an oxide structure, a nitride structure) extending from a top surface of the device region 420 to the p-type implant region 422.

[0159] The p-type implant region 422 may be included to reduce the etch depth in the device region 420 for forming the DTI structure 424. Etching of the device region 420 may damage the device region 420 and the photodiode 212 in the device region 420. The likelihood and / or amount of damage to the photodiode 212 may increase as a function of the etch duration used to etch the recess in which the DTI structure 424 is formed. The deeper the DTI structure 424, the longer the etch duration. The inclusion of the p-type implant region 422 enables the DTI structure 424 to be formed to a smaller depth in the device region 420 while still providing electrical isolation and / or optical isolation along the entire depth of the device region 420. The reduced depth of the DTI structure 424 in the device region 420 may reduce the etch duration of the recess used to form the DTI structure 424, which may reduce the likelihood and / or amount of damage to the photodiode 212 during the formation of the DTI structure 424.

[0160] like Figure 4 As further shown, a plurality of transistors of the pixel sensor 200 can be located below the device region 420. For example, the transfer gate transistor 214 can be located below the photodiode 212 of the pixel sensor 200. The photodiode 212 can correspond to (or can be electrically connected to) a source / drain region of the transfer gate transistor 214. When the transfer gate transistor 214 is enabled, the photocurrent 210 generated by the photodiode 212 can be transferred to another source / drain region of the transfer gate transistor 214. As another example, the reset gate transistor 218 can be located below the device region 420. As another example, a plurality of source follower transistors 224a and 224b can be located below the device region 420. As another example, the column select transistor 226 can be located below the device region 420.

[0161] The transistors 214, 218, 224a, 224b, and 226 may be electrically connected to one or more metallization layers 412 in the BEOL region 312a through one or more electrical contacts. For example, each transistor 214, 218, 224a, 224b, and 226 may be electrically connected to the metallization layer 412 through a set of corresponding source / drain contacts and a corresponding gate contact. In some embodiments, the transfer gate transistor 214, the reset gate transistor 218, and the column select transistor 226 may be electrically connected to the same metallization layer 412a. In some embodiments, the source follower transistors 224a and 224b may be electrically connected to the same metallization layer 412b.

[0162] like Figure 4 As further shown, the BEOL region 312a may include a capacitor 232, and the capacitor 232 may be electrically connected to the metallization layer 412 in the BEOL region 312a. In some embodiments, the capacitor 232 is vertically located below one or more source follower transistors 224a and / or 224b. In some embodiments, the capacitor 232 is electrically connected to the same metallization layer 412b as the source follower transistors 224a and 224b. The transfer gate transistor 214, the reset gate transistor 218, the source follower transistors 224a and 224b, the column select transistor 226, and the capacitor 232 may be included in the same control circuit region 208 in the sensing die 306.

[0163] like Figure 4As further shown, one or more layers may be included on and / or above device region 420. The one or more layers may include one or more dielectric layers, one or more antireflective coating (ARC) layers, one or more buffer layers, and / or one or more passivation layers, etc. In some embodiments, an oxide layer 426 may be included on and / or above device region 420. In some embodiments, the thickness of oxide layer 426 may be included in the range of about 30 angstroms to about 50 angstroms. However, other numerical ranges are also within the scope of the present disclosure. As another example, an oxide layer 428 may be included on and / or above oxide layer 426. In some embodiments, the thickness of oxide layer 428 may be included in the range of about 50 angstroms to about 70 angstroms. However, other numerical ranges are also within the scope of the present disclosure.

[0164] As another example, an oxide layer 430 may be included on and / or above the oxide layer 428. In some embodiments, the thickness of the oxide layer 430 may be included in the range of about 450 angstroms to about 500 angstroms. However, other numerical ranges are also within the scope of the present disclosure. As another example, an oxide layer 432 may be included on and / or above the oxide layer 430. In some embodiments, the thickness of the oxide layer 432 may be included in the range of about 500 angstroms to about 1000 angstroms. However, other numerical ranges are also within the scope of the present disclosure.

[0165] The oxide layers 426 to 432 may include hafnium oxide (HfO x For example, HfO2), aluminum oxide (Al x O y For example, Al2O3), tantalum oxide (Ta x O y For example, Ta2O5), silicon oxide (SiO x For example, SiO2), and / or zirconium oxide (ZrO), etc. Additionally and / or alternatively, one or more of the oxide layers 426 to 432 may include nitrides, such as silicon carbonitride (SiCN) and / or silicon nitride (Si x N y , such as Si3N4), and other examples.

[0166] like Figure 4As further shown, the pixel sensor array 316 may include a mesh structure 434 above the pixel sensors 200. The mesh structure 434 may be configured to direct light toward the photodiodes 212 in the device region 420 to increase photon absorption in the pixel sensor 200, which may increase the quantum efficiency of the pixel sensor 200. The mesh structure 434 may include a metal mesh structure including one or more metal layers, a dielectric mesh structure including one or more dielectric layers, or a composite mesh structure including a combination of metal layers, dielectric layers, and / or ceramic layers, among other examples.

[0167] For example, mesh structure 434 may include a ceramic layer 436 located on and / or above oxide layer 432, a metal layer 438 located on and / or above ceramic layer 436, and / or an oxide layer 440 located on and / or above metal layer 438, etc. Ceramic layer 436 may include titanium nitride (TiN) and / or other suitable materials. In some embodiments, the thickness of ceramic layer 436 is included in the range of about 200 angstroms to about 400 angstroms. However, other numerical ranges are also within the scope of the present disclosure. Metal layer 438 may include tungsten (W) and / or other suitable metal materials. In some embodiments, the thickness of metal layer 438 is included in the range of about 1500 angstroms to about 1700 angstroms. However, other numerical ranges are also within the scope of the present disclosure. Oxide layer 440 may include hafnium oxide (HfO x , such as HfO2), aluminum oxide (Al x O y , such as Al2O3), tantalum oxide (Ta x O y , such as Ta2O5), silicon oxide (SiO x , such as SiO2), and / or zirconium oxide (ZrO), etc. In some embodiments, the thickness of the oxide layer 440 is included in the range of about 3000 angstroms to about 5000 angstroms. However, other numerical ranges are also within the scope of the present disclosure.

[0168] A buffer oxide layer 442 may be included on and / or over the mesh structure 434. The buffer oxide layer 442 may include hafnium oxide (HfO x , such as HfO2), aluminum oxide (Al x O y , such as Al2O3), tantalum oxide (Ta x O y , such as Ta2O5), silicon oxide (SiO x , such as SiO2), and / or zirconium oxide (ZrO), etc. In some embodiments, the thickness of the buffer oxide layer 442 is within the range of about 200 angstroms to about 300 angstroms. However, other numerical ranges are also within the scope of the present disclosure.

[0169] In some embodiments, the pixel sensor array 316 includes one or more additional layers and / or structures. For example, a filter layer may be included on and / or above the buffer oxide layer 442 for one or more pixel sensors 200 in the pixel sensor array 316. The filter layer may include one or more visible light color filter regions configured to filter specific wavelengths or wavelength ranges of visible light (e.g., allowing visible light of a specific wavelength or wavelength range to pass through the filter layer), one or more near infrared (NIR) filter regions (e.g., NIR bandpass filter regions) configured to allow wavelengths associated with NIR light to pass through the filter layer and block light of other wavelengths, one or more NIR cutoff filter regions configured to block NIR light from passing through the filter layer, and / or other types of filter regions. In some embodiments, one or more pixel sensors 200 in the pixel sensor array 316 are each configured with a filter region of the filter layer. In some embodiments, the filter region may be omitted from the filter layer of one or more pixel sensors 200 in the pixel sensor array 316 to allow all wavelengths of light to pass through the filter layer of the one or more pixel sensors 200. In these examples, one or more pixel sensors 200 may be configured as white pixel sensors.

[0170] As another example, a microlens layer may be included on and / or above the filter layer. The microlens layer may include a plurality of microlenses. Specifically, the microlens layer may include a corresponding microlens for each pixel sensor 200 included in the pixel sensor array 316.

[0171] The BLC region 416 may include a light blocking structure 444 that prevents light from entering the sensing region in the device region 420 below the light blocking structure 444. The sensing region is "dark" because the light blocking structure 444 prevents incident light from entering the sensing region. This enables the sensing region to generate dark current measurements for black level correction (or black level calibration) of the pixel sensor array 316.

[0172] Light blocking structure 444 may include one or more layers. One or more layers may include a portion of ceramic layer 436 and a portion of metal layer 438. In some embodiments, light blocking structure 444 includes one or more portions extending through oxide layer 426, oxide layer 428, and oxide layer 430 to reflect light away from the sensing region, which may otherwise enter device region 420 around light blocking structure 444.

[0173] The bonding pad region 418 may include a bonding pad 446 electrically connected to the metallization layer 412 in the BEOL region 312a of the sensing die 306. The bonding pad 446 may be included in a recess in the dielectric region 410 of the BEOL region 312a. Specifically, a top surface of the bonding pad 446 may be located below the device region 420 of the sensing die 306 (e.g., below a bottom surface of the device region 420).

[0174] The bonding pad 446 may include a conductive material such as gold, silver, aluminum, copper, aluminum-copper, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, a metal alloy, other metals, or a combination thereof. The bonding pad 446 may provide an electrical connection between the metallization layer 412 of the sensing die 306 and an external device and / or external package.

[0175] The bond pad 446 may be at least partially surrounded by a dielectric plug 448 in the bond pad region 418, wherein the dielectric plug 448 extends through the device region 420. The dielectric plug 448 may extend completely through the device region 420 (e.g., from the top surface of the device region 420 to the bottom surface of the device region 420) and pass into a portion of the dielectric region 410 in the BEOL region 312a. In this way, the dielectric plug 448 may completely isolate (e.g., electrically, thermally, and / or optically) the photodiode 212 of the pixel sensor 200 in the device region 420 from noise sources (e.g., electrical noise and / or optical noise) in the device region 420. The dielectric plug 448 may also extend through the etch stop layer 450 and / or the dielectric layer 452 included between the device region 420 and the dielectric region 410 of the BEOL region 312a, through the oxide layer 426 to the oxide layer 430, and / or through another layer in the sensing die 306, etc. The dielectric plug 448 may include one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (silicon nitride; Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide (tetraethyl orthosilicate oxide), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG) and / or carbon doped silicon oxide (carbon doped silicon oxide), etc.

[0176] The dielectric plug 448 extending completely through the device region 420 can provide electrical, thermal, and / or optical isolation in the device region 420 without using additional STI regions in the bond pad region 418. Omitting the STI regions can enable the inclusion of multiple source follower transistors 224a and 224b in the pixel sensor 200, and / or can enable the size of the source follower transistors 224a and / or 224b to be increased. In other examples, increasing the size and / or increasing the number of source follower transistors 224 in the sensing die 306 can improve the amplification of the photocurrent 210 by reducing noise in the amplified photocurrent 210, and / or by increasing the amplitude of the amplified photocurrent 210.

[0177] Therefore, in the embodiment 400 of the image sensing device 310, the image sensing device 310 may include a sensing die 306 and a circuit die 308 bonded to the sensing die 306 at a bonding interface 314. The sensing die 306 includes a pixel sensor 200, the pixel sensor 200 includes a sensing region 206, the sensing region 206 includes a photodiode 212 located in a device region 420 of the sensing die 306. The pixel sensor 200 may include a control circuit region 208 located below the device region 420, which includes a transfer gate transistor 214, a reset gate transistor 218 electrically connected to the transfer gate transistor 214, a plurality of source follower transistors 224a and 224b electrically connected to the transfer gate transistor 214 and the reset gate transistor 218, a capacitor 232 electrically connected to the plurality of source follower transistors 224a and 224b, and a column select transistor 226 electrically connected to the capacitor 232. The capacitor 232 is configured to store the photocurrent 210 received from the source-follower transistors 224a and 224b. The capacitor 232 may be included in the BEOL region 312a of the sensing die 306. The source-follower transistors 224a and 224b and the capacitor 232 may be electrically connected to the same metallization layer 412b in the BEOL region 312a of the sensing die 306.

[0178] As mentioned above, providing Figure 4 As an example. Other examples may be related to Figure 4 Different than described.

[0179] Figure 5 is a schematic diagram of an embodiment 500 of the capacitor 232 described herein. Embodiment 500 includes an implementation of an example structure of the capacitor 232 (eg, an example capacitor structure that may be used to implement the capacitor 232).

[0180] like Figure 5As shown in , the capacitor 232 may include a first conductive layer 502, an insulating layer 504, and a second conductive layer 506. The first conductive layer 502 and the second conductive layer 506 may correspond to conductive electrode layers of the capacitor 232. The first conductive layer 502 may be referred to as a capacitor bottom metal (CBM) layer of the capacitor 232, and the second conductive layer 506 may be referred to as a capacitor top metal (CTM) layer of the capacitor 232. The insulating layer 504 may be located between the first conductive layer 502 and the second conductive layer 506. The first conductive layer 502, the insulating layer 504, and the second conductive layer 506 may form a metal-insulator-metal (MIM) structure of the capacitor 232.

[0181] The first conductive layer 502 and the second conductive layer 506 may each include one or more conductive materials, such as one or more metals, one or more metal alloys, and / or one or more conductive materials of another type. For example, tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu) or gold (Au), titanium nitride (TiN) and / or tantalum nitride (TaN), etc. The insulating layer 504 may include one or more electrically insulating materials and / or dielectric materials. In some embodiments, the insulating layer 504 includes one or more dielectric materials with a relatively high dielectric constant (high k), such as a dielectric constant higher than the dielectric constant of silicon dioxide (SiO2). For example, zirconium oxide (ZrO x , such as ZrO2), aluminum oxide (Al x O y , such as Al2O3), silicon nitride (Si x N y , such as Si3N4), yttrium oxide (Y x O y , such as Y2O3), lanthanum oxide (La x O y , such as La2O3), yttrium titanium oxide (Y x TiO y , such as Y2TiO5), hafnium oxide (HfO x , such as HfO2) and / or tantalum oxide (Ta x O y , such as Ta2O5) and so on.

[0182] like Figure 5As further shown, capacitor 232 can be electrically connected to a plurality of contacts that electrically connect capacitor 232 to other conductive structures in image sensing device 310. Bottom metal contact 508 can be located in dielectric layer 510, and top metal contact 512 can be located in dielectric layer 510. Bottom metal contact 508 can be electrically connected to first conductive layer 502. Top metal contact 512 can be electrically connected to second conductive layer 506. The width of second conductive layer 506 can be less than the width of first conductive layer 502, so that bottom metal contact 508 can fall on first conductive layer 502 without contacting (and electrically shorting) second conductive layer 506. Bottom metal contact 508 and top metal contact 512 can each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), among other example conductive materials.

[0183] In some embodiments, the dielectric layer 510 corresponds to the dielectric region 410 of the BEOL region 312a included in the sensing die 306. Therefore, the bottom metal contact 508 and the top metal contact 512 can electrically connect the capacitor 232 to the one or more metallization layers 412 in the BEOL region 312a. In some embodiments, the dielectric layer 510 corresponds to the dielectric region 406 of the BEOL region 312b included in the sensing die 306. Therefore, the capacitor 232 can be included in the circuit die 308 (e.g., in the BEOL region 312b of the circuit die 308), and the bottom metal contact 508 and the top metal contact 512 can electrically connect the capacitor 232 to the one or more metallization layers 408 in the BEOL region 312b.

[0184] like Figure 5 As further shown, one or more capping layers are depicted, such as capping layer 514, capping layer 516, and / or capping layer 518, etc. Capping layers 514 to 518 may be included on and / or over capacitor 232. Capping layers 514 to 518 may electrically isolate capacitor 232 from other structures in dielectric layer 510. Additionally and / or alternatively, capping layers 514 to 518 may be used as hard mask layers and / or etch stop layers during fabrication of capacitor 232.

[0185] As mentioned above, providing Figure 5 As an example. Other examples may be related to Figure 5 For example, although Figure 5 The capacitor 232 is shown implemented as a planar capacitor, but the capacitor 232 may instead be implemented as a deep trench capacitor (DTC) and / or another type of capacitor.

[0186] FIG. 6A to FIG. 6R 600 is a schematic diagram of an embodiment described herein. Embodiment 600 may be an example process for forming an image sensing device 310 or a portion thereof including a pixel sensor array 316 (which may include a plurality of pixel sensors 200). In some embodiments, in combination with FIG. 6A to FIG. 6R One or more semiconductor process operations described may be performed by one or more semiconductor process tools 102 to 116. In some embodiments, in combination with FIG. 6A to FIG. 6R One or more of the semiconductor processing operations described may be performed by another semiconductor processing tool.

[0187] Reference to Fig. 6A , a device region 420 may be provided. The device region 420 may be provided in the form of a semiconductor wafer, a semiconductor die, and / or another type of semiconductor workpiece.

[0188] like Figure 6B As shown in FIG. 4 , one or more regions of device region 420 may be doped to form one or more photodiodes 212 of one or more pixel sensors 200 in pixel sensor array 316 of image sensing device 310. Additionally, one or more regions of device region 420 may be doped to form p-type implant regions 422. Ion implantation tool 114 may perform one or more ion implantation operations to implant ions in device region 420 to form one or more photodiodes 212 and p-type implant regions 422.

[0189] like Figure 6C As shown in , a plurality of transistors may be formed on and / or over device region 420. For example, one or more semiconductor process tools 102-116 may form transfer gate transistor 214 over photodiode 212, may form reset gate transistor 218, may form source follower transistors 224a and 224b, and / or may form column select transistor 226 for pixel sensor 200.

[0190] In some embodiments, forming a transistor may include depositing a gate electrode of the transistor using a deposition tool 102. The deposition tool 102 may perform one or more deposition operations to form the gate electrode, and the deposition operation may include an ALD operation, a CVD operation, an epitaxy operation, a PVD operation, and / or another type of deposition operation. In some embodiments, one or more semiconductor process tools 102 to 116 use a self-aligned double patterning (SADP) technique and / or another type of multiple patterning technique to form a plurality of patterns for depositing the gate electrode. In some embodiments, EUV lithography is used to form the pattern for forming the gate electrode.

[0191] In some embodiments, forming the transistor may further include doping one or more regions of the device region 420 using the ion implantation tool 114 to form one or more source / drain regions for the transistor. In some embodiments, forming the transistor may include forming spacers on the sidewalls of the gate electrode. The deposition tool 102 may perform one or more deposition operations to form the spacers, and the deposition operations may include an ALD operation, a CVD operation, an epitaxial operation, a PVD operation, and / or another type of deposition operation. In some embodiments, the deposition tool 102 performs a deposition operation to deposit material for the spacers, and the etching tool 108 removes some portion of the material so that the remaining portion corresponds to the spacers.

[0192] In some embodiments, forming the transistor may further include forming a capping layer on and / or over the gate electrode. Deposition tool 102 may perform one or more deposition operations to form the capping layer, and the deposition operations may include an ALD operation, a CVD operation, an epitaxial operation, a PVD operation, and / or another type of deposition operation.

[0193] like Figure 6C As further shown, dielectric layer 452 may be formed on and / or over device region 420 and on and / or over transistors in pixel sensor array 316. Dielectric layer 452 may be referred to as an ILD0 layer. Deposition tool 102 may be used in PVD operations, ALD operations, CVD operations, epitaxy operations, oxidation operations, combined operations, etc. Figure 1 Dielectric layer 452 is deposited in another type of deposition operation as described, and / or in another suitable deposition operation. In some embodiments, planarization tool 110 planarizes dielectric layer 452 after deposition tool 102 deposits dielectric layer 452 .

[0194] like FIG. 6D to FIG. 6F As shown in FIG. 3 , the BEOL region 312 a of the sensing die 306 may be formed. Fig.6D As shown in FIG. 1 , the deposition tool 102 can form the etch stop layer 450 and the first portion of the dielectric region 410. The deposition tool 102 can be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 The etch stop layer 450 and the first portion of the dielectric region 410 are deposited in another type of deposition operation as described, and / or in another suitable deposition operation. In some embodiments, after the deposition tool 102 deposits the etch stop layer 450 and / or the first portion of the dielectric region 410, the planarization tool 110 planarizes the etch stop layer 450 and / or the first portion of the dielectric region 410.

[0195] like Fig.6DAs further shown, contacts (e.g., source / drain contacts, gate contacts) may be formed for transistors of pixel sensors 200 in pixel sensor array 316. To form the contacts, the first portion of dielectric region 410 and / or dielectric layer 452 are etched using the pattern in the photoresist layer to form recesses in which the contacts are to be formed. In these embodiments, deposition tool 102 forms a photoresist layer over the first portion of dielectric region 410. Exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 develops and removes portions of the photoresist layer to expose the pattern. Etching tool 108 etches the first portion of dielectric region 410 and / or dielectric layer 452 based on the pattern to form a plurality of recesses. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for etching the recesses according to a pattern.

[0196] The deposition tool 102 and / or the electroplating tool 112 can deposit the contact in the groove. The deposition tool 102 and / or the electroplating tool 112 can be operated by CVD, PVD, ALD, electroplating, or a combination of the above. Figure 1 The contact is deposited in another deposition operation described and / or another suitable deposition operation. In some embodiments, a seed layer is first deposited, and the contact is deposited above the seed layer. In some embodiments, after the deposition tool 102 and / or the electroplating tool 112 deposits the contact, the planarization tool 110 planarizes the contact.

[0197] like Fig. 6E As shown, additional portions of dielectric region 410 and metallization layer 412 may be formed in BEOL region 312a. For example, deposition tool 102 may deposit a second portion of dielectric region 410 (e.g., using CVD techniques, ALD techniques, PVD techniques, and / or other types of deposition techniques), etching tool 108 may remove portions of the second portion to form a plurality of recesses in the second portion, and deposition tool 102 and / or electroplating tool 112 may form a first metallization layer of metallization layer 412 in the recesses (e.g., using CVD techniques, ALD techniques, PVD techniques, electroplating techniques, and / or other types of deposition techniques), etc. Transfer gate transistor 214, reset gate transistor 218, and column select transistor 226 may be electrically connected to metallization layer 412a. Source follower transistors 224a and 224b may be electrically connected to metallization layer 412b.

[0198] like Fig. 6E As further shown, one or more semiconductor process tools 102 to 116 may form capacitor 232 in BEOL region 312a of sensing die 306. For example, etching tool 108 may form a recess in dielectric region 410, deposition tool 102 and / or electroplating tool 112 may form first conductive layer 502, insulating layer 504, and second conductive layer 506 of capacitor 232. Deposition tool 102 and / or electroplating tool 112 may additionally form bottom metal contact 508, top metal contact 512, and / or capping layers 514 to 518.

[0199] like Fig. 6F As shown in , the deposition tool 102 , the etching tool 108 , the plating tool 112 , and / or another semiconductor processing tool may successively perform similar process operations to form the BEOL region 312 a until a sufficient or desired arrangement of the metallization layer 412 is achieved.

[0200] like Figure 6G As shown in , the bonding tool 116 can perform a bonding operation to bond the sensing die 306 and the circuit die 308 at the bonding interface 314. The bonding tool 116 can use a direct bonding technique, a eutectic bonding technique, a hybrid bonding technique, and / or another type of bonding technique to bond the sensing die 306 and the circuit die 308. Figure 6G As shown, the sensing die 306 and the circuit die 308 can be oriented so that the BEOL region 312a and the BEOL region 312b face each other. This allows the metallization layer 412 of the BEOL region 312a and the metallization layer 408 of the BEOL region 312b to be electrically connected through the bonding contact 414 to electrically connect the sensing die 306 and the circuit die 308 to form the image sensing device 310.

[0201] like Figure 6H As shown in , the backside processing of the sensing die 306 can be performed after the sensing die 306 and the circuit die 308 are bonded. A recess 602 can be formed in the bottom surface of the device region 420 above the p-type implant region 422. The recess 602 can extend partially into the device region 420 to reach the p-type implant region 422.

[0202] In some embodiments, the device area 420 is etched using the pattern in the photoresist layer to form the recess 602. In these embodiments, the deposition tool 102 forms a photoresist layer above the device area 420. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops and removes a portion of the photoresist layer to expose the pattern. The etching tool 108 etches the device area 420 based on the pattern to form the recess 602 in the device area 420. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (for example, using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etch the device area 420 according to the pattern.

[0203] like Fig.6I As shown, the recess 602 may be filled with a dielectric material to form a DTI structure 424. The deposition tool 102 may be operated in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, or a combination of the above. Figure 1 The dielectric material is deposited in another deposition operation as described, and / or in another suitable deposition operation. In some embodiments, after the deposition tool 102 deposits the dielectric material, the planarization tool 110 planarizes the DTI structure 424 .

[0204] like Figure 6J As shown, after forming DTI structure 424, one or more dielectric layers may be formed on and / or over the back side of device region 420. For example, oxide layer 426 may be formed on and / or over device region 420. As another example, oxide layer 428 may be formed on and / or over oxide layer 426. As another example, oxide layer 430 may be formed on and / or over oxide layer 428. Deposition tool 102 may be operated in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, or a combination of the above. Figure 1 The oxide layer 426, the oxide layer 428, and / or the oxide layer 430 are deposited in another deposition operation as described, and / or in another suitable deposition operation. In some embodiments, after the oxide layer 426, the oxide layer 428, and / or the oxide layer 430 are deposited by the deposition tool 102, the planarization tool 110 planarizes the oxide layer 426, the oxide layer 428, and / or the oxide layer 430.

[0205] like Figure 6KAs shown in FIG. 4 , a recess 604 can be formed in the bonding pad region 418. The recess 604 can be formed through the oxide layer 426, the oxide layer 428, and the oxide layer 430, through the device region 420, through the dielectric layer 452, through the etch stop layer 450, and through to the dielectric region 410 located in the BEOL region 312a. The recess 604 is formed completely through the device region 420 so that a dielectric plug can be formed completely through the device region 420 for electrical and / or optical isolation of the pixel sensor 200 in the device region 420. One or more metallization layers 412 in the BEOL region 312a can be exposed through the recess so that a bonding pad can be located above the one or more metallization layers 412.

[0206] In some embodiments, the pattern in the photoresist layer is used to etch the oxide layer 426 to the oxide layer 430, through the device area 420, through the dielectric layer 452, through the etch stop layer 450 and / or the dielectric area 410 to form the recess 604. In these embodiments, the deposition tool 102 forms the photoresist layer above the oxide layer 430. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops and removes a portion of the photoresist layer to expose the pattern. The etching tool 108 etches the oxide layer 426 to the oxide layer 430 through the device area 420, through the dielectric layer 452, through the etch stop layer 450 and / or the dielectric area 410 based on the pattern to form the recess 604. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for forming the grooves 604 according to a pattern.

[0207] like Figure 6L As shown in FIG. 4 , a bonding pad 446 can be formed in a recess 604 in the bonding pad region 418. The bonding pad 446 can be formed so that a top surface of the bonding pad 446 is located below the device region 420. The deposition tool 102 and / or the electroplating tool 112 can be operated in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, a combination of the above, or a combination of the above. Figure 1 Bond pad 446 is deposited in another deposition operation as described, and / or another suitable deposition operation. In some embodiments, a seed layer is deposited first, and bond pad 446 is deposited over the seed layer. In some embodiments, planarization tool 110 planarizes bond pad 446 after deposition tool 102 and / or electroplating tool 112 deposits bond pad 446.

[0208] like Figure 6MAs shown in FIG. 4 , an oxide material is deposited to form an oxide layer 432 on and / or over oxide layer 430. In addition, an oxide material is filled in recess 604 to form a dielectric plug 448 in recess 604. Dielectric plug 448 at least partially surrounds bonding pad 446 and provides electrical and / or optical isolation for pixel sensor 200 in device region 420. Deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, or a combination of the above. Figure 1 The oxide material of oxide layer 432 and dielectric plug 448 is deposited in another deposition operation as described, and / or another suitable deposition operation. In some embodiments, after deposition tool 102 deposits oxide layer 432 and / or dielectric plug 448, planarization tool 110 planarizes oxide layer 432 and / or dielectric plug 448.

[0209] like Figure 6N As shown in , a recess 606 can be formed in the BLC region 416. The recess 606 can be formed through the oxide layer 426, the oxide layer 428, the oxide layer 430, and the oxide layer 432 and reach the device region 420. In some embodiments, the pattern in the photoresist layer is used to etch the oxide layer 426, the oxide layer 428, the oxide layer 430, and the oxide layer 432 to form a plurality of recesses 606. In these embodiments, the deposition tool 102 forms a photoresist layer above the oxide layer 432. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops and removes a portion of the photoresist layer to expose the pattern. The etching tool 108 etches the oxide layer 426, the oxide layer 428, the oxide layer 430, and the oxide layer 432 based on the pattern to form the recess 606. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etch oxide layers 426, 428, 430, and 432 according to a pattern.

[0210] like Fig.6O As shown in , ceramic layer 436 may be formed on and / or over oxide layer 432. Metal layer 438 may be formed on and / or over ceramic layer 436. Ceramic layer 436 and metal layer 438 may be filled in groove 606 to form light blocking structure 444. Deposition tool 102 and / or plating tool 112 may be operated by CVD, PVD, ALD, plating, or a combination of the above. Figure 1The ceramic layer 436 and / or the metal layer 438 are deposited in another deposition operation as described and / or another suitable deposition operation. In some embodiments, the seed layer is deposited first, and the metal layer 438 is deposited on top of the seed layer. In some embodiments, after the deposition tool 102 and / or the electroplating tool 112 deposits the ceramic layer 436 and / or the metal layer 438, the planarization tool 110 planarizes the ceramic layer 436 and / or the metal layer 438.

[0211] like Figure 6P As shown, an oxide layer 440 may be formed on and / or over metal layer 438. Deposition tool 102 may be operated by CVD, PVD, ALD, or a combination of the above. Figure 1 The oxide layer 440 is deposited in another deposition operation as described, and / or in another suitable deposition operation. In some embodiments, after the oxide layer 440 is deposited by the deposition tool 102 , the planarization tool 110 planarizes the oxide layer 440 .

[0212] like Figure 6Q As shown, a portion of the oxide layer 432, a portion of the ceramic layer 436, a portion of the metal layer 438, and / or a portion of the oxide layer 440 may be removed in the pixel sensor array 316 to form a grid structure 434 above the pixel sensor 200. In some embodiments, the oxide layer 432, the ceramic layer 436, the metal layer 438, and / or the oxide layer 440 are etched using a pattern in the photoresist layer to form the grid structure 434. In these embodiments, the deposition tool 102 forms a photoresist layer above the oxide layer 440. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops and removes a portion of the photoresist layer to expose the pattern. The etching tool 108 etches the oxide layer 432, the ceramic layer 436, the metal layer 438, and / or the oxide layer 440 based on the pattern to form the grid structure 434. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for etching oxide layer 432, ceramic layer 436, metal layer 438, and / or oxide layer 440 according to a pattern.

[0213] like Figure 6QAs further shown, a portion of oxide layer 432, a portion of ceramic layer 436, a portion of metal layer 438, and / or a portion of oxide layer 440 may be removed in bonding pad region 418. Additionally, a portion of dielectric plug 448 may be removed to expose bonding pad 446 through dielectric plug 448. This allows an electrical connection to bonding pad 446 to be formed.

[0214] like Figure 6R As shown, buffer oxide layer 442 may be formed on and / or over oxide layer 440 and on and / or over dielectric plug 448. Deposition tool 102 may be operated by CVD, PVD, ALD, or a combination of the above. Figure 1 Buffer oxide layer 442 is deposited in another deposition operation as described, and / or in another suitable deposition operation. In some embodiments, after deposition tool 102 deposits buffer oxide layer 442 , planarization tool 110 planarizes buffer oxide layer 442 .

[0215] As mentioned above, providing FIG. 6A to FIG. 6R As an example. Other examples may be related to FIG. 6A to FIG. 6R Different than described.

[0216] Figure 7 is a schematic diagram of an embodiment 700 of the image sensing device 310 described herein. Figure 7 A cross-sectional view of an embodiment 700 of the image sensing device 310 is depicted. In the embodiment 700, the capacitor 232 can be electrically connected to a metallization layer that is different from the metallization layer that is electrically connected to the source follower transistors 224a and 224b. This allows the capacitor 232 to be flexibly disposed in the sensing die 306, and further allows the size and / or number of the source follower transistors 224a and 224b to be increased.

[0217] like Figure 7 As shown, in the embodiment 700, the image sensing device 310 may include Figure 4For example, in embodiment 700, image sensing device 310 may include a sensing die 306 and a circuit die 308 bonded to sensing die 306 at a bonding interface 314. Sensing die 306 includes pixel sensor 200, pixel sensor 200 includes sensing region 206, sensing region 206 includes photodiode 212 located in device region 420 of sensing die 306. Pixel sensor 200 may include control circuit region 208 located below device region 420, including transfer gate transistor 214, reset gate transistor 218 electrically connected to transfer gate transistor 214, source follower transistors 224a and 224b electrically connected to transfer gate transistor 214 and reset gate transistor 218, capacitor 232 electrically connected to source follower transistors 224a and 224b, and column select transistor 226 electrically connected to capacitor 232. The capacitor 232 is configured to store the photocurrent 210 received from the source-follower transistors 224a and 224b.

[0218] like Figure 7 As further shown, the capacitor 232 can be included in the BEOL region 312a of the sensing die 306. In the embodiment 700 of the image sensing device 310, the capacitor 232 and the source follower transistors 224a and 224b can be electrically connected to different metallization layers. For example, the source follower transistors 224a and 224b can be electrically connected to the metallization layer 412b in the BEOL region 312a of the sensing die 306, and the capacitor 232 can be electrically connected to the metallization layer 412c in the BEOL region 312a of the sensing die 306. This allows the capacitor 232 to be flexibly disposed in the BEOL region 312a, further allowing the size and / or number of the source follower transistors 224a and 224b to be increased. In addition, the placement of the capacitor 232 can be selected to accommodate other devices and / or structures in the BEOL region 312a.

[0219] like Figure 7 As further shown, in embodiment 700 , image sensing device 310 may include an arrangement of elements 402 to 452 similar to image sensing device 310 in embodiment 400 .

[0220] As mentioned above, providing Figure 7 As an example. Other examples may be related to Figure 7 Different than described.

[0221] Figure 8 is a schematic diagram of an embodiment 800 of the image sensing device 310 described herein. Figure 8A cross-sectional view of an embodiment 800 of an image sensing device 310 is depicted. In the embodiment 800, capacitor 232 may be included in circuit die 308 instead of (or in addition to) including capacitor 232 in sensing die 306. This may free up space in sensing die 306 to further increase the size and / or number of source-follower transistors 224a and 224b.

[0222] like Figure 8 As shown in the embodiment 800, the image sensing device 310 may include Figure 4 For example, in embodiment 800, image sensing device 310 may include a sensing die 306 and a circuit die 308 bonded to sensing die 306 at a bonding interface 314. Sensing die 306 includes pixel sensor 200, pixel sensor 200 includes sensing region 206, sensing region 206 includes photodiode 212 located in device region 420 of sensing die 306. Pixel sensor 200 may include a first control circuit region 208a located below device region 420, including transfer gate transistor 214, reset gate transistor 218 electrically connected to transfer gate transistor 214, source follower transistors 224a and 224b electrically connected to transfer gate transistor 214, reset gate transistor 218, and column select transistor 226.

[0223] like Figure 8 As further shown in the embodiment 800, the image sensing device 310 may include a capacitor 232 in the BEOL region 312b of the circuit die 308. This may free up space in the sensing die 306 to further increase the size and / or number of source follower transistors 224a and 224b in the sensing die 306. The capacitor 232 may be included in the second control circuit region 208b associated with the pixel sensor 200 and may be electrically connected to the metallization layer 408 in the BEOL region 312b. The capacitor 232 may be electrically connected to the source follower transistors 224a, 224b and the column select transistor 226 through the metallization layer 408, the metallization layer 412, and the bonding contact 414. The capacitor 232 may be configured to store the photocurrent 210 received from the source follower transistors 224a, 224b.

[0224] like Figure 8 As further shown, in embodiment 800 , image sensing device 310 may include an arrangement of components 402 to 452 similar to image sensing device 310 in embodiment 400 .

[0225] As mentioned above, providing Figure 8 As an example. Other examples may be related to Figure 8Different than described.

[0226] Fig. 9 is a schematic diagram of an embodiment 900 of the image sensing device 310 described herein. Fig. 9 A cross-sectional view of an embodiment 900 of an image sensing device 310 is depicted. In the embodiment 900, source follower transistors 224a, 224b and capacitor 232 may be included in circuit die 308 instead of (or in addition to) including source follower transistors 224a, 224b and capacitor 232 in sensing die 306. Including source follower transistors 224a and 224b in circuit die 308 (e.g., in device region 402 of circuit die 308) may provide a larger area for source follower transistors 224a and 224b relative to including source follower transistors 224a and 224b in sensing die 306. The increased area of ​​source follower transistors 224a and 224b in circuit die 308 may further enable an increase in the size and / or number of source follower transistors 224a and 224b. Additionally, including source follower transistors 224 a and 224 b in circuit die 308 may provide additional area in sense die 306 for other devices and / or layers in sense die 306 .

[0227] like Fig. 9 As shown in the embodiment 900, the image sensing device 310 may include Figure 4 4. For example, in embodiment 900, image sensing device 310 may include a sensing die 306 and a circuit die 308 bonded to sensing die 306 at a bonding interface 314. Sensing die 306 includes pixel sensor 200, pixel sensor 200 includes sensing region 206, sensing region 206 includes photodiode 212 located in device region 420 of sensing die 306. Pixel sensor 200 may include a first control circuit region 208a located below device region 420, including transfer gate transistor 214, reset gate transistor 218 electrically connected to transfer gate transistor 214, and column select transistor 226.

[0228] like Fig. 9As further shown, in the embodiment 900, the source follower transistors 224a and 224b may be included in the second control circuit region 208b in the circuit die 308. The source follower transistors 224a and 224b may be electrically connected to the metallization layer 408 in the BEOL region 312b of the circuit die 308. The source follower transistors 224a and 224b may be electrically connected to the transfer gate transistor 214 and the reset gate transistor 218 through the metallization layer 408, the metallization layer 412, and the bonding contact 414. Including the source follower transistors 224a and 224b in the circuit die 308 (e.g., in the device region 402 of the circuit die 308) may provide a larger area for the source follower transistors 224a and 224b relative to including the source follower transistors 224a and 224b in the sense die 306. Increasing the area of ​​the source follower transistors 224 a and 224 b in the circuit die 308 may further increase the size and / or number of the source follower transistors 224 a and 224 b .

[0229] like Fig. 9 As further shown, in the embodiment 900, the image sensing device 310 may include a capacitor 232 in the BEOL region 312b of the circuit die 308. The capacitor 232 may be included in the third control circuit region 208c associated with the pixel sensor 200 and may be electrically connected to the metallization layer 408 in the BEOL region 312b. The capacitor 232 may be electrically connected to the source follower transistors 224a, 224b through the metallization layer 408. The capacitor 232 may be electrically connected to the column select transistor 226 through the metallization layer 408, the metallization layer 412, and the bonding contact 414. The capacitor 232 may be configured to store the photocurrent 210 received from the source follower transistors 224a, 224b.

[0230] like Fig. 9 As further shown, in embodiment 900 , image sensing device 310 may include an arrangement of components 402 to 452 similar to image sensing device 310 in embodiment 400 .

[0231] As mentioned above, providing Fig. 9 As an example. Other examples may be related to Fig. 9 Different than described.

[0232] Fig.10 is a schematic diagram of an embodiment 1000 of an image sensing device 310 described herein. Fig.10A cross-sectional view of an embodiment 1000 of an image sensing device 310 is depicted. In the embodiment 1000, a plurality of source follower transistors 224a, 224b may be included in a circuit die 308 instead of (or in addition to) including a plurality of source follower transistors 224a, 224b in a sensing die 306. A capacitor 232 is included in the sensing die 306. Including the source follower transistors 224a and 224b in the circuit die 308 and including the capacitor 232 in the sensing die 306 may provide a larger area for the source follower transistors 224a and 224b relative to including the source follower transistors 224a and 224b in the sensing die 306. The increased area of ​​the source follower transistors 224a and 224b in the circuit die 308 may further enable an increase in the size and / or number of the source follower transistors 224a and 224b. Additionally, including source follower transistors 224 a and 224 b in circuit die 308 may provide additional area in sense die 306 for other devices and / or layers in sense die 306 .

[0233] like Fig.10 As shown in the embodiment 1000, the image sensing device 310 may include Figure 4 1000. For example, in embodiment 1000, image sensing device 310 may include sensing die 306 and circuit die 308 bonded to sensing die 306 at bonding interface 314. Sensing die 306 includes pixel sensor 200, pixel sensor 200 includes sensing region 206, sensing region 206 includes photodiode 212 located in device region 420 of sensing die 306. Pixel sensor 200 may include first control circuit region 208a located below device region 420, including transfer gate transistor 214, reset gate transistor 218 electrically connected to transfer gate transistor 214, and column select transistor 226. Second control circuit region 208b may be included in sensing die 306, including capacitor 232. Capacitor 232 may be electrically connected to metallization layer 412 in BEOL region 312a of sensing die 306. The capacitor 232 may be electrically connected to the column select transistor 226 through the metallization layer 412 .

[0234] like Fig.10As further shown, in the embodiment 1000, the source follower transistors 224a, 224b may be included in the third control circuit region 208c in the circuit die 308. The source follower transistors 224a, 224b may be electrically connected to the metallization layer 408 in the BEOL region 312b of the circuit die 308. The source follower transistors 224a and 224b may be electrically connected to the transfer gate transistor 214, the reset gate transistor 218, and the capacitor 232 through the metallization layer 408, the metallization layer 412, and the bonding contact 414. Including the source follower transistors 224a and 224b in the circuit die 308 (e.g., in the device region 402 of the circuit die 308) may provide a larger area for the source follower transistors 224a and 224b relative to including the source follower transistors 224a and 224b in the sense die 306. Increasing the area of ​​the source follower transistors 224 a and 224 b in the circuit die 308 may further increase the size and / or number of the source follower transistors 224 a and 224 b .

[0235] like Fig.10 As further shown, in embodiment 1000 , image sensing device 310 may include an arrangement of components 402 to 452 similar to image sensing device 310 in embodiment 400 .

[0236] As mentioned above, providing Fig.10 As an example. Other examples may be related to Fig.10 Different than described.

[0237] Fig.11 1 is a schematic diagram of example elements of the apparatus 1100 described herein. In some embodiments, one or more semiconductor process tools 102 to 116 and / or wafer / die transport tool 118 may include one or more apparatuses 1100 and / or one or more components of apparatuses 1100. Fig.11 As shown in , device 1100 may include a bus 1110 , a processor 1120 , a memory 1130 , an input component 1140 , an output component 1150 , and / or a communication component 1160 .

[0238] The bus 1110 may include one or more components that enable wired and / or wireless communication between components of the device 1100. The bus 1110 may include one or more components that enable wired and / or wireless communication between components of the device 1100. Fig.11Two or more components of a computer system are coupled together, for example, by operative coupling, communicative coupling, electronic coupling, and / or electric coupling. For example, bus 1110 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 1120 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and / or another type of processing component. Processor 1120 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1120 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0239] The memory 1130 may include volatile and / or non-volatile memory. For example, the memory 1130 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 1130 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 1130 may be a non-transitory computer-readable medium. The memory 1130 may store information related to the operation of the device 1100, one or more instructions, and / or software (e.g., one or more application software). In some embodiments, the memory 1130 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 1120), for example, via the bus 1110. The communicative coupling between processor 1120 and memory 1130 may enable processor 1120 to read and / or process information stored in memory 1130 , and / or store information in memory 1130 .

[0240] Input component 1140 enables device 1100 to receive input, such as user input and / or sensed input. For example, input component 1140 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and / or an actuator. Output component 1150 enables device 1100 to provide output, such as via a display, a speaker, and / or a light emitting diode. Communication component 1160 enables device 1100 to communicate with other devices via a wired connection and / or a wireless connection. For example, communication component 1160 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0241] The device 1100 can perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1130) can store a set of instructions (e.g., one or more instructions or codes) to be executed by the processor 1120. The processor 1120 can execute a set of instructions to perform one or more operations or processes described herein. In some embodiments, a set of instructions executed by one or more processors 1120 prompts one or more processors 1120 and / or the device 1100 to perform one or more operations or processes described herein. In some embodiments, hardwired circuits can be used instead of instructions or in combination with instructions to perform one or more operations or processes described herein. Additionally or alternatively, the processor 1120 can be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuits and software.

[0242] supply Fig.11 The number and arrangement of components shown are provided as an example. Fig.11 Compared to the components shown in , device 1100 may have additional components, fewer components, different components, or components arranged differently. Additionally or alternatively, one group of components (e.g., one or more components) of device 1100 may perform one or more functions described by another group of components of device 1100.

[0243] Fig.12 FIG. 1 is a flow chart of an exemplary process 1200 associated with forming an image sensing device. In some embodiments, the process is performed by one or more semiconductor process tools (eg, one or more semiconductor process tools 102 to 116). Fig.12Additionally or alternatively, Fig.12 One or more process blocks may be performed by one or more components of the apparatus 1100 , such as the processor 1120 , the memory 1130 , the input component 1140 , the output component 1150 , and / or the communication component 1160 .

[0244] like Fig.12 As shown in , process 1200 may include forming, in a sensing die: a photodiode located in a sensing region of a pixel sensor, wherein the pixel sensor includes a transfer gate transistor electrically connected to the photodiode in a pixel sensor array, a reset gate transistor electrically connected to the transfer gate transistor, and a column select transistor (block 1210). For example, one or more semiconductor process tools 102 to 116 as described herein may form, in sensing die 306: a photodiode 212 located in a sensing region 206 of a pixel sensor 200, wherein the pixel sensor 200 includes a transfer gate transistor 214 electrically connected to the photodiode 212 in a pixel sensor array 316, a reset gate transistor 218 electrically connected to the transfer gate transistor 214, and a column select transistor 226.

[0245] like Fig.12 As further shown, the process 1200 may include forming a plurality of source-follower transistors associated with the pixel sensor in at least one of the sensing die or the circuit die (block 1220). For example, one or more semiconductor process tools 102 to 116 described herein may form a plurality of source-follower transistors 224 (e.g., source-follower transistors 224a, source-follower transistors 224b) associated with the pixel sensor 200 in at least one of the sensing die 306 or the circuit die 308.

[0246] like Fig.12 As further shown, the process 1200 may include forming a capacitor in at least one of the sensing die or the circuit die (block 1230). For example, one or more semiconductor process tools 102 to 116 described herein may form a capacitor 232 in at least one of the sensing die 306 or the circuit die 308. In some embodiments, the capacitor 232 is electrically connected to the column select transistor 226 and the plurality of source follower transistors.

[0247] like Fig.12 As further shown, the process 1200 can bond the sensing die and the circuit die (block 1240 ). For example, one or more semiconductor process tools 102 - 116 described herein can bond the sensing die 306 and the circuit die 308 .

[0248] Process 1200 may include additional embodiments, such as any single embodiment, or any combination of embodiments, described below and / or in combination with one or more other processes described elsewhere herein.

[0249] In a first embodiment, forming a capacitor 232 in a sensing die 306 includes forming a capacitor 232 in a control circuit region 208 below the sensing region 206, which includes a photodiode 212, and wherein forming a transfer gate transistor, a reset gate transistor, a plurality of source follower transistors, and a column select transistor includes forming a transfer gate transistor, a reset gate transistor, a plurality of source follower transistors, and a column select transistor in a control circuit region 208 (e.g., the same control circuit region as the capacitor 232).

[0250] In the second embodiment, alone or in combination with the first embodiment, forming the capacitor 232 includes forming the capacitor 232 such that the source follower transistor and the capacitor 232 are electrically connected to the same metallization layer 412 b in the BEOL region 312 a of the sensing die 306 .

[0251] In a third embodiment, alone or in combination with one or more of the first or second embodiments, the source follower transistor is electrically connected to the first metallization layer 412 b in the BEOL region 312 a of the sensing die 306, and forming the capacitor 232 includes: forming the capacitor 232 so that the capacitor 232 is electrically connected to the second metallization layer 412 c in the BEOL region 312 a of the sensing die 306, wherein the second metallization layer 412 c is below the first metallization layer 412 b in the BEOL region 312 a.

[0252] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, forming a transfer gate transistor 214 includes: forming the transfer gate transistor 214 in the first control circuit area 208a, forming a reset gate transistor 218 includes: forming the reset gate transistor 218 in the first control circuit area 208a, forming a column selection transistor 226 includes: forming the column selection transistor 226 in the first control circuit area 208a, and forming a source follower transistor includes: forming a plurality of source follower transistors in the second control circuit area 208b of the sensing die 306.

[0253] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, forming the capacitor 232 includes: forming the capacitor 232 in the sensing die 306 .

[0254] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, forming the capacitor 232 in the sensing die 306 includes: forming the capacitor 232 in the BEOL region 312 a of the sensing die 306 .

[0255] In the seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, forming the capacitor 232 includes: forming the capacitor 232 in the circuit die 308 .

[0256] In the eighth embodiment, alone or in combination with one or more of the first to seventh embodiments, forming the capacitor 232 in the circuit die 308 includes forming the capacitor 232 in the BEOL region 312 b of the circuit die 308 .

[0257] In a ninth embodiment, alone or in combination with one or more of the first to eighth embodiments, the process 1200 includes: after bonding the sensing die 306 and the circuit die 308, forming a recess 604 extending through the device region 420 of the sensing die 306 and penetrating to the BEOL region 312 a of the sensing die 306, forming a bonding pad 446 in the recess 604, wherein the bonding pad 446 is electrically connected to the metallization layer 412 in the BEOL region 312 a, and forming a dielectric plug 448 over the bonding pad 446 in the recess 604.

[0258] In the tenth embodiment, alone or in combination with one or more of the first to ninth embodiments, forming the bonding pad 446 includes: forming the bonding pad 446 in the recess 604 such that a top surface of the bonding pad 446 is located below a bottom surface of the device region 420 .

[0259] In the eleventh embodiment, alone or in combination with one or more of the first to tenth embodiments, forming a transfer gate transistor 214 includes: forming a transfer gate transistor 214 in a first control circuit area 208a in a sensing die 306, forming a reset gate transistor 218 includes: forming a reset gate transistor 218 in a first control circuit area 208a in a sensing die 306, forming a column selection transistor 226 includes: forming a column selection transistor 226 in a first control circuit area 208a in a sensing die 306, forming multiple source follower transistors includes: forming multiple source follower transistors in a first control circuit area 208a in a sensing die 306, and forming a capacitor 232 in a second control circuit area 208b in a circuit die 308.

[0260] Although Fig.12 Example blocks of process 1200 are shown, but in some embodiments, Fig.12 The process 1200 may include additional blocks, fewer blocks, different blocks, or blocks arranged differently than those depicted in FIG. Additionally or alternatively, two or more of the blocks of the process 1200 may be performed in parallel.

[0261] Thus, an image sensing device may include a pixel sensor array, the pixel sensor array including a plurality of pixel sensors. Under the pixel sensors, a plurality of transistors may be included and electrically connected to a back-end-of-line (BEOL) region of the image sensing device. The image sensing device may also include a bonding pad region, including a bonding pad. The dielectric plug may surround a portion of the bonding pad and may extend completely through the semiconductor device region to provide electrical, thermal and / or optical isolation for the pixel sensors of the pixel sensing array. The inclusion of the dielectric plug may provide enhanced electrical, thermal and / or optical isolation while occupying a smaller lateral area. The smaller lateral area of ​​the dielectric plug enables more lateral area in the semiconductor device region to be used for transistors of the pixel sensors of the image sensing device. Thus, one or more transistors may be formed to a larger size, so that one or more transistors may achieve better performance. Additionally and / or alternatively, one or more capacitors in the BEOL region of the image sensing device. The one or more capacitors may enable the photocurrent generated by the one or more pixel sensors to be directly transferred from the one or more source-follower transistors to the one or more capacitors for storage, so that an early shutter operation of the image sensing device may be achieved.

[0262] As described in greater detail above, embodiments described herein provide an image sensing device. The image sensing device includes a sensing die. The image sensing device includes a circuit die bonded to the sensing die at a bonding interface. The sensing die includes a pixel sensor, the pixel sensor includes a sensing region, the sensing region includes a photodiode located in a device region of the sensing die. The pixel sensor includes a control circuit region located below the sensing region, which includes a transfer gate transistor, a reset gate transistor electrically connected to the transfer gate transistor, a plurality of source follower transistors electrically connected to the transfer gate transistor and the reset gate transistor, a capacitor electrically connected to the plurality of source follower transistors, and a column select transistor electrically connected to the capacitor. In some embodiments, the capacitor is configured to store a photocurrent received from the source follower transistor. In some embodiments, the capacitor is included in a back end of line (BEOL) region of the sensing die. In some embodiments, the source follower transistor and the capacitor are electrically connected to the same metallization layer in the BEOL region of the sensing die. In some embodiments, the source follower transistor is electrically connected to a first metallization layer in a BEOL region of the sensing die, the capacitor is electrically connected to a second metallization layer in the BEOL region of the sensing die, and the second metallization layer is located below the first metallization layer in the BEOL region. In some embodiments, the sensing die further comprises: a black level correction (BLC) region adjacent to the pixel sensor and a bonding pad region adjacent to the BLC region, the bonding pad region comprising: a bonding pad electrically connected to a metallization layer in a back-end of line (BEOL) region of the sensing die, wherein a top surface of the bonding pad is located below a device region of the sensing die. In some embodiments, the sensing die further comprises: a dielectric plug located in the bonding pad region and extending through the device region, wherein the dielectric plug at least partially surrounds the bonding pad.

[0263] As described in greater detail above, embodiments described herein provide a method. The method includes forming in a sensing die: a photodiode in a sensing region of a pixel sensor in a pixel sensor array. The method includes forming in a sensing die: a transfer gate transistor in a first control circuit region of the sensing die and electrically connected to the photodiode. The method includes forming in a sensing die: a reset gate transistor in the first control circuit region and electrically connected to the transfer gate transistor. The method includes forming in a sensing die: a column select transistor in the first control circuit region. The method includes forming in a circuit die: a plurality of source follower transistors in a second control circuit region associated with the pixel sensor. The method includes forming a capacitor in at least one of the sensing die or the circuit die, wherein the capacitor is electrically connected to the column select transistor and the plurality of source follower transistors. The method includes joining the sensing die and the circuit die. In some embodiments, wherein forming the capacitor includes: forming the capacitor in the sensing die. In some embodiments, forming a capacitor in the sensing die includes: forming a capacitor in a back-end-of-line (BEOL) region of the sensing die, wherein in the BEOL region, the capacitor is included in a third control circuit region associated with the pixel sensor. In some embodiments, forming a capacitor includes: forming a capacitor in a circuit die. In some embodiments, forming a capacitor in the circuit die includes: forming a capacitor in a back-end-of-line (BEOL) region of the circuit die. In some embodiments, the method further includes: after bonding the sensing die and the circuit die, forming a recess extending through the device region of the sensing die and passing into the back-end-of-line (BEOL) region of the sensing die; forming a bonding pad in the recess, wherein the bonding pad is electrically connected to a metallization layer in the BEOL region; and forming a dielectric plug above the bonding pad in the recess. In some embodiments, forming a bonding pad includes: forming the bonding pad in the recess so that a top surface of the bonding pad is below a bottom surface of the device region.

[0264] As described in greater detail above, embodiments described herein provide an image sensing device. The image sensing device includes a sensing die, the sensing die including a pixel sensor. The pixel sensor includes a sensing region, the sensing region including a photodiode located in a device region of the sensing die. The pixel sensor includes a first control circuit region located below the sensing region. The first control circuit region includes a transfer gate transistor, a reset gate transistor electrically connected to the transfer gate transistor, a plurality of source follower transistors electrically connected to the transfer gate transistor and the reset gate transistor, and a column select transistor. The image sensing device includes a circuit die, bonded to the sensing die at a bonding interface, including a second control circuit region. The second control circuit region includes a capacitor electrically connected to the plurality of source follower transistors and the column select transistor, wherein the capacitor is configured to store a photocurrent received from the source follower transistor. In some embodiments, wherein the capacitor is included in a back-end-of-line (BEOL) region of the circuit die. In some embodiments, wherein the capacitor is vertically located below the source follower transistor. In some embodiments, the sensing die further comprises: a p-type implant region at least partially surrounding the photodiode, and a deep trench isolation region (DTI) located above the p-type implant region and at least partially surrounding the photodiode. In some embodiments, the sensing die further comprises: a black level correction (BLC) region adjacent to the pixel sensor, and a bonding pad region adjacent to the BLC region. The bonding pad region comprises: a bonding pad electrically connected to a metallization layer in a back-end of line (BEOL) region of the sensing die, wherein a top surface of the bonding pad is located below the device region of the sensing die. In some embodiments, the sensing die further comprises: a dielectric plug in the bonding pad region and extending through the device region.

[0265] As described in more detail above, embodiments described herein provide an image sensing device. The image sensing device includes a sensing die and a circuit die. The circuit die is bonded to the sensing die at a bonding interface, and wherein the sensing die includes a pixel sensor. The pixel sensor includes a sensing region and a control circuit region. The sensing region includes a photodiode located in the device region of the sensing die. The control circuit region is located below the device region and includes a transfer gate transistor, a reset gate transistor, a plurality of source follower transistors, a capacitor, and a column select transistor. The reset gate transistor is electrically connected to the transfer gate transistor. A plurality of source follower transistors are electrically connected to the transfer gate transistor and the reset gate transistor. The capacitor is electrically connected to these source follower transistors. The column select transistor is electrically connected to the capacitor. In some embodiments, the capacitor is included in a back-end process region of the sensing die. In some embodiments, these source follower transistors and the capacitor are electrically connected to the same metallization layer in the back-end process region of the sensing die. In some embodiments, the source follower transistors are electrically connected to a first metallization layer in a back-end process region of the sensing die; the capacitor is electrically connected to a second metallization layer in a back-end process region of the sensing die; and the second metallization layer is located below the first metallization layer in the back-end process region. In some embodiments, the sensing die further comprises a black level correction region and a bonding pad region. The black level correction region is adjacent to the pixel sensor. The bonding pad region is adjacent to the black level correction region. The bonding pad region comprises a bonding pad, the bonding pad being electrically connected to the metallization layer in the back-end process region of the sensing die, wherein the top surface of the bonding pad is located below the device region of the sensing die. In some embodiments, the sensing die further comprises a dielectric plug, the dielectric plug being located in the bonding pad region and extending through the device region, wherein the dielectric plug at least partially surrounds the bonding pad. In some embodiments, the capacitor is vertically located below the source follower transistors. In some embodiments, the sensing die further comprises a p-type implant region and a deep trench isolation region. The p-type implant region at least partially surrounds the photodiode. A deep trench isolation region is located above the p-type implant region and at least partially surrounds the photodiode.

[0266] As described in more detail above, embodiments described herein provide an image sensing device. The image sensing device includes a sensing die, a circuit die, and a capacitor. The sensing die includes a photodiode in a sensing region of a pixel sensor, wherein the pixel sensor is included in a pixel sensor array; a transfer gate transistor, included in a first control circuit region of the sensing die, electrically connected to the photodiode; a reset gate transistor, included in the first control circuit region, electrically connected to the transfer gate transistor; and a column select transistor, included in the first control circuit region. The circuit die includes a plurality of source follower transistors, included in a second control circuit region associated with the pixel sensor. The capacitor is included in at least one of the sensing die or the circuit die, wherein the capacitor is electrically connected to the column select transistor and these source follower transistors. In some embodiments, wherein the capacitor is included in a back-end process region of the sensing die. In some embodiments, wherein these source follower transistors and the capacitor are electrically connected to the same metallization layer in the back-end process region of the sensing die. In some embodiments, the source follower transistors are electrically connected to a first metallization layer in a back-end process region of the sensing die; the capacitor is electrically connected to a second metallization layer in a back-end process region of the sensing die; and the second metallization layer is located below the first metallization layer in the back-end process region. In some embodiments, the capacitor is vertically located below the source follower transistors. In some embodiments, the sensing die further includes a p-type implant region and a deep trench isolation region. The p-type implant region at least partially surrounds the photodiode. The deep trench isolation region is located above the p-type implant region and at least partially surrounds the photodiode.

[0267] As described in more detail above, embodiments described herein provide an image sensing device. The image sensing device includes a sensing die and a circuit die. The sensing die includes a pixel sensor. The pixel sensor includes a sensing region and a first control circuit region. The sensing region includes a photodiode in a device region of the sensing die. The first control circuit region is located below the sensing region and includes a transfer gate transistor, a reset gate transistor, a plurality of source follower transistors, and a column select transistor. The reset gate transistor is electrically connected to the transfer gate transistor. A plurality of source follower transistors are electrically connected to the transfer gate transistor and the reset gate transistor. The circuit die is bonded to the sensing die at a bonding interface and includes a capacitor, which is electrically connected to these source follower transistors and the column select transistor. In some embodiments, the capacitor is included in a back-end process region of the sensing die. In some embodiments, these source follower transistors and the capacitor are electrically connected to the same metallization layer in the back-end process region of the sensing die. In some embodiments, the source follower transistors are electrically connected to a first metallization layer in a back-end process region of the sensing die; the capacitor is electrically connected to a second metallization layer in a back-end process region of the sensing die; and the second metallization layer is located below the first metallization layer in the back-end process region. In some embodiments, the capacitor is vertically located below the source follower transistors. In some embodiments, the sensing die further includes a p-type implant region and a deep trench isolation region. The p-type implant region at least partially surrounds the photodiode. The deep trench isolation region is located above the p-type implant region and at least partially surrounds the photodiode.

[0268] As used herein, "satisfies a threshold" may refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc., depending on the context.

[0269] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. It should be understood by those skilled in the art that they can easily use the present disclosure as a basis to design or modify other processes and structures to perform the same purpose and / or achieve the same advantages of the embodiments described herein. It should also be recognized by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various modifications, substitutions and changes may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensing device, characterized in that: Include: a sensing die; and A circuit die is bonded to the sensing die at a bonding interface, and the sensing die includes a pixel sensor, and the pixel sensor includes: a sensing region including a photodiode located in a device region of the sensing die; and A control circuit area, located below the device area, comprising: a transfer gate transistor; a reset gate transistor electrically connected to the transfer gate transistor; A plurality of source follower transistors electrically connected to the transfer gate transistor and the reset gate transistor; a capacitor electrically connected to the plurality of source follower transistors; as well as A column selection transistor is electrically connected to the capacitor.

2. An image sensing device, characterized in that: Include: A sensing chip, comprising: a photodiode in a sensing region of a pixel sensor, wherein the pixel sensor is included in a pixel sensor array; a transfer gate transistor, included in a first control circuit region of the sensing die and electrically connected to the photodiode; a reset gate transistor, included in the first control circuit region, electrically connected to the transfer gate transistor; and a column selection transistor included in the first control circuit region; A circuit chip, comprising: a plurality of source follower transistors included in a second control circuit region associated with the pixel sensor; and A capacitor is included in at least one of the sensing die or the circuit die, wherein the capacitor is electrically connected to the column selection transistor and the plurality of source follower transistors.

3. An image sensing device, characterized in that: Include: A sensing chip, comprising: A pixel sensor comprising: a sensing region including a photodiode in a device region of the sensing die; A first control circuit area, located below the sensing area, includes: a transfer gate transistor; a reset gate transistor electrically connected to the transfer gate transistor; a plurality of source follower transistors electrically connected to the transfer gate transistor and the reset gate transistor; and a column selection transistor; and A circuit die is bonded to the sensing die at a bonding interface, comprising: A second control circuit area, comprising: A capacitor is electrically connected to the plurality of source follower transistors and the column selection transistor.

4. The image sensing device according to claim 1, 2 or 3, characterized in that: The capacitor is included in a back-end process area of ​​the sensing die.

5. The image sensing device according to claim 4, wherein: The plurality of source follower transistors and the capacitor are electrically connected to a same metallization layer in the back-end process area of ​​the sensing die.

6. The image sensing device according to claim 4, wherein: wherein the plurality of source follower transistors are electrically connected to a first metallization layer in the back-end process area of ​​the sensing die; wherein the capacitor is electrically connected to a second metallization layer in the back-end process area of ​​the sensing die; as well as In the back-end process area, the second metallization layer is located below the first metallization layer.

7. The image sensing device according to claim 1 or 3, characterized in that: The sensing chip further comprises: a black level correction region adjacent to the pixel sensor; and A bonding pad area, adjacent to the black level correction area, comprising: A bonding pad is electrically connected to a metallization layer in a back-end process area of ​​the sensing die, wherein a top surface of the bonding pad is located below the device area of ​​the sensing die.

8. The image sensing device according to claim 7, wherein: The sensing chip further comprises: A dielectric plug is located in the bonding pad region and extends through the device region, wherein the dielectric plug at least partially surrounds the bonding pad.

9. The image sensing device according to claim 1, 2 or 3, characterized in that: The capacitor is vertically located below the plurality of source follower transistors.

10. The image sensing device according to claim 1, 2 or 3, characterized in that: The sensing chip further comprises: a p-type implant region at least partially surrounding the photodiode; and A deep trench isolation region is located above the p-type implant region and at least partially surrounds the photodiode.

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