Low-cost satellite high-speed bus data transceiving device based on 10-gigabit network

Abstract

The utility model relates to the technical field of low-cost satellite ground test platforms, in particular to a low-cost satellite high-speed bus data transceiving device based on a 10-gigabit network. Comprising a power supply module, a core board card, an FPGA chip, ten RS422 transceiver chips, ten LVDS transceiver chips, an external storage chip and a shell, the core board card is arranged in the shell, the FPGA chip, the ten RS422 transceiver chips and the ten LVDS transceiver chips are arranged on the core board card, the FPGA chip is electrically connected with each RS422 transceiver chip, each LVDS transceiver chip and the external storage chip, and the external storage chip is electrically connected with the shell. Through the above structure, receiving, transmitting, processing and analyzing of satellite high-speed bus data can be completed, and the system is suitable for various aerospace satellite digital bus data test platforms.

Description

Technical Field

[0001] The utility model relates to the technical field of low-cost satellite ground test platforms, in particular to a low-cost satellite high-speed bus data transceiver based on a 10 Gigabit network. Background Art

[0002] The satellite high-speed bus ground test platform is a diversified and highly integrated dedicated platform. At present, it is mainly based on standard platform systems such as CPCI / PXI / PCIE and other customized designs, which are extremely expensive. The cost is mainly concentrated on the platform control module and the corresponding board-level classification design, resulting in a high test platform and a long cycle.

[0003] In order to meet the demand for low cost and improve the general integration requirements of satellite processing systems, the use of mature network communication technology for general networking design is a better solution. Therefore, there is an urgent need for a highly integrated, low-cost satellite high-speed bus data transceiver based on a 10 Gigabit network for ground testing of aerospace satellite high-speed data transceiver. Utility Model Content

[0004] The purpose of the utility model is to provide a low-cost satellite high-speed bus data transceiver based on a 10 Gigabit network, which can complete satellite high-speed bus data transceiver, processing and analysis, and is suitable for various aerospace satellite digital bus data test platforms.

[0005] To achieve the above-mentioned purpose, the utility model adopts a low-cost satellite high-speed bus data transceiver device based on a 10 Gigabit network, including a power module, a core board, an FPGA chip, ten RS422 transceiver chips, ten LVDS transceiver chips, an external storage chip and a shell. The core board is arranged in the shell, and the core board is provided with the FPGA chip, ten RS422 transceiver chips and ten LVDS transceiver chips. The FPGA chip is electrically connected to each of the RS422 transceiver chips, each of the LVDS transceiver chips and the external storage chip respectively.

[0006] Among them, the low-cost satellite high-speed bus data transceiver device based on 10 Gigabit network also includes a temperature control module, and the temperature control module is arranged on the core board.

[0007] Wherein, the low-cost satellite high-speed bus data transceiver device based on 10 Gigabit network also includes a fan control module, and the fan control module is connected to the FPGA chip.

[0008] The low-cost satellite high-speed bus data transceiver device based on 10 Gigabit network also includes a network interface chip, and the network interface chip is arranged on the FPGA chip.

[0009] Wherein, the FPGA chip has a device synchronization interface.

[0010] The utility model discloses a low-cost satellite high-speed bus data transceiver device based on a 10 Gigabit network. A plurality of double-row connectors are arranged on the back panel of the shell. The power module, the RS422 transceiver chip and the LVDS transceiver chip are installed inside the shell. The device supports satellite high-speed LVDS / RS422 electrical data transceiver and communication interaction capabilities, can perform LVDS / RS422 conversion design according to actual electrical types, supports communication protocol network update solidification form, can complete satellite high-speed bus data transceiver, processing and analysis, and is suitable for various aerospace satellite digital bus data test platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0012] Figure 1 The utility model is a structural schematic diagram of a low-cost satellite high-speed bus data transceiver device based on 10 Gigabit network.

[0013] Figure 2 It is a structural front view of the shell of the utility model.

[0014] Figure 3 It is a structural rear view of the shell of the utility model.

[0015] 1-power module, 2-core board, 3-FPGA chip, 4-temperature control module, 5-fan control module, 6-RS422 transceiver chip, 7-LVDS transceiver chip, 8-device synchronization interface, 9-external storage chip, 10-network interface chip, 11-housing. DETAILED DESCRIPTION

[0016] See also Figure 1 to Figure 3 ,in Figure 1 This is a schematic diagram of the structure of a low-cost satellite high-speed bus data transceiver based on 10G network. Figure 2 This is the front view of the shell structure. Figure 3 It is the rear view of the shell structure.

[0017] The utility model provides a low-cost satellite high-speed bus data transceiver device based on a 10 Gigabit network, comprising a power module 1, a core board 2, an FPGA chip 3, ten RS422 transceiver chips 6, ten LVDS transceiver chips 7, an external storage chip 9 and a shell 11, wherein the core board 2 is arranged in the shell 11, and the core board 2 is provided with the FPGA chip 3, the ten RS422 transceiver chips 6 and the ten LVDS transceiver chips 7, and the FPGA chip 3 is electrically connected to each of the RS422 transceiver chips 6, each of the LVDS transceiver chips 7 and the external storage chip 9 respectively.

[0018] In this embodiment, a plurality of double-row connectors are provided on the back panel of the shell 11, and the power module 1, the RS422 transceiver chip 6, and the LVDS transceiver chip 7 are installed inside the shell 11. Each of the RS422 transceiver chip 6 provides four differential interfaces, and each of the LVDS transceiver chip 7 provides four differential interfaces, supporting the satellite high-speed LVDS / RS422 electrical data transceiver and communication interaction capabilities, and can perform LVDS / RS422 conversion design according to the actual electrical type, support communication protocol network update solidification form, and use a general high-integration form to achieve up to a maximum of 40xLVDS / RS422 interface physical differential design, which can complete satellite high-speed bus data transceiver, processing and analysis, and adapt to various types of aerospace satellite digital bus data test platforms.

[0019] Furthermore, the low-cost satellite high-speed bus data transceiver device based on 10 Gigabit network also includes a temperature control module 4, and the temperature control module 4 is arranged on the core board 2.

[0020] In this embodiment, the temperature control module 4 is used to monitor the temperature inside the housing 11 .

[0021] Furthermore, the low-cost satellite high-speed bus data transceiver device based on 10 Gigabit network also includes a fan control module 5, and the fan control module 5 is connected to the FPGA chip 3.

[0022] In this embodiment, a fan is installed in the housing 11, and the fan control module 5 is used to control the fan to achieve the effect of air cooling and heat dissipation.

[0023] Furthermore, the low-cost satellite high-speed bus data transceiver device based on 10 Gigabit network also includes a network interface chip 10, and the network interface chip 10 is arranged on the FPGA chip 3.

[0024] In this embodiment, a standard 10 Gigabit network interface communication form is adopted, supporting TCP / IP or UDP transmission. The low-cost satellite high-speed bus data transceiver based on the 10 Gigabit network directly interacts with the PC through the network interface chip 10 to perform upper computer software data processing and forwarding, and receives an external synchronous PPS / clock interface to realize synchronization of the entire machine.

[0025] Furthermore, the FPGA chip 3 has a device synchronization interface 8 .

[0026] In this implementation, the FPGA chip 3 is responsible for synchronization and network connection between devices, and a custom protocol is used in the device synchronization interface 8 for synchronization cascading.

[0027] The above disclosure is only a preferred embodiment of the present invention, and certainly cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made according to the claims of the present invention still fall within the scope covered by the utility model.

Claims

1. A low-cost satellite high-speed bus data transceiver based on 10 Gigabit network, characterized in that: It includes a power module, a core board, an FPGA chip, ten RS422 transceiver chips, ten LVDS transceiver chips, an external storage chip and a shell. The core board is arranged in the shell. The core board is provided with the FPGA chip, ten RS422 transceiver chips and ten LVDS transceiver chips. The FPGA chip is electrically connected to each RS422 transceiver chip, each LVDS transceiver chip and the external storage chip respectively.

2. The low-cost satellite high-speed bus data transceiver device based on 10 Gigabit network as claimed in claim 1, characterized in that: The low-cost satellite high-speed bus data transceiver device based on 10 Gigabit network also includes a temperature control module, and the temperature control module is arranged on the core board.

3. The low-cost satellite high-speed bus data transceiver based on 10 Gigabit network as claimed in claim 2, characterized in that: The low-cost satellite high-speed bus data transceiver device based on 10 Gigabit network also includes a fan control module, and the fan control module is connected to the FPGA chip.

4. The low-cost satellite high-speed bus data transceiver based on 10 Gigabit network as claimed in claim 2, characterized in that: The low-cost satellite high-speed bus data transceiver device based on 10 Gigabit network also includes a network interface chip, and the network interface chip is arranged on the FPGA chip.

5. The low-cost satellite high-speed bus data transceiver based on 10 Gigabit network as claimed in claim 1, characterized in that: The FPGA chip has a device synchronization interface.

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