CMOS (complementary metal oxide semiconductor) data clearing circuit
By using the initial clear signal generation circuit and diode parallel structure in the CMOS data clearing circuit, automatic restart is realized when CMOS is cleared, solving the problem of manual restart in the prior art, simplifying user operations and ensuring signal isolation.
Patent Information
- Application Number
- CN202420232171.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-31
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2034-01-31
AI Technical Summary
The existing computer motherboard needs to restart independently when clearing CMOS settings, resulting in the user having to manually execute the restart operation after clearing CMOS, which increases the operation complexity.
Design a CMOS data clearing circuit, through the initial clear signal generation circuit, the first diode D1 and the second diode D2, and connect the button switch in parallel to realize the simultaneous processing of the SYSRST signal and the RTCRST signal, using pull-up resistors and filtering Capacitors are signal isolation, allowing the use of a button switch to simultaneously enable restart and clear CMOS functions.
It realizes automatic restart operation when clearing CMOS, simplifies user operation process, avoids manual restart steps, and ensures that the two sets of signals are isolated from each other and are not affected.
Smart Images
Figure CN222300025U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electronic circuits, in particular to a CMOS data clearing circuit. Background Art
[0002] CMOS is the abbreviation of Complementary Metal Oxide Semiconductor. It refers to a technology used to manufacture large-scale integrated circuit chips or chips manufactured using this technology. It is a readable and writable RAM chip on the computer motherboard, which is used to save the data after the BIOS sets the computer hardware parameters. BIOS setup / clear (restore default settings) is also customarily called CMOS setup / clear (restore default settings).
[0003] Most existing computer motherboards have a separate clear CMOS switch button and a separate computer restart button. The two functions are separate and independent. When clearing the CMOS settings, you need to restart or reboot the computer to restore the default settings after clearing the CMOS settings and reconfigure the system, so as to correct some errors or setting conflicts in the CMOS settings that may not take effect. Therefore, after clearing the CMOS, the user must manually restart the computer. Utility Model Content
[0004] In view of the above technical problems, the utility model provides a CMOS data clearing circuit which can realize a system restarting action while clearing the CMOS.
[0005] An embodiment of the utility model provides a CMOS data clearing circuit, which is used to clear the CMOS data of a computer. The circuit includes an initial clearing signal generating circuit, a first diode D1, a second diode D2 and a key switch. The cathodes of the first diode D1 and the second diode D2 are connected in parallel to a first end of the key switch, and the second end of the key switch is grounded. The anode of the first diode D1 is connected to a restart signal source, and the anode of the second diode D2 is connected to the initial clearing signal generating circuit.
[0006] Optionally, the circuit includes a pull-up resistor R1 and a first power supply, one end of the pull-up resistor R1 is connected to the anode of the first diode D1, and the other end is connected to the first power supply.
[0007] Optionally, the circuit includes a pull-up resistor R2 and a second power supply, one end of the pull-up resistor R2 is connected to the anode of the second diode D2, and the other end is connected to the second power supply.
[0008] Optionally, the resistance value of the pull-up resistor R1 is different from the resistance value of the pull-up resistor R2.
[0009] Optionally, the circuit comprises a filtering circuit.
[0010] Optionally, the filtering circuit includes a filtering capacitor C1, one end of the filtering capacitor C1 is connected to the anode of the first diode D1, and the other end is grounded.
[0011] Optionally, the filtering circuit includes a filtering capacitor C2, one end of the filtering capacitor C2 is connected to the anode of the second diode D2, and the other end is grounded.
[0012] Optionally, the filter circuit includes a filter capacitor C3, one end of the filter capacitor C3 is connected to the first end of the key switch, and the other end of the filter capacitor C3 is grounded.
[0013] Optionally, the capacitance values of the filter capacitor C1, the filter capacitor C2 and the filter capacitor C3 are equal.
[0014] In the technical solution provided by the embodiment of the present utility model, the cathodes of the first diode D1 and the second diode D2 are connected in parallel to the first end of the push switch, the second end of the push switch is grounded, the anode of the first diode D1 is connected to the restart signal source, and the anode of the second diode D2 is connected to the initial clear signal generating circuit. Compared with the prior art, the present utility model uses two groups of signals, SYSRST signal and RTCRST signal, to simultaneously realize the restart and clear CMOS functions through a push switch; by adding two diode devices, the first diode D1 and the second diode D2, the two groups of signals can be isolated from each other without being affected. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 The utility model is a circuit diagram of a CMOS data clearing circuit. DETAILED DESCRIPTION
[0016] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.
[0017] It should be noted that when an element is described as being "connected" or "connected to" another element, it may be directly connected to the other element, or one or more intermediate elements may exist therebetween. The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning.
[0018] Please refer to Figure 1 The present invention shows a CMOS data clearing circuit for clearing CMOS data of a computer. The circuit includes an initial clear signal generating circuit, a first diode D1, a second diode D2 and a key switch. The cathodes of the first diode D1 and the second diode D2 are connected in parallel to a first end of the key switch, and the second end of the key switch is grounded. The anode of the first diode D1 is connected to a restart signal source, and the anode of the second diode D2 is connected to the initial clear signal generating circuit.
[0019] In the present invention, the initial clear signal generating circuit is used to maintain a high potential RTCRST signal, and the restart signal source provides a restart signal SYSRST during the operation of the mainboard. A restart button is usually provided on the host of the electronic device. When the restart button is pressed, a restart signal is provided to the reset circuit.
[0020] Please refer to Figure 1 As shown, when the system is restarted, the "SYSRST_N" signal is grounded (level 0 potential) through the key switch. Similarly, when clearing CMOS, the "RTCRST_N" signal is grounded (level 0 potential) through the key switch. This can be achieved by connecting these two sets of signals together and using the same key switch SW1. At the same time, two diode devices, the first diode D1 and the second diode D2, are added to achieve signal reverse isolation. The SYSRST_N signal can be forward-conducted through the first diode D1 to reach the key switch SW1 to achieve the key restart function, but at the same time it will reach the cathode of the second diode D2. Since the second diode D2 is reverse-cutoff, the signal cannot reach the anode through the second diode D2. Since the anode of the second diode D2 is the connected RTCRST_N signal, the SYSRST_N signal can be restarted through the first diode D1, but cannot pass through the second diode D2 to affect the function of the RTCRST_N signal; similarly, the RTCRST_N signal can be forward-conducted through the second diode D2 to reach the key switch SW1 to achieve the key clear CMOS function, but at the same time it will reach the cathode of the first diode D1, that is, pin 1. Since the first diode D1 is reverse-cutoff, the signal cannot reach the anode, that is, pin 2, through the first diode D1. Since the anode, that is, pin 2, of the first diode D1 is the connected SYSRST_N signal, the RTCRST_N signal can be restarted through the first diode D1, but cannot pass through the second diode D2 to affect the function of the RTCRST_N signal; so that the two groups of signals will not affect each other, and the clear CMOS and restart functions are achieved at the same time.
[0021] In one embodiment of the present utility model, the circuit includes a pull-up resistor R1 and a pull-up resistor R2, one end of the pull-up resistor R1 is connected to the anode of the first diode D1, and the other end is connected to the first power supply, one end of the pull-up resistor R2 is connected to the anode of the second diode D2, and the other end is connected to the second power supply, and the resistance value of the pull-up resistor R1 is different from the resistance value of the pull-up resistor R2. Specifically, for example, the resistance value of the pull-up resistor R1 is 10K ohms, and the resistance value of the pull-up resistor R2 is 20K ohms.
[0022] In the utility model, the pull-up resistors R1 and R2 are used to realize the default high level, so that the two groups of signals are defaulted to the high level, and the low level is the low effective state, realizing the corresponding restart and clear CMOS functions.
[0023] In one embodiment of the present utility model, the circuit includes a filter circuit, the filter circuit includes a filter capacitor C1, one end of the filter capacitor C1 is connected to the anode of the first diode D1, and the other end is grounded, the filter circuit includes a filter capacitor C2, one end of the filter capacitor C2 is connected to the anode of the second diode D2, and the other end is grounded.
[0024] In one embodiment of the present invention, the filter circuit further includes a filter capacitor C3, one end of the filter capacitor C3 is connected to the first end of the key switch, and the other end of the filter capacitor C3 is grounded. The capacitance values of the filter capacitors C1, C2 and C3 are equal, and are used to filter out the interference of miscellaneous signals.
[0025] The utility model uses two groups of signals, SYSRST signal and RTCRST signal, to simultaneously realize restart and clear CMOS functions through a key switch; and by adding two diode devices, a first diode D1 and a second diode D2, the two groups of signals can be isolated from each other without being affected.
[0026] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A CMOS data clearing circuit, used for clearing the CMOS data of a computer, characterized in that: The circuit includes an initial clear signal generating circuit, a first diode D1, a second diode D2 and a key switch, wherein the cathodes of the first diode D1 and the second diode D2 are connected in parallel to a first end of the key switch, the second end of the key switch is grounded, the anode of the first diode D1 is connected to a restart signal source, and the anode of the second diode D2 is connected to the initial clear signal generating circuit.
2. The CMOS data clearing circuit according to claim 1, characterized in that: The circuit includes a pull-up resistor R1 and a first power supply. One end of the pull-up resistor R1 is connected to the anode of the first diode D1, and the other end is connected to the first power supply.
3. The CMOS data clearing circuit according to claim 2, characterized in that: The circuit includes a pull-up resistor R2 and a second power supply, wherein one end of the pull-up resistor R2 is connected to the anode of the second diode D2, and the other end of the pull-up resistor R2 is connected to the second power supply.
4. The CMOS data clearing circuit according to claim 3, characterized in that: The resistance value of the pull-up resistor R1 is different from the resistance value of the pull-up resistor R2.
5. The CMOS data clearing circuit according to claim 3, characterized in that: The circuit includes a filtering circuit.
6. The CMOS data clearing circuit according to claim 5, characterized in that: The filter circuit comprises a filter capacitor C1 , one end of which is connected to the anode of the first diode D1 , and the other end of which is grounded.
7. The CMOS data clearing circuit according to claim 6, characterized in that: The filter circuit comprises a filter capacitor C2, one end of the filter capacitor C2 is connected to the anode of the second diode D2, and the other end is grounded.
8. The CMOS data clearing circuit according to claim 7, characterized in that: The filter circuit comprises a filter capacitor C3, one end of the filter capacitor C3 is connected to the first end of the key switch, and the other end of the filter capacitor C3 is grounded.
9. The CMOS data clearing circuit according to claim 8, characterized in that: The capacitance values of the filter capacitor C1, the filter capacitor C2 and the filter capacitor C3 are equal.