Delay circuit and delay trigger control circuit
By introducing adjustable resistors and capacitors, low-pass filtering circuits and trigger level adjustment circuits into the delay circuit, the precise adjustment of the delay time is achieved, which solves the problem of poor flexibility of the existing delay circuits and improves the circuit Stability and adaptability.
Patent Information
- Application Number
- CN202420111182.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-16
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2034-01-16
AI Technical Summary
The existing delay circuit has poor flexibility and cannot accurately adjust the delay time according to actual conditions, resulting in a high probability of false triggering and affecting the stability of the circuit.
Design a delay circuit including a delay structure, a delay adjustment structure and a comparator. Through adjustable resistors and adjustable capacitors, low-pass filtering circuits and trigger level adjustment circuits, precise adjustment of the delay time is achieved, and the delay time is enhanced. Circuit flexibility.
It improves the flexibility and accuracy of the delay circuit, reduces the probability of false triggering, enhances the stability and adaptability of the circuit, and can accurately adjust the delay time according to actual needs.
Smart Images
Figure CN222301796U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of electronic technology, in particular to a delay circuit and a delay trigger control circuit. Background Art
[0002] With the vigorous development of power electronics, the requirements for the integration and power density of power electronic products are getting higher and higher. In power electronic design, due to the small space, limited layout, and serious internal interference problems, the internal trigger circuit is often triggered by mistake, resulting in the product not working properly. In order to solve this problem, it is necessary to design a delay trigger circuit to greatly reduce the probability of false triggering and allow the circuit to operate correctly and stably. At present, the delay effect of the commonly used delay trigger circuit is achieved through a resistor-capacitor (RC) delay circuit. Figure 1 It is the circuit structure diagram of the traditional RC delay circuit; Figure 1 As shown, the RC delay circuit consists of a resistor R and a capacitor C. After the power passes through the resistor R, the capacitor C will be charged, and the voltage at point A will start to increase from 0. For the subsequent circuit, the time t taken for point A to rise to the effective voltage required by the subsequent circuit is the delay time.
[0003] However, conventional RC delay circuits have a single circuit and fixed components, and are less flexible in use. The delay time control is not precise and flexible enough, and the delay time cannot be accurately adjusted according to actual conditions.
[0004] In view of the above technology, it is an urgent problem to be solved by those skilled in the art to find a delay circuit with high flexibility and the ability to accurately adjust the delay duration. Utility Model Content
[0005] The utility model aims to provide a delay circuit and a delay trigger control circuit to solve the problem that the current delay circuit has poor flexibility and cannot accurately adjust the delay duration according to actual conditions.
[0006] In order to solve the above technical problems, the utility model provides a delay circuit, comprising: a delay structure, a delay adjustment structure and a first comparator; wherein the delay structure comprises a delay resistor and a delay capacitor;
[0007] The first end of the delay resistor is connected to the output end of the trigger circuit; after receiving the original trigger signal, the trigger circuit outputs a high level / low level to the delay resistor;
[0008] The second end of the delay resistor, the first end of the delay capacitor, and the in-phase input terminal / inverting input terminal of the first comparator are connected to each other, and the second end of the delay capacitor is grounded;
[0009] The delay adjustment structure is connected to the inverting input terminal / non-inverting input terminal of the first comparator to output a threshold voltage to the inverting input terminal / non-inverting input terminal of the first comparator; wherein the delay structure and the delay adjustment structure are connected to different terminals;
[0010] The output terminal of the first comparator is connected to a subsequent circuit.
[0011] Preferably, the delay adjustment structure includes a first delay adjustment resistor and a second delay adjustment resistor;
[0012] The first end of the first delay adjustment resistor is connected to a power supply;
[0013] The second end of the first delay adjustment resistor is connected to the first end of the second delay adjustment resistor, and the common end of the connections is connected to the inverting input end / non-inverting input end of the first comparator;
[0014] The second end of the second delay adjusting resistor is grounded.
[0015] Preferably, the first delay adjusting resistor and / or the second delay adjusting resistor are adjustable resistors.
[0016] Preferably, the delay resistor is an adjustable resistor, and the delay capacitor is an adjustable capacitor.
[0017] Preferably, the delay adjustment structure further includes: a first voltage stabilizing capacitor;
[0018] A first end of the first voltage-stabilizing capacitor is connected to a first end of the second delay adjusting resistor, and a second end of the first voltage-stabilizing capacitor is grounded.
[0019] In order to solve the above technical problems, an embodiment of the utility model provides a delay trigger control circuit, including the above delay circuit and trigger circuit.
[0020] Preferably, the trigger circuit comprises: a low-pass filter circuit, a trigger level adjustment circuit and a second comparator;
[0021] The input end of the low-pass filter circuit is connected to the original trigger signal, and the output end of the low-pass filter circuit is connected to the non-inverting input end / inverting input end of the second comparator;
[0022] The trigger level adjustment circuit is connected to the inverting input terminal / non-inverting input terminal of the second comparator to output a threshold voltage to the inverting input terminal / non-inverting input terminal of the second comparator; wherein the low-pass filter circuit and the trigger level adjustment circuit are connected to different terminals;
[0023] The output end of the second comparator is connected to the first end of the delay resistor in the delay circuit as the output end of the trigger circuit.
[0024] Preferably, the low-pass filter circuit comprises: a filter capacitor and a filter resistor;
[0025] The first end of the filter resistor is used as the input end of the low-pass filter circuit to access the original trigger signal;
[0026] The second end of the filter resistor is connected to the first end of the filter capacitor, and the common end of the connections is connected to the non-inverting input end / inverting input end of the second comparator as the output end of the low-pass filter circuit;
[0027] The second end of the filter capacitor is grounded.
[0028] Preferably, the trigger level adjustment circuit comprises: a first trigger level adjustment resistor and a second trigger level adjustment resistor;
[0029] The first end of the first trigger level adjustment resistor is connected to a power supply;
[0030] The second end of the first trigger level adjustment resistor is connected to the first end of the second trigger level adjustment resistor, and the common end of the connections is connected to the inverting input end / non-inverting input end of the second comparator;
[0031] A second end of the second trigger level adjusting resistor is grounded.
[0032] Preferably, the trigger level adjustment circuit further comprises: a second voltage stabilizing capacitor;
[0033] A first end of the second voltage-stabilizing capacitor is connected to a first end of the second trigger level adjusting resistor, and a second end of the second voltage-stabilizing capacitor is grounded.
[0034] The delay circuit provided by the utility model includes a delay structure, a delay adjustment structure and a first comparator; wherein the delay structure includes a delay resistor and a delay capacitor. The first end of the delay resistor is connected to the output end of the trigger circuit, and the trigger circuit outputs a high level / low level to the delay resistor after receiving the original trigger signal. The second end of the delay resistor, the first end of the delay capacitor and the in-phase input end / inverting input end of the first comparator are connected to each other, and the second end of the delay capacitor is grounded. The delay adjustment structure is connected to the inverting input end / in-phase input end of the first comparator to output a threshold voltage to the inverting input end / in-phase input end of the first comparator, and the output end of the first comparator is connected to the subsequent circuit. Here, the delay structure and the delay adjustment structure are connected to different ends respectively, and the maximum delay time and the delay time are controlled respectively. When the delay structure is connected to the same-phase input end of the first comparator, the delay adjustment structure is connected to the inverting input end, and the input of the delay circuit is converted from a low level to a high level, the output is also converted from a low level to a high level. In this case, the delay between the same potential and the same potential is realized; on the contrary, when the delay structure is connected to the inverting input end of the comparator, the delay adjustment structure is connected to the same-phase input end, and the input of the delay circuit is converted from a low level to a high level, the output is a high level converted to a low level. In this case, the delay between different potentials is realized. This scheme can not only adjust the maximum delay time by changing the resistance value of the delay resistor and the capacitance value of the delay capacitor in the delay structure, but also adjust the specific size of the threshold voltage by changing the delay adjustment structure, thereby further adjusting the delay time, increasing the flexibility of the delay circuit, and being able to accurately adjust the delay time according to actual conditions.
[0035] In addition, the delay trigger control circuit provided by the present invention includes the delay circuit mentioned above, and the effect is the same as above. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the embodiments of the present utility model, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0037] Figure 1 It is the circuit structure diagram of the traditional RC delay circuit;
[0038] Figure 2 A circuit structure diagram of a time-delay trigger control circuit provided by an embodiment of the utility model;
[0039] Figure 3 A waveform diagram of a delayed trigger provided by an embodiment of the utility model;
[0040] The reference numerals are as follows: 1 is a trigger circuit, and 2 is a delay circuit. DETAILED DESCRIPTION
[0041] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of them. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the utility model.
[0042] The core of the utility model is to provide a delay circuit and a delay trigger control circuit to solve the problem that the current delay circuit has poor flexibility and cannot accurately adjust the delay duration according to actual conditions.
[0043] In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0044] The delay circuit of the utility model can be used in various scenarios, such as controlling the alarm time of an electronic alarm clock, and realizing the delay of the alarm time by adjusting the values of the capacitor and the resistor. It can also be used in electronic timers and electronic doorbells, etc.
[0045] The delay circuit provided by the embodiment of the utility model includes a delay structure, a delay adjustment structure and a first comparator; wherein the delay structure includes a delay resistor and a delay capacitor. The first end of the delay resistor is connected to the output end of the trigger circuit; after receiving the original trigger signal, the trigger circuit outputs a high level / low level to the delay resistor. The second end of the delay resistor, the first end of the delay capacitor and the in-phase input end / inverting input end of the first comparator are interconnected, and the second end of the delay capacitor is grounded. The delay adjustment structure is connected to the inverting input end / inverting input end of the first comparator to output a threshold voltage to the inverting input end / inverting input end of the first comparator, and the output end of the first comparator is connected to the subsequent circuit. Here, the delay structure and the delay adjustment structure are connected to different ends, that is, when the second end of the delay resistor, the first end of the delay capacitor and the in-phase input end of the first comparator are connected to each other, the delay adjustment structure is connected to the inverting input end of the first comparator; and vice versa.
[0046] This embodiment also provides a specific structure of a trigger circuit, including a low-pass filter circuit, a trigger level adjustment circuit, and a second comparator. The input end of the low-pass filter circuit is connected to the original trigger signal, the output end of the low-pass filter circuit is connected to the in-phase input end / inverting input end of the second comparator, the trigger level adjustment circuit is connected to the inverting input end / inverting input end of the second comparator to output a threshold voltage to the inverting input end / inverting input end of the second comparator, and the output end of the second comparator is connected to the first end of the delay resistor in the delay circuit as the output end of the trigger circuit.
[0047] Among them, the delay structure and the delay adjustment structure, the low-pass filter circuit and the trigger level adjustment circuit are specifically connected to the same-phase input terminal or the inverting input terminal, which can be set according to actual needs. The delay structure is connected to the same-phase input terminal of the first comparator, and the original trigger signal of the trigger circuit is connected to the same-phase input terminal of the second comparator through the low-pass filter circuit. When the trigger circuit receives the original trigger signal (taking the signal from low level to high level as an example), the delay circuit also outputs a high level. The delay structure is connected to the same-phase input terminal of the first comparator, and the original trigger signal of the trigger circuit is connected to the inverting input terminal of the second comparator through the low-pass filter. After the trigger circuit receives the original trigger signal (taking the signal from low level to high level as an example), the delay circuit outputs a low level. The delay structure is connected to the inverting input terminal of the first comparator, and the original trigger signal of the trigger circuit is connected to the same-phase input terminal of the second comparator through the low-pass filter. After the trigger circuit receives the original trigger signal (taking the signal from low level to high level as an example), the delay circuit outputs a low level. When the delay structure is connected to the inverting input terminal of the first comparator, and the original trigger signal of the trigger circuit is connected to the inverting input terminal of the second comparator through a low-pass filter, the delay circuit outputs a high level after the trigger circuit receives the original trigger signal (taking the signal changing from a low level to a high level as an example). The above four implementations are respectively used to meet different needs. If the original trigger signal received changes from a high level to a low level, the level output by the delay circuit is opposite to the level output in the corresponding situation above.
[0048] First, when the delay structure is connected to the non-inverting input of the first comparator, the delay adjustment structure is used to provide the required threshold voltage and output it to the inverting input of the first comparator, and the delay structure is used to achieve delay. The original trigger signal is connected to the non-inverting input of the second comparator through a low-pass filter circuit; the trigger level adjustment circuit is connected to the inverting input of the second comparator to output the threshold voltage to the inverting input of the second comparator, and the low-pass filter circuit is used to filter out the low-frequency noise of the original trigger signal; wherein, when the original trigger signal (from low to high) is received, the trigger circuit outputs a high level to the delay resistor, and the delay capacitor starts to charge to increase the voltage of the non-inverting input of the first comparator. When it is increased to the threshold voltage, that is, the voltage of the non-inverting input of the first comparator is greater than the voltage of the inverting input, the first comparator starts to output a high level to the subsequent circuit, thereby completing the delay of the trigger signal with the same potential. Similarly, the original trigger signal changes from a high level to a low level, and finally outputs a low level.
[0049] Secondly, when the delay structure is connected to the non-inverting input of the first comparator, the delay adjustment structure is used to provide the required threshold voltage and output it to the inverting input of the first comparator, and the delay structure is used to achieve delay. The original trigger signal is connected to the inverting input of the second comparator through a low-pass filter circuit; the trigger level adjustment circuit is connected to the non-inverting input of the second comparator to output the threshold voltage to the non-inverting input of the second comparator. Among them, when the original trigger signal (from low to high) is received, the trigger circuit outputs a low level, and after the first end of the delay resistor is pulled down to a low level, the delay capacitor begins to discharge, and after it is reduced to the threshold voltage, that is, the voltage at the non-inverting input of the first comparator is less than the voltage at the inverting input, the first comparator begins to output a low level to the subsequent circuit, thereby completing the delay of the trigger signal at different potentials.
[0050] Third, when the delay structure is connected to the inverting input of the first comparator, the delay adjustment structure is used to provide the required threshold voltage and output it to the non-inverting input of the first comparator, and the delay structure is used to achieve delay. The original trigger signal is connected to the non-inverting input of the second comparator through a low-pass filter circuit; the trigger level adjustment circuit is connected to the inverting input of the second comparator to output the threshold voltage to the inverting input of the second comparator. Among them, when the original trigger signal (from low to high) is received, the trigger circuit outputs a high level to the delay resistor, and the delay capacitor starts to charge to increase the voltage of the inverting input of the first comparator. When it is increased to the threshold voltage, that is, the voltage of the inverting input of the first comparator is greater than the voltage of the non-inverting input, the first comparator starts to output a low level to the subsequent circuit, thereby completing the delay of the trigger signal with different potentials.
[0051] Fourth, when the delay structure is connected to the inverting input of the first comparator, the delay adjustment structure is used to provide the required threshold voltage and output it to the non-inverting input of the first comparator, and the delay structure is used to achieve delay. The original trigger signal is connected to the inverting input of the second comparator through a low-pass filter circuit, and the trigger level adjustment circuit is connected to the non-inverting input of the second comparator to output the threshold voltage to the non-inverting input of the second comparator. Among them, when the original trigger signal (from low to high) is received, the trigger circuit outputs a low level to the delay resistor, and after the first end of the delay resistor is pulled down to a low level, the delay capacitor begins to discharge to reduce the voltage of the inverting input of the first comparator. When it is reduced to the threshold voltage, that is, the voltage of the non-inverting input of the first comparator is greater than the voltage of the inverting input, the first comparator begins to output a high level to the subsequent circuit, thereby completing the delay of the trigger signal with the same potential.
[0052] It should be noted that the specific structures of the delay structure, delay adjustment structure and trigger circuit mentioned in this embodiment are not limited and can be designed according to actual needs. Here, the above schemes are explained in conjunction with the accompanying drawings; Figure 2 A circuit structure diagram of a time-delay trigger control circuit provided by an embodiment of the utility model; Figure 2 As shown, it includes a trigger circuit 1 and a delay circuit 2. The delay circuit 2 includes a delay structure, a delay adjustment structure and a first comparator COMP1; the delay structure is composed of a delay resistor R4 and a delay capacitor C3, which determines the maximum delay duration. The first end of the delay resistor R4 is connected to the output end of the second comparator COMP2 in the trigger circuit 1; after the trigger circuit 1 receives the original trigger signal Vtrig1, the second comparator COMP2 outputs a high level / low level to the delay resistor R4. The second end of the delay resistor R4, the first end of the delay capacitor C3 and the in-phase input end / inverting input end of the first comparator COMP1 are connected to each other, and the second end of the delay capacitor C3 is grounded. The delay adjustment structure is composed of a first delay adjustment resistor R5, a second delay adjustment resistor R6 and a first voltage stabilizing capacitor C4. The first end of the first delay adjustment resistor R5 is connected to the power supply V dd , the second end of the first delay adjustment resistor R5 is connected to the first end of the second delay adjustment resistor R6, and the common end of the connection is connected to the inverting input end / non-inverting input end of the first comparator COMP1; the second end of the second delay adjustment resistor R6 is grounded. The first end of the first voltage stabilizing capacitor C4 is connected to the first end of the second delay adjustment resistor R6, and the second end of the first voltage stabilizing capacitor C4 is grounded. The output end of the first comparator COMP1 is connected to the subsequent circuit, and the corresponding trigger signal Vtrig2 is output to the subsequent circuit.
[0053] The trigger circuit 1 includes a low-pass filter circuit, a trigger level adjustment circuit and a second comparator COMP2; the low-pass filter circuit includes a filter capacitor C2 and a filter resistor R3; the first end of the filter resistor R3 is connected to the original trigger signal Vtrig1 as the input end of the low-pass filter circuit; the second end of the filter resistor R3 is connected to the first end of the filter capacitor C2, and the common end of the connection is connected to the in-phase input end / inverting input end of the second comparator COMP2 as the output end of the low-pass filter circuit; the second end of the filter capacitor C2 is grounded. The trigger level adjustment circuit includes a first trigger level adjustment resistor R1, a second trigger level adjustment resistor R2 and a second voltage stabilizing capacitor C1; the first end of the first trigger level adjustment resistor R1 is connected to the power supply V dd, the second end of the first trigger level adjustment resistor R1 is connected to the first end of the second trigger level adjustment resistor R2, and the common end of the connection is connected to the inverting input terminal / non-inverting input terminal of the second comparator COMP2; the second end of the second trigger level adjustment resistor R2 is grounded. The first end of the second voltage stabilizing capacitor C1 is connected to the first end of the second trigger level adjustment resistor R2, and the second end of the second voltage stabilizing capacitor C1 is grounded. The output end of the second comparator COMP2 is connected to the first end of the delay resistor R4. Among them, the low-pass filter circuit and the trigger level adjustment circuit are connected to different input ends of the second comparator COMP2; generally, the output end of the low-pass filter circuit is connected to the non-inverting input terminal of the second comparator COMP2, and when the voltage of the non-inverting input terminal of the second comparator COMP2 is greater than the inverting input terminal, the output is a high level, and if it is less than, the output is a low level. In actual circuits, the trigger level is often a fixed value (such as the logic threshold of the logic circuit / the threshold of the protection circuit).
[0054] The models and electrical values of the components in the above circuit are not required and can be selected according to the requirements. For example, the first delay adjustment resistor R5 and / or the second delay adjustment resistor R6 can be selected as adjustable resistors, the delay resistor R4 can be selected as an adjustable resistor, and the delay capacitor C3 can be selected as an adjustable capacitor.
[0055] The original trigger signal Vtrig1 is mostly a (voltage / current) sampling signal, and may also be an on / off signal. In order to ensure the accuracy of the sampling signal, the adjustment range of the filter resistor R3 and the filter capacitor C2 is limited, which often leads to the RC low-pass filter composed of the filter resistor R3 and the filter capacitor C2 being unable to filter out all interference signals in the circuit. In this way, the probability of the trigger circuit 1 being interfered with is greatly increased. In power electronic applications, active switching devices have been widely used. Various switching noises that are coupled in the circuit will also cause the oscillation of the sampling signal when the input is dynamic and the load is dynamic, and also increase the risk of being falsely triggered. Based on these problems, a delay circuit 2 is added to shield unnecessary interference by increasing the delay trigger and increase the stability of the circuit. When the second comparator COMP2 is triggered to output a signal, the delay time td can be accurately set by adjusting the relevant parameters of each resistor and capacitor in the delay circuit 2. The trigger signal Vtrig2 is delayed td after the original trigger signal Vtrig1 is triggered and then output. By adjusting the delay time td, the switching noise interference and the circuit dynamic oscillation interference are effectively shielded.
[0056] Specifically, here, the output end of the low-pass filter circuit is connected to the non-inverting input end of the second comparator COMP2, and the delay structure is connected to the non-inverting input end of the first comparator COMP1 as an example; when the voltage of Vtrig1 increases, the voltage at the non-inverting input end of the second comparator COMP2 is greater than the voltage V at point a. a, the second comparator COMP2 output is high level, that is, the voltage V b From low level to high level, affected by the delay circuit of delay resistor R4 and delay capacitor C3, the voltage V c Will not reach V immediately b , V c In V b When V c >V d When the voltage is high, Vtrig2 changes from low to high. b The time interval between Vtrig2 being high and Vtrig3 being high is the delay time td that needs to be controlled. The calculation formula of td is as follows. The parameter values of the first delay adjustment resistor R5, the second delay adjustment resistor R6, the delay resistor R4 and the delay capacitor C3 can be accurately set according to the following formula.
[0057]
[0058] Where, td is the delay time; rc is the time constant of the R4, C3 delay circuit, that is, R4*C3 (here represents the respective parameter values); V dd is the supply voltage of COMP2 (where V b When the voltage is high, it is equal to V dd same); V d is the voltage at point d.
[0059] Among them, V b C4 is charged through R3 until the voltage across C4 reaches V b When charging is terminated, theoretically V d =V dd The maximum charging time calculated by formula (1) is infinite. In the actual circuit, the maximum charging time is approximately equal to 5*R4*C3. If V d The voltage reaches V b , the delay time at this time is the maximum delay time will be 5*R4*C3. The above are the theoretical maximum times. In practical applications, in order to ensure the stable operation of the circuit, V d The maximum setting voltage will usually be higher than V dd Low, the specific setting voltage should be based on V dd Therefore, if you want to set the required delay time, you can change the maximum delay time by changing the parameter values of R3 and C4, or you can change the ratio of R5 and R6 to change V d , that is, changing the trigger position of the first comparator COMP1, thereby accurately adjusting the delay.
[0060] Figure 3 A waveform diagram of a delayed trigger provided by an embodiment of the utility model; Figure 3 As shown, through Figure 2 The proposed delay circuit 2 realizes the delay of the trigger signal. When the trigger circuit 1 receives the original trigger signal Vtrig1, the second comparator COMP2 outputs a high level, thereby pulling up the voltage at point b. The first comparator COMP1 outputs the corresponding trigger signal Vtrig2 to the subsequent circuit after a delay of td.
[0061] The delay circuit provided by the embodiment of the utility model includes a delay structure, a delay adjustment structure and a first comparator; wherein the delay structure includes a delay resistor and a delay capacitor. The first end of the delay resistor is connected to the output end of the trigger circuit, and the trigger circuit outputs a high level / low level to the delay resistor after receiving the original trigger signal. The second end of the delay resistor, the first end of the delay capacitor and the in-phase input end / inverting input end of the first comparator are connected to each other, and the second end of the delay capacitor is grounded. The delay adjustment structure is connected to the inverting input end / in-phase input end of the first comparator to output a threshold voltage to the inverting input end / in-phase input end of the first comparator, and the output end of the first comparator is connected to the subsequent circuit. Here, the delay structure and the delay adjustment structure are connected to different ends respectively, and the maximum delay time and the delay time are controlled respectively. When the delay structure is connected to the same-phase input end of the first comparator, the delay adjustment structure is connected to the inverting input end, and the input of the delay circuit is converted from a low level to a high level, the output is also converted from a low level to a high level. In this case, the delay between the same potential and the same potential is realized; on the contrary, when the delay structure is connected to the inverting input end of the comparator, the delay adjustment structure is connected to the same-phase input end, and the input of the delay circuit is converted from a low level to a high level, the output is a high level converted to a low level. In this case, the delay between different potentials is realized. This scheme can not only adjust the maximum delay time by changing the resistance value of the delay resistor and the capacitance value of the delay capacitor in the delay structure, but also adjust the specific size of the threshold voltage by changing the delay adjustment structure, thereby further adjusting the delay time, increasing the flexibility of the delay circuit, and being able to accurately adjust the delay time according to actual conditions.
[0062] In the above embodiment, it is mentioned that the delay adjustment structure includes a first delay adjustment resistor and a second delay adjustment resistor, and the user can change the delay length by changing the resistance value of the two delay adjustment resistors. Among them, the first end of the first delay adjustment resistor is connected to the power supply; the second end of the first delay adjustment resistor is connected to the first end of the second delay adjustment resistor, and the common end of the connection is connected to the inverting input end of the first comparator; the second end of the second delay adjustment resistor is grounded. Both the first delay adjustment resistor and the second delay adjustment resistor can be set as adjustable resistors. In order to ensure the stability of the circuit, the delay adjustment structure also includes a first voltage stabilizing capacitor; the first end of the first voltage stabilizing capacitor is connected to the first end of the second delay adjustment resistor, and the second end of the first voltage stabilizing capacitor is grounded.
[0063] This embodiment provides a specific structure of a trigger circuit, including a low-pass filter circuit, a trigger level adjustment circuit and a second comparator. The input end of the low-pass filter circuit is connected to the original trigger signal, the output end of the low-pass filter circuit is connected to the in-phase input end / inverting input end of the second comparator, the trigger level adjustment circuit is connected to the inverting input end / inverting input end of the second comparator to output a threshold voltage to the inverting input end / inverting input end of the second comparator, and the output end of the second comparator is connected to the first end of the delay resistor in the delay circuit as the output end of the trigger circuit. Specifically, the low-pass filter circuit can be composed of a filter capacitor and a filter resistor, the first end of the filter resistor is connected to the original trigger signal as the input end of the low-pass filter circuit, the second end of the filter resistor is connected to the first end of the filter capacitor, and the common end of the connection is connected to the in-phase input end / inverting input end of the second comparator as the output end of the low-pass filter circuit; the second end of the filter capacitor is grounded. The trigger level adjustment circuit may include a first trigger level adjustment resistor and a second trigger level adjustment resistor; the first end of the first trigger level adjustment resistor is connected to a power supply; the second end of the first trigger level adjustment resistor is connected to the first end of the second trigger level adjustment resistor, and the common end of the connection is connected to the inverting input terminal / non-inverting input terminal of the second comparator; the second end of the second trigger level adjustment resistor is grounded. In addition, in order to maintain the stability of the circuit, the trigger level adjustment circuit also includes a second voltage-stabilizing capacitor; the first end of the second voltage-stabilizing capacitor is connected to the first end of the second trigger level adjustment resistor, and the second end of the second voltage-stabilizing capacitor is grounded. The circuits of the non-inverting input terminal and the reverse input terminal of the trigger circuit can be interchangeably connected to achieve the adjustment of the trigger level (that is, the high and low levels of the original trigger signal are not the only factors affecting the high and low output levels of the trigger circuit) to meet different usage requirements.
[0064] In order to solve the above technical problems, an embodiment of the utility model provides a delay trigger control circuit, including the delay circuit and the trigger circuit in the above embodiment.
[0065] Since the embodiments of the delay trigger control circuit part correspond to the embodiments of the delay circuit part, please refer to the description of the embodiments of the delay circuit part for the embodiments of the delay trigger control circuit part, which will not be repeated here.
[0066] The delay trigger control circuit provided in this embodiment corresponds to the above-mentioned delay circuit, and thus has the same beneficial effects as the above-mentioned delay circuit.
[0067] The above is a detailed introduction to a delay circuit and a delay trigger control circuit provided by the utility model. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the utility model, the utility model can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the utility model.
[0068] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method, article or device including the above elements.
Claims
1. A delay circuit, characterized in that: include: A delay structure, a delay adjustment structure and a first comparator; wherein the delay structure includes a delay resistor and a delay capacitor; The first end of the delay resistor is connected to the output end of the trigger circuit (1); after receiving the original trigger signal, the trigger circuit (1) outputs a high level / low level to the delay resistor; The second end of the delay resistor, the first end of the delay capacitor, and the in-phase input terminal / inverting input terminal of the first comparator are connected to each other, and the second end of the delay capacitor is grounded; The delay adjustment structure is connected to the inverting input terminal / non-inverting input terminal of the first comparator to output a threshold voltage to the inverting input terminal / non-inverting input terminal of the first comparator; wherein the delay structure and the delay adjustment structure are connected to different terminals; The output terminal of the first comparator is connected to a subsequent circuit.
2. The delay circuit according to claim 1, characterized in that: The delay adjustment structure includes a first delay adjustment resistor and a second delay adjustment resistor; The first end of the first delay adjustment resistor is connected to a power supply; The second end of the first delay adjustment resistor is connected to the first end of the second delay adjustment resistor, and the common end of the connections is connected to the inverting input end / non-inverting input end of the first comparator; The second end of the second delay adjusting resistor is grounded.
3. The delay circuit according to claim 2, characterized in that: The first delay adjusting resistor and / or the second delay adjusting resistor are adjustable resistors.
4. The delay circuit according to claim 2, characterized in that: The delay resistor is an adjustable resistor, and the delay capacitor is an adjustable capacitor.
5. The delay circuit according to claim 3, characterized in that: The delay adjustment structure further includes: a first voltage stabilizing capacitor; A first end of the first voltage-stabilizing capacitor is connected to a first end of the second delay adjusting resistor, and a second end of the first voltage-stabilizing capacitor is grounded.
6. A time-delay trigger control circuit, characterized in that: It comprises the delay circuit and trigger circuit as described in any one of claims 1 to 5.
7. The delay trigger control circuit according to claim 6, characterized in that: The trigger circuit (1) comprises: a low-pass filter circuit, a trigger level adjustment circuit and a second comparator; The input end of the low-pass filter circuit is connected to the original trigger signal, and the output end of the low-pass filter circuit is connected to the non-inverting input end / inverting input end of the second comparator; The trigger level adjustment circuit is connected to the inverting input terminal / non-inverting input terminal of the second comparator to output a threshold voltage to the inverting input terminal / non-inverting input terminal of the second comparator; wherein the low-pass filter circuit and the trigger level adjustment circuit are connected to different terminals; The output end of the second comparator is connected to the first end of the delay resistor in the delay circuit (2) as the output end of the trigger circuit (1).
8. The delay trigger control circuit according to claim 7, characterized in that: The low-pass filter circuit comprises: a filter capacitor and a filter resistor; The first end of the filter resistor is used as the input end of the low-pass filter circuit to access the original trigger signal; The second end of the filter resistor is connected to the first end of the filter capacitor, and the common end of the connections is connected to the non-inverting input end / inverting input end of the second comparator as the output end of the low-pass filter circuit; The second end of the filter capacitor is grounded.
9. The delay trigger control circuit according to claim 7, characterized in that: The trigger level adjustment circuit comprises: a first trigger level adjustment resistor and a second trigger level adjustment resistor; The first end of the first trigger level adjustment resistor is connected to a power supply; The second end of the first trigger level adjustment resistor is connected to the first end of the second trigger level adjustment resistor, and the common end of the connections is connected to the inverting input end / non-inverting input end of the second comparator; A second end of the second trigger level adjusting resistor is grounded.
10. The delay trigger control circuit according to claim 9, characterized in that: The trigger level adjustment circuit further includes: a second voltage stabilizing capacitor; A first end of the second voltage-stabilizing capacitor is connected to a first end of the second trigger level adjusting resistor, and a second end of the second voltage-stabilizing capacitor is grounded.