Semiconductor device

Abstract

The embodiment of the utility model provides a semiconductor device. The semiconductor device comprises a plurality of single-bit flip-flop regions, a plurality of single-bit flip-flop regions and a plurality of single-bit flip-flop regions, the multi-bit flip-flop region has a two-dimensional planar arrangement represented by a grid, the grid including rows and first columns extending in a corresponding first direction and a corresponding vertical second direction, each single-bit flip-flop region of the plurality of single-bit flip-flop regions representing an intersection of a corresponding row and a corresponding column of the rows; the plurality of single-bit flip-flop regions are coupled in a daisy chain, and the output of the previous single-bit flip-flop region in the plurality of single-bit flip-flop regions in the daisy chain is coupled to the input of the next single-bit flip-flop region in the plurality of single-bit flip-flop regions in the daisy chain; and the orientation of the plurality of single bit flip-flop regions with respect to the first direction is arranged in an alternating pattern with respect to the second direction such that a two-dimensional representation of a flow path of the data signal along the first column has a spiral shape. The helically configured flow path reduces wiring congestion in the metallization layer.

Description

Technical Field

[0001] The embodiment of the utility model relates to a semiconductor device, and more particularly to a semiconductor device having a multi-bit flip-flop region with a spiral data flow path. Background Art

[0002] In the integrated circuit (IC) industry, flip-flops (latches) are used as data storage components. In some cases, a flip-flop stores a single bit (binary digit) of data and is called a single-bit flip-flop (SBFF). In some cases, the SBFFs are grouped to form a multi-bit flip-flop (MBFF). In some cases, the SBFF regions of an MBFF are coupled in a daisy chain between the input and output of the MBFF, and the output of the previous SBFF region in the daisy chain is coupled to the input of the next SBFF region in the daisy chain. In some cases, flip-flops (latches) are used for state storage and represent the basic storage component of sequential logic in electronic devices (such as shift registers).

[0003] One type of flip-flop is a delay flip-flop (DFF). A DFF is a digital electronic circuit that delays the change of state of its output signal (Q) until the next rising edge of a frequency-timing input signal occurs. A DFF is a modified set (S) and reset (R) flip-flop with an inverter added to prevent the S input from being at the same logic level as the R input.

[0004] One type of DFF is a scan DFF (SDFQ) used, for example, to implement design for testing (DFT). An SDFQ is a delay flip-flop that includes a multiplexer for controllably selecting between input delays during normal operation and scan inputs during scan / test operation. Scan flip-flops such as SDFQs are widely used for device testing. Utility Model Content

[0005] An embodiment of the utility model provides a semiconductor device including: a plurality of single-bit flip-flop regions, including a multi-bit flip-flop region; the multi-bit flip-flop region has a two-dimensional planar layout represented by a grid, the grid includes rows and a first column extending in a corresponding first direction and a corresponding vertical second direction, each single-bit flip-flop region in the plurality of single-bit flip-flop regions represents the intersection of a corresponding row and a corresponding column in the row; the plurality of single-bit flip-flop regions are coupled in a daisy chain, the output of a previous single-bit flip-flop region in the plurality of single-bit flip-flop regions in the daisy chain is coupled to the input of a subsequent single-bit flip-flop region in the plurality of single-bit flip-flop regions in the daisy chain; and the orientation of the plurality of single-bit flip-flop regions relative to the first direction is arranged in an alternating pattern relative to the second direction, so that the two-dimensional representation of the flow path of a data signal along the first column has a spiral shape.

[0006] An embodiment of the utility model provides a semiconductor device comprising: a plurality of single-bit flip-flop regions, including a multi-bit flip-flop region; the multi-bit flip-flop region has a two-dimensional planar layout represented by a grid, the grid comprising rows extending in a corresponding first direction and a corresponding perpendicular second direction and a first column and a second column, each single-bit flip-flop region in the plurality of single-bit flip-flop regions represents the intersection of a corresponding row in the row and a corresponding column; the plurality of single-bit flip-flop regions are coupled in a daisy chain, the output of a previous single-bit flip-flop region in the plurality of single-bit flip-flop regions in the daisy chain is coupled to the input of a subsequent single-bit flip-flop region in the plurality of single-bit flip-flop regions in the daisy chain; and the orientation of the plurality of single-bit flip-flop regions relative to the first direction is arranged in an alternating pattern relative to the second direction, so that a two-dimensional representation of a flow path of a data signal along each of the first column and the second column has a corresponding spiral shape.

[0007] Based on the above, the single bit flip-flop (SBFF) regions are arranged in an alternating pattern with respect to the Y axis with respect to the X-axis, so that the portion of the flow path along each of the first column and the second column has a corresponding spiral shape. The spirally configured flow path reduces routing congestion in the metallization layer and thus increases routing opportunities in the area of ​​the metallization layer located above the corresponding multi-bit flip-flop (MBFF) region.

[0008] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1A to FIG. 1I is a corresponding block diagram of a semiconductor device according to some embodiments.

[0010] FIG. 2A to FIG. 2E is a corresponding layout diagram of a multi-bit flip-flop (MBFF) region according to some embodiments.

[0011] FIG. 3A to FIG. 3B is a corresponding cross-section according to some embodiments.

[0012] FIG. 4A to FIG. 4B is a corresponding schematic circuit diagram according to some embodiments.

[0013] Figure 5 is a flow chart of a method of manufacturing a semiconductor device according to some embodiments.

[0014] Figure 6 is a flow chart of a method of operating an MBFF according to some embodiments.

[0015] FIG. 7A to FIG. 7B is a corresponding flow chart of a corresponding method of manufacturing a semiconductor device according to some embodiments.

[0016] Figure 8 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0017] Fig. 9 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated with the IC manufacturing system according to some embodiments.

[0018] Description of Reference Numerals

[0019] 3A-3A', 3B-3B': cross-section lines; 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I: semiconductor devices; 102A, 102B, 102C, 102D, 102E, 102F, 102G, 102H, 102I, 202A, 202B, 202C, 202D, 202E: multi-bit flip-flop (MBFF) region; 1 06A, 106B, 106C, 106D, 106E, 106F, 106G, 106H, 106I: flow path; 218N(1), 218N(2), 218N(3), 218N(4), 218N(5), 218N(6), 218N(7), 218N(8), 218N(13), 218N(14), 218N(15), 218N(16): NMOS AR / AR; 218P(1), 218P(2), 218P(3), 218P(4), 218P(5), 218P(6), 218P(7), 218P(8): PMOS AR / AR; 218P(13), 218P(14), 218P(15), 218P(16): PMOS AR / P type AR / AR; 242, 342: VIA0 contact structure; 246, 346: VIA1 contact structure; 316: substrate; 318N(16): active region (AR); 320: transistor layer; 321A, 321B: cross section; 322(1), 322(2): source / drain (S / D) region; 324: channel region; 326, N11, N12, N13, N14, N15, N21, N22, N23, N24, N25, N26, N27, N28, N31, N32, N 41, N51, N52, P11, P12, P13, P14, P15, P21, P22, P23, P24, P25, P26, P27, P28, P31, P32, P41, P51, P52: transistor; 332(1): gate segment; 334(1), 334(2): MD contact structure; 336: VG contact structure; 338: VD contact structure; 340(1), 340(2), 344(1), 344(2), 348(1): segment; 430A, 430B: scan D FF (SDFQ); 432: multiplexer; 434A, 434B: D flip-flops; 436: main latch; 438: auxiliary latch; 440: transmission gate; 441A, 441B: internal buffer; 442: output buffer; 444: scan buffer; 446: frequency buffer; 448 (1), 448 (2), 448 (3), 448 (4), 448 (5), 448 (6): NS inverters; 450 (1), 450 (2): sleep inverters;500, 600, 700: flow chart; 502, 504, 610, 612, 614, 616, 710, 712, 714, 716, 718, 720, 732, 734, 736, 738, 740, 742: blocks; 707: database; 800: system; 802: processor; 804: storage medium; 806: computer program code / instructions; 808: bus; 810: input / output (I / O) interface; 811: layout Figure; 812: network interface; 814: network; 842: user interface (UI); 900: manufacturing system; 920: design company; 922: IC design layout; 930: mask company; 932: data preparation; 934: mask production; 935: mask; 950: IC foundry; 952: production tool; 953: semiconductor wafer; 960: IC device; C1: first column; C2: second column; CP, clkb, clkbb: signals; D: input signal;FA1, FA2, FA3, FA4, FA5, FA6, FA7, FA8, FA9, FA10, FA11, FA12, FA13, FA14, FA15, FB1, FB2, FB3, FB4, FB5, FB6, FB7, FB8, FB9, FB10, FB11, FB12, FB13, F B14, FB15, FC1, FC2, FC3, FC4, FC5, FC6, FC7, FC8, FC9, FC10, FC11, FC12, FC13, FC14, FC15, FC16, FC17, FC18, FC19, FC20, FC21, FC22, FC23, FD1, FD2, FD3,FD4,FD5,FD6,FD7,FD8,FD9,FD10,FD11,FD12,FD13,FD14,FD15,FD16,FD17,FD18,FD19,FD20,FD21,FD22,FD23,FE1,FE2,FE3,FE4,FE5,FE6,F E7, FE8, FE9, FE10, FE11, FE12, FE13, FE14, FE15, FF1, FF2, FF3, FF4, FF5, FF6, FF7, FF8, FF9, FF10, FF11, FF12, FF13, FF14, FF15, FG1, FG2, FG3, FG4, FG5, FG6, FG7, FG8, FG9, FG10, FG11, FG12, FG13, FG14, FG15, FH1, FH2, FH3, FH4, FH5, FH6, FH7, FH8, FH9, FH10, FH11, FH12, FH13, FH14, FH15, FI1, FI2, FI3, FI4, FI5, FI6, FI7, FI8, FI9, FI10, FI11, FI12, FI13, FI14, FI15: path segments (arrows); M1, M2: layers; M1(1) to M1(6), M1(7), M1(8), M1(9), M1(10), M1(11), M1( 12), M1(13), M1(14), M1(15), M1(16), M1(17), M1(18), M2(1), M2(2), M2(3): segments; MID, MID4A, MID4B: middle region; ml_ax, ml_b, SE, SI, SQ, seb, sl_a, sl_bx: signals; nd11, nd12, nd13, nd14, nd15, nd16, nd17, nd21, nd22, nd23, nd24, nd25, nd26, nd27, nd31, nd32, nd41, nd51, nd52: nodes; OP1, OP4A1, OP4B1: first outer region;OP2, OP4A2, OP4B2: second outer region; R1, R2, R3, R4, R5, R6: row; SBFF1, SBFF2, SBFF3, SBFF4, SBFF5, SBFF6, SBFF7, SBFF8, SBFF9, SBFF10, SBFF11, SBFF12: area; SC11, SC21: first sub-column; SC12, SC22: second sub-column; SC13, SC23: third sub-column; SI1, SI2, SI3, SI4, SI5, SI6, SI7, SI8, SI9, SI10, SI11, SI12, MI: input; SQ1, SQ2, SQ3, SQ4, SQ5, SQ6, SQ7, SQ8, SQ9, SQ10, SQ11, SQ12, MQ: output; VDD, VSS: voltage. ; DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component numbers and / or letters in each example. Such repetition is for the purpose of simplifying and clearly describing the present disclosure, rather than for limiting the relationship between various embodiments and / or configurations.

[0021] In addition, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one component or feature shown in the figure to another (other) component or feature. In addition to the orientation shown in the figure, the spatially relative terms also cover different orientations of the device in use or operation. The device can have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used therein can also be interpreted in the same manner. In some embodiments, the term "standard cell structure" refers to a standardized building block included in a database of various standard cell structures. In some embodiments, various standard cell structures are selected from the database of standard cell structures and used as components in a layout diagram representing a circuit.

[0022] In some embodiments, a semiconductor device includes a single-bit flip-flop region (SBFF region), the single-bit flip-flop region including a multi-bit flip-flop (MBFF) region. The MBFF region has a two-dimensional floorplan represented by a grid, the grid including rows and at least a first column extending in a corresponding first direction (e.g., parallel to the X-axis) and a corresponding perpendicular second direction (e.g., parallel to the Y-axis). Each SBFF region represents an intersection of a corresponding row and a corresponding column. The SBFF regions are coupled in a daisy chain, with the output of a previous SBFF region in the daisy chain coupled to the input of a subsequent SBFF region in the daisy chain. The orientation of the SBFF regions relative to the X-axis (X-orientation) is arranged in an alternating pattern relative to the Y-axis, so that a two-dimensional representation of a flow path of a data signal along the first column has a serpentine shape (a flow path in a spiral configuration). In some embodiments, with respect to the Y-axis, each SBFF region has a first type in the X-orientation (first X-orientation) or an opposite second type in the X-orientation (second X-orientation), as follows: the first X-orientation has an input region of the SBFF on a first side of the column and an output region on a second side of the column; and the second X-orientation has an input region of the SBFF on the second side of the column and an output region of the SBFF on the first side of the column.

[0023] According to another approach, corresponding MBFF regions of a semiconductor device include corresponding columns formed by stacking corresponding SBFF regions. According to the another approach, each SBFF region in a column according to the another approach has the same X orientation, i.e., an input region of each SBFF region is located on a first side of the column and an output region of each SBFF region is located on a second side of the column. As part of the insights that led the inventors to develop at least some embodiments, the inventors recognized at least the following: a two-dimensional representation of a flow path of a data signal along a column according to the another approach has a sawtooth shape (a sawtooth-configured flow path); and wiring a sawtooth pattern in an MBFF region according to the another approach increases wiring congestion in a second metallization layer (M_2nd layer) and a third metallization layer (M_3rd layer), which reduces wiring opportunities in regions of the M_2nd layer and the M_3rd layer that are located above the corresponding MBFF region. In contrast, the spirally configured flow paths of the MBFFs according to at least some embodiments reduce routing congestion in the M_2nd and M_3rd layers compared to the zigzag configured flow paths of the MBFFs according to the other approach. Thus, the spirally configured flow paths of the MBFFs according to at least some embodiments increase routing opportunities in the M_2nd and M_3rd layers in areas above the MBFF regions compared to the fewer opportunities of the zigzag configured flow paths of the MBFFs according to the other approach.

[0024] Figure 1A is a block diagram of a semiconductor device 100A including an MBFF region 102A according to some embodiments.

[0025] MBFF area 102A includes SBFF areas. More specifically, MBFF area 102A includes first to (N)th SBFF areas, such that MBFF area 102A is an N-bit MBFF area, where N is a positive integer. First to (N)th SBFF areas represent single bits b(0) to b(N-1) of MBFF area 102A, such that MBFF area 102A is an N-bit MBFF. In some embodiments, each of first to (N)th SBFF areas of MBFF area 102A is a scan D FF (SDFQ). Examples of SDFQ include Figure 4A SDFQ 430A shown, Figure 4B SDFQ 430B or similar as shown. Figure 2A (discussed below) is a layout diagram of the MBFF area corresponding to MBFF area 102A.

[0026] about Figure 1A To keep the example concise, Figure 1A Assume that N=8, so that MBFF area 102A is an 8-bit MBFF including SBFF areas 1 to 8 (SBFF1 to SBFF8). Area SBFF1 represents bit b(0). Area SBFF2 represents bit b(1). Area SBFF3 represents bit b(2). Area SBFF4 represents bit b(3). Area SBFF5 represents bit b(4). Area SBFF6 represents bit b(5). Area SBFF7 represents bit b(6). Area SBFF8 represents bit b(N-1) (i.e., b(7)). In some embodiments, N is a positive integer other than N=8.

[0027] exist Figure 1A In FIG. 1 , the MBFF region 102A has a two-dimensional floor plan represented by a grid including rows R1 to R4 and columns extending in a corresponding first direction (e.g., parallel to the X-axis) and a corresponding perpendicular second direction (e.g., parallel to the Y-axis). In general, the number of rows in the MBFF region 102A is N / 2. Figure 1A It is assumed that N = 8, so Figure 1A MBFF region 102A is shown to include four rows R1 to R4. In some embodiments, the first direction is perpendicular to the second direction, but is not a direction parallel to the X-axis and the Y-axis, respectively. Each SBFF region represents the intersection of a corresponding row and a corresponding column. The columns include a first column C1 and a second column C2. In some embodiments, the columns are referred to as legs.

[0028] Areas SBFF1 to SBFF8 include corresponding inputs SI1 to SI8 and corresponding outputs SQ1 to SQ8. The input (MI) of MBFF area 102A is represented by input SI1 of area SBFF1. The output (MQ) of MBFF area 102A is represented by output SQ8 of area SBFF8.

[0029] The regions SBFF1 to SBFF8 are daisy-chain coupled (i.e., coupled in a daisy-chain format). The flow path 106A is a two-dimensional representation of the flow path of the data signal through the daisy chain (i.e., through the MBFF region 102A). The flow path 106A is composed of path segments FA1 to FA15, wherein each of the path segments FA1 to FA15 is Figure 1A Shown as arrows.

[0030] exist Figure 1A In each of the SBFF regions shown, the internal circuitry ( FIG. 4A to FIG. 4B The input of the SBFF region is coupled to the output of the SBFF region. This intra-SBFF coupling is Figure 1A , each of which is parallel to the X-axis.

[0031] As shown by arrow FA1, input SI1 of block SBFF1 is coupled to output SQ1 of block SBFF1. As shown by arrow FA3, input SI2 of block SBFF2 is coupled to output SQ2 of block SBFF2. As shown by arrow FA5, input SI3 of block SBFF3 is coupled to output SQ3 of block SBFF3. As shown by arrow FA7, input SI4 of block SBFF4 is coupled to output SQ4 of block SBFF4. As shown by arrow FA9, input SI5 of block SBFF5 is coupled to output SQ5 of block SBFF5. As shown by arrow FA11, input SI6 of block SBFF6 is coupled to output SQ6 of block SBFF6. As shown by arrow FA13, input SI7 of block SBFF7 is coupled to output SQ7 of block SBFF7. As shown by arrow FA15, input SI8 of block SBFF8 is coupled to output SQ8 of block SBFF8.

[0032] exist Figure 1A In the daisy chain, the output of the previous SBFF area in the daisy chain is coupled to the input of the next SBFF area in the daisy chain. This inter-SBFF coupling is Figure 1A, each of which is parallel to the Y axis.

[0033] As shown by arrow FA2, input SI2 of block SBFF2 is coupled to output SQ1 of block SBFF1. As shown by arrow FA4, input SI3 of block SBFF3 is coupled to output SQ2 of block SBFF2. As shown by arrow FA6, input SI4 of block SBFF4 is coupled to output SQ3 of block SBFF3. As shown by arrow FA8, input SI5 of block SBFF5 is coupled to output SQ4 of block SBFF4. As shown by arrow FA10, input SI6 of block SBFF6 is coupled to output SQ5 of block SBFF5. As shown by arrow FA12, input SI7 of block SBFF7 is coupled to output SQ6 of block SBFF6. As shown by arrow FA14, input SI8 of block SBFF8 is coupled to output SQ7 of block SBFF7.

[0034] Each of the path segments FA2, FA4, FA6, FA10, FA12, and FA14 extends upward from the first row to the immediately adjacent second row. Each of the path segments FA2 and FA10 extends from R1 to row R2. Each of the path segments FA4 and FA12 extends from R2 to row R3. Each of the path segments FA6 and FA14 extends from R3 to row R4.

[0035] exist Figure 1A , each of the first column C1 and the second column C2 is arranged as a stack of SBFF regions relative to the Y axis. Relative to the Y axis, in the first column C1, region SBFF2 is stacked on region SBFF1. Region SBFF3 is stacked on region SBFF2. Region SBFF4 is stacked on region SBFF3. In this way, in the first column C1, relative to the Y axis, bit b(0) is located at the bottom of the stack and bit b(3) is located at the top of the stack, so that the bit order from bottom to top is b(0)→b(1)→b(2)→b(3). In the second column C2, relative to the Y axis, bit b(4) is located at the bottom of the stack and bit b(7) is located at the top of the stack, so that the bit order from bottom to top is b(4)→b(5)→b(6)→b(7).

[0036] Each of rows R1 to R4 includes a corresponding single SBFF region located in the first column C1 and a corresponding single SBFF region located in the second column C2. Generally, the first column C1 includes the first SBFF region to the (i + 1)-th SBFF region representing bits b(0) to b(i), and the second column C2 includes the (i + 2)-th SBFF region to the (N)-th SBFF region representing bits b(i + 1) to b(N - 1), where i is a positive integer and i < N. Recall Figure 1A it is assumed that N = 4, Figure 1A the first column C1 is shown as including regions SBFF1 to SBFF4 representing bits b(0) to b(3) and the second column C2 is shown as including regions SBFF5 to SBFF8 representing bits b(4) to b(7).

[0037] In Figure 1A each of the SBFF regions includes at least one first active region (AR) ( Figure 2A ) and at least one second AR ( Figure 2A ). The first AR has a first conductivity type and the second AR has a different second conductivity type. In Figure 1A it is assumed that: the first conductivity type is a positive (P-type) conductivity, as indicated by the braces and the capital letter P, and the second conductivity type is a negative (N-type) conductivity, as indicated by the braces and the capital letter N. In some embodiments, the first conductivity type is a negative (N-type) conductivity and the second conductivity type is a positive (P-type) conductivity.

[0038] Generally, with respect to the Y-axis, each of the SBFF regions in the MBFF region 102A has a first orientation or a second orientation (Y-orientation). The first Y-orientation has the first AR stacked on the second AR. The second Y-orientation has the second AR (P-channel metal-oxide-semiconductor (PMOS)) stacked on the first AR. In Figure 1A each of rows R1 to R4 has the first Y-orientation. In some embodiments, some rows (e.g., Figure 1G etc.) or all rows of the rows of the MBFF region have the second Y-orientation.

[0039] Generally, with respect to the X-axis, each of the SBFF regions in the MBFF region 102A has a first orientation or a second orientation (X-orientation). The first X-orientation has the input region of the SBFF on the first side of the column and the output region on the second side of the column. The second X-orientation has the input region of the SBFF on the second side of the column and the output region of the SBFF on the first side of the column. In Figure 1AIn some embodiments, the first side and the second side of each of the first column C1 and the second column C2 are assumed to be the left side and the second side of each of the first column C1 and the second column C2 are assumed to be the right side. Figure 1A The opposite of what is assumed in .

[0040] exist Figure 1A In order to make the example concise, it is assumed that each column includes three sub-columns. The first column C1 includes three sub-columns (SC11, SC12, and SC13), wherein the second sub-column SC12 is located between the first sub-column SC11 and the third sub-column SC13. The second column C2 includes three sub-columns (SC21, SC22, and SC23), wherein the second sub-column SC22 is located between the first sub-column SC21 and the third sub-column SC23. In general, each of the first column C1 and the second column C2 includes at least two sub-columns. In some embodiments, each of the first column C1 and the second column C2 includes four or more sub-columns.

[0041] In general, the X orientations of the SBFF regions are as follows: The first X orientation of each SBFF region has an input region substantially located in the first sub-row (SC11 or SC21) and an output region substantially located in the third sub-row (SC13 or SC23). The second X orientation of each SBFF region has an input region substantially located in the third sub-row (SC13 or SC23) and an output region of the SBFF substantially located in the first sub-row (SC11 or SC21).

[0042] In some embodiments (not shown), the X orientations of the SBFF regions are as follows: A first X orientation of each SBFF region has an input region substantially located in the third subcolumn (SC13 or SC23) and an output region substantially located in the first subcolumn (SC11 or SC21). A second X orientation of each SBFF region has an input region substantially located in the first subcolumn (SC11 or SC21) and an output region of the SBFF substantially located in the third subcolumn (SC13 or SC23).

[0043] exist Figure 1A , the X orientations of the SBFF regions are as follows. Each of the regions SBFF1, SBFF3, SBFF6, and SBFF8 has a first X orientation. With respect to region SBFF1, input SI1 is located in the first sub-column SC11 and output SQ1 is located in the third sub-column SC13. With respect to region SBFF3, input SI3 is located in the first sub-column SC11 and output SQ3 is located in the third sub-column SC13. With respect to region SBFF6, input SI6 is located in the first sub-column SC21 and output SQ6 is located in the third sub-column SC23. With respect to region SBFF8, input SI8 is located in the first sub-column SC21 and output SQ8 is located in the third sub-column SC23.

[0044] Each of the regions SBFF2, SBFF4, SBFF5, and SBFF7 has a second X orientation. With respect to the region SBFF2, the input SI2 is located in the third sub-column SC13 and the output SQ2 is located in the first sub-column SC11. With respect to the region SBFF4, the input SI4 is located in the third sub-column SC13 and the output SQ3 is located in the first sub-column SC11. With respect to the region SBFF5, the input SI5 is located in the third sub-column SC23 and the output SQ5 is located in the first sub-column SC21. With respect to the region SBFF7, the input SI7 is located in the third sub-column SC23 and the output SQ7 is located in the first sub-column SC21.

[0045] exist Figure 1A , the X-orientation of the SBFF zones relative to the X-axis is arranged in an alternating pattern relative to the Y-axis, so that the portion of the flow path 106A along each of the first column C1 and the second column C2 has a corresponding spiral shape. More specifically, the spiral shape of the portion of the flow path 106A along each of the first column C1 and the second column C2 is a non-self-overlapping spiral shape relative to the Y-axis. The portion of the flow path 106A along the first column C1 does not overlap itself (i.e., non-self-overlapping) relative to the Y-axis. The portion of the flow path 106A along the second column C2 does not overlap itself (i.e., non-self-overlapping). In contrast, in some embodiments of the MBFF, the portion of the flow path along each of the first column C1 and the second column C2 is a self-overlapping spiral shape (e.g., Figure 1B , Figure 1D wait).

[0046] exist Figure 1A , path segment FA8 couples the first column C1 to the second column C2 by coupling the output SQ4 of block SBFF4 to the input SI5 of block SBFF5. Path segment FA8 extends from R4 into row R1. In some embodiments, path segment FA8 is described as a diagonal segment because it couples the top of the first column C1 (i.e., the output SQ4 of block SBFF4) to the bottom of the second column C2 (i.e., the input SI5 of block SBFF5). In some embodiments, the two-dimensional representation of the overall flow path of the data signal in MBFF block 102A is described as being similar to a capital letter N (i.e., described as an N-shape).

[0047] According to another approach, corresponding MBFF regions of a semiconductor device include corresponding columns represented by stacks of SBFF regions, the columns including Figure 1AThe first sub-column, the second sub-column and the third sub-column corresponding to the sub-columns (SC11 to SC13 or SC21 to SC23) shown. According to the another method, each SBFF area in the column according to the another method has the same X orientation: the input area of ​​each SBFF area is located in the first sub-column and the output area of ​​each SBFF area is located in the third sub-column; or the input area of ​​each SBFF area is located in the third sub-column and the output area of ​​each SBFF area is located in the first sub-column. As part of the insights that led the inventors to develop at least some embodiments, the inventors recognized at least the following: the two-dimensional representation of the flow path of the data signal along the column according to the another method has a sawtooth shape (a flow path in a sawtooth configuration); and the path segments of the sawtooth shape extending in the Y-axis direction are all located in the first sub-column or all located in the third sub-column. In addition, as part of the insights that led the inventors to develop at least some embodiments, the inventors further recognized at least the following: Routing the zigzag pattern in the MBFF region according to the alternative method increases routing congestion in the second metallization layer (M_2nd layer) and the third metallization layer (M_3rd layer), which reduces routing opportunities in the M_2nd layer and the M_3rd layer in the area above the corresponding MBFF region. In contrast, the spiral configuration of the MBFF region 102A reduces the routing congestion in the M_2nd layer (M_3rd layer) compared to the zigzag configuration of the MBFF according to the alternative method. FIG. 2A to FIG. 2E ) and M_3rd layer ( FIG. 2A to FIG. 2E Therefore, the spirally configured flow path 106A of the MBFF region 102A increases the routing opportunities in the regions of the M_2nd layer and the M_3rd layer located above the MBFF region, compared to the fewer opportunities of the zigzag-configured flow path of the MBFF according to the other method.

[0048] Figure 1B is a block diagram of a semiconductor device 100B including an MBFF region 102B according to some embodiments.

[0049] Figure 1B MBFF region 102B is shown with Figure 1A For simplicity, the discussion will focus on the differences of MBFF region 102B compared to MBFF region 102A rather than the similarities. Figure 1B and Figure 1A For the sake of brevity, the discussion will focus on other similar examples. Figure 1B Relative to Figure 1A The difference.

[0050] exist Figure 1B In the stacking order of the SBFF regions in each of the first column C1 and the second column C2, Figure 1A In the first column C1, with respect to the Y axis, region SBFF3 is stacked on region SBFF1. Region SBFF2 is stacked on region SBFF3. Region SBFF4 is stacked on region SBFF2. In the second column C2, with respect to the Y axis, region SBFF7 is stacked on region SBFF5. Region SBFF6 is stacked on region SBFF7. Region SBFF8 is stacked on region SBFF6.

[0051] Despite Figure 1B The stacking order in the first column C1 shown is different, however, with respect to the Y axis, bit b(0) is at the bottom of the stack and bit b(3) is at the top of the stack, so that the bit order remains b(0)→b(1)→b(2)→b(3). Although the stacking order in the second column C2 is different, however, with respect to the Y axis, bit b(4) is at the bottom of the stack and bit b(7) is at the top of the stack, so that the bit order remains b(4)→b(5)→b(6)→b(7).

[0052] Figure 1B The different stacking orders of the SBFF regions in the MBFF result in a portion of the flow path 106B along each of the first column C1 and the second column C2 having a spiral shape that is also self-overlapping with respect to the Y-axis. The portion of the flow path 106B along the first column C1 overlaps itself (i.e., is self-overlapping with respect to the Y-axis). The portion of the flow path 106B along the second column C2 overlaps itself (i.e., is self-overlapping with respect to the Y-axis). In contrast, in some embodiments of the MBFF, the portion of the flow path along each of the first column C1 and the second column C2 is a non-self-overlapping spiral shape (e.g., Figure 1A , Figure 1C , Figure 1E to Figure 1H wait).

[0053] The flow path 106B of the data signal in the MBFF area 102B is composed of path segments FB1 to FB15. Each of the path segments FB4 and FB12 extends downward from the first row to the second row that is immediately adjacent (first adjacent). More specifically, each of the path segments FB4 and FB12 extends downward from R3 to the row R2. Each of the path segments FB2, FB6, FB10, and FB14 extends upward from the first row to the second adjacent second row. Each of the path segments FB2 and FB10 extends upward from R1 to the row R3. Each of the path segments FB6 and FB14 extends upward from R2 to the row R4.

[0054] The advantages of the spirally configured flow path 106B of the MBFF zone 102B relative to the corresponding zigzag configured flow path according to the other method are similar to the advantages of the spirally configured flow path 106A of the MBFF zone 102A relative to the corresponding zigzag configured flow path according to the other method.

[0055] exist Figure 1B In the first row C1 shown, the path segments FB2, FB4 and FB6 at least partially overlap one another with respect to the Y axis. Figure 1B In the first column C1 shown, the path segment FB4 completely overlaps each of the path segments FB2 and FB6. Figure 1B In the second column C2 shown, the path segments FB10, FB12 and FB14 overlap each other at least partially with respect to the Y axis. Figure 1B In the second column C2 shown, path segment FB12 completely overlaps each of path segments FB10 and FB14.

[0056] exist Figure 1B , the overlapping spiral shape of the portion of the flow path 106B along each of the first column C1 and the second column C2 is a self-intersecting and overlapping spiral shape. The portion of the flow path 106B along the first column C1 intersects with itself (i.e., self-intersecting). The portion of the flow path 106B along the second column C2 intersects with itself (i.e., self-intersecting). In contrast, in some embodiments of the MBFF, the portion of the flow path along each of the first column C1 and the second column C2 is non-self-intersecting, but is an overlapping spiral shape (not shown).

[0057] exist Figure 1B In the embodiment, each of the rows R1 to R4 has a first Y orientation. In some embodiments (not shown), some or all of the rows of the MBFF region 102B have a second Y orientation.

[0058] exist Figure 1B , path segment FB8 couples the first column C1 to the second column C2 by coupling the output SQ4 of block SBFF4 to the input SI5 of block SBFF5. Path segment FB8 extends from row R4 to row R1. In some embodiments, path segment FB8 is illustrated as a diagonal segment because it couples the top of the first column C1 (i.e., the output SQ4 of block SBFF4) to the bottom of the second column C2 (i.e., the input SI5 of block SBFF5). In some embodiments, the two-dimensional representation of the overall flow path of the data signal in MBFF block 102B is illustrated as being similar to a capital letter N (i.e., illustrated as an N-shape).

[0059] Figure 1C is a block diagram of a semiconductor device 100C including an MBFF region 102C according to some embodiments.

[0060] Figure 1C MBFF region 102C is shown with Figure 1A MBFF region 102A is shown similar.

[0061] MBFF region 102C includes six rows R1 to R6, while MBFF region 102A includes four rows R1 to R4. MBFF region 102C is a 12-bit MBFF, while MBFF region 102A is an 8-bit MBFF. A first column C1 of MBFF region 102C includes regions SBFF1 to SBFF6 representing bits b(0) to b(5). A second column C2 of MBFF region 102C includes regions SBFF7 to SBFF12 representing bits b(6) to b(11). Each of rows R1 to R6 has a first Y orientation. In some embodiments (not shown), some or all of the rows of MBFF region 102C have a second Y orientation.

[0062] exist Figure 1C SBFF1 to SBFF12 are daisy-chain coupled. Flow path 106C is a two-dimensional representation of the flow path of the data signal through the daisy chain (i.e., through MBFF region 102C). Flow path 106C is composed of path segments FC1 to FC23, wherein each of path segments FC1 to FC23 is connected to the daisy chain. Figure 1C Indicated by arrows.

[0063] SBFF internal coupling Figure 1C , shown as path segments FC1, FC3, FC5, FC7, FC9, FC11, FC13, FC15, FC17, FC19, FC21 and FC23, each of which is parallel to the X-axis.

[0064] As shown by arrow FC1, input SI1 of block SBFF1 is coupled to output SQ1 of block SBFF1. As shown by arrow FC3, input SI2 of block SBFF2 is coupled to output SQ2 of block SBFF2. As shown by arrow FC5, input SI3 of block SBFF3 is coupled to output SQ3 of block SBFF3. As shown by arrow FC7, input SI4 of block SBFF4 is coupled to output SQ4 of block SBFF4. As shown by arrow FC9, input SI5 of block SBFF5 is coupled to output SQ5 of block SBFF5. As shown by arrow FC11, input SI6 of block SBFF6 is coupled to output SQ6 of block SBFF6. As shown by arrow FC13, input SI7 of block SBFF7 is coupled to output SQ7 of block SBFF7. As shown by arrow FC15, input SI8 of block SBFF8 is coupled to output SQ8 of block SBFF8. As shown by arrow FC17, input SI9 of block SBFF9 is coupled to output SQ9 of block SBFF9. As indicated by arrow FC19, input SI10 of block SBFF10 is coupled to output SQ10 of block SBFF10. As indicated by arrow FC21, input SI11 of block SBFF11 is coupled to output SQ11 of block SBFF11. As indicated by arrow FC23, input SI12 of block SBFF12 is coupled to output SQ12 of block SBFF12.

[0065] SBFF coupling Figure 1C , shown as path segments FC2, FC4, FC6, FC8, FC10, FC12, FC14, FC16, FC18, FC20 and FC22, each of which is parallel to the Y axis.

[0066] As shown by arrow FC2, input SI2 of block SBFF2 is coupled to output SQ1 of block SBFF1. As shown by arrow FC4, input SI3 of block SBFF3 is coupled to output SQ2 of block SBFF2. As shown by arrow FC6, input SI4 of block SBFF4 is coupled to output SQ3 of block SBFF3. As shown by arrow FC8, input SI5 of block SBFF5 is coupled to output SQ4 of block SBFF4. As shown by arrow FC10, input SI6 of block SBFF6 is coupled to output SQ5 of block SBFF5. As shown by arrow FC12, input SI7 of block SBFF7 is coupled to output SQ6 of block SBFF6. As shown by arrow FC14, input SI8 of block SBFF8 is coupled to output SQ7 of block SBFF7. As shown by arrow FC16, input SI9 of block SBFF9 is coupled to output SQ8 of block SBFF8. As shown by arrow FC18, input SI10 of block SBFF10 is coupled to output SQ9 of block SBFF9. As indicated by arrow FC20, input SI11 of block SBFF11 is coupled to output SQ10 of block SBFF10. As indicated by arrow FC22, input SI12 of block SBFF12 is coupled to output SQ11 of block SBFF11.

[0067] exist Figure 1C , path segment FC12 couples the first column C1 to the second column C2 by coupling the output SQ6 of block SBFF6 to the input SI7 of block SBFF7. Path segment FC12 extends from R6 to row R1.

[0068] exist Figure 1C In the embodiment of the present invention, the X-orientation of the SBFF zones relative to the X-axis is arranged in an alternating pattern relative to the Y-axis, so that the portion of the flow path 106C along each of the first column C1 and the second column C2 has a corresponding spiral shape. More specifically, the spiral shape of the portion of the flow path 106C along each of the first column C1 and the second column C2 is a non-self-overlapping spiral shape. The advantages of the spirally configured flow path 106C of the MBFF zone 102C relative to the corresponding zigzag configured flow path according to the other method are similar to the advantages of the spirally configured flow path 106A of the MBFF zone 102A relative to the corresponding zigzag configured flow path according to the other method.

[0069] Figure 1D is a block diagram of a semiconductor device 100D including an MBFF region 102D according to some embodiments.

[0070] Figure 1D The MBFF region 102D is shown with Figure 1B MBFF region 102B is shown similar.

[0071] MBFF region 102D includes six rows R1 to R6, while MBFF region 102B includes four rows R1 to R4. MBFF region 102D is a 12-bit MBFF, while MBFF region 102B is an 8-bit MBFF. A first column C1 of MBFF region 102D includes regions SBFF1 to SBFF6 representing bits b(0) to b(5). A second column C2 of MBFF region 102D includes regions SBFF7 to SBFF12 representing bits b(6) to b(11). Each of rows R1 to R6 has a first Y orientation. In some embodiments (not shown), some or all of the rows of MBFF region 102D have a second Y orientation.

[0072] exist Figure 1D 106D is a two-dimensional representation of the flow path of the data signal through the daisy chain (i.e., through the MBFF area 102D). The flow path 106D is composed of path segments FD1 to FD23, wherein each of the path segments FD1 to FD23 is in Figure 1D Shown as arrows.

[0073] SBFF internal coupling Figure 1D Shown as path segments FD1, FD3, FD5, FD7, FD9, FD11, FD13, FD15, FD17, FD19, FD21 and FD23, each of the path segments FD1, FD3, FD5, FD7, FD9, FD11, FD13, FD15, FD17, FD19, FD21 and FD23 is parallel to the X-axis.

[0074] As indicated by arrow FD1, input SI1 of block SBFF1 is coupled to output SQ1 of block SBFF1. As indicated by arrow FD3, input SI2 of block SBFF2 is coupled to output SQ2 of block SBFF2. As indicated by arrow FD5, input SI3 of block SBFF3 is coupled to output SQ3 of block SBFF3. As indicated by arrow FD7, input SI4 of block SBFF4 is coupled to output SQ4 of block SBFF4. As indicated by arrow FD9, input SI5 of block SBFF5 is coupled to output SQ5 of block SBFF1. As indicated by arrow FD11, input SI6 of block SBFF6 is coupled to output SQ6 of block SBFF6. As indicated by arrow FD13, input SI7 of block SBFF7 is coupled to output SQ7 of block SBFF7. As indicated by arrow FD15, input SI8 of block SBFF8 is coupled to output SQ8 of block SBFF8. As indicated by arrow FD17, input SI9 of block SBFF9 is coupled to output SQ9 of block SBFF9. As indicated by arrow FD19, input SI10 of block SBFF10 is coupled to output SQ10 of block SBFF10. As indicated by arrow FD21, input SI11 of block SBFF11 is coupled to output SQ11 of block SBFF11. As indicated by arrow FD23, input SI12 of block SBFF12 is coupled to output SQ12 of block SBFF12.

[0075] SBFF coupling Figure 1D Shown in the figure are path segments FD2, FD4, FD6, FD8, FD10, FD12, FD14, FD16, FD18, FD20 and FD22, each of which is parallel to the Y axis.

[0076] As indicated by arrow FD2, input SI2 of block SBFF2 is coupled to output SQ1 of block SBFF1. As indicated by arrow FD4, input SI3 of block SBFF3 is coupled to output SQ2 of block SBFF2. As indicated by arrow FD6, input SI4 of block SBFF4 is coupled to output SQ3 of block SBFF3. As indicated by arrow FD8, input SI5 of block SBFF5 is coupled to output SQ4 of block SBFF4. As indicated by arrow FD10, input SI6 of block SBFF6 is coupled to output SQ5 of block SBFF5. As indicated by arrow FD12, input SI7 of block SBFF7 is coupled to output SQ6 of block SBFF6. As indicated by arrow FD14, input SI8 of block SBFF8 is coupled to output SQ7 of block SBFF7. As indicated by arrow FD16, input SI9 of block SBFF9 is coupled to output SQ8 of block SBFF8. As indicated by arrow FD18, input SI10 of block SBFF10 is coupled to output SQ9 of block SBFF9. As indicated by arrow FD20, input SI11 of block SBFF11 is coupled to output SQ10 of block SBFF10. As indicated by arrow FD22, input SI12 of block SBFF12 is coupled to output SQ11 of block SBFF11.

[0077] exist Figure 1D , path segment FD12 couples the first row C1 to the second row C2 by coupling the output SQ6 of block SBFF6 to the input SI7 of block SBFF7. Path segment FD12 extends from R6 to row R1.

[0078] exist Figure 1D , the X-orientation of the SBFF zones relative to the X-axis is arranged in an alternating pattern relative to the Y-axis, so that the portion of the flow path 106D along each of the first column C1 and the second column C2 has a corresponding spiral shape. More specifically, the spiral shape of the flow path 106D along the portion of each of the first column C1 and the second column C2 is a self-overlapping spiral shape. The advantages of the spirally configured flow path 106D of the MBFF zone 102D relative to the corresponding zigzag configured flow path according to the other method are similar to the advantages of the spirally configured flow path 106B of the MBFF zone 102B relative to the corresponding zigzag configured flow path according to the other method.

[0079] Figure 1E is a block diagram of a semiconductor device 100E including an MBFF region 102E according to some embodiments.

[0080] Figure 1E MBFF region 102E is shown with Figure 1A MBFF region 102A is shown similar. Figure 2C(discussed below) is a layout diagram of the MBFF area corresponding to MBFF area 102E.

[0081] exist Figure 1E In the second column, the stacking order of the SBFF area in C2 is the same as Figure 1A . With respect to the Y axis, in the second column C2, region SBFF7 is stacked on region SBFF8. Region SBFF6 is stacked on region SBFF7. Region SBFF5 is stacked on region SBFF6. Thus, in the second column C2, with respect to the Y axis, bit b(7) is at the bottom of the stack and bit b(4) is at the top of the stack, such that the bit order from bottom to top is b(7)→b(6)→b(5)→b(4).

[0082] because Figure 1E The X orientation of the SBFF region in each of the rows R1 to R4 is different from the stacking order of the SBFF region in the second column C2 in FIG. Figure 1E In and Figure 1A In this way, Figure 1E Each of the regions SBFF1, SBFF3, SBFF5, and SBFF7 in FIG. 1 has a first X orientation, and Figure 1E Each of the regions SBFF2, SBFF4, SBFF6, and SBFF8 in has a second X orientation. Portions of the flow path 106E along each of the first column C1 and the second column C2 have corresponding non-overlapping spiral shapes.

[0083] The data signal flow path 106E in the MBFF area 102E is composed of path segments FE1 to FE15. Figure 1E , the path segment FE4 is located in the first sub-column SC11, and the path segments FE2 and FE6 are located in the third sub-column SC13. The path segment FE12 is located in the first sub-column SC21. The path segments FE10 and FE14 are located in the third sub-column SC23.

[0084] Each of the path segments FE2, FE4, and FE6 extends upward from the first row into the immediately adjacent second row. Path segment FE2 extends upward from R1 into row R2. Path segment FE4 extends upward from R2 into row R3. Path segment FE6 extends upward from R3 into row R4. Each of the path segments FE10, FE12, and FE14 extends downward from the first row into the immediately adjacent second row. Path segment FE10 extends downward from R4 into row R3. Path segment FE12 extends downward from R3 into row R2. Path segment FE14 extends downward from R2 into row R1.

[0085] Figure 1EThe stacking order of the SBFF regions in the MBFF region 102A is such that the portion of the flow path 106E along each of the first column C1 and the second column C2 has a non-self-overlapping spiral shape. The advantages of the spirally configured flow path 106E of the MBFF region 102E relative to the corresponding zigzag configured flow path according to the other method are similar to the advantages of the spirally configured flow path 106A of the MBFF region 102A relative to the corresponding zigzag configured flow path according to the other method.

[0086] exist Figure 1E , path segment FE8 couples the first column C1 to the second column C2 by coupling the output SQ4 of the block SBFF4 to the input SI5 of the block SBFF5. Path segment FE8 stays within row R4. In some embodiments, path segment FE8 is illustrated as a horizontal segment because it couples the top of the first column C1 (i.e., the output SQ4 of the block SBFF4) to the top of the second column C2 (i.e., the input SI5 of the block SBFF5). In some embodiments, the two-dimensional representation of the overall flow path of the data signal in the MBFF block 102E is illustrated as being similar to the capital letter Π (i.e., being interpreted as a Π shape).

[0087] exist Figure 1E In some embodiments, each of the rows R1 to R4 has a first Y orientation. Figure 1H ) or some rows have a second Y orientation.

[0088] Figure 1F is a block diagram of a semiconductor device 100F including an MBFF region 102F according to some embodiments.

[0089] Figure 1F The MBFF region 102F shown is Figure 1E MBFF region 102E is shown similarly. Figure 2D (discussed below) is a layout diagram of the MBFF area corresponding to the MBFF area 102F.

[0090] exist Figure 1F In the example, the X orientation of the SBFF region in each of the first column C1 and the second column C2 is the same as Figure 1E In different. Figure 1F In each row shown, the X orientation of the SBFF region is the same; in contrast, Figure 1E In each row shown, the X orientation of the SBFF region is different. Figure 1F Each of regions SBFF2, SBFF4, SBFF5, and SBFF7 in has a first X orientation. Figure 1FEach of the regions SBFF1, SBFF3, SBFF6, and SBFF8 in has a second X orientation. The portion of the flow path 106F along each of the first column C1 and the second column C2 has a corresponding non-overlapping spiral shape.

[0091] The data signal flow path 106F in the MBFF area 102F is composed of path segments FF1 to FF15. Figure 1F , path segments FF2 and FF6 are located in the first sub-column SC11. Path segment FF4 is located in the third sub-column SC13. Path segment FF12 is located in the first sub-column SC21. Path segments FF10 and FF14 are located in the third sub-column SC23.

[0092] Figure 1F The stacking order of the SBFF regions in the MBFF region 102A is such that the portion of the flow path 106F along each of the first column C1 and the second column C2 has a non-self-overlapping spiral shape. The advantages of the spirally configured flow path 106F of the MBFF region 102F relative to the corresponding zigzag configured flow path according to the other method are similar to the advantages of the spirally configured flow path 106A of the MBFF region 102A relative to the corresponding zigzag configured flow path according to the other method.

[0093] exist Figure 1F , path segment FF8 couples the first column C1 to the second column C2 by coupling the output SQ4 of block SBFF4 to the input SI5 of block SBFF5. Path segment FF8 stays within row R4. In some embodiments, path segment FF8 is illustrated as a horizontal segment because it couples the top of the first column C1 (i.e., the output SQ4 of block SBFF4) to the top of the second column C2 (i.e., the input SI5 of block SBFF5). In some embodiments, the two-dimensional representation of the overall flow path of the data signal in MBFF block 102F is illustrated as being similar to the capital letter Π (i.e., illustrated as a Π shape).

[0094] exist Figure 1F In some embodiments, each of the rows R1 to R4 has a first Y orientation. Figure 1H ) or some rows have a second Y orientation.

[0095] Figure 1G is a block diagram of a semiconductor device 100G including an MBFF region 102G according to some embodiments.

[0096] Figure 1G The MBFF region 102G (including path segments FG1 to FG15) is shown with Figure 1A MBFF region 102A is shown similar. Figure 2B (Discussed below) is a layout diagram of the MBFF area corresponding to the MBFF area 102G.

[0097] exist Figure 1G In FIG. 1 , each of rows R2 and R4 has a second Y orientation. In contrast, Figure 1A Each of rows R2 and R4 and rows R1 and R3 in has a first Y orientation.

[0098] Figure 1H is a block diagram of a semiconductor device 100H including an MBFF region 102H according to some embodiments.

[0099] Figure 1H The MBFF region 102H (including path segments FH1 to FH15) is shown with Figure 1F MBFF region 102F is shown similarly. Figure 1H (discussed below) is a layout diagram of the MBFF area corresponding to the MBFF area 102H.

[0100] exist Figure 1H In some embodiments, each of the rows R1 to R4 has a second Y orientation. Figure 1F ) or some rows have a first Y orientation.

[0101] Fig. 1I is a block diagram of a semiconductor device 100I including an MBFF region 102I according to some embodiments.

[0102] Fig. 1I The MBFF region 102I shown is Figure 1E MBFF region 102E is shown similarly.

[0103] The X orientation of the SBFF region in the second column C2 is Figure 1E In different. Fig. 1I In each row shown, the X orientation of the SBFF region is the same; in contrast, Figure 1E In each row shown, the X orientation of the SBFF region is different. Fig. 1I Each of the regions SBFF1, SBFF3, SBFF6, and SBFF8 in has a first X orientation, and Fig. 1I Each of the regions SBFF2, SBFF4, SBFF5, and SBFF7 in has a second X orientation. The portion of the flow path 106I along each of the first column C1 and the second column C2 has a corresponding non-overlapping spiral shape.

[0104] The data signal flow path 106I in the MBFF area 102I is composed of path segments FI1 to FI15. Fig. 1I , path segment FI4 is located in the first sub-column SC11, and path segments FI2 and FI6 are located in the third sub-column SC13. Path segments FI10 and FI14 are located in the first sub-column SC21. Path segment FI12 is located in the third sub-column SC23.

[0105] Each of the path segments FI2, FI4, and FI6 extends upward from the first row into the immediately adjacent second row. Path segment FI2 extends upward from R1 into row R2. Path segment FI4 extends upward from R2 into row R3. Path segment FI6 extends upward from R3 into row R4. Each of the path segments FI10, FI12, and FI14 extends downward from the first row into the immediately adjacent second row. Path segment FI10 extends downward from R4 into row R3. Path segment FI12 extends downward from R3 into row R2. Path segment FI14 extends downward from R2 into row R1.

[0106] Fig. 1I The stacking order of the SBFF regions in the MBFF region 102A is such that the portion of the flow path 106I along each of the first column C1 and the second column C2 has a non-self-overlapping spiral shape. The advantages of the spirally configured flow path 106I of the MBFF region 102I over the corresponding zigzag configured flow path according to the other method are similar to the advantages of the spirally configured flow path 106A of the MBFF region 102A over the corresponding zigzag configured flow path according to the other method.

[0107] exist Fig. 1I , path segment FI8 couples the first column C1 to the second column C2 by coupling the output SQ4 of block SBFF4 to the input SI5 of block SBFF5. Path segment FI8 stays within row R4. In some embodiments, path segment FI8 is illustrated as a horizontal segment because it couples the top of the first column C1 (i.e., the output SQ4 of block SBFF4) to the top of the second column C2 (i.e., the input SI5 of block SBFF5). In some embodiments, the two-dimensional representation of the overall flow path of the data signal in MBFF block 102I is illustrated as being similar to the capital letter Π (i.e., being interpreted as a Π shape).

[0108] exist Fig. 1I In some embodiments, each of rows R1 to R4 has a first Y orientation. Figure 1H ) or some rows have a second Y orientation.

[0109] Figure 2A is a layout diagram of a multi-bit flip-flop (MBFF) region 202A according to some embodiments.

[0110] Figure 2A MBFF region 202A is shown corresponding to Figure 1A MBFF region 102A is shown.

[0111] Generally speaking, a layout diagram represents a semiconductor device. The shapes in the layout diagram represent corresponding components in the semiconductor device. The layout diagram itself is a top view. The shapes in the layout diagram are two-dimensional relative to, for example, the X-axis and the Y-axis, while the semiconductor device shown is three-dimensional. Relative to the Z-axis, the semiconductor device is generally organized as a stack of layers, and the corresponding structure is located in the stack (i.e., the corresponding structure belongs to the stack). Therefore, each shape in the layout diagram more specifically represents a component in a corresponding layer of the corresponding semiconductor device. The layout diagram generally represents the relative depth of the shape and the layer (i.e., the position along the Z-axis) by superimposing a second shape on a first shape so that the second shape at least partially overlaps the first shape. For the sake of brevity (i.e., for the convenience of discussion), the layout diagram (e.g., FIG. 2A to FIG. 2C Some components in EMBODIMENTS (such as EMBODIMENTS) are referred to as corresponding structures in corresponding semiconductor devices rather than the patterns / shapes themselves.

[0112] The layout diagrams vary in the amount of detail shown. In some cases, selected layers of the layout diagrams are combined / abstracted into a single layer, e.g., for simplicity. Alternatively and / or additionally, in some cases, not all layers of the corresponding semiconductor device are shown (i.e., selected layers of the layout diagrams are omitted, e.g., for simplicity of illustration). FIG. 2A to FIG. 2E is an example of a layout diagram in which selected layers have been omitted. As a specific example, FIG. 2A to FIG. 2E Each of the layers of the corresponding semiconductor device is omitted ( FIG. 3A to FIG. 3B ), which is located at a layer including a via-to-M_1st (VIA0) contact structure ( FIG. 3A to FIG. 3B ). In some embodiments, Figure 2A The layout shown is part of a larger layout.

[0113] as Figure 1A The MBFF region 102A shown, Figure 2A MBFF area 202A is shown to include SBFF areas SBFF1 to SBFF8. However, for simplicity of illustration, Figure 2A Only the boundaries between area SBFF1 and area SBFF8 are emphasized.

[0114] exist Figure 2A In the embodiment, each of the SBFF regions includes at least one first active region (AR) and at least one second AR. The first AR has a first conductivity type and the second AR has a different second conductivity type. For simplicity of illustration, Figure 2AA single first AR and a single second AR are shown in each of the SBFF regions. In some embodiments, Figure 2A The layout diagram shown is a portion of a larger layout diagram. The first AR and the second AR extend in a first direction (eg, parallel to the X-axis).

[0115] exist Figure 2A In, as in Figure 1A As in the example, it is assumed that the first conductivity type is positive (P-type) conductivity, such as labeled as PMOS, where PMOS is an abbreviation of the term "positive-channel metal-oxide-semiconductor" (PMOS) or the term "P-channel MOS"; and the second conductivity type is negative (N-type) conductivity, such as labeled as NMOS, where NMOS is an abbreviation of the term "negative-channel metal-oxide-semiconductor" (NMOS) or the term "N-channel MOS". In some embodiments, the first conductivity type is negative (N-type) conductivity and the second conductivity type is positive (P-type) conductivity.

[0116] MBFF region 202A includes PMOS AR 218P(1) to 218P(4) and NMOS AR 218N(1) to 218N(4). AR 218P(1) and 218N(1) are located in row R1. AR 218P(2) and 218N(2) are located in row R2. AR 218P(3) and 218N(3) are located in row R3. AR 218P(4) and 218N(4) are located in row R4.

[0117] exist Figure 2A In, as in Figure 1A As in , each of the rows R1 to R4 has a first Y orientation, where a first AR is stacked on a second AR with respect to the Y axis (ie, a PMOS AR is stacked on an NMOS AR).

[0118] Relative to the X-axis, including Figure 2A The transistors ( FIG. 4A to FIG. 4B ) is organized into three areas (or portions): a first outer area (or portion) OP1, a middle area (or portion) MID, and a second outer area (or portion) OP2. For each of the SBFF areas, the first outer area OP1 substantially corresponds to an input area of ​​the SBFF area, and the second outer area OP2 substantially corresponds to an output area of ​​the SBFF area.

[0119] about Figures 1A to 1H and FIG. 2A to FIG. 2E For each of the above, the following should be kept in mind: the first row C1 includes the first sub-row SC11 to the third sub-row SC13; the second row C2 includes the first sub-row SC21 to the third sub-row SC23; it is assumed that the first X orientation of each SBFF region has an input region substantially located in the first sub-row (SC11 or SC21) and an output region substantially located in the third sub-row (SC13 or SC23); and it is assumed that the second X orientation of each SBFF region has an input region substantially located in the third sub-row (SC13 or SC23) and an output region of the SBFF substantially located in the first sub-row (SC11 or SC21).

[0120] In view of this, Figure 2A The first X-orientation of the SBFF region is shown to have a first outer region OP1 substantially located in the first sub-column (SC11 or SC21) and a second outer region OP2 located in the third sub-column (SC13 or SC23); and Figure 2A The second X-orientation of the SBFF region is shown to have a second outer region OP2 substantially located in the third sub-column (SC13 or SC23) and a first outer region OP1 substantially located in the first sub-column (SC11 or SC21).

[0121] In the layer corresponding to the semiconductor device ( FIG. 3A to FIG. 3B ) Figure 2A (and also from FIG. 2B to FIG. 2E ) The first metallization layer (M_1st layer) is omitted. The segments in the M_1st layer (M_1st segments) extend parallel to the X-axis.

[0122] In some embodiments, the end view is used to make Figure 2A According to the numbering convention of the corresponding process node of the semiconductor device corresponding to the layout diagram shown, the M_1st layer is the zeroth metallization layer (M0) or the first metallization layer (M1), and correspondingly, the first interconnection line layer VIA_1st is VIA0 or VIA1. FIG. 2A to FIG. 2E In some embodiments, M0 is a transistor layer ( FIG. 3A to FIG. 3B 320, as shown, and discussed below) above the first metallization layer.

[0123] exist Figure 2A In the embodiment, the MBFF region 202A further includes a via-to-M0 (VIA0) contact structure 242, segments M1(1) to M1(8), a via-to-M1 (VIA1) contact structure 246 and segment M2(1).

[0124] The VIA0 contact structure 242 is located in the first interconnect layer and in the corresponding segment ( FIG. 3A to FIG. 3B ). Segments M1(1) to M1(8) are located on the second metallization layer (M_2nd layer, which is assumed to be Figure 2A The segments M1(1) to M1(8) extend in a second direction perpendicular to the first direction (e.g., parallel to the Y axis). In some embodiments, the first direction and the second direction are directions other than directions parallel to the X axis and the Y axis, respectively. Some portions of the segments M1(1) to M1(8) are correspondingly located above the VIA0 contact structure 242. For simplicity of illustration, the VIA0 contact structure 242 is Figure 2A , and appear above segments M1(1) to M1(8) respectively; however, it should be understood that VIA0 contact structure 242 is located below segments M1(1) to M1(8) respectively.

[0125] In the MBFF region 202A, the VIA1 contact structure 246 is located in the second interconnect layer and correspondingly located above the segments M1(7) to M1(8). The segment M2(1) is located in the third metallization layer (M_3rd layer, which is assumed to be Figure 2A The segment M2(1) extends parallel to the X-axis. For simplicity of illustration, the VIA1 contact structure 246 is Figure 2A , and correspondingly appears above segment M2 ( 1 ); however, it should be understood that VIA1 contact structure 246 is correspondingly located below segment M2 ( 1 ).

[0126] Figure 2A The segments M1(1) to M1(6) shown correspond to Figure 1A Path segments FA2, FA4, FA6, FA10, FA12, and FA14 are shown for flow path 106A. Figure 2A The segments M1(7), M2(1) and M1(8) shown together correspond to Figure 1A The flow path 106A is shown as a path segment FA8. Figure 2A With Figure 1A The illustrated flow path 106A corresponds to a flow path (not shown).

[0127] Figure 2A The portions of the flow paths shown along each of the first column C1 and the second column C2 have corresponding non-overlapping spiral shapes. The advantages of the spirally configured flow paths of the MBFF region 202A relative to the corresponding zigzag configured flow paths according to the other method are similar to the advantages of the spirally configured flow paths 106A of the MBFF region 102A relative to the corresponding zigzag configured flow paths according to the other method.

[0128] According to the other method, the corresponding 8-bit MBFF region of the semiconductor device includes two corresponding columns represented by the corresponding stack of SBFF regions. The corresponding 8-bit MBFF region includes a corresponding third metallization layer (M_3rd layer, which is assumed to be an M2 layer). According to the flow path of the zigzag configuration of the other method, in each of the second SBFF region to the eighth SBFF region, an M2 segment is used to couple the input region of the SBFF region to the output region of the SBFF region. In this way, the MBFF region according to the other method uses a total of (2*N)-2 M1 segments (i.e., 14 M1 segments, where N=8) for inter-SBFF coupling, which increases the wiring congestion in the area of ​​the M1 layer located above the corresponding MBFF region and thereby reduces the wiring opportunities in the area of ​​the M1 layer located above the corresponding MBFF region. In addition, as a result, the MBFF region according to the other method uses a total of N-1 M2 segments (i.e., 7 M2 segments, where N=8) for intra-SBFF coupling, which increases the routing congestion of the M2 layer in the area above the corresponding MBFF region, thereby reducing the routing opportunities of the M2 layer in the area above the corresponding MBFF region. In contrast, the flow path of the spiral configuration of the MBFF region 202A uses N M1 segments (i.e., 8 M1 segments, where N=8) for inter-SBFF coupling, which (compared to the corresponding MBFF) reduces the routing congestion of the M1 layer in the area above the corresponding MBFF region and thereby increases the routing opportunities of the M1 layer in the area above the corresponding MBFF region. In addition, in contrast, the flow path of the spiral configuration of the MBFF region 202A uses one of the M2 segments for intra-SBFF coupling, which (compared to the corresponding MBFF) reduces the routing congestion of the M2 layer in the area above the corresponding MBFF region and thereby increases the routing opportunities of the M2 layer in the area above the corresponding MBFF region.

[0129] Figure 2B is a layout diagram of a multi-bit flip-flop (MBFF) region 202B according to some embodiments.

[0130] Figure 2B MBFF region 202B is shown corresponding to Figure 1G MBFF region 102G is shown. Recall that MBFF region 102G is similar to MBFF region 102A, so Figure 2B MBFF region 202B is shown with Figure 2A MBFF region 202A is shown similar.

[0131] MBFF region 202B includes PMOS AR 218P(5) to 218P(8) and NMOS AR 218N(5) to 218N(8). AR 218P(5) and 218N(5) are located in row R1. AR 218P(6) and 218N(6) are located in row R2. AR 218P(7) and 218N(7) are located in row R3. AR 218P(8) and 218N(8) are located in row R4.

[0132] exist Figure 2B In FIG. 1 , each of rows R2 and R4 has a second Y orientation. In contrast, Figure 2A Each of rows R2 and R4 and rows R1 and R3 in has a first Y orientation.

[0133] Figure 2C is a layout diagram of a multi-bit flip-flop (MBFF) region 202C according to some embodiments.

[0134] Figure 2C The MBFF region 202C shown corresponds to Figure 1E MBFF region 102E is shown. Figure 2C MBFF region 202C is shown with Figure 2A MBFF region 202A is shown similar.

[0135] as Figure 1E The MBFF region 102E shown, Figure 2C MBFF area 202C is shown to include SBFF areas SBFF1 to SBFF8. However, for simplicity of illustration, Figure 2C Only the boundaries between regions SBFF1 and SBFF5 are emphasized.

[0136] Figure 2C MBFF region 202C is shown with Figure 2A MBFF region 202A is shown to be different, for example, in terms of the segments in layers M1 and M2. MBFF region 202C does not include segments M1(7)-M1(8) and M2(1) of MBFF region 202A, but instead includes segments M1(9)-M1(10) and M2(2). Figure 2C The segments M1(1) to M1(6) shown correspond to Figure 1E Path segments FE2, FE4, FE6, FE10, FE12, and FE14 of flow path 106E are shown. Figure 2C The segments M1(9) to M1(10) and M2(2) together correspond to Figure 1E The flow path 106E is shown as path segment FE8. Figure 2C With Figure 1E The illustrated flow path 106E corresponds to a flow path (not shown).

[0137] Figure 2C The portions of the flow paths shown along each of the first column C1 and the second column C2 have corresponding non-overlapping spiral shapes. The advantages of the spirally configured flow paths of the MBFF region 202C relative to the corresponding zigzag configured flow paths according to the other method are similar to the advantages of the spirally configured flow paths 106E of the MBFF region 102E relative to the corresponding zigzag configured flow paths according to the other method.

[0138] In terms of reducing the number of segments used / consumed by the spirally configured flow paths of the MBFF region 202C in the M1 layer compared to the corresponding MBFF according to the other method, the spirally configured flow paths of the MBFF region 202C reduce the routing congestion in the area of ​​the M1 layer located above the corresponding MBFF region and thus increase the routing opportunities in the area of ​​the M1 layer located above the corresponding MBFF region, which is consistent with Figure 2A The illustrated MBFF region 202A is similar in how it reduces M1 routing congestion and increases M1 routing opportunities compared to the MBFF corresponding to the MBFF region 202A according to the other approach.

[0139] In terms of reducing the number of segments used / consumed by the spirally configured flow paths of the MBFF region 202C in the M2 layer compared to the corresponding MBFF according to the other method, the spirally configured flow paths of the MBFF region 202C reduce the routing congestion in the area of ​​the M2 layer located above the corresponding MBFF region and thus increase the routing opportunities in the area of ​​the M2 layer located above the corresponding MBFF region, which is consistent with Figure 2A The MBFF region 202A shown is similar in how it reduces M2 routing congestion and increases M2 routing opportunities compared to the MBFF corresponding to the MBFF region 202A according to the other approach.

[0140] Figure 2D is a layout diagram of a multi-bit flip-flop (MBFF) region 202D according to some embodiments.

[0141] Figure 2D The MBFF region 202D shown corresponds to Figure 1F MBFF region 102F is shown. Figure 2D MBFF region 202D is shown with Figure 2A MBFF region 202A is shown similar.

[0142] as Figure 1F The MBFF region 102F shown, Figure 2D MBFF area 202D is shown to include SBFF areas SBFF1 to SBFF8. However, for simplicity of illustration, Figure 2D Only the boundaries between regions SBFF1 and SBFF5 are emphasized.

[0143] exist Figure 2D In the figure, the section line 3A-3A' corresponds to Figure 3A In the cross section 321A. Figure 2D In the figure, the section line 3B-3B' corresponds to Figure 3B Section 321B in.

[0144] MBFF region 202D includes PMOS AR 218P(13) to 218P(16) and NMOS AR 218N(13) to 218N(16). AR 218P(13) and 218N(13) are located in row R1. AR 218P(14) and 218N(14) are located in row R2. AR 218P(15) and 218N(15) are located in row R3. AR 218P(16) and 218N(16) are located in row R4.

[0145] Figure 2D MBFF region 202D is shown with Figure 2A MBFF region 202A is shown to be different, for example, in terms of the segments in layers M1 and M2. MBFF region 202D does not include segments M1(1) to M1(8) and M2(1) of MBFF region 202A, but instead includes segments M1(11) to M1(18) and M2(3). Segments M1(11) to M1(16) correspond to Figure 1F Path segments FF2, FF4, FF6, FF10, FF12, and FF14 are shown in flow path 106F. Figure 2D The segments M1(17) to M1(18) and M2(3) together correspond to Figure 1F The flow path shown is path segment FF8 in path 106F. Figure 2D With Figure 1F The illustrated flow path 106F corresponds to a flow path (not shown).

[0146] Figure 2D The portions of the flow paths shown along each of the first column C1 and the second column C2 have corresponding non-overlapping spiral shapes. The advantages of the spirally configured flow paths of the MBFF region 202D relative to the corresponding zigzag configured flow paths according to the other method are similar to the advantages of the spirally configured flow paths 106F of the MBFF region 102F relative to the corresponding zigzag configured flow paths according to the other method.

[0147] In terms of reducing the number of segments used / consumed by the spirally configured flow path of the MBFF area 202D in the M1 layer compared to the corresponding MBFF according to the other method, the spirally configured flow path of the MBFF area 202D reduces the wiring congestion in the area of ​​the M1 layer located above the corresponding MBFF area and thus increases the wiring opportunities in the area of ​​the M1 layer located above the corresponding MBFF area, which is consistent with Figure 2A The illustrated MBFF region 202A is similar in how it reduces M1 routing congestion and increases M1 routing opportunities compared to the MBFF corresponding to the MBFF region 202A according to the other approach.

[0148] In terms of reducing the number of segments used / consumed by the spirally configured flow path of the MBFF area 202D in the M2 layer compared to the corresponding MBFF according to the other method, the spirally configured flow path of the MBFF area 202D reduces the wiring congestion in the area of ​​the M2 layer located above the corresponding MBFF area and thus increases the wiring opportunities in the area of ​​the M2 layer located above the corresponding MBFF area, which is consistent with Figure 2A The MBFF region 202A shown is similar in how it reduces M2 routing congestion and increases M2 routing opportunities compared to the MBFF corresponding to the MBFF region 202A according to the other approach.

[0149] Figure 2E is a layout diagram of a multi-bit flip-flop (MBFF) region 202E according to some embodiments.

[0150] Figure 2E MBFF region 202E is shown corresponding to Figure 1H MBFF region 102H is shown. Recall that MBFF region 102H is similar to MBFF region 102F, so Figure 2E MBFF region 202E is shown with Figure 2D MBFF region 202D is shown to be similar.

[0151] exist Figure 2E In FIG. 1 , each of rows R1 to R4 has a second Y orientation. In contrast, Figure 2D Each of the rows R1 - R4 shown has a first Y orientation.

[0152] FIG. 3A to FIG. 3B According to some embodiments, Figure 2D The layout diagram of MBFF region 202D shown in FIG. 1 shows corresponding cross sections 321A and 321B of the MBFF region in the semiconductor device.

[0153] about Figure 3A , section 321A corresponds to Figure 2D Section line 3A-3A' in. Figure 3B, section 321B corresponds to Figure 2D Section line 3B-3B' in FIG.

[0154] exist Figure 3A In the embodiment of the present invention, AR 318N(16) includes source / drain (S / D) regions 322(1) and 322(2). Each of the S / D regions 322(1) and 322(2) has a second concentration of negative (N-type) dopants that is different from the first concentration relative to an initial (first) concentration of negative (N-type) dopants that originally existed in non-S / D regions of AR 318N(16). AR 318N(16) is formed in substrate 316. The source / drain (S / D) regions 322(1) and 322(2), a region (324) between the S / D regions 322(1) and the S / D regions 322(2), and a gate segment 332(1) together comprise a transistor 326, wherein the region (324) represents a reversible region that is generally referred to as a channel region. In some embodiments, transistor 326 is an N-type field-effect transistor (FET). In some embodiments, transistor 326 is more specifically an N-type metal oxide semiconductor FET (N-type MOSFET). In some embodiments, transistor 326 is a transistor type other than an N-type FET. Figure 2D The different cross-sections shown (not shown) will show the third S / D region and the fourth S / D region with a third concentration of positive (P-type) dopants, wherein the third concentration is different from the initial (fourth) concentration of the P-type dopant originally present in the non-S / D region of the P-type AR, and there is a P-type channel between the third P-type S / D region and the fourth P-type S / D region, and the third S / D region and the fourth S / D region together with the gate segment located above the P-channel region comprise a P-type MOSFET.

[0155] about Figure 3B Therefore, with respect to a third direction (eg, Z axis) perpendicular to each of the first direction (eg, X axis) and the second direction (eg, Y axis), Figure 3A The layer occupied by AR 318N(16) is Figure 3B Shown in FIG. 3 is substrate 316 .

[0156] FIG. 3A to FIG. 3B It further includes a gate segment 332 (1) and metal-to-S / D (MD) contact structures 334 (1) and 334 (2) extending parallel to the Y-axis. Figure 3A, with respect to the X-axis, the gate segment 332(1) is aligned over the channel region 324, and the MD contact structures 334(1) to 334(2) are aligned over the S / D regions 322(1) to 322(2), respectively.

[0157] Figure 3A Further included is a via-to-gate (VG) contact structure 336 located above the gate segment 332 ( 1 ). Figure 3B Further included are via-to-MD (VD) contact structures correspondingly located above the MD contact structures 334(1)-334(2). The MD contact structures 334(1)-334(2) extend parallel to the Y axis. The layers correspondingly including AR 318N(16), gate segment 332(1), MD contact structures 334(1)-334(2), VG contact structure 336, and VD contact structure 338 collectively represent transistor layer 320.

[0158] FIG. 3A to FIG. 3B Further comprising corresponding segments 340(1) and 340(2) (M_1st segments) in a conductive first metallization (M_1st) layer, wherein for Figure 2D It is assumed that the M_1st layer is the M0 layer. The M_1st segments 340 ( 1 ) to 340 ( 2 ) extend parallel to the X-axis. Figure 3A The M_1st segment 340 ( 1 ) in FIG. 3 is located above the VG contact structure 336 . Figure 3B The M_1st segment 340 ( 2 ) in is located above an instance of the VD contact structure 338 .

[0159] FIG. 3A to FIG. 3B Further included are via-to-M0 (VIA0) contact structures 342 correspondingly aligned over the M_1st segments 340 ( 1 ) to 340 ( 2 ).

[0160] FIG. 3A to FIG. 3B The present invention further includes segments 344(1) and 344(2) (M_2nd segments) located in a conductive second metallization layer (M_2nd), wherein for Figure 2D The M_2nd layer is assumed to be the M1 layer. The M_2nd segments 344 ( 1 ) to 344 ( 2 ) extend parallel to the Y axis. Figure 3A The M_2nd segment 344 ( 2 ) in is located above an instance of the VIA0 contact structure 342 . Figure 3B The M_2nd segment 344 ( 2 ) in is located above another instance of the VIA0 contact structure 342 .

[0161] FIG. 3A to FIG. 3B Further included is a via-to-M1 (VIA1) contact structure 346 correspondingly aligned over the M_1st segment 344 ( 1 ).

[0162] Figure 3A It further includes a segment 348(1) (M_3rd segment) located in a third conductive metallization layer (M_3rd), wherein in order to Figure 2D The M_3rd layer is assumed to be the M2 layer. The M_3rd segment 348 ( 1 ) extends parallel to the X-axis. Figure 3A The M_3rd segment 348 ( 2 ) is located above the VIA1 contact structure 346 .

[0163] FIG. 4A to FIG. 4B is a corresponding schematic circuit diagram according to some embodiments.

[0164] More specifically, FIG. 4A to FIG. 4B 4 is a schematic circuit diagram of the scanning D FF (SDFQ) 430A and 430B. Figure 4A SDFQ 430A and Figure 4B Each of the SDFQ 430B shown is Figures 1A to 1H and FIG. 2A to FIG. 2E Examples of SBFF regions in each of the .

[0165] Figure 4A and Figure 4B The difference between the SDFQ 430A and SDFQ 430B is that SDFQ 430A is based on a transmission-gate-based design (discussed below), while SDFQ 430B is based on a stack-gate-based design (discussed below). Each of SDFQ 430A and SDFQ 430B is an edge-triggered arrangement that is triggered on the rising edge (positive edge) of the clock signal. A variation that causes each of SDFQ 430A and SDFQ 430B to be triggered on the falling edge (negative edge) of the clock signal is discussed below.

[0166] Relative to the X-axis, including Figure 4A SDFQ 430A and Figure 4B The transistors of each of the illustrated SDFQs 430B are organized to include three regions (or portions). Figure 4A The illustrated SDFQ 430A includes a first outer region (or portion) OP4A1, a middle region (or portion) MID4A, and a second outer region (or portion) OP4A2. Figure 4B The SDFQ 430B shown includes a first outer region (or portion) OP4B1, a middle region (or portion) MID4B, and a second outer region (or portion) OP4B2. The first outer regions OP4A1 and OP4B1 correspond approximately to Figures 1A to 1H and FIG. 2A to FIG. 2EThe second outer regions OP4A2 and OP4B2 correspond approximately to the input region of each SBFF region in each of the . Figures 1A to 1H and FIG. 2A to FIG. 2E The output region of each SBFF region in each of .

[0167] about Figures 1A to 1H and FIG. 2A to FIG. 2E For each of the above, the following should be recalled: the first row C1 includes the first sub-row SC11 to the third sub-row SC13; the second row C2 includes the first sub-row SC21 to the third sub-row SC23; it is assumed that the first X-orientation of each SBFF region has an input region substantially located in the first sub-row (SC11 or SC21) and an output region substantially located in the third sub-row (SC13 or SC23); and it is assumed that the second X-orientation of each SBFF region has an input region substantially located in the third sub-row (SC13 or SC23) and an output region of the SBFF substantially located in the first sub-row (SC11 or SC21).

[0168] In view of this, in some embodiments, the first X orientation of each of the SDFQs 430A and 430B has a corresponding first outer region OP4A1 and OP4B1 substantially located in the first sub-column (SC11 or SC21) and a corresponding second outer region OP4A2 and OP4B2 substantially located in the third sub-column (SC13 or SC23); and the second X orientation of each of the SDFQs 430A and 430B has a corresponding second outer region OP4A2 and OP4B2 substantially located in the third sub-column (SC13 or SC23) and a corresponding first outer region OP4A1 and OP4B1 substantially located in the first sub-column (SC11 or SC21). Additional discussion of the first outer regions OP4A1 and OP4B1, the middle regions MID4A and MID4B, and the second outer regions OP4A2 and OP4B2 is provided below.

[0169] exist Figure 4A In the embodiment, SDFQ 430A includes multiplexer 432, D flip-flop 434A, scan buffer 444 and clock buffer 446. SDFQ 430A further includes two types of inverters, namely, sleep inverters and non-sleepy (NS) inverters; the terms "sleepy" and "non-sleepy" are explained below.

[0170] exist Figure 4A, scan buffer 444 receives a Scan / Test Enable (SE) signal that selects between normal operation relative to input signal D or scan operation relative to a Scan-In (SI) signal. Scan buffer 444 includes a non-sleep (NS) inverter 484 (4), which includes a PFET (transistor P41) and an NFET (transistor N41) connected in series. The NS inverter (e.g., 448 (4)) is the counterpart of the sleep inverter (e.g., 450 (1) (discussed below)). Hereinafter, a transistor whose reference alphanumeric number is prefixed with an uppercase letter P (e.g., P41) is a PFET, and a transistor whose reference alphanumeric number is prefixed with an uppercase letter N (e.g., N41) is an NFET.

[0171] In NS inverter 448 (4), transistor P41 is connected between a node having a first reference voltage (e.g., VDD) and node nd41. Transistor N41 is connected between node nd41 and a node having a second reference voltage (e.g., VSS). The gate terminals of each of transistors P41 and N41 are connected together and configured to receive signal SE. Node nd41 has signal seb which is an inversion of signal SE.

[0172] exist Figure 4A , the frequency buffer 446 includes a pair of NS inverters 448(5) and 448(6). The NS inverter 448(5) includes a transistor P31 and a transistor N31 connected in series. The transistor P31 is connected between a node having a voltage VDD and a node nd31. The transistor N31 is connected between the node nd31 and a node having a voltage VSS. The gate terminals of each of the transistors P31 and N31 are connected together and are configured to receive a frequency signal CP. The node nd31 represents an output node of the NS inverter 448(5) and has a frequency signal clkb representing an inversion of the frequency signal CP.

[0173] In the frequency buffer 446, the NS inverter 448 (6) includes a transistor P32 and a transistor N32 connected in series. The transistor P32 is connected between a node having a voltage VDD and a node nd32. The transistor N32 is connected between the node nd32 and a node having a voltage VSS. The gate terminals of each of the transistors P32 and N32 are connected together and connected to a node nd31, and are thus configured to receive the frequency signal clkb. The node nd32 represents the output node of the NS inverter 448 (6) and has a frequency signal clkbb representing an inversion of the frequency signal clkb.

[0174] exist Figure 4AIn the embodiment, the multiplexer 432 includes transistors P11 to P15 and N11 to N15. The transistor P11 is connected between a node having a voltage VDD and a node nd11. The gate terminal of the transistor P11 receives a signal SI. The transistor P12 is connected between a node nd11 and a node nd13. The gate terminal of the transistor P12 receives a signal seb. The transistor P13 is connected between a node having a voltage VDD and a node nd12. The gate terminal of the transistor P13 receives an input signal D. The transistor P14 is connected between a node nd12 and a node nd13. The gate terminal of the transistor P14 receives a signal SE. The transistor P15 is connected between a node nd13 and a node nd14 having a signal ml_ax. The gate terminal of the transistor P15 receives a signal clkbb. The transistor N11 is connected between a node nd14 and a node nd15. The gate terminal of the transistor N11 receives a signal clkb. The transistor N12 is connected between a node nd15 and a node nd16. The gate terminal of transistor N12 receives signal SE. Transistor N13 is connected between node nd16 and a node having voltage VSS. The gate terminal of transistor N13 receives signal SI. Transistor N14 is connected between node nd15 and node nd17. The gate terminal of transistor N14 receives signal seb. Transistor N15 is connected between node nd17 and a node having voltage VSS. The gate terminal of transistor N15 receives input signal D.

[0175] exist Figure 4A In the embodiment, the D flip-flop 434A includes a main latch 436 , an internal buffer 441A, an auxiliary latch 438 and an output buffer 442 .

[0176] The master latch 436 includes a NS inverter 448 (1) and a dormant inverter 450 (1). The NS inverter 448 (1) includes transistors P21 and N21. The transistor P21 is connected between a node having a voltage VDD and a node nd21. The transistor N21 is located between the node nd21 and a node having a voltage VSS. The gate terminal of the transistor P21 is connected together with the gate terminal of the transistor N21 and is connected to the node nd14, and is thus configured to receive the signal ml_ax. As such, the signal ml_ax represents the input signal of the D flip-flop 434A. The node nd21 represents the output node of the NS inverter 448 (1) and has a signal ml_b representing the inversion of the signal ml_ax.

[0177] In the master latch 436, the sleep inverter 450 (1) includes transistors P22 to P23 and N22 to N23. Transistor P22 is connected between a node having a voltage VDD and a node nd22. Transistor P23 is connected between node nd22 and node nd14. The gate terminal of transistor P23 receives a signal clkb. Transistor N22 is connected between node nd14 and node nd23. The gate terminal of transistor N22 receives a signal clkbb. In some embodiments, the gate terminal of transistor N22 receives a frequency signal CP instead of the signal clkbb. Transistor N23 is connected between node nd23 and a node having a voltage VSS. Due to transistors P23 and N22, the sleep inverter 450 (1) can be placed in a sleep operation mode. In contrast, NS inverter 448(1) lacks transistors corresponding to transistors P23 and N22, so that inverter 448(1) of master latch 436 lacks a sleep mode of operation; therefore, NS inverter 448(1) is described as a non-sleep (NS) inverter. The gate terminal of transistor P22 is connected together with the gate terminal of transistor N23 and connected to node nd21. Therefore, sleep inverter 450(1) feeds back an inverted version of signal ml_b (from node nd21) to node nd14.

[0178] exist Figure 4A In the embodiment, the internal buffer 441A includes a transmission gate 440, which includes transistors P24 and N24. The SDFQ 430A including the transmission gate 440 is referred to as a transmission gate-based design. The transistor P24 and the transistor N24 are connected in parallel between the node nd21 and the node nd24. The gate terminal of the transistor P24 receives the signal clkb. The gate terminal of the transistor N24 receives the signal clkbb. The node nd24 has the signal sl_a.

[0179] In the D flip-flop 434A, the auxiliary latch 438 includes a NS inverter 448 (2) and a dormant inverter 450 (2). The NS inverter 448 (2) includes transistors P25 and N25. The transistor P25 is connected between a node having a voltage VDD and a node nd25. The transistor N25 is connected between the node nd25 and a node having a voltage VSS. The gate terminal of the transistor P25 is connected together with the gate terminal of the transistor N25 and connected to the node nd24, and is thus configured to receive the signal sl_a. The node nd25 represents the output node of the NS inverter 448 (2) and has a signal sl_bx representing the inversion of the signal sl_a.

[0180] In the auxiliary latch 438, the dormant inverter 450 (2) includes transistors P26 to P27 and N26 to N27. Transistor P26 is connected between a node having a voltage VDD and a node nd26. Transistor P27 is connected between node nd26 and node nd24. The gate terminal of transistor P27 receives a signal clkbb. Transistor N26 is connected between node nd24 and node nd27. Transistor N27 is connected between node nd27 and a node having a voltage VSS. The gate terminal of transistor N26 receives a signal clkb. Due to transistors P27 and N26, the dormant inverter 450 (2) can be placed in a dormant mode. The gate terminal of transistor P22 is connected together with the gate terminal of transistor N23 and connected to node nd25. Therefore, the dormant inverter 450 (2) feeds back an inverted version of the signal sl_bx (from node nd25) to node nd24.

[0181] In the D flip-flop 434A, the output buffer 442 includes an NS inverter 448 (3), which includes transistors P28 and N28. Transistor P28 is connected between a node having a voltage VDD and a node nd26. Transistor N28 is connected between node nd28 and a node having a voltage VSS. The gate terminal of transistor P28 is connected together with the gate terminal of transistor N28 and connected to node nd25, and is thus configured to receive the signal sl_bx. Node nd26 represents the output node of NS inverter 448 (3) and thus represents the output node of D flip-flop 434A. In addition, node nd26 also represents the output node of SDFQ 430A. Node 464 has a signal SQ representing the inversion of signal sl_bx.

[0182] Recall that SDFQ 430A is triggered on the rising edge (positive edge) of the frequency signal. Changes that cause SDFQ 430A to be triggered on the falling edge (negative edge) of the frequency signal include the following. The gate terminal of each of transistors P31 and N31 is configured to receive CPN instead of receiving the frequency signal CP, where CPN is an inverted version of the frequency signal CP. The gate terminal of transistor P15 receives signal clkb instead of receiving signal clkbb. The gate terminal of transistor N11 receives signal clkbb instead of receiving signal clkb. The gate terminal of transistor P23 receives signal clkbb instead of receiving signal clkb. In some embodiments, the gate terminal of transistor P23 receives signal CPN instead of signal clkbb. The gate terminal of transistor N22 receives signal clkb instead of receiving signal clkbb. The gate terminal of transistor P24 receives signal clkbb instead of receiving signal clkb. The gate terminal of transistor N24 receives signal clkb instead of receiving signal clkbb. The gate terminal of transistor P27 receives the signal clkb instead of the signal clkbb. The gate terminal of transistor N26 receives the signal clkbb instead of the signal clkb.

[0183] exist Figure 4A In the embodiment, the first outer region OP4A1 includes a scan buffer 444, a multiplexer 432, and a frequency buffer 446. The middle region MID4A includes some components of the D flip-flop 434A (i.e., the main latch 436 and the internal buffer 441A of the D flip-flop 434A). The second outer region OP4A2 includes the remaining components of the D flip-flop 434A (i.e., the auxiliary latch 438 and the output buffer 442 of the D flip-flop 434A).

[0184] about Figure 4B , recall that SDFQ 430B is based on a stacked gate design, Figure 4A The SDFQ 430A shown is based on a transmission gate design. More specifically, although Figure 4A The D flip-flop 434A of the SDFQ 430A shown includes an internal buffer 441A including a transmission gate 440, however Figure 4B The D flip-flop 434B of the illustrated SDFQ 430B includes an internal buffer 441B. The internal buffer 441B includes a sleep inverter 450(3), which is an example of a stacked gate based circuit.

[0185] exist Figure 4B, the dormant inverter 450 (3) of the internal buffer 441B includes transistors P51 to P52 and N51 to N52. Transistor P51 is connected between a node having a voltage VDD and a node nd51. Transistor P52 is connected between node nd51 and node nd24. The gate terminal of transistor P52 receives a signal clkb. Transistor N51 is connected between node nd24 and node nd52. The gate terminal of transistor N51 receives a signal clkbb. In some embodiments, the gate terminal of transistor N51 receives a frequency signal CP instead of a signal clkbb. Transistor N52 is connected between node nd52 and a node having a voltage VSS. The gate terminal of transistor N51 receives a signal clkbb. Due to transistors P52 and N51, the dormant inverter 450 (3) can be placed in a dormant mode. The gate terminal of transistor P51 is connected together with the gate terminal of transistor N52 and connected to node nd14. Therefore, the signal ml_ax is provided as an input to the sleep inverter 450 (3). Figure 4A Unlike the transmission gate 440 shown, the input of the sleep inverter 450 (3) is not connected to the node nd21. Specifically, Figure 4B In FIG. 4 , only the input of the sleep inverter 450 ( 1 ) (ie, the gate terminal of each of the transistors P22 and N23 ) receives the signal ml_b from the node nd21 .

[0186] Recall that SDFQ 430B is triggered on the rising edge (positive edge) of the frequency signal. Changes that cause SDFQ 430B to be triggered on the falling edge (negative edge) of the frequency signal include the following. The gate terminal of each of transistors P31 and N31 is configured to receive CPN instead of receiving the frequency signal CP, where CPN is an inverted version of the frequency signal CP. The gate terminal of transistor P15 receives signal clkb instead of receiving signal clkbb. The gate terminal of transistor N11 receives signal clkbb instead of receiving signal clkb. The gate terminal of transistor P23 receives signal clkbb instead of receiving signal clkb. In some embodiments, the gate terminal of transistor P23 receives signal CPN instead of signal clkbb. The gate terminal of transistor N22 receives signal clkb instead of receiving signal clkbb. The gate terminal of transistor P52 receives signal clkbb instead of receiving signal clkb. The gate terminal of transistor N51 receives signal clkb instead of receiving signal clkbb. The gate terminal of transistor P27 receives the signal clkb instead of the signal clkbb. The gate terminal of transistor N26 receives the signal clkbb instead of the signal clkb.

[0187] exist Figure 4BIn the embodiment, the first outer region OP4B1 includes a scan buffer 444, a multiplexer 432, and a frequency buffer 446. The middle region MID4B includes some components of the D flip-flop 434B (i.e., a main latch 436 and an internal buffer 441B of the D flip-flop 434B). The second outer region OP4B2 includes the remaining components of the D flip-flop 434B (i.e., an auxiliary latch 438 and an output buffer 442 of the D flip-flop 434B).

[0188] Figure 5 is a flow chart 500 of a method of fabricating a semiconductor device according to some embodiments.

[0189] According to some embodiments, the EDA system 800 ( Figure 8 , discussed below) and IC manufacturing system 900 ( Fig. 9 , discussed below) to implement the method of flowchart (flowchart) 500. Examples of semiconductor devices that can be manufactured according to the method of flowchart 500 include Figures 1A to 1H The semiconductor device shown, the semiconductor device based on the layout diagram disclosed herein, the semiconductor device based on the cross-section disclosed herein, or the like.

[0190] exist Figure 5 , the method of flowchart 500 includes blocks 502 to 504. At block 502, a layout diagram is generated, which includes, among other things, one or more of the layout diagrams disclosed herein or a similar layout diagram. According to some embodiments, the EDA system 800 ( Figure 8 , discussed below) to implement block 502. From block 502, the flow proceeds to block 504.

[0191] At block 504, at least one of the following operations is performed based on the layout diagram: (A) performing one or more photolithography exposures or (B) making one or more semiconductor masks or (C) making one or more components in a layer of a semiconductor device. Fig. 9 Detailed description of the IC manufacturing system 900 is given below.

[0192] Figure 6 is a flowchart 600 of a method of operating a multi-bit flip-flop (MBFF) region of a semiconductor device according to some embodiments.

[0193] Flowchart 600 includes block 610 , wherein block 610 includes blocks 612 - 616 .

[0194] An example of an MBFF region whose operation is illustrated by flow chart 600 includes FIG. 1A to FIG. 1I The MBFF area corresponding to the block diagram shown in FIG. 2A to FIG. 2EThe MBFF area corresponding to the layout diagram shown or an area similar to the MBFF area.

[0195] The MBFF area operating according to flowchart 600 is composed of a first single-bit flip-flop area (SBFF area) corresponding to bits b0 to b(N-1) to an (N)th single-bit flip-flop area (SBFF area), such that the MBFF is an N-bit MBFF, where N is a positive integer. The first SBFF area to the (N)th SBFF area (e.g., Figure 1A to Figure 1B , FIG. 1E to FIG. 1I , FIG. 2A to FIG. 2E shown areas SBFF1 to area SBFF8, Figure 1C to Figure 1D shown areas SBFF1 to area SBFF12 or similar SBFF areas) are daisy-chained in ascending numerical order from the first SBFF area to the (N)th SBFF area. The input of the first SBFF area represents the input of the MBFF area. The output of the (N)th SBFF area represents the output of the MBFF area. The MBFF area has a two-dimensional layout diagram represented by a grid, the grid including rows (e.g., Figure 1A to Figure 1B , FIG. 1E to FIG. 1I , FIG. 2A to FIG. 2E shown rows R1 to R4, Figure 1C to Figure 1D shown rows R1 to R6 or similar rows) extending in a corresponding first direction (e.g., parallel to the X-axis) and a corresponding perpendicular second direction (e.g., parallel to the Y-axis), and a first column (C1) and a second column (C2), each SBFF area representing the intersection of a corresponding row and a corresponding column.

[0196] Regarding the MBFF area operating according to flowchart 600, the first column (e.g., FIG. 1A to FIG. 1I , FIG. 2A to FIG. 2E shown C1 or a similar first column) includes the first SBFF area to the (i + 1)th SBFF area in the SBFF areas corresponding to bits b(0) to b(i), where i is a positive integer and i < N. The second column (e.g., FIG. 1A to FIG. 1I , FIG. 2A to FIG. 2E shown C2 or a similar second column) includes the (i + 2)th SBFF area to the (N)th SBFF area in the SBFF areas corresponding to bits b(i + 1) to b(N - 1).

[0197] In Figure 6 , at block 610, the data signal is advanced through the MBFF area. An example of advancing the data signal through the two-dimensional representation of the MBFF area is FIG. 1A to FIG. 1I shown flow paths 106A to 106I, FIG. 2A to FIG. 2E shown flow paths or similar flow paths. Inside block 610, the process proceeds to block 612.

[0198] At block 612, the data signal is propagated in the first column such that a two-dimensional representation of a first flow path of the data signal along the first column has a first spiral shape. Examples of a first flow path along the first column having a first spiral shape include FIG. 1A to FIG. 1I The portions of the flow paths 106A to 106I shown are located in the first column C1, FIG. 2A to FIG. 2E In some embodiments, the propagation of the data signal in the first column propagates the data signal in a manner such that the two-dimensional representation of the first flow path has a non-self-overlapping spiral shape. In some embodiments, the propagation of the data signal in the first column propagates the data signal in a manner such that the two-dimensional representation of the first flow path has a self-overlapping spiral shape. Flow proceeds from block 612 to block 614.

[0199] At block 614, the data signal is propagated from the first column to the second column. Examples of propagating the data signal from the first column to the second column include Figure 1A The flow path segment FA8 is shown. Figure 1B The flow path segment FB8 is shown. Figure 1C The flow path segment FC12 is shown. Figure 1D The flow path segment FD12 is shown. Figure 1E The flow path segment FE8 is shown. Figure 1F The flow path segment FF8 is shown. Figure 1G The flow path segment FG8 is shown. Figure 1H The flow path segment FH8 is shown. Fig. 1I The flow path segment FI8 shown in FIG. FIG. 2A to FIG. 2B The flow path segments corresponding to segments M1(7) to M1(8) and M2(1) in Figure 2C The flow path segments corresponding to segments M1(9) to M1(10) and M2(2) in Figure 2C The flow path segments corresponding to segments M1(9) to M1(10) and M2(2) in FIG. 2D to FIG. 2E The flow path segments corresponding to segments M1(17) to M1(18) and M2(3) in FIG. 6A or similar flow path segments. The process proceeds from block 614 to block 616.

[0200] At block 616, the data signal is propagated in the second column (C2) such that a two-dimensional representation of a second flow path of the data signal along the second column (C2) has a second spiral shape. Examples of a second flow path along the second column having a second spiral shape include FIG. 1A to FIG. 1I The portion of the flow paths 106A to 106I shown in FIG. 1 is located in the second column C2. FIG. 2A to FIG. 2EIn some embodiments, the propagation of the data signal in the second column propagates the data signal in a manner such that the two-dimensional representation of the second flow path has a non-self-overlapping spiral shape. In some embodiments, the propagation of the data signal in the second column propagates the data signal in a manner such that the two-dimensional representation of the second flow path has a self-overlapping spiral shape.

[0201] In some embodiments of MBFF zones operating according to flowchart 600, each SBFF zone has an input zone on a first side of the SBFF zone and an output zone on an opposite second side of the SBFF zone relative to a first direction (e.g., X-axis), and each of the first column (e.g., C1) and the second column (e.g., C2) includes at least a first sub-column (e.g., SC11, SC21) and a third sub-column (e.g., SC13, SC23). A given SBFF zone in the SBFF zone has an input zone in the first sub-column (e.g., SC11, SC21) and an output zone in the third sub-column (e.g., SC13, SC23) relative to a first orientation (a first α orientation) relative to the X-axis. A second α orientation of a given SBFF zone in the SBFF zone has an input zone in the third sub-column (e.g., SC13, SC23) and an output zone in the first sub-column (e.g., SC11, SC21). For each of the first column (e.g., C1) and the second column (e.g., C2), the rows present an alternating α orientation pattern such that the rows alternate between the first α orientation and the second α orientation. In such an embodiment, with respect to block 612, causing the data signal to propagate in the first column (e.g., C1) includes transmitting the data signal in a manner such that each portion of the two-dimensional representation of the first flow path is parallel to the second direction (e.g., the Y axis), the first flow path coupling the first SBFF area to the (i+1)th SBFF area to the next SBFF area in the first SBFF area to the (i+1)th SBFF area, for example, see FIG. 1A to FIG. 1I , FIG. 2A to FIG. 2E Etc. In such an embodiment, with respect to block 616, causing the data signal to propagate in the second column (e.g., C2) includes transmitting the data signal in a manner such that each portion of the two-dimensional representation of the second flow path is parallel to a second direction (e.g., the Y axis), the second flow path coupling the first SBFF area of ​​the (i+2)th SBFF area to the second SBFF area of ​​the (i+2)th SBFF area to the second SBFF area of ​​the (N)th SBFF area; see, for example, FIG. 1A to FIG. 1I , FIG. 2A to FIG. 2E wait.

[0202] In some embodiments related to block 614, causing the data signal to propagate from the first column (e.g., C1) to the second column (e.g., C2) includes transmitting the data signal in a manner such that a two-dimensional representation of a third flow path of the data signal from the first column (e.g., C1) to the second column (e.g., C2) includes a first portion parallel to a first direction (e.g., an X-axis), e.g., see FIG. 1A to FIG. 1I , FIG. 2A to FIG. 2E wait.

[0203] In some embodiments of block 614, the transmitted data signal is transmitted in a manner such that a first portion of the third flow path extends from a first subcolumn (e.g., SC11) of a first column (e.g., C1) to a third subcolumn (e.g., SC23) of a second column (e.g., C2), e.g., see Figures 1A to 1D , Figure 1G , Fig. 1I , FIG. 2A to FIG. 2B , FIG. 2A to FIG. 2E wait.

[0204] In some embodiments of block 614, the transmitted data signal is transmitted in a manner such that a first portion of the third flow path extends from a first sub-column (e.g., SC11) of a first column (e.g., C1) to a first sub-column (e.g., SC21) of a second column (e.g., C2), e.g., see Figure 1E , Figure 2C wait.

[0205] In some embodiments of block 614, the transmitted data signal is transmitted in a manner such that a first portion of the third flow path extends from a second sub-column (e.g., SC13) of a first column (e.g., C1) to a first sub-column (e.g., SC21) of a second column (e.g., C2), e.g., see Figure 1F , Figure 1H , FIG. 2D to FIG. 2E wait.

[0206] In some embodiments of block 614, the transmitted data signal is transmitted in such a manner that the third flow path includes a second portion extending from a row including the first SBFF region to a row including, for example, the i-th SBFF region, for example, see Figures 1A to 1D , Figure 1G , Fig. 1I , FIG. 2A to FIG. 2B , FIG. 2A to FIG. 2E wait.

[0207] Fig. 7A is a flowchart 700 of a method of fabricating a multi-bit flip-flop (MBFF) region of a semiconductor device according to some embodiments.

[0208] Figure 7Bis a flowchart illustrating block 710 in greater detail, according to some embodiments.

[0209] Flowchart 700 includes blocks 710 to 720. According to some embodiments, IC manufacturing system 900 ( Fig. 9 , discussed below) to implement the method of flowchart 700. Examples of semiconductor devices that can be manufactured according to the method of flowchart 700 include Figures 1A to 1H The semiconductor device shown, the semiconductor device based on the layout diagram disclosed herein, the semiconductor device based on the cross-section disclosed herein, or the like.

[0210] Examples of MBFF regions made according to flowchart 700 include FIG. 1A to FIG. 1I The MBFF area corresponding to the block diagram shown in FIG. 2A to FIG. 2E The layout diagram shown corresponds to an MBFF area or a similar MBFF area.

[0211] The MBFF region produced according to the flow chart 700 is composed of a first single-bit flip-flop region (SBFF region) to an (N)th single-bit flip-flop region (SBFF region) correspondingly representing bits b0 to b(N-1), so that the MBFF is an N-bit MBFF, where N is a positive integer. The first SBFF region to the (N)th SBFF region (e.g. Figure 1A to Figure 1B , FIG. 1E to FIG. 1I , FIG. 2A to FIG. 2E As shown in area SBFF1 to area SBFF8, Figure 1C to Figure 1D The MBFF regions are daisy-chain coupled in ascending order of value from the first SBFF region to the (N)th SBFF region. The input of the first SBFF region represents the input of the MBFF region. The output of the (N)th SBFF region represents the output of the MBFF region. The MBFF region has a two-dimensional floor plan represented by a grid, the grid including rows (e.g., parallel to the X-axis) extending in a corresponding first direction (e.g., parallel to the X-axis) and a corresponding perpendicular second direction (e.g., parallel to the Y-axis). Figure 1A to Figure 1B , FIG. 1E to FIG. 1I , FIG. 2A to FIG. 2E The rows R1 to R4 shown, Figure 1C to Figure 1D The rows R1 to R6 or similar rows) and the first column (C1) and the second column (C2) are shown, and each SBFF area represents the intersection of the corresponding row and the corresponding column.

[0212] With respect to the MBFF region produced according to the flowchart 700, the first column (e.g. FIG. 1A to FIG. 1I , FIG. 2A to FIG. 2EThe first column (e.g., C1 or a similar first column) includes the first SBFF region to the (i + 1)-th SBFF region in the SBFF regions respectively representing bits b(0) to b(i), where i is a positive integer and i < N. The second column (e.g., FIG. 1A to FIG. 1I , FIG. 2A to FIG. 2E the second column such as C2 or a similar second column) includes the (i + 2)-th SBFF region to the N-th SBFF region in the SBFF regions respectively representing bits b(i + 1) to b(N - 1).

[0213] At Fig. 7A , at block 710, a transistor layer is formed, and the transistor layer includes an active region (AR) located in a corresponding region of the substrate. An example of the transistor layer is FIG. 3A to FIG. 3B the transistor layer 320 shown or a similar transistor layer. An example of the substrate is Figure 3B the substrate 316 shown or a similar substrate. Examples of the AR include Figure 3A the AR 318N(16) shown, FIG. 2A to FIG. 2E the AR shown or a similar AR. The process proceeds from block 710 to block 712. Additionally, at block 710, S / D regions are formed at positions in the AR, including doping regions of the AR, where the second region between the corresponding S / D regions is the channel region. Examples of the S / D regions include Figure 3A the S / D regions 322(1) to 322(2) shown or similar S / D regions. An example of the channel region is Figure 3B the channel region 324 shown or a similar channel region. The process proceeds from block 710 to block 712.

[0214] As Figure 7B shown, block 710 includes blocks 732 to 742. At block 732, an AR is formed, including doping a corresponding region of the substrate. The process proceeds from block 732 to block 734. At block 734, S / D regions are formed in the AR, including doping a corresponding first region of the AR, where the second region between the corresponding S / D regions is the channel region, see the discussion of the AR 318N(16) in the context shown in Figure 3A . The process proceeds from block 734 to block 736.

[0215] At block 736, a gate segment is formed over the substrate and over the corresponding channel region. An example of the gate segment is Figure 3A the gate segment 332(1) in

[0216] or a similar gate segment. The process proceeds from block 736 to block 738. FIG. 3A to FIG. 3BThe MD contact structures 334 ( 1 ) to 334 ( 2 ) or similar MD contact structures are shown. Flow proceeds from block 738 to block 740 .

[0217] At block 740, via-to-gate (VG) contact structures are formed over corresponding gate segments. Examples of VG contact structures include Figure 3A The process proceeds from block 740 to block 742.

[0218] At block 742, a via-to-MD (VD) contact structure is formed over the corresponding MD contact structure. Examples of VD contact structures include Figure 3B Flow exits block 710 from block 742 and proceeds to block 712.

[0219] At block 712, M_1st segments (which are conductive) are formed in a first metallization layer (M_1st layer), at least some of the M_1st segments being coupled to components of the transistor. At least some of the M_1st segments are formed over corresponding instances of the VD contact structure. For each SBFF region formed, an intra-SBFF flow path for a data signal coupling an input region to an output region is comprised of the M_1st segments of the M_1st segments that are within the SBFF region. A two-dimensional representation of the intra-SBFF flow path extends parallel to the first direction (e.g., parallel to the X-axis). For each of the first column and the second column, a two-dimensional representation of a column-by-column flow path of a data signal along the column is comprised of the intra-SBFF flow path. Examples of M_1st segments include Figure 3A Segments 340(1) and 340(2) or the like in the M0 layer are shown. Figure 3A , the M0 layer is an example of the M_1st layer. Figure 3A The M_1st segment 340 ( 1 ) in FIG. 3 is located above the VG contact structure 336 . Figure 3B The M_1st segment 340(2) in FIG. 7 is located above an instance of the VD contact structure 338. Flow proceeds from block 712 to block 714.

[0220] At block 714, a via-to-M_1st (V_1st) contact structure is formed over a corresponding one of the M_1st segments. Examples of the V_1st contact structure include FIG. 2A to FIG. 2E VIA0 contact structure 242, FIG. 3A to FIG. 3B The process proceeds from block 714 to block 716.

[0221] At block 716, M_2nd segments (which are conductive) are formed in a second metallization layer (M_2nd layer), at least some of the M_2nd segments representing portions of inter-SBFF signal paths. For each pair of immediately adjacent SBFF regions (SBFF pair), corresponding ones of the inter-SBFF signal paths couple the output region of the first one of the SBFF pair to the second one of the SBFF pair. For each of the first and second columns, the two-dimensional representation of the column-by-column flow paths is further comprised of the inter-SBFF signal paths, and the two-dimensional representation of the column-by-column flow paths has a corresponding spiral shape. Examples of M_2nd segments include FIG. 2A to FIG. 2E The M1(x) segment in FIG. 3A to FIG. 3B The M1 segments 344(1) to 344(2) or the like are shown. Flow proceeds from block 716 to block 718. Examples of column-wise flow paths having a spiral shape include corresponding FIG. 1A to FIG. 1I The portion of the flow paths 106A to 106I shown in each of the first column C1 and the second column C2, FIG. 2A to FIG. 2E The flow path shown is located at FIG. 2A to FIG. 2E A portion or similar flow path in each of the first column C1 and the second column C2 is shown. Flow proceeds from block 716 to block 718 .

[0222] At block 718, a via-to-M_2nd (V_2nd) contact structure is formed over a corresponding M_2nd segment in the M_2nd segments. Examples of V_2nd contact structures include FIG. 2A to FIG. 2E VIA1 contact structure 246, Figure 3A The process proceeds from block 718 to block 720 .

[0223] At block 720, an M_3rd segment (which is conductive) is formed in a third metallization layer (M_3rd layer), the M_3rd segment representing at least a portion of an inter-column signal path that couples a column-by-column flow path of a first column to a column-by-column flow path of a second column. Examples of the M_3rd segment include FIG. 2A to FIG. 2E The M2(x) segment in Figure 3A M2 section 348(1) or the like.

[0224] In some embodiments regarding block 720, the inter-column signal path is further comprised of one of the M_2nd segments in the first column (C_1stM_2nd segment) and one of the M_2nd segments in the second column (C2) (C_2ndM_2nd segment). Examples of C_1stM_2nd segments include FIG. 2A to FIG. 2B Segment M1(7) Figure 2C Segment M1(9) FIG. 2D to FIG. 2EC_2nd M_2nd segment examples include FIG. 2A to FIG. 2B Segment M1(8) Figure 2C Segment M1(10) FIG. 2D to FIG. 2E Section M1(18) or the like.

[0225] In some embodiments regarding block 720, the C_1st M_2nd segment of the inter-column signal path overlies portions of at least two of the rows. Examples of such C_1st M_2nd segments include FIG. 2A to FIG. 2B Segment M1(7) Figure 2C Segment M1(9) FIG. 2D to FIG. 2E Section M1(17) or the like.

[0226] In some embodiments regarding block 720, the C_2nd M_2nd segment of the inter-column signal path overlies portions of at least two of the rows. Examples of such C_2nd M_2nd segments include FIG. 2A to FIG. 2B Segment M1(8) in Figure 2C Segment M1(10) FIG. 2D to FIG. 2E M1(18) or similar.

[0227] In some embodiments of block 720, the C_1st M_2nd segment of the inter-column signal path extends from within the first SBFF region to within the (i+1)th SBFF region. Examples of such C_1st M_2nd segments include FIG. 2A to FIG. 2B Section M1(7) or similar.

[0228] Figure 8 is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0229] In some embodiments, EDA system 800 includes an automatic placement and routing (APR) system. In some embodiments, EDA system 800 is a general purpose computing device that includes a hardware processor 802 and a non-transitory computer-readable storage medium 804. Storage medium 804 is encoded with (i.e., stores) computer program code 806 (i.e., a set of executable instructions), among other things. Execution of instructions 806 by hardware processor 802 (at least in part) represents implementation of, for example, Figure 5 The method shown (block 502), generates e.g. FIG. 2A to FIG. 2E Methods for layout diagrams, generation and e.g. Figures 1A to 1HStorage medium 804 stores, among other things, layout diagram 811, such as the layout diagram disclosed herein or a similar layout diagram.

[0230] The processor 802 is electrically coupled to the computer readable storage medium 804 via a bus 808. The processor 802 is further electrically coupled to an input / output (I / O) interface 810 via the bus 808. A network interface 812 is further electrically coupled to the processor 802 via the bus 808. The network interface 812 is connected to a network 814 so that the processor 802 and the computer readable storage medium 804 can be connected to external components via the network 814. The processor 802 is configured to execute a computer program code 806 encoded in the computer readable storage medium 804 so that the system 800 can be used to implement part or all of the proposed process and / or method. In one or more embodiments, the processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0231] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 804 includes semiconductor memory or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 804 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0232] In one or more embodiments, the storage medium 804 stores computer program code 806 configured to enable the system 800 (where such execution (at least in part) represents an EDA tool) to perform some or all of the proposed processes and / or methods. In one or more embodiments, the storage medium 804 further stores information that facilitates the performance of some or all of the proposed processes and / or methods. In one or more embodiments, the storage medium 804 stores a database 707 of standard cells, including such standard cells disclosed herein. In some embodiments, the storage medium 804 stores one or more layout diagrams 811.

[0233] The EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to an external circuit system. In one or more embodiments, the I / O interface 810 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor arrow keys for transmitting information and commands to the processor 802.

[0234] The EDA system 800 further includes a network interface 812 coupled to the processor 802. The network interface 812 enables the system 800 to communicate with a network 814, which is connected to one or more other computer systems. The network interface 812 includes a wireless network interface, such as BLUETOOTH, wireless fidelity (WIFI), Worldwide Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), or wideband code division multiple access (WCDMA); or a wired network interface, such as Ethernet (ETHERNET), universal serial bus (USB), or Institute of Electrical and Electronic Engineers-1364 (IEEE-1364). In one or more embodiments, part or all of the proposed process and / or method is implemented in two or more systems 800.

[0235] The system 800 is configured to receive information via an I / O interface 810. The information received via the I / O interface 810 includes one or more of instructions, data, design rules, a standard cell database, and / or other parameters for processing by the processor 802. The information is transmitted to the processor 802 via a bus 808. The EDA system 800 is configured to receive information related to a user interface (UI) via the I / O interface 810. The information is stored in a computer-readable storage medium 804 as a UI 842.

[0236] In some embodiments, some or all of the proposed processes and / or methods are implemented in the form of a stand-alone software application executed by a processor. In some embodiments, some or all of the proposed processes and / or methods are implemented in the form of a software application that is part of an additional software application. In some embodiments, some or all of the proposed processes and / or methods are implemented in the form of a plug-in to a software application. In some embodiments, at least one of the proposed processes and / or methods is implemented in the form of a software application that is part of an EDA tool. In some embodiments, some or all of the proposed processes and / or methods are implemented in the form of a software application used by the EDA system 800. In some embodiments, a tool (e.g., available from Cadence Design Systems) is used to implement the proposed processes and / or methods. or another suitable layout generation tool) to generate a layout including standard cells.

[0237] In some embodiments, the process is implemented in the functional form of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or memory units, such as one or more of optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM), memory cards, and the like.

[0238] Fig. 9 is a block diagram of an integrated circuit (IC) manufacturing system 900 and an IC manufacturing flow associated with the integrated circuit (IC) manufacturing system 900 according to some embodiments.

[0239] Based on Figure 5 The layout diagram generated by block 502 is implemented by the IC manufacturing system 900 Figure 5 As shown in block 504 , at block 504 , at least one of the following is fabricated using the fabrication system 900 : (A) one or more semiconductor masks or (B) at least one component of a layer of an initial semiconductor integrated circuit.

[0240] exist Fig. 9 In the present invention, the IC manufacturing system 900 includes entities such as a design company 920, a mask company 930, and an IC manufacturer / fabricator ("fab") 950, which interact with each other in the design, development, and manufacturing cycles and / or services associated with manufacturing IC devices 960. The entities in the manufacturing system 900 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired channels and / or wireless communication channels. Each entity interacts with one or more of the other entities and supplies services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, a single larger company owns two or more of the design company 920, the mask company 930, and the IC foundry 950. In some embodiments, two or more of the design company 920, the mask company 930, and the IC foundry 950 coexist in a common facility and use common resources.

[0241] The design company (or design team) 920 generates an IC design layout 922. The IC design layout 922 includes various geometric patterns designed for the IC device 960. The geometric patterns correspond to the patterns of the metal layers, oxide layers, or semiconductor layers of the various components constituting the IC device 960 to be manufactured. Various layers are combined to form various IC features. For example, a portion of the IC design layout 922 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer) (such as an active region, a gate electrode, a source and a drain, a metal wire or a through hole of an interlayer interconnection line, and an opening for a bonding pad) and various material layers disposed on the semiconductor substrate. Depending on the context, the source / drain region may refer to a source or a drain individually or collectively. The design company 920 implements an appropriate design program to form the IC design layout 922. The design program includes one or more of a logical design, a physical design, or a layout and wiring. The IC design layout 922 is presented in the form of one or more data files having information of a geometric pattern. For example, the IC design layout 922 is expressed in a GDSII file format or a DFII file format.

[0242] The mask company 930 includes data preparation 932 and mask production 934. The mask company 930 uses the IC design layout 922 to manufacture one or more masks 935 based on the IC design layout 922 for use in making various layers of the IC device 960. The mask company 930 performs mask data preparation 932, and when performing the mask data preparation 932, the IC design layout 922 is translated into a representative data file ("representative data file, RDF"). The mask data preparation 932 supplies the RDF to the mask production 934. The mask production 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (photomask) or a semiconductor wafer. The mask data preparation 932 manipulates the design layout to comply with the specific characteristics of the mask writer and / or the requirements of the IC foundry 950. In Fig. 9 , mask data preparation 932, mask fabrication 934, and mask 935 are shown as separate components. In some embodiments, mask data preparation 932 and mask fabrication 934 may be collectively referred to as mask data preparation.

[0243] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors (e.g., image errors that may be caused by diffraction, interference, other process effects, and the like). OPC adjusts IC design layout 922. In some embodiments, mask data preparation 932 further includes resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution assist features, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is further used, which treats OPC as an inverse imaging problem.

[0244] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that checks the IC design layout that has undergone the process in OPC with a set of mask creation rules containing certain geometric restrictions and / or connectivity restrictions to ensure that there is sufficient margin to take into account the variability of semiconductor manufacturing processes and similar factors. In some embodiments, the MRC modifies the IC design layout to compensate for the restrictions during mask production 934, which can cancel a portion of the modifications implemented by OPC to meet the mask creation rules.

[0245] In some embodiments, mask data preparation 932 includes lithography process checking (LPC), which simulates the process to be performed by IC foundry 950 to fabricate IC device 960. LPC simulates such process based on IC design layout 922 to fabricate simulated manufactured devices, such as IC device 960. Process parameters in LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after the simulated manufactured device has been fabricated by LPC, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further improve IC design layout 922.

[0246] The above description of mask data preparation 932 has been simplified for clarity. In some embodiments, mask data preparation 932 includes additional features, such as logic operations (LOP) that modify IC design layout according to manufacturing rules. In addition, the processes applied to IC design layout 922 during data preparation 932 can be performed in a variety of different orders.

[0247] After mask data preparation 932 and during mask fabrication 934, a mask 935 or a group of masks 935 are fabricated based on the modified IC design layout. In some embodiments, an electron-beam (e-beam) or a mechanism consisting of multiple electron beams is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The mask is formed with various techniques. In some embodiments, the mask is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, the binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque area of ​​the mask. In another example, the mask is formed using a phase shift technique. In a phase shift mask (PSM), various features in a pattern formed on the mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask is an attenuated PSM or an alternating PSM. The mask produced by mask making 934 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0248] IC foundry 950 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC foundry 950 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line, FEOL) manufacturing of multiple IC products, while a second manufacturing facility may be used for back-end manufacturing (back-end-of-line, BEOL) manufacturing of interconnects and packaging for IC products, and a third manufacturing facility may provide other services for the foundry company.

[0249] IC foundry 950 uses mask (or multiple masks) 935 made by mask company 930 to make IC device 960 using fabrication tool 952. Therefore, IC foundry 950 uses IC design layout 922 at least indirectly to make IC device 960. In some embodiments, mask (or multiple masks) 935 is used by IC foundry 950 to make semiconductor wafer 953 to form IC device 960. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate with material layers formed thereon. The semiconductor wafer further includes one or more of various doped regions, dielectric features, multi-level interconnects, and similar features (formed at subsequent manufacturing steps).

[0250] In some embodiments, a semiconductor device includes: a single-bit flip-flop region (SBFF region), including a multi-bit flip-flop (MBFF) region; the MBFF region has a two-dimensional planar layout represented by a grid, the grid includes rows and first columns extending in a corresponding first direction and a corresponding perpendicular second direction, each SBFF region represents the intersection of a corresponding row and a corresponding column; the SBFF regions are coupled in a daisy chain, the output of a previous SBFF region in the SBFF regions in the daisy chain is coupled to the input of a subsequent SBFF region in the SBFF regions in the daisy chain; and the orientation (α orientation) of the SBFF regions relative to the first direction is arranged in an alternating pattern relative to the second direction, so that the two-dimensional representation of the flow path of a data signal along the first column has a spiral shape.

[0251] In some embodiments, the first column includes at least a first sub-column and a second sub-column; relative to the first direction, each SBFF region has an input region on a first side of the SBFF region and an output region on an opposite second side of the SBFF region; for each SBFF region located in an odd row in the first column, the input region is located in the first sub-column and the output region is located in the second sub-column; and for each SBFF region located in an even row of the first column, the input region is located in the second sub-column and the output region is located in the first sub-column.

[0252] In some embodiments, the grid further includes a second column extending in the second direction, the second column including at least a first sub-column and a second sub-column; for each SBFF region located in an odd row of the second column, the input region is located in the second sub-column and the output region is located in the first sub-column; and for each SBFF region located in an even row of the second column, the input region is located in the first sub-column and the output region is located in the second sub-column.

[0253] In some embodiments, the grid further includes a second column extending in the second direction; for each SBFF region located in an odd row of the second column, the input region is located in the first sub-column and the output region is located in the second sub-column; and for each SBFF region located in an even row of the second column, the input region is located in the second sub-column and the output region is located in the first sub-column.

[0254] In some embodiments, the grid further includes a second column extending in the second direction; each of the first column and the second column includes at least a first sub-column and a second sub-column; relative to the first direction, each SBFF region has an input region on a first side of the SBFF region and an output region on an opposite second side of the SBFF region; for each SBFF region located in an odd row of each of the first column and the second column, the input region is located in the second sub-column and the output region is located in the first sub-column; for each SBFF region located in an even row of each of the first column and the second column, the input region is located in the first sub-column and the output region is located in the second sub-column.

[0255] In some embodiments, the semiconductor device further includes: a transistor layer, including an active region (AR), in which a plurality of source / drain (S / D) regions and a channel region of corresponding transistors are formed, the channel region being correspondingly located between the S / D regions as a channel region, the SBFF region being composed of corresponding transistors among the transistors; and wherein: some of the ARs have a first conductivity type (first AR) and some of the ARs have a different second conductivity type (second AR); each SBFF includes at least one first AR and at least one second AR; each SBFF has a first orientation or a second orientation (a first β orientation or a second β orientation) relative to a second direction, the first β orientation having a first AR stacked on a second AR, and the second β orientation having a second AR stacked on the first AR; and for each SBFF region in an odd row, the SBFF region has a first β orientation.

[0256] In some embodiments, for each SBFF region in an even-numbered row, the SBFF region has a first β orientation.

[0257] In some embodiments, for each SBFF region in an even-numbered row, the SBFF region has the second β orientation.

[0258] In some embodiments, the semiconductor device further includes: a transistor layer, including an active region (AR), in which source / drain (S / D) regions and a channel region of a corresponding transistor are formed, the channel region being correspondingly located between the S / D regions as a channel region, and the SBFF region being composed of corresponding transistors of the transistors; and wherein: some of the ARs have a first conductivity type (first AR) and some of the ARs have a different second conductivity type (second AR); each SBFF includes at least one first AR and at least one second AR; each SBFF has a first orientation or a second orientation (a first β orientation or a second β orientation) relative to a second direction, the first β orientation having a first AR stacked on the second AR, and the second β orientation having a second AR stacked on the first AR; and for each SBFF region in an even-numbered row, the SBFF region has a second β orientation.

[0259] In some embodiments, for each SBFF region in odd rows of a first column, the SBFF region has a first β orientation.

[0260] In some embodiments, for each SBFF region in the odd rows of the first column, the SBFF region has the second β orientation.

[0261] In some embodiments, the grille further includes a second column extending in the second direction; the semiconductor device further includes: a transistor layer including an active region (AR), in which source / drain (S / D) regions and a channel region of corresponding transistors are formed, the channel region being correspondingly located between the S / D regions as a channel region, the SBFF region being constituted by corresponding transistors in the transistors; a first metallization layer (M_1st layer) located above the transistor layer, a conductive segment (M_1st segment) in the M_1st layer extending in the first direction; a second metallization layer (M_2nd layer) located above the M_1st layer, a conductive segment (M_2nd segment) in the M_2nd layer extending in the second direction; and a third metallization layer (M_3rd layer) located above the M_2nd layer, a conductive segment (M_3rd segment) in the M_3rd layer extending in the first direction; the SBFF regions in the first column represent bits b0 to b(i) of the MBFF, where i is a positive integer and i < N; the SBFF regions in the second column represent bits b(i + 1) to b(N - 1) of the MBFF; a coupling member between an output of the SBFF region representing bit b(i) in the first column and an input of the SBFF representing bit b(i + 1) in the second column includes the first M_3rd segment in the M_3rd segment; and for each of the first column and the second column, some parts of the daisy chain that couple an input of a given SBFF region to an output of the given SBFF region do not include the M_3rd segment.

[0262] In some embodiments, in each of the first column and the second column, with respect to the second direction, the SBFF regions are arranged in a stack in which the SBFF regions are stacked on top of each other; and the coupling member between the output of the SBFF region representing bit b(i) in the first column and the input of the SBFF region representing bit b(i + 1) in the second column includes the first M_2nd segment, and the first M_2nd segment extends from the SBFF region representing bit b0 in the first column to the SBFF region representing bit b(i) in the first column.

[0263] In some embodiments, an input representing the head of the daisy chain of the SBFF region represents an input of the MBFF region, and an output representing the tail of the daisy chain of the SBFF region represents an output of the MBFF region.

[0264] In some embodiments, the grille further includes a second column extending in the second direction; the first half of the total number of SBFF regions are located in the first column; the second half of the total number of SBFF regions are located in the second column.

[0265] In some embodiments, in the first column, the spiral shape of the data signal along the flow path of the first column is a non-self-overlapping spiral shape.

[0266] In some embodiments, in the first column, the spiral shape of the data signal along the flow path of the first column is a self-overlapping spiral shape.

[0267] In some embodiments, a semiconductor device includes: a single-bit flip-flop region (SBFF region) including a multi-bit flip-flop (MBFF) region; the MBFF region has a two-dimensional layout represented by a grid, the grid including rows extending in a corresponding first direction and a corresponding perpendicular second direction, and a first column and a second column, each SBFF region representing an intersection of a corresponding row and a corresponding column; the SBFF regions are coupled in a daisy chain, an output of a previous SBFF region in the daisy chain being coupled to an input of a subsequent SBFF region in the daisy chain; and an orientation (α orientation) of the SBFF regions with respect to the first direction is arranged in an alternating pattern with respect to the second direction such that a two-dimensional representation of the flow path of the data signal along each of the first column and the second column has a corresponding spiral shape.

[0268] In some embodiments, the SBFF regions include a first SBFF region to an (N)th SBFF region such that the MBFF is an N-bit MBFF, where N is a positive integer; the daisy chain couples the first SBFF region to the (N)th SBFF region in a numerically increasing order from the first SBFF region to the (N)th SBFF region; in each of the first column and the second column, with respect to the second direction, the SBFF regions are arranged in a stack where the SBFF regions are stacked on top of each other; the SBFF regions located in the first column represent bits b0 to bi of the MBFF, where i is a positive integer and i < N; with respect to the second direction, the SBFF region representing bit b0 is located at the bottom of the first column, and the SBFF region representing bit bi is located at the top of the first column.

[0269] In some embodiments, the SBFF regions located in the second column represent bits b(i + 1) to b(N - 1) of the MBFF; with respect to the second direction, the SBFF region representing bit b(i + 1) is located at the bottom of the second column, and the SBFF region representing bit b(N - 1) is located at the top of the second column.

[0270] In some embodiments, the SBFF regions in the second column represent bits b(i + 1) to b(N - 1); with respect to the second direction, the SBFF region representing bit b(i + 1) is at the top of the second column, and the SBFF region representing bit b(N - 1) is at the bottom of the second column.

[0271] In some embodiments, a method of operating a multi-bit flip-flop (MBFF) region of a semiconductor device, the MBFF being composed of a first single-bit flip-flop region (SBFF region) to an (N)th SBFF region respectively representing bits b0 to b(N - 1), such that the MBFF is an N-bit MBFF, where N is a positive integer, the first SBFF region to the (N)th SBFF region being daisy-chained in ascending numerical order from the first SBFF region to the (N)th SBFF region, the MBFF region having a two-dimensional floorplan represented by a grid, the grid including rows extending in a corresponding first direction and a corresponding perpendicular second direction, and a first column and a second column, each SBFF region representing the intersection of a corresponding row and a corresponding column; the first column includes the first SBFF region to the (i + 1)th SBFF region among the SBFF regions respectively representing bits b(0) to b(i), where i is a positive integer and i < N, the second column includes the (i + 2)th SBFF region to the (N)th SBFF region among the SBFF regions respectively representing bits b(i + 1) to b(N - 1), the method includes advancing a data signal through the MBFF region, including: propagating the data signal in the first column such that a two-dimensional representation of the first flow path of the data signal along the first column has a first helical shape; propagating the data signal from the first column to the second column; and propagating the data signal in the second column such that a two-dimensional representation of the second flow path of the data signal along the second column has a second helical shape.

[0272] In some embodiments, propagating the data signal in the first column propagates the data signal in such a way that the two-dimensional representation of the first flow path has a non-self-overlapping helical shape; and propagating the data signal in the second column propagates the data signal in such a way that the two-dimensional representation of the second flow path has a non-self-overlapping helical shape.

[0273] In some embodiments, propagating the data signal in the first column propagates the data signal in such a way that the two-dimensional representation of the first flow path has a self-overlapping helical shape; and propagating the data signal in the second column propagates the data signal in such a way that the two-dimensional representation of the second flow path has a self-overlapping helical shape.

[0274] In some embodiments, each SBFF region has an input region on a first side of the SBFF region and an output region on an opposite second side of the SBFF region relative to the first direction, each of the first column and the second column includes at least a first sub-column and a second sub-column; a given SBFF region in the SBFF region has the input region in the first sub-column and the output region in the second sub-column for a first orientation (a first α orientation) relative to the first direction, and a given SBFF region in the SBFF region has the input region in the second sub-column and the output region in the first sub-column for a second α orientation, and for each of the first column and the second column, the row presents an alternating α orientation pattern such that the row alternates between the first α orientation and the second α orientation, so that the Propagating the data signal in the first column includes transmitting the data signal in a manner such that each portion of the two-dimensional representation of the first flow path is parallel to the second direction, and the first flow path couples the previous SBFF area from the first SBFF area to the (i+1)th SBFF area to the next SBFF area from the first SBFF area to the (i+1)th SBFF area; and propagating the data signal in the second column includes transmitting the data signal in a manner such that each portion of the two-dimensional representation of the second flow path is parallel to the second direction, and the second flow path couples the previous SBFF area from the (i+2)th SBFF area to the (N)th SBFF area to the next SBFF area from the (i+2)th SBFF area to the (N)th SBFF area.

[0275] In some embodiments, causing the data signal to propagate from the first column to the second column includes routing the data signal such that a two-dimensional representation of a third flow path of the data signal from the first column to the second column includes a first portion parallel to the first direction.

[0276] In some embodiments, transmitting the data signal transmits the data signal in a manner such that the first portion extends from the first sub-column of the first column to the second sub-column of the second column.

[0277] In some embodiments, transmitting the data signal transmits the data signal in a manner such that the first portion extends from the first sub-column of the first column to the first sub-column of the second column.

[0278] In some embodiments, transmitting the data signal transmits the data signal in a manner such that the first portion extends from the second sub-column of the first column to the first sub-column of the second column.

[0279] In some embodiments, causing the data signal to propagate from the first column to the second column includes transmitting the data signal in such a manner that the two-dimensional representation of the third flow path further includes a second portion extending from a row including the first SBFF region to a row including the (i)th SBFF region.

[0280] In some embodiments, a method of forming a multi-bit flip-flop (MBFF) region of a semiconductor device, the MBFF being composed of a first single-bit flip-flop region (SBFF region) to an (N)th SBFF region correspondingly representing bit b0 to bit b(N-1), such that the MBFF is an N-bit MBFF, where N is a positive integer, the first SBFF region to the (N)th SBFF region being daisy-chained in ascending numerical order from the first SBFF region to the (N)th SBFF region, the MBFF region having a two-dimensional floorplan represented by a grid, the grid including rows and a first column and a second column extending in a corresponding first direction and a corresponding perpendicular second direction, each SBFF region representing an intersection of a corresponding row and a corresponding column; the first column including the first SBFF region to the (i + 1)th SBFF region among the SBFF regions correspondingly representing bit b(0) to bit b(i), where i is a positive integer and i < N, the second column including the (i + 2)th SBFF region to the (N)th SBFF region among the SBFF regions correspondingly representing bit b(i + 1) to bit b(N-1), the method comprising: forming a transistor layer including an active region (AR) in which source / drain (S / D) regions and channel regions of corresponding transistors are formed, the channel regions being located between the S / D regions as channel regions, the SBFF regions being composed of corresponding transistors among the transistors; forming segments (M_1st segments) in a first metallization layer above the transistor layer, the M_1st segments extending in the first direction, at least some of the M_1st segments in the M_1st segments being coupled to corresponding components of the transistors including the S / D regions, with respect to the first direction, each SBFF region having an input region on a first side of the SBFF region and an output region on a relatively second side of the SBFF region, with respect to the second direction, for each SBFF region, the in-SBFF flow path of the data signal coupling the input region and the output region is composed of the M_1st segments (in-SBFF segments) in the M_1st segments located within the SBFF region, the two-dimensional representation of the in-SBFF flow path extends parallel to the first direction, and for each of the first column and the second column, the two-dimensional representation of the column-by-column flow path of the data signal along the column is composed of the in-SBFF flow paths;and forming segments (M_2nd segments) in the second metallization layer, the M_2nd segments extending in the second direction, at least some of the M_2nd segments representing portions of inter-SBFF signal paths, for each pair of immediately adjacent SBFF regions (SBFF pair) relative to the second direction, a corresponding one of the inter-SBFF signal paths coupling an output region of a former one of the SBFF pair to a latter one of the SBFF pair, for each of the first and second columns, the two-dimensional representation of the column-by-column flow paths further consisting of the inter-SBFF signal paths, and for each of the first and second columns, the two-dimensional representation of the column-by-column flow paths having a corresponding spiral shape.;

[0281] In some embodiments, the forming of the transistor layer includes: forming an active region (AR) in a substrate, wherein the AR extends in a first direction; forming a source / drain (S / D) region in the AR, including doping a first region of the AR, and wherein a second region of the AR correspondingly located between the S / D regions is a channel region; correspondingly forming a gate segment above the channel region of the AR and the gate segment extends in a second direction perpendicular to the first direction; correspondingly forming a metal to source / drain region (MD) contact structure above the AR, and the source / drain region (MD) contact structure is dispersed between the gate segments; correspondingly forming a through-hole to gate (VG) contact structure above the gate segment and below a corresponding one of the M_1st segments; and correspondingly forming a through-hole to MD (VD) contact structure above the MD contact structure; and wherein the M_1st segment is correspondingly located above the VG contact structure and the VD contact structure.

[0282] In some embodiments, before forming the M_2nd segment, a via to M_1st (V_1st) contact structure is correspondingly formed above the M_1st segment; and wherein the M_2nd segment is correspondingly located above the V_1st contact structure.

[0283] In some embodiments, the method further includes forming a segment (M_3rd segment) in the third metallization layer, wherein the M_3rd segment extends in the second direction, and the M_3rd segment represents at least a portion of an inter-column signal path that couples a column-by-column flow path of a first column to a column-by-column flow path of a second column.

[0284] In some embodiments, the inter-column signal path is further composed of an M_2nd segment located in the first column (C_1st M_2nd segment) among the M_2nd segments and an M_2nd segment located in the second column (C_2nd M_2nd segment) among the M_2nd segments.

[0285] In some embodiments, the C_1st M_2nd segment of the inter-column signal path overlies portions of at least two of the rows; or the C_2nd M_2nd segment of the inter-column signal path overlies portions of at least two of the rows.

[0286] In some embodiments, the C_1st M_2nd segment of the inter-column signal path extends from within the first SBFF region to the (i+1)th SBFF region.

[0287] In some embodiments, before forming the M_3rd segment, a via-to-M_2nd (VIA2) contact structure is formed over the M_2nd segment.

[0288] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the utility model, rather than to limit them. Although the embodiments of the utility model are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the embodiments of the utility model.

Claims

1. A semiconductor device, characterized in that: include: A plurality of single-bit flip-flop regions, including a multi-bit flip-flop region; The multi-bit flip-flop region has a two-dimensional plan view represented by a grid, the grid including rows and first columns extending in a corresponding first direction and a corresponding perpendicular second direction, each single-bit flip-flop region in the plurality of single-bit flip-flop regions representing an intersection of a corresponding row and a corresponding column in the rows; The plurality of single-bit flip-flop regions are coupled in a daisy chain, and an output of a previous single-bit flip-flop region among the plurality of single-bit flip-flop regions in the daisy chain is coupled to an input of a subsequent single-bit flip-flop region among the plurality of single-bit flip-flop regions in the daisy chain; and The orientations of the plurality of single bit flip-flop regions relative to the first direction are arranged in an alternating pattern relative to the second direction such that a two-dimensional representation of a flow path of a data signal along the first column has a spiral shape.

2. The semiconductor device according to claim 1, wherein: in: The first column includes at least a first sub-column and a second sub-column; With respect to the first direction, each of the plurality of single-bit flip-flop regions has an input region on a first side of the single-bit flip-flop region and an output region on an opposite second side of the single-bit flip-flop region; For each single-bit flip-flop region in the plurality of single-bit flip-flop regions located in odd-numbered rows of the first column, the input region is located in the first sub-column and the output region is located in the second sub-column; as well as For each single-bit flip-flop region in the plurality of single-bit flip-flop regions located in an even-numbered row of the first column, the input region is located in the second sub-column and the output region is located in the first sub-column.

3. The semiconductor device according to claim 2, wherein: in: The grid further includes a second row extending in the second direction, the second row including at least a first sub-row and a second sub-row; For each single-bit flip-flop region in the plurality of single-bit flip-flop regions located in odd-numbered rows of the second column, the input region is located in the second sub-column and the output region is located in the first sub-column; as well as For each single-bit flip-flop region in the plurality of single-bit flip-flop regions located in an even-numbered row of the second column, the input region is located in the first sub-column and the output region is located in the second sub-column.

4. The semiconductor device according to claim 2, wherein: in: The grid further includes a second row extending in the second direction; For each single-bit flip-flop region in the plurality of single-bit flip-flop regions located in odd-numbered rows of the second column, the input region is located in the first sub-column and the output region is located in the second sub-column; as well as For each single-bit flip-flop region in the plurality of single-bit flip-flop regions located in an even-numbered row of the second column, the input region is located in the second sub-column and the output region is located in the first sub-column.

5. The semiconductor device according to claim 1, wherein: in: The grid further includes a second row extending in the second direction; Each of the first column and the second column includes at least a first sub-column and a second sub-column; With respect to the first direction, each of the plurality of single-bit flip-flop regions has an input region on a first side of the single-bit flip-flop region and an output region on an opposite second side of the single-bit flip-flop region; For each single-bit flip-flop region in the plurality of single-bit flip-flop regions located in odd-numbered rows of each of the first column and the second column, the input region is located in the second sub-column and the output region is located in the first sub-column; as well as For each single-bit flip-flop region of the plurality of single-bit flip-flop regions located in even-numbered rows of each of the first column and the second column, the input region is located in the first sub-column and the output region is located in the second sub-column.

6. The semiconductor device according to claim 1, wherein: in: The grid further includes a second row extending in the second direction; The semiconductor device further comprises: A transistor layer, comprising an active region, wherein a plurality of source / drain regions and a channel region of corresponding transistors are formed in the active region, wherein the channel region is correspondingly located between the source / drain regions as a channel, and the plurality of single-bit flip-flop regions are composed of corresponding transistors among the plurality of corresponding transistors; A first metallization layer, located above the transistor layer, wherein the conductive segments in the first metallization layer extend in the first direction; a second metallization layer located on the first metallization layer, wherein the conductive segments in the second metallization layer extend in the second direction; and A third metallization layer, located on the second metallization layer, wherein the conductive segments in the third metallization layer extend in the first direction; The single-bit flip-flop region in the first column of the plurality of single-bit flip-flop regions represents bit b0 to bit b(i) of the multi-bit flip-flop region, where i is a positive integer and i <N; The single-bit flip-flop regions in the second column among the plurality of single-bit flip-flop regions represent bits b(i+1) to b(N-1) of the plurality of single-bit flip-flop regions; a coupling between an output of a single-bit flip-flop region of the plurality of single-bit flip-flop regions representing the bit b(i) in the first column and an input of a single-bit flip-flop region of the plurality of single-bit flip-flop regions representing the bit b(i+1) in the second column comprising a first conductive segment of the conductive segments in the third metallization layer; and For each of the first column and the second column, some portions of the daisy chain that couples the input of a given one of the multiple single-bit flip-flop regions to the output of a given one of the multiple single-bit flip-flop regions do not include the conductive segments in the third metallization layer.

7. The semiconductor device according to claim 1, wherein: in: In the first column, the spiral shape of the flow path of the data signal along the first column is a non-self-overlapping spiral shape or a self-overlapping spiral shape.

8. A semiconductor device, characterized in that: include: A plurality of single-bit flip-flop regions, including a multi-bit flip-flop region; The multi-bit flip-flop region has a two-dimensional plan view represented by a grid, the grid including rows extending in a corresponding first direction and a corresponding perpendicular second direction and a first column and a second column, each single-bit flip-flop region in the plurality of single-bit flip-flop regions representing an intersection of a corresponding row and a corresponding column in the rows; The plurality of single-bit flip-flop regions are coupled in a daisy chain, and an output of a previous single-bit flip-flop region among the plurality of single-bit flip-flop regions in the daisy chain is coupled to an input of a subsequent single-bit flip-flop region among the plurality of single-bit flip-flop regions in the daisy chain; and The orientations of the plurality of single bit flip-flop regions relative to the first direction are arranged in an alternating pattern relative to the second direction such that a two-dimensional representation of a flow path of a data signal along each of the first and second columns has a corresponding spiral shape.

9. The semiconductor device according to claim 8, wherein: in: The plurality of single-bit flip-flop regions include a first single-bit flip-flop region to an (N)th single-bit flip-flop region, so that the multi-bit flip-flop region is a multi-bit flip-flop region of N bits, wherein N is a positive integer; The daisy chain couples the first single-bit flip-flop region to the (N)th single-bit flip-flop region in an increasing order of values ​​from the first single-bit flip-flop region to the (N)th single-bit flip-flop region; In each of the first column and the second column, the plurality of single-bit flip-flop regions are arranged into a stack in which the plurality of single-bit flip-flop regions are stacked on each other with respect to the second direction; The single-bit flip-flop region in the first column of the plurality of single-bit flip-flop regions represents bit b0 to bit b(i) of the multi-bit flip-flop region, where i is a positive integer and i <N; With respect to the second direction, The single-bit flip-flop region representing the bit b0 among the plurality of single-bit flip-flop regions is located at the bottom of the first column, and The single-bit flip-flop region representing the bit b(i) among the plurality of single-bit flip-flop regions is located at the top of the first column.

10. The semiconductor device according to claim 8, wherein: in: The single-bit flip-flop regions in the second column among the plurality of single-bit flip-flop regions represent bits b(i+1) to b(N-1) of the plurality of single-bit flip-flop regions; With respect to the second direction, The single-bit flip-flop region representing the bit b(i+1) among the plurality of single-bit flip-flop regions is located at the bottom of the second column, and The single-bit flip-flop region representing the bit b(N-1) among the plurality of single-bit flip-flop regions is located at the top of the second column.

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