Chip and radio frequency amplifier

Abstract

The embodiment of the utility model discloses a chip and a radio frequency amplifier. The chip comprises a radio frequency amplification circuit, the radio frequency amplification circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor, the first MOS transistor comprises n first sub-MOS transistors, the second MOS transistor comprises n second sub-MOS transistors, the third MOS transistor comprises n third sub-MOS transistors, the fourth MOS transistor comprises n fourth sub-MOS transistors, the third MOS transistor is used for counteracting the gate-drain capacitance of the first MOS transistor, and the fourth MOS transistor is used for counteracting the gate-drain capacitance of the second MOS transistor. The fourth MOS tube is used for counteracting the gate-drain capacitance of the second MOS tube; and the n first sub MOS transistors, the n second sub MOS transistors, the n third sub MOS transistors and the n fourth sub MOS transistors are arranged according to a multi-dimensional common axis layout or a multi-dimensional common centroid layout. According to the embodiment of the invention, the gain effect and stability of the radio frequency amplification circuit during working can be enhanced.

Description

Technical Field

[0001] The present application relates to radio frequency technology, applied in the field of electronics, and in particular to a chip and a radio frequency amplifier. Background Art

[0002] RF transmitting circuits are widely used in the field of communications. RF amplifier circuits are an important part of RF transmitting circuits and are used to amplify the power of input RF signals. The parasitic capacitance of active devices in RF amplifier circuits is prone to be too large when the gain is large, thus affecting the gain effect and stability of RF amplifier circuits. Utility Model Content

[0003] The embodiments of the present application disclose a chip and a radio frequency amplifier, which can enhance the gain effect and stability of the radio frequency amplification circuit during operation.

[0004] In a first aspect, an embodiment of the present application provides a chip, the chip includes a radio frequency amplifier circuit 10, the radio frequency amplifier circuit 10 includes a first MOS tube M1, a second MOS tube M2, a third MOS tube MC1 and a fourth MOS tube MC2, the first MOS tube M1 includes n first sub-MOS tubes, the second MOS tube M2 includes n second sub-MOS tubes, the third MOS tube MC1 includes n third sub-MOS tubes, the fourth MOS tube MC2 includes n fourth sub-MOS tubes, n is a positive integer greater than or equal to 2, wherein the third MOS tube MC1 is used to offset the gate-drain capacitance of the first MOS tube M1, the fourth MOS tube MC2 is used to offset the gate-drain capacitance of the second MOS tube M2, and the n first sub-MOS tubes, the n second sub-MOS tubes, the n third sub-MOS tubes and the n fourth sub-MOS tubes are arranged in a multi-dimensional co-axial layout or a multi-dimensional co-centroid layout.

[0005] In the above chip, each MOS tube in the radio frequency amplifier circuit 10 is divided into multiple sub-MOS tubes, and can be arranged on the chip according to a multi-dimensional coaxial center layout or a multi-dimensional co-centroid layout, each first sub-MOS tube of the first MOS tube M1 is arranged adjacent to each third sub-MOS tube in the third MOS tube MC1, and each second sub-MOS tube of the second MOS tube M2 is arranged adjacent to a fourth sub-MOS tube in the fourth MOS tube MC2. Then, the first MOS tube M1 and the third MOS tube MC1 can be regarded as closer, and the second MOS tube M2 and the fourth MOS tube MC2 can be regarded as closer, which can improve the matching degree of the circuit environment where the first MOS tube M1 and the third MOS tube MC1 are located, and the matching degree of the circuit environment where the second MOS tube M2 and the fourth MOS tube MC2 are located, thereby improving the system matching, and then enhancing the gain effect and stability of the radio frequency amplifier circuit 10 when working.

[0006] In combination with the first aspect, in a possible implementation, the first MOS tube M1 includes a first first sub-MOS tube M1-1 and a second first sub-MOS tube M1-2, the second MOS tube M2 includes a first second sub-MOS tube M2-1 and a second second sub-MOS tube M2-2, the third MOS tube MC1 includes a first third sub-MOS tube MC1-1 and a second third sub-MOS tube MC1-2, the fourth MOS tube MC2 includes a first fourth sub-MOS tube MC2-1 and a second fourth sub-MOS tube MC2-2, wherein the first first sub-MOS tube M1-1, the first third sub-MOS tube MC1-1, the first fourth sub-MOS tube MC2-1 and the second fourth sub-MOS tube MC2-2 are The four sub-MOS tubes MC2-1 and the first second sub-MOS tube M2-1 are arranged in sequence in the first direction, the first first sub-MOS tube M1-1 and the second first sub-MOS tube M1-2 are arranged in sequence in the second direction, the first second sub-MOS tube M2-1 and the second second sub-MOS tube M2-2 are arranged in sequence in the second direction, the first third sub-MOS tube MC1-1 and the second third sub-MOS tube MC1-2 are arranged in sequence in the second direction, the first fourth sub-MOS tube MC2-1 and the second fourth sub-MOS tube MC2-2 are arranged in sequence in the second direction, and the first direction and the second direction are perpendicular to each other.

[0007] In combination with the first aspect, or any of the foregoing possible implementations of the first aspect, in another possible implementation, the first MOS tube M1 includes a first first sub-MOS tube M1-1 and a second first sub-MOS tube M1-2, the second MOS tube M2 includes a first second sub-MOS tube M2-1 and a second second sub-MOS tube M2-2, the third MOS tube MC1 includes a first third sub-MOS tube MC1-1 and a second third sub-MOS tube MC1-2, the fourth MOS tube MC2 includes a first fourth sub-MOS tube MC2-1 and a second fourth sub-MOS tube MC2-2, wherein the first first sub-MOS tube M1-1, the first third sub-MOS tube M1-1 and the second third sub-MOS tube MC1-2 are connected to each other. The sub-MOS tube MC1-1, the first fourth sub-MOS tube MC2-1 and the first second sub-MOS tube M2-1 are arranged in sequence in the first direction, the first first sub-MOS tube M1-1 and the second third sub-MOS tube MC1-2 are arranged in sequence in the second direction, the second first sub-MOS tube M1-2 and the first third sub-MOS tube MC1-1 are arranged in sequence in the second direction, the first second sub-MOS tube M2-1 and the second fourth sub-MOS tube MC2-2 are arranged in sequence in the second direction, the second second sub-MOS tube M2-2 and the first fourth sub-MOS tube MC2-1 are arranged in sequence in the second direction, and the first direction and the second direction are perpendicular to each other.

[0008] In combination with the first aspect, or any of the above-mentioned possible implementation methods of the first aspect, in another possible implementation method, the positive input terminal of the RF amplification circuit 10 is connected to the gate of the first MOS tube M1 and the drain of the third MOS tube MC1, the negative input terminal of the RF amplification circuit 10 is connected to the gate of the second MOS tube M2 and the drain of the fourth MOS tube MC2, the source of the first MOS tube M1 and the source of the second MOS tube M2 are connected to the reference ground, the drain of the first MOS tube M1 is connected to the gate of the fourth MOS tube MC2, the drain of the fourth MOS tube MC2 and the positive output terminal of the RF amplification circuit 10, and the drain of the second MOS tube M2 is connected to the gate of the third MOS tube MC1, the drain of the third MOS tube MC1 and the negative output terminal of the RF amplification circuit 10.

[0009] In combination with the first aspect, or any of the foregoing possible implementations of the first aspect, in another possible implementation, a gate of the first MOS tube M1 is connected to a gate of any first sub-MOS tube among the n first sub-MOS tubes, a source of the first MOS tube M1 is connected to a source of any first sub-MOS tube among the n first sub-MOS tubes, and a drain of the first MOS tube M1 is connected to a drain of any first sub-MOS tube among the n first sub-MOS tubes; a gate of the second MOS tube M2 is connected to a gate of any second sub-MOS tube among the n second sub-MOS tubes, a source of the second MOS tube M2 is connected to a source of any second sub-MOS tube among the n second sub-MOS tubes, and a drain of the second MOS tube M2 is connected to a gate of any second sub-MOS tube among the n second sub-MOS tubes. the drain of any second sub-MOS tube in the n third sub-MOS tube; the gate of the third MOS tube MC1 is connected to the gate of any third sub-MOS tube in the n third sub-MOS tubes, the source of the third MOS tube MC1 is connected to the source of any third sub-MOS tube in the n third sub-MOS tubes, and the drain of the third MOS tube MC1 is connected to the drain of any third sub-MOS tube in the n third sub-MOS tubes; the gate of the fourth MOS tube MC2 is connected to the gate of any fourth sub-MOS tube in the n fourth sub-MOS tubes, the source of the fourth MOS tube MC2 is connected to the source of any fourth sub-MOS tube in the n fourth sub-MOS tubes, and the drain of the fourth MOS tube MC2 is connected to the drain of any fourth sub-MOS tube in the n fourth sub-MOS tubes.

[0010] In combination with the first aspect, or any one of the foregoing possible implementations of the first aspect, in yet another possible implementation, the channel directions and the number of gate channels of the n first sub-MOS transistors, the n second sub-MOS transistors, the n third sub-MOS transistors, and the n fourth sub-MOS transistors are the same.

[0011] In a second aspect, an embodiment of the present application provides a radio frequency amplifier, which includes the chip described in the first aspect or any possible implementation manner of the first aspect.

[0012] The beneficial effects of the RF amplifier provided in the second aspect of the present application can refer to the beneficial effects of the technical solution in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The following is a brief introduction to the drawings required for describing the embodiments of the present application.

[0014] Figure 1 It is a structural schematic diagram of a radio frequency amplification circuit involved in the prior art;

[0015] Figure 2 It is a schematic diagram of a layout of a radio frequency amplifier circuit involved in the prior art;

[0016] Figure 3 is a structural schematic diagram of a radio frequency amplification circuit provided in an embodiment of the present application;

[0017] Figure 4 It is a schematic diagram of a layout of a radio frequency amplifier circuit provided in an embodiment of the present application;

[0018] Figure 5 It is a structural schematic diagram of a sub-MOS tube provided in an embodiment of the present application;

[0019] Figure 6 It is a schematic diagram of the layout of another radio frequency amplifier circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0021] At present, technicians usually introduce neutralizing capacitors into RF amplifier circuits and offset the parasitic capacitance of active devices by designing the connection method of the circuit to enhance the gain effect and stability of the RF amplifier circuit. For example, see Figure 1 , Figure 1 This is a schematic diagram of the structure of a radio frequency amplifier circuit involved in the prior art. Figure 1 As shown, the radio frequency amplifying circuit 10 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor MC1 and a fourth MOS transistor MC2.

[0022] The positive input terminal INP of the RF amplifying circuit 10 is connected to the gate of the first MOS tube M1 and the drain of the third MOS tube MC1, the negative input terminal INN of the RF amplifying circuit 10 is connected to the gate of the second MOS tube M2 and the drain of the fourth MOS tube MC2, the source of the first MOS tube M1 and the source of the second MOS tube M2 are connected to the reference ground, the drain of the first MOS tube M1 is connected to the gate of the fourth MOS tube MC2, the drain of the fourth MOS tube MC2 and the positive output terminal OUTP of the RF amplifying circuit 10, and the drain of the second MOS tube M2 is connected to the gate of the third MOS tube MC1, the drain of the third MOS tube MC1 and the negative output terminal OUTN of the RF amplifying circuit 10.

[0023] The radio frequency amplifier circuit 10 is used to amplify the power of the input radio frequency signal. Optionally, the input radio frequency signal can be a differential signal. It can be seen from the circuit connection relationship that the third MOS tube MC1 can offset the gate-drain capacitance Cgd1 of the first MOS tube M1, and the fourth MOS tube MC2 is used to offset the gate-drain capacitance Cgd2 of the second MOS tube M2, that is, the first MOS tube M1 and the second MOS tube M2 can be regarded as amplifier tubes, and the third MOS tube MC1 and the fourth MOS tube MC2 can be regarded as neutralizing capacitors. It can be understood that the gate-drain capacitance is a parasitic capacitance between the gate and drain of the MOS tube.

[0024] In practical applications, the RF amplifier circuit 10 is placed on a chip, and the layout of the components in the RF amplifier circuit 10 on the chip is usually as follows: Figure 2 See Figure 2 , Figure 2 Schematic diagram of a radio frequency amplifier circuit in the prior art. Figure 2 As shown, the radio frequency amplifier circuit 10 can be placed on a chip. The first MOS transistor M1, the third MOS transistor MC1, the fourth MOS transistor MC2 and the second MOS transistor M2 in the radio frequency amplifier circuit 10 are arranged in sequence in the horizontal direction.

[0025] It can be understood that the axis a1 and the mass center a2 of the first MOS tube M1 coincide with each other, the axis b1 and the mass center b2 of the second MOS tube M2 coincide with each other, the axis c1 and the mass center c2 of the third MOS tube MC1 coincide with each other, and the axis d1 and the mass center d2 of the fourth MOS tube MC2 coincide with each other.

[0026] However, considering that the actual area of ​​a single MOS tube is relatively large, both the axial center distance and the centroid distance between the first MOS tube M1 and the third MOS tube MC1 are relatively large, and both the axial center distance and the centroid distance between the second MOS tube M2 and the fourth MOS tube MC2 are relatively large, then the first MOS tube M1 and the third MOS tube MC1 can be considered to be relatively far apart, and the second MOS tube M2 and the fourth MOS tube MC2 can be considered to be relatively far apart, and the circuit environment where the first MOS tube M1 and the third MOS tube MC1 are located is not highly matched, and the circuit environment where the second MOS tube M2 and the fourth MOS tube MC2 are located is not highly matched, and a system mismatch problem is prone to occur, thereby affecting the neutralization effect of the third MOS tube MC1 on the gate-drain capacitance Cgd1 of the first MOS tube M1 (that is, the third MOS tube MC1 fails to completely offset the gate-drain capacitance Cgd1 of the first MOS tube M1), and the neutralization effect of the fourth MOS tube MC2 on the gate-drain capacitance Cgd2 of the second MOS tube M2, thereby affecting the gain effect and stability of the RF amplifier circuit 10 when working.

[0027] In view of this, the embodiments of the present application enhance the gain effect and stability of the RF amplifier circuit during operation from the perspective of layout design.

[0028] See also Figure 3 , Figure 3 It is a structural schematic diagram of a radio frequency amplification circuit provided in an embodiment of the present application. Figure 3 The device types, connection methods between multiple MOS tubes and working principles of the RF amplifier circuit 10 shown in FIG. Figure 1 The description of the RF amplifier circuit 10 in the illustrated embodiment will not be repeated here. Figure 1 The radio frequency amplifier circuit 10 shown, Figure 3 Each MOS tube in the RF amplifier circuit 10 shown is divided into n sub-MOS tubes, that is, the first MOS tube M1 includes n first sub-MOS tubes, the second MOS tube M2 includes n second sub-MOS tubes, the third MOS tube MC1 includes n third sub-MOS tubes, and the fourth MOS tube MC2 includes n fourth sub-MOS tubes. The gate of the sub-MOS tube in each MOS tube is connected to serve as the gate of the MOS tube, the source of the sub-MOS tube in each MOS tube is connected to serve as the source of the MOS tube, and the drain of the sub-MOS tube in each MOS tube is connected to serve as the drain of the MOS tube. Wherein, n is a positive integer greater than or equal to 2.

[0029] For example, Figure 3As shown, the first MOS tube M1 includes a first first sub-MOS tube M1-1, a second first sub-MOS tube M1-2, ..., and an nth first sub-MOS tube M1-n. The gate G of the first MOS tube M1 is connected to the gate of any first sub-MOS tube among the n first sub-MOS tubes, the source S of the first MOS tube M1 is connected to the source of any first sub-MOS tube among the n first sub-MOS tubes, and the drain D of the first MOS tube M1 is connected to the drain of any first sub-MOS tube among the n first sub-MOS tubes. It should be noted that

[0030] Furthermore, the RF amplifier circuit 10 can be placed on a chip, and the n first sub-MOS transistors, n second sub-MOS transistors, n third sub-MOS transistors and n fourth sub-MOS transistors in the RF amplifier circuit 10 are arranged according to a multi-dimensional coaxial layout or a multi-dimensional co-centroid layout.

[0031] It can be understood that, according to the multi-dimensional co-axial layout or the multi-dimensional co-centroid layout, each first sub-MOS tube of the first MOS tube M1 is arranged adjacent to each third sub-MOS tube in the third MOS tube MC1, and each second sub-MOS tube of the second MOS tube M2 is arranged adjacent to a fourth sub-MOS tube in the fourth MOS tube MC2. Figure 2 In the circuit layout shown, the axial center spacing or the centroid spacing between the first MOS tube M1 and the third MOS tube MC1 is smaller, and the axial center spacing or the centroid spacing between the second MOS tube M2 and the fourth MOS tube MC2 is smaller. Then, the first MOS tube M1 and the third MOS tube MC1 can be regarded as closer, and the second MOS tube M2 and the fourth MOS tube MC2 can be regarded as closer, which can improve the matching degree of the circuit environment where the first MOS tube M1 and the third MOS tube MC1 are located, and the matching degree of the circuit environment where the second MOS tube M2 and the fourth MOS tube MC2 are located, thereby improving the system matching, and further enhancing the gain effect and stability of the RF amplifier circuit 10 when working.

[0032] Below Figure 3 The multi-dimensional co-axial center layout and the multi-dimensional co-centroid layout are further introduced by taking the example that each MOS tube in the radio frequency amplifier circuit 10 is divided into two sub-MOS tubes.

[0033] See also Figure 4 , Figure 4 Schematic diagram of a radio frequency amplifier circuit provided in an embodiment of the present application. Figure 4As shown, the RF amplifier circuit 10 can be placed on a chip. The first MOS tube M1 in the RF amplifier circuit 10 includes a first first sub-MOS tube M1-1 and a second first sub-MOS tube M1-2, the second MOS tube M2 includes a first second sub-MOS tube M2-1 and a second second sub-MOS tube M2-2, the third MOS tube MC1 includes a first third sub-MOS tube MC1-1 and a second third sub-MOS tube MC1-2, and the fourth MOS tube MC2 includes a first fourth sub-MOS tube MC2-1 and a second fourth sub-MOS tube M2-2.

[0034] Specifically, the first first sub-MOS tube M1-1, the first third sub-MOS tube MC1-1, the first fourth sub-MOS tube MC2-1 and the first second sub-MOS tube M2-1 are arranged in sequence in the first direction, the first first sub-MOS tube M1-1 and the second first sub-MOS tube M1-2 are arranged in sequence in the second direction, the first second sub-MOS tube M2-1 and the second second sub-MOS tube M2-2 are arranged in sequence in the second direction, the first third sub-MOS tube MC1-1 and the second third sub-MOS tube MC1-2 are arranged in sequence in the second direction, and the first fourth sub-MOS tube MC2-1 and the second fourth sub-MOS tube MC2-2 are arranged in sequence in the second direction. Among them, the first direction and the second direction are perpendicular to each other. It should be noted that the embodiment of the present application does not strictly limit the physical spacing L1 between each sub-MOS tube and the adjacent sub-MOS tube in the first direction, and the physical spacing L2 between each sub-MOS tube and the adjacent sub-MOS tube in the second direction. In actual applications, the physical spacing L1 and the physical spacing L2 can be set according to actual needs. The embodiment of the present application does not strictly limit the first direction and the second direction. Figure 4 An example is given in which the first direction is a horizontal direction and the second direction is a vertical direction.

[0035] In terms of specific physical structure, each sub-MOS tube contains multiple gate channels, source channels and drain channels. The channel direction and the number of gate channels (also called gate index) in each sub-MOS tube in the RF amplifier circuit 10 are the same. Taking the first sub-MOS tube M1-1 as an example, the physical structure of the sub-MOS tube is briefly described. Figure 5 , Figure 5 It is a structural schematic diagram of a sub-MOS tube provided in an embodiment of the present application.

[0036] like Figure 5As shown, the first sub-MOS transistor M1-1 includes 8 gate channels g, 5 source channels s and 4 drain channels d. The channel direction is a vertical direction. Each gate channel is connected to serve as the gate G1 of the first sub-MOS transistor M1-1, each source channel is connected to serve as the source S1 of the first sub-MOS transistor M1-1, and each drain channel is connected to serve as the drain D1 of the first sub-MOS transistor M1-1.

[0037] It is understandable that the number of the source channels s and the drain channels d of the first sub-MOS transistor M1-1 is related to the gate channel g. It should be noted that: Figure 5 The outer side of the first sub-MOS transistor M1-1 is a source channel. In practical applications, the outer side may also be a drain channel. Figure 5 The source channel s can be the drain channel d, and the drain channel d can be the source channel s, which is not limited in the present embodiment. In addition, the present embodiment does not strictly limit the number and direction of the channels of the first sub-MOS transistor M1-1. Figure 5 Just an example.

[0038] Combination Figure 4 and Figure 5 It can be seen that the two sub-MOS tubes split from each MOS tube in the RF amplifier circuit 10 are axially symmetrical in the horizontal and vertical directions, and the axis a1 of the first MOS tube M1 and the axis c1 of the third MOS tube MC1 are collinear, and the axis b1 of the second MOS tube M2 and the axis d1 of the fourth MOS tube MC2 are collinear, that is, the multiple sub-MOS tubes in the RF amplifier circuit 10 are arranged in a multi-dimensional coaxial layout. Figure 2 In the circuit layout shown, the axial center spacing between the first MOS tube M1 and the third MOS tube MC1 in the RF amplifier circuit 10 is smaller, and the axial center spacing between the second MOS tube M2 and the fourth MOS tube MC2 is smaller, that is, the first MOS tube M1 and the third MOS tube MC1 can be regarded as closer, and the second MOS tube M2 and the fourth MOS tube MC2 can be regarded as closer. It should be noted that the number of sub-MOS tubes divided into each MOS tube in the RF amplifier circuit 10 is different, and the specific placement rules of the sub-MOS tubes when arranged according to the multi-dimensional coaxial layout are also different, which are not listed here one by one, and are only shown in FIG. Figure 4 As an example.

[0039] See also Figure 6 , Figure 6 It is a schematic diagram of the layout of another radio frequency amplifier circuit provided in an embodiment of the present application. Figure 6 The number and type of the multiple sub-MOS transistors in the RF amplifier circuit 10 are similar to those shown in FIG. Figure 5 The RF amplifying circuit 10 shown is the same and will not be described again here.

[0040] Figure 6In the RF amplification circuit 10 shown, the first first sub-MOS transistor M1-1, the first third sub-MOS transistor MC1-1, the first fourth sub-MOS transistor MC2-1 and the first second sub-MOS transistor M2-1 are arranged sequentially in the first direction, the first first sub-MOS transistor M1-1 and the second third sub-MOS transistor MC1-2 are arranged sequentially in the second direction, the second first sub-MOS transistor M1-2 and the first third sub-MOS transistor MC1-1 are arranged sequentially in the second direction, the first second sub-MOS transistor M2-1 and the second fourth sub-MOS transistor MC2-2 are arranged sequentially in the second direction, and the second second sub-MOS transistor M2-2 and the first fourth sub-MOS transistor MC2-1 are arranged sequentially in the second direction.

[0041] For the description of the first and third directions, please refer to Figure 4 The description of the corresponding parts of the embodiment shown is not repeated here. For the description of the physical spacing L1 between each sub-MOS transistor and the adjacent sub-MOS transistor in the first direction and the physical spacing L2 between each sub-MOS transistor and the adjacent sub-MOS transistor in the second direction in the RF amplifier circuit 10, please refer to Figure 4 The description of the corresponding parts in the embodiment shown is not repeated here. For the specific physical structure of the sub-MOS tube, please refer to Figure 4 The description of the corresponding parts in the illustrated embodiment will not be repeated here.

[0042] Combination Figure 6 and Figure 5 It can be seen that the centroid a2 of the first MOS transistor M1 coincides with the centroid c2 of the third MOS transistor MC1, and the centroid b2 of the second MOS transistor M2 coincides with the centroid d2 of the fourth MOS transistor MC2, that is, the multiple sub-MOS transistors in the RF amplifier circuit 10 are arranged according to a multi-dimensional common centroid layout. Figure 2 In the circuit layout shown, the distance between the centers of mass of the first MOS tube M1 and the third MOS tube MC1 in the RF amplifier circuit 10 is smaller, and the distance between the centers of mass of the second MOS tube M2 and the fourth MOS tube MC2 is smaller, that is, the first MOS tube M1 and the third MOS tube MC1 can be considered to be closer, and the second MOS tube M2 and the fourth MOS tube MC2 can be considered to be closer. It should be noted that the number of sub-MOS tubes divided into each MOS tube in the RF amplifier circuit 10 is different, and the specific placement rules of the sub-MOS tubes when arranged according to the multi-dimensional coaxial layout are also different, which are not listed here one by one, and are only shown in FIG. Figure 6 As an example.

[0043] To sum up, each MOS tube in the RF amplifier circuit 10 provided in the embodiment of the present application is divided into multiple sub-MOS tubes, and can be arranged on the chip according to a multi-dimensional co-axial layout or a multi-dimensional co-centroid layout, thereby improving the system matching and further enhancing the gain effect and stability of the RF amplifier circuit 10 during operation.

[0044] The "multiple" mentioned in the embodiments of this application refers to two or more. Also, unless otherwise specified, the "first" mentioned in the embodiments of this application is only used as a name identifier and is not used to limit the order, timing, priority or importance of multiple objects, such as the first MOS tube, the first sub-MOS tube, etc. The same rule applies to "second", "third" and "fourth", etc.

[0045] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A chip, characterized in that: The chip comprises a radio frequency amplifying circuit (10), the radio frequency amplifying circuit (10) comprising a first MOS tube (M1), a second MOS tube (M2), a third MOS tube (MC1) and a fourth MOS tube (MC2), the first MOS tube (M1) comprising n first sub-MOS tubes, the second MOS tube (M2) comprising n second sub-MOS tubes, the third MOS tube (MC1) comprising n third sub-MOS tubes, the fourth MOS tube (MC2) comprising n fourth sub-MOS tubes, wherein n is a positive integer greater than or equal to 2, wherein: The third MOS transistor (MC1) is used to offset the gate-drain capacitance of the first MOS transistor (M1), and the fourth MOS transistor (MC2) is used to offset the gate-drain capacitance of the second MOS transistor (M2); The n first sub-MOS transistors, the n second sub-MOS transistors, the n third sub-MOS transistors and the n fourth sub-MOS transistors are arranged according to a multi-dimensional co-axial layout or a multi-dimensional co-centroid layout.

2. The chip according to claim 1, characterized in that: The first MOS transistor (M1) includes a first first sub-MOS transistor (M1-1) and a second first sub-MOS transistor (M1-2), the second MOS transistor (M2) includes a first second sub-MOS transistor (M2-1) and a second second sub-MOS transistor (M2-2), the third MOS transistor (MC1) includes a first third sub-MOS transistor (MC1-1) and a second third sub-MOS transistor (MC1-2), and the fourth MOS transistor (MC2) includes a first fourth sub-MOS transistor (MC2-1) and a second fourth sub-MOS transistor (MC2-2), wherein: The first first sub-MOS transistor (M1-1), the first third sub-MOS transistor (MC1-1), the first fourth sub-MOS transistor (MC2-1) and the first second sub-MOS transistor (M2-1) are arranged in sequence in a first direction, the first first sub-MOS transistor (M1-1) and the second first sub-MOS transistor (M1-2) are arranged in sequence in a second direction, the first second sub-MOS transistor (M2-1) and the second second sub-MOS transistor (M2-2) are arranged in sequence in the second direction, the first third sub-MOS transistor (MC1-1) and the second third sub-MOS transistor (MC1-2) are arranged in sequence in the second direction, the first fourth sub-MOS transistor (MC2-1) and the second fourth sub-MOS transistor (MC2-2) are arranged in sequence in the second direction, and the first direction and the second direction are perpendicular to each other.

3. The chip according to claim 1, characterized in that: The first MOS transistor (M1) includes a first first sub-MOS transistor (M1-1) and a second first sub-MOS transistor (M1-2), the second MOS transistor (M2) includes a first second sub-MOS transistor (M2-1) and a second second sub-MOS transistor (M2-2), the third MOS transistor (MC1) includes a first third sub-MOS transistor (MC1-1) and a second third sub-MOS transistor (MC1-2), and the fourth MOS transistor (MC2) includes a first fourth sub-MOS transistor (MC2-1) and a second fourth sub-MOS transistor (MC2-2), wherein: The first first sub-MOS transistor (M1-1), the first third sub-MOS transistor (MC1-1), the first fourth sub-MOS transistor (MC2-1) and the first second sub-MOS transistor (M2-1) are arranged in sequence in a first direction, the first first sub-MOS transistor (M1-1) and the second third sub-MOS transistor (MC1-2) are arranged in sequence in a second direction, the second first sub-MOS transistor (M1-2) and the first third sub-MOS transistor (MC1-1) are arranged in sequence in the second direction, the first second sub-MOS transistor (M2-1) and the second fourth sub-MOS transistor (MC2-2) are arranged in sequence in the second direction, and the second second sub-MOS transistor (M2-2) and the first fourth sub-MOS transistor (MC2-1) are arranged in sequence in the second direction, and the first direction and the second direction are perpendicular to each other.

4. The chip according to any one of claims 1 to 3, characterized in that: The positive input end of the radio frequency amplifying circuit (10) is connected to the gate of the first MOS transistor (M1) and the drain of the third MOS transistor (MC1); the negative input end of the radio frequency amplifying circuit (10) is connected to the gate of the second MOS transistor (M2) and the drain of the fourth MOS transistor (MC2); the source of the first MOS transistor (M1) and the source of the second MOS transistor (M2) are connected to a reference ground; the drain of the first MOS transistor (M1) is connected to the gate of the fourth MOS transistor (MC2), the drain of the fourth MOS transistor (MC2) and the positive output end of the radio frequency amplifying circuit (10); and the drain of the second MOS transistor (M2) is connected to the gate of the third MOS transistor (MC1), the drain of the third MOS transistor (MC1) and the negative output end of the radio frequency amplifying circuit (10).

5. The chip according to claim 4, characterized in that: The gate of the first MOS tube (M1) is connected to the gate of any first sub-MOS tube among the n first sub-MOS tubes, the source of the first MOS tube (M1) is connected to the source of any first sub-MOS tube among the n first sub-MOS tubes, and the drain of the first MOS tube (M1) is connected to the drain of any first sub-MOS tube among the n first sub-MOS tubes; The gate of the second MOS tube (M2) is connected to the gate of any second sub-MOS tube among the n second sub-MOS tubes, the source of the second MOS tube (M2) is connected to the source of any second sub-MOS tube among the n second sub-MOS tubes, and the drain of the second MOS tube (M2) is connected to the drain of any second sub-MOS tube among the n second sub-MOS tubes; The gate electrode of the third MOS tube (MC1) is connected to the gate electrode of any third sub-MOS tube among the n third sub-MOS tubes, the source electrode of the third MOS tube (MC1) is connected to the source electrode of any third sub-MOS tube among the n third sub-MOS tubes, and the drain electrode of the third MOS tube (MC1) is connected to the drain electrode of any third sub-MOS tube among the n third sub-MOS tubes; The gate of the fourth MOS tube (MC2) is connected to the gate of any fourth sub-MOS tube among the n fourth sub-MOS tubes, the source of the fourth MOS tube (MC2) is connected to the source of any fourth sub-MOS tube among the n fourth sub-MOS tubes, and the drain of the fourth MOS tube (MC2) is connected to the drain of any fourth sub-MOS tube among the n fourth sub-MOS tubes.

6. The chip according to claim 5, characterized in that: The channel directions and the number of gate channels of the n first sub-MOS transistors, the n second sub-MOS transistors, the n third sub-MOS transistors and the n fourth sub-MOS transistors are the same.

7. A radio frequency amplifier, characterized in that: The radio frequency amplifier comprises the chip according to any one of claims 1-6.

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