Semiconductor device structure

Abstract

Embodiments of the present disclosure provide a semiconductor device structure. The structure includes a source / drain region disposed on a substrate, a first interlayer dielectric layer surrounding a first portion of the source / drain region, a second interlayer dielectric layer different from the first interlayer dielectric layer surrounding a second portion of the source / drain region, a silicide layer disposed on the source / drain region, and a conductive contact disposed on the source / drain region. The conductive contact is disposed in the second interlayer dielectric layer.

Description

Technical Field

[0001] The utility model relates to a semiconductor technology, in particular to a semiconductor device structure and a forming method thereof. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in integrated circuit materials and design have produced successive generations of integrated circuits, each with smaller and more complex circuits than the previous one. In the course of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be formed using a manufacturing process) has decreased. This process of miniaturization generally provides benefits by increasing production efficiency and reducing associated costs. This miniaturization has also increased the complexity of processing and manufacturing integrated circuits.

[0003] Therefore, there is a need for improvements in processing and manufacturing integrated circuits. Utility Model Content

[0004] The present disclosure aims to provide a semiconductor device structure to solve at least one of the above problems.

[0005] In some embodiments, a semiconductor device structure includes: a source / drain region disposed on a substrate, a first interlayer dielectric layer surrounding a first portion of the source / drain region, a second interlayer dielectric layer different from the first interlayer dielectric layer surrounding a second portion of the source / drain region, a silicide layer disposed on the source / drain region, and a conductive contact disposed on the source / drain region. The conductive contact is disposed in the second interlayer dielectric layer.

[0006] According to one embodiment of the present disclosure, a size of the silicide layer in one direction is larger than a size of the conductive contact in the same direction.

[0007] According to one embodiment of the present disclosure, the first interlayer dielectric layer has an upper surface that is lower than the height of a portion of the source / drain region having a maximum dimension in the direction.

[0008] According to one embodiment of the present disclosure, the semiconductor device structure further includes one or more semiconductor layers in contact with the source / drain region.

[0009] In some embodiments, a semiconductor device structure is provided, comprising: a source / drain region disposed on a substrate, a first contact etch stop layer in contact with a bottom of the source / drain region, a first interlayer dielectric layer in contact with the first contact etch stop layer, a silicide layer in contact with a top of the source / drain region, a second contact etch stop layer different from the first contact etch stop layer and in contact with the first contact etch stop layer, the silicide layer and the first interlayer dielectric layer, and a second interlayer dielectric layer in contact with the second contact etch stop layer.

[0010] According to one embodiment of the present disclosure, a conductive contact is further included, which is disposed in the second interlayer dielectric layer.

[0011] According to one embodiment of the present disclosure, the second contact etch stop layer is disposed between the first interlayer dielectric layer and the second interlayer dielectric layer.

[0012] According to one embodiment of the present disclosure, the first contact etch stop layer is disposed between the first interlayer dielectric layer and the source / drain region.

[0013] According to one embodiment of the present disclosure, a size of the silicide layer in one direction is larger than a size of the conductive contact in the same direction.

[0014] According to one embodiment of the present disclosure, the first interlayer dielectric layer has an upper surface that is lower than the height of a portion of the source / drain region having a maximum dimension in the direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1-Figure 6 Schematic perspective views showing different stages of fabricating a semiconductor device structure according to some embodiments.

[0016] Figures 7A-10A According to some embodiments, Figure 6 AA line is a schematic cross-sectional view of different stages of fabricating a semiconductor device structure.

[0017] Figure 7B-Figure 10B According to some embodiments, Figure 6 BB line is a cross-sectional schematic diagram of different stages of fabricating a semiconductor device structure.

[0018] Figure 7C-Figure 10C According to some embodiments, Figure 6 Schematic cross-sectional view of the CC line at different stages of fabricating a semiconductor device structure.

[0019] Figures 11A-12A Schematic perspective views showing different stages of fabricating a semiconductor device structure according to some embodiments.

[0020] Figure 11B-Figure 12B According to some embodiments, Figure 6 Schematic cross-sectional view of the CC line at different stages of fabricating a semiconductor device structure.

[0021] Figure 13-Figure 16 Schematic perspective views showing different stages of fabricating a semiconductor device structure according to some embodiments.

[0022] Figures 17A-19A According to some embodiments, Figure 6 AA line is a schematic cross-sectional view of different stages of fabricating a semiconductor device structure.

[0023] Figure 17B-Figure 19B According to some embodiments, Figure 6 BB line is a cross-sectional schematic diagram of different stages of fabricating a semiconductor device structure.

[0024] Figure 17C-Figure 19C According to some embodiments, Figure 6 Schematic cross-sectional view of the CC line at different stages of fabricating a semiconductor device structure.

[0025] Figure 20A-Figure 23A According to some embodiments, Figure 6 AA line is a schematic cross-sectional view of different stages of fabricating a semiconductor device structure.

[0026] Figure 20B-Figure 23B According to some embodiments, Figure 6 BB line is a cross-sectional schematic diagram of different stages of fabricating a semiconductor device structure.

[0027] Figure 24A-Figure 25A According to some embodiments, Figure 6 AA line is a schematic cross-sectional view of different stages of fabricating a semiconductor device structure.

[0028] Figure 24B-Figure 25B According to some embodiments, Figure 6 BB line is a cross-sectional schematic diagram of different stages of fabricating a semiconductor device structure.

[0029] Figure 24C-Figure 25C According to some embodiments, Figure 6 Schematic cross-sectional view of the CC line at different stages of fabricating a semiconductor device structure.

[0030] Fig.26 A perspective schematic diagram illustrates one of the different stages in the fabrication of a semiconductor device structure according to an alternative embodiment.

[0031] Figure 27A-27B A schematic cross-sectional view illustrating one of the different stages in fabricating a semiconductor device structure according to an alternative embodiment.

[0032] The reference numerals are as follows:

[0033] 100:Semiconductor device structure

[0034] 101: Base

[0035] 106: first semiconductor layer

[0036] 108: Second semiconductor layer

[0037] 112: Fin structure

[0038] 114: Groove

[0039] 116: Well Area Department

[0040] 118: Insulation material

[0041] 120: Isolation Area

[0042] 130: Sacrificial gate structure

[0043] 132: Sacrificial gate dielectric layer

[0044] 134: Sacrificial gate electrode layer

[0045] 136: mask layer

[0046] 138: Gate spacer

[0047] 144: Dielectric spacer layer

[0048] 146, 146n, 146p: Source / drain (S / D) region

[0049] 162,184: Contact Etch Stop Layer (CESL)

[0050] 163: first interlayer dielectric (ILD) layer

[0051] 164: Sacrificial dielectric layer

[0052] 170: Gate dielectric layer

[0053] 171: Covering layer

[0054] 172: Gate electrode layer

[0055] 174: Gate structure

[0056] 180: Silicide layer

[0057] 186: Second interlayer dielectric (ILD) layer

[0058] 188: Conductive contact

[0059] 202:Hard mask

[0060] 204,208: Opening

[0061] 206,210: Dielectric materials DETAILED DESCRIPTION

[0062] The following disclosure provides many different embodiments or examples to implement different characteristic components of the present invention. The following disclosure is a specific example describing each component and its arrangement in order to simplify the present disclosure. Of course, these are only examples and are not used to define the present invention. For example, if the following disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which an additional characteristic component can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the present disclosure will repeat numbers and / or text in each different example. Repetition is for the purpose of simplification and clarification, rather than listing and specifying the relationship between the various different embodiments and / or configurations discussed.

[0063] Spatially related terms, such as "below", "under", "down", "above", "above", "top", "upper", etc., are used here to easily express the relationship between an element or feature in the drawings shown in this specification and another element or feature. In addition to covering the orientations shown in the drawings, these spatially related terms also cover different orientations of the device during use or operation. For example, if the device in the figure is turned over, what is described as being "below" or "below" other elements or features will be oriented as being "above" other elements or features. Therefore, the exemplary term "below" can cover both above and below orientations. This device can have different orientations (rotated 90 degrees or other orientations) and the spatially related symbols used here are also interpreted accordingly.

[0064] The embodiments of the present disclosure provide a semiconductor device structure with a power network moved from the front side to the back side, so that the routing resources of the back side power supply and the front side signal are relaxed.

[0065] Although the embodiments of the present disclosure are described for nanostructure channel FETs (field effect transistors), certain types of embodiments of the present disclosure can be used for other processes and / or other devices, such as planar FETs, fin FETs, horizontal gate all around (Horizontal Gate All Around, HGAA) FETs, vertical gate all around (Vertical Gate All Around, VGAA) FETs, and other suitable devices. It is easy for a person skilled in the art to understand that other modifications can be considered within the scope of the present disclosure. In the case of a gate all around (GAA) transistor structure, the gate all around (GAA) transistor structure can be patterned by any suitable method. For example, these structures can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the formation of patterns (e.g., spacing) that are smaller than those obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern a gate-all-around (GAA) structure.

[0066] Figure 1-27B FIG. 1 shows an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It can be understood that Figure 1-27B Additional steps may be provided before, during, and after the processes shown, and some of the steps described below may be replaced or removed for additional embodiments of the above methods. The order of the steps / processes is not limited and may be interchanged.

[0067] Figure 1-Figure 6 Schematic diagrams of different stages of manufacturing a semiconductor device structure 100 according to some embodiments are shown. Figure 1As shown, the semiconductor device structure 100 includes a stack of semiconductor layers 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for strengthening. In one embodiment, the insulating layer is an oxygen-containing layer.

[0068] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, phosphorus for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).

[0069] The stack of semiconductor layers 104 includes alternating semiconductor layers made of different materials to help form a nanostructure channel in a multi-gate device (e.g., a nanostructure channel FET). In some embodiments, the stack of semiconductor layers 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the stack of semiconductor layers 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 can be made of Si, and the second semiconductor layer 108 can be made of SiGe. In some examples, the first semiconductor layer 106 can be made of SiGe, and the second semiconductor layer 108 can be made of Si. Alternatively, in some embodiments, any one of the first and second semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP or any combination thereof.

[0070] The first and second semiconductor layers 106 and 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the semiconductor layer 104 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0071] The first semiconductor layer 106 or a part thereof can form a nanostructure channel of the semiconductor device structure 100 in a subsequent manufacturing stage. The term nanostructure is used here to refer to any material portion having nanometer or micrometer dimensions and having an elongated shape, regardless of the cross-sectional shape of the material portion. Therefore, this term refers to elongated material portions with circular and substantially circular cross-sections, and columnar or strip-shaped material portions, including, for example, cylindrical or substantially rectangular cross-sections. The nanostructure channel of the semiconductor device structure 100 can be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructure transistor. The nanostructure transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel. The use of the first semiconductor layer 106 to define a channel or multiple \ channels of the semiconductor device structure 100 will be further described below.

[0072] Each first semiconductor layer 106 may have a thickness in a range of about 5 nm to 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the first semiconductor layer 106. In some embodiments, the thickness of each second semiconductor layer 108 is about 2 nm to 50 nm. Figure 1 As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, which is for illustrative purposes and is not intended to limit the specific contents of the claims. It is understood that any number of first and second semiconductor layers 106, 108 can be formed in the stack of semiconductor layers 104, and the number of layers depends on the number of channels predetermined by the semiconductor device structure 100.

[0073] exist Figure 2In the embodiment of the present invention, the fin structure 112 is formed by a stack of semiconductor layers 104. Each fin structure 112 has an upper portion including first and second semiconductor layers 106, 108 and a well portion 116 formed by the substrate 101. The fin structure 112 can be made by patterning a hard mask layer (not shown) formed on the stack of semiconductor layers 104 using multiple patterning operations including photolithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask component including the photoresist layer. In some embodiments, an electron beam (e-beam) photolithography process may be used to pattern the photoresist layer to form a mask component. The etching process forms trenches 114 in the unprotected areas, through the hard mask layer, through the stack of semiconductor layers 104, and into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend along the X direction. Etching the trenches 114 may be performed using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0074] exist Figure 3 In the embodiment of the present invention, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is buried in the insulating material 118. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and / or an etch-back method, is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-K dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD).

[0075] exist Figure 4In the embodiment of the present invention, the insulating material 118 is recessed to form an isolation region 120. The recessed insulating material 118 exposes a portion of the fin structure 112, such as a stack of semiconductor layers 104. The recessed insulating material 118 reveals the trench 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The upper surface of the insulating material 118 can be flush with the surface of the second semiconductor layer 108 or lower than the surface of the second semiconductor layer 108 that contacts the well region 116 formed from the substrate 101.

[0076] exist Figure 5 , one or more sacrificial gate structures 130 (only one is shown) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing blanket layers constituting the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these film layers to form the sacrificial gate structure 130. Then, a gate spacer 138 is formed on the sidewall of the sacrificial gate structure 130. For example, the gate spacer 138 may be formed by conformally depositing one or more film layers for the gate spacer 138 and anisotropically etching the one or more film layers. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be disposed along the X direction.

[0077] The sacrificial gate dielectric layer 132 may include one or more dielectric material layers, such as materials such as silicon oxide. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The mask layer 136 may include more than one film layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN and / or combinations thereof.

[0078] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100 .

[0079] exist Figure 6In the embodiment, the portion of the fin structure 112 not covered by the sacrificial gate structure 130 and the gate spacer 138 is recessed to a height above, at, or below the upper surface of the isolation region 120. The recessed portion of the fin structure 112 can be completed by an etching process, which can be an isotropic or anisotropic etching process, and the etching process can be selective to one or more crystal planes of the substrate 101. The etching process can be a dry etch (e.g., RIE, NBE, or similar etching) or a wet etch (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant).

[0080] Fig. 7A , Figure 7B and Figure 7C Shown along Figure 6 Schematic cross-sectional view of the semiconductor device structure 100 taken along line AA, line BB and line CC.

[0081] Fig. 8A , Figure 8B and Figure 8C FIG. 1 is a cross-sectional view of one of the different stages of manufacturing the semiconductor device structure 100 along the AA line, the BB line, and the CC line of FIG. 6 according to some embodiments. Fig. 8A As shown, the edge portion of each second semiconductor layer 108 in the stack of semiconductor layers 104 is removed laterally along the X direction. The removal of the edge portion of the second semiconductor layer 108 forms a cavity. In some embodiments, the removed portion of the second semiconductor layer 108 is through a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP) or potassium hydroxide (KOH) solution.

[0082] After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 may be made of a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacer 144 may be formed by first forming a compliant dielectric layer using a compliant deposition process (e.g., ALD), and then removing the portion of the compliant dielectric layer other than the dielectric spacer 144 by anisotropic etching. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 covers between the dielectric spacer layers 144 along the X direction.

[0083] Fig. 9A , Fig. 9B and Fig. 9C The following diagrams are respectively shown according to some embodiments. Figure 6 AA line, BB line and CC line of the semiconductor device structure 100 are cross-sectional views of different stages of manufacturing the semiconductor device structure 100. Fig. 9A and Fig. 9C As shown, source / drain (S / D) regions 146n, 146p are formed by the well portion 116. In some embodiments, the source / drain (S / D) region 146p can be grown vertically and horizontally to form facets, which can correspond to the crystal planes of the material used for the well portion 116. In the present disclosure, source region and drain region can be used interchangeably, and their structures are substantially the same. Furthermore, the source / drain region can refer to the source or drain, alone or together depending on the context. For n-channel field effect transistors, the source / drain (S / D) region 146n can be made of one or more layers of Si, SiP, SiC and SiCP, and for p-channel field effect transistors, the source / drain (S / D) region 146p can be made of one or more layers of Si, SiGe, Ge. For p-channel field effect transistors, p-type dopants (e.g., boron (B)) can also be included in the source / drain (S / D) region 146p. The source / drain (S / D) regions 146n, 146p may be formed by an epitaxial growth method using CVD, ALD, or MBE.

[0084] Fig. 10A , Fig. 10B and Fig. 10C The following diagrams are respectively shown according to some embodiments. Figure 6 A cross-sectional view of one of the different stages of manufacturing a semiconductor device structure 100 along the AA line, the BB line, and the CC line. Fig. 10A , Fig. 10B and Fig. 10CIn the process, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the source / drain (S / D) regions 146n, 146p. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbide nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, the like, or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a first interlayer dielectric (ILD) layer 163 is formed on the CESL 162 above the semiconductor device structure 100. The material of the first interlayer dielectric (ILD) layer 163 may be a compound including Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials, such as polymers, may also be used for the first interlayer dielectric (ILD) layer 163. The first interlayer dielectric (ILD) layer 163 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the first interlayer dielectric (ILD) layer 163, the semiconductor device structure 100 may be subjected to a thermal process to cure the first interlayer dielectric (ILD) layer 163. The curing temperature may be approximately 550 degrees Celsius to 700 degrees Celsius.

[0085] The first interlayer dielectric (ILD) layer 163 can be made by first depositing a dielectric material to bury the source / drain (S / D) regions 146n, 146p, and then exposing a portion of the source / drain (S / D) regions 146n, 146p through an etch-back process. The thickness of the first interlayer dielectric (ILD) layer 163 can be approximately in the range of 25nm to 75nm, for example, approximately 50nm. In some embodiments, the upper surface of the first interlayer dielectric (ILD) layer 163 is located at the height of the portion of the source / drain (S / D) region 146n, 146p having the largest size along the Y direction. In other words, the height at which the upper surface of the first interlayer dielectric (ILD) layer 163 is located is the widest point of the source / drain (S / D) region 146n, 146p along the Y direction.

[0086] Next, a sacrificial dielectric layer 164 is deposited on the first interlayer dielectric (ILD) layer 163. The sacrificial dielectric layer 164 may include the same material as the first interlayer dielectric (ILD) layer 163 and be formed by the same process, except that the curing temperature is substantially lower than the curing temperature of the first interlayer dielectric (ILD) layer 163. In some embodiments, the curing temperature of the sacrificial dielectric layer 164 is approximately in the range of 350 degrees Celsius to 500 degrees Celsius. At different curing temperatures, the first interlayer dielectric (ILD) layer 163 is substantially denser than the sacrificial dielectric layer 164. In the etching process, the etching rate of the sacrificial dielectric layer 164 is substantially faster than the etching rate of the first interlayer dielectric (ILD) layer 163. The first interlayer dielectric (ILD) layer 163 can serve as an etch stop layer in the etching process to remove the sacrificial dielectric layer 164.

[0087] After forming the sacrificial dielectric layer 164, the semiconductor device structure 100 is planarized (eg, by CMP) until the sacrificial gate electrode layer 134 is exposed. Fig. 10A and Fig. 10B shown.

[0088] Figures 11A-12A 11B-12B show schematic diagrams of different stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 6 Schematic cross-sectional view of different stages of manufacturing a semiconductor device structure 100 through a CC line. Fig.11A and Fig. 11B As shown, a hard mask 202 is formed on the sacrificial dielectric layer 164. The hard mask 202 may include a dielectric material, such as SiN, SiCN, SiOCN, SiOC or other suitable dielectric materials. The hard mask 202 may be used to form one or more openings 204 in the sacrificial dielectric layer 164, the first interlayer dielectric (ILD) layer 163, the contact etch stop layer (CESL) 162 and the isolation region 120. The openings 204 may be formed between adjacent source / drain (S / D) regions 146n, adjacent source / drain (S / D) regions 146p, or between adjacent source / drain (S / D) regions 146n, 146p. In the channel region, the openings 204 are formed in the sacrificial gate electrode layer 134, the sacrificial gate dielectric layer 132 and the isolation region 120. The formed openings 204 may separate the sacrificial gate electrode layer 134 into a plurality of portions. The above process may be referred to as a cut poly gate (CPG) process. The opening 204 may be formed by one or more etching processes. In some embodiments, a portion of the substrate 101 is exposed in the opening 204 .

[0089] like Fig. 12A and Fig. 12BAs shown, a dielectric material 206 is formed in each opening 204. The dielectric material 206 may include any suitable dielectric material, such as SiN. In some embodiments, the dielectric material 206 includes the same material as the hard mask 202. The dielectric material 206 may also be formed on the hard mask 202. The dielectric material 206 electrically isolates the multiple portions of the sacrificial gate electrode layer 134. Fig.17A and Fig. 17B After the gate replacement process described in the above, the dielectric material 206 electrically isolates the gate electrode layer 172 ( Fig.17A and Fig. 17B ).

[0090] Figure 13-Figure 16 Schematic diagrams of different stages of manufacturing a semiconductor device structure 100 according to some embodiments are shown. Fig.13 As shown, an opening 208 is formed in the hard mask 202 to expose the sacrificial gate electrode layer 134. In some embodiments, the opening 208 also exposes the gate spacer 138 and a portion of the dielectric material 206. A patterned photoresist (not shown) (e.g., a three-layer photoresist) may be formed on the hard mask 202 to form the opening 208.

[0091] like Fig.14 As shown, the sacrificial gate electrode layer 134 exposed in the opening 208 is removed. The first semiconductor layer 106 and the second semiconductor layer 108 are also removed. The sacrificial gate electrode layer 134, the first semiconductor layer 106 and the second semiconductor layer 108 can be removed by one or more etching processes. The one or more etching processes can be selective etching processes. In this way, the gate spacer 138, the hard mask 202 and the dielectric material 206 are not greatly affected. Furthermore, the one or more etching processes can include at least one anisotropic etching process, and the first semiconductor layer 106 portion located below the gate spacer 138 and between the dielectric spacer layer 144 is not removed.

[0092] like Fig.15 As shown, a dielectric material 210 is formed in the opening 208. The dielectric material 210 may include any suitable dielectric material, such as SiN. In some embodiments, the dielectric material 210 includes the same material as the dielectric material 206. The process of forming the dielectric material 206 and the dielectric material 210 may be selective. In some embodiments, the etching rate of the sacrificial dielectric layer 164 may be substantially faster than the etching rate of the dielectric materials 206 and 210.

[0093] like Fig.16As shown, the hard mask 202 is removed. The hard mask 202 may be removed by any suitable process. In some embodiments, a planarization process (eg, a CMP process) is performed to remove the hard mask 202.

[0094] Figures 17A-19A According to some embodiments, Figure 6 AA line is a schematic cross-sectional view of different stages of manufacturing the semiconductor device structure 100. Figure 17B-Figure 19B According to some embodiments, Figure 6 BB line is a schematic cross-sectional view of different stages of manufacturing a semiconductor device structure 100. Figure 17C-Figure 19C According to some embodiments, Figure 6 Schematic cross-sectional view of different stages of manufacturing a semiconductor device structure 100 through a CC line. Fig.17A and Fig. 17B As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening between the gate spacers 138 and between the first semiconductor layer 106. The sacrificial dielectric layer 164 protects the source / drain (S / D) region 146 during the removal. The dielectric materials 206, 210 are not substantially affected by the removal process. The sacrificial gate structure 130 can be removed by plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof, and then the sacrificial gate dielectric layer 132 is removed, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, may be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacers 138 , the dielectric materials 206 , 210 , the sacrificial dielectric layer 164 , and the contact etch stop layer (CESL) 162 .

[0095] Portions of the second semiconductor layer 108 may be removed using a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemical used in the selective wet etching process may remove SiGe without substantially affecting Si, the dielectric material of the gate spacer 138, the dielectric materials 206, 210, the sacrificial dielectric layer 164, and the dielectric spacer layer 144. In one embodiment, the second semiconductor layer 108 may be removed using a wet etchant (e.g., but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4)), a dry etchant (e.g., a fluorine-based (e.g., F2) or a chlorine-based gas (e.g., Cl2)), or any suitable isotropic etchant.

[0096] After forming the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 includes one or more dielectric material layers, such as silicon oxide, silicon nitride or high-K dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-K dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-K dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed by CVD, ALD or any suitable deposition technique. The gate electrode layer 172 may include one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or any combination thereof. The gate electrode layer 172 may be formed by CVD, ALD, electroplating or other suitable deposition techniques. The gate electrode layer 172 may also be deposited on the upper surface of the sacrificial dielectric layer 164. The gate dielectric layer 170 and the gate electrode layer 172 formed on the sacrificial dielectric layer 164 may then be removed by using CMP until the upper surface of the sacrificial dielectric layer 164 is exposed.

[0097] Next, if 18A to 18C As shown, a capping layer 171 is selectively formed on the gate electrode layer 172 and the dielectric materials 206 and 210. In some embodiments, the dielectric materials 206 and 210 are made of nitride, and the sacrificial dielectric layer 164 is made of oxide. In this way, the capping layer 171 is selectively formed on the metal or semiconductor material of the gate layer 172 and the nitride material of the dielectric materials 206 and 210, but is not substantially formed on the oxide material of the sacrificial dielectric layer 164. In some embodiments, the gate dielectric layer 170 and the gate spacer 138 are also made of nitride material, and the capping layer 171 is formed on the gate dielectric layer 170 and the gate spacer 138, as shown in FIG. Fig.18AAs shown. In some embodiments, a small amount of capping layer 171 is initially formed on the sacrificial dielectric layer 164, and then the small amount of capping layer 171 formed on the sacrificial dielectric layer 164 is removed by a cleaning process (e.g., a wet cleaning process using an HF solution). For example, during the formation of the capping layer 171, a thicker capping layer 171 is formed on the gate electrode layer 172, the gate dielectric layer 170, the gate spacer 138, and the dielectric materials 206, 210, and a thinner capping layer 171 is formed on the sacrificial dielectric layer 164. Then, a cleaning process is performed to remove the capping layer 171 formed on the sacrificial dielectric layer 164. The thickness of the capping layer 171 formed on the gate electrode layer 172, the gate dielectric layer 170, the gate spacer 138, and the dielectric materials 206, 210 is reduced by the cleaning process. In some embodiments, the cap layer 171 finally formed on the gate layer 172, the gate dielectric layer 170, the gate spacer 138 and the dielectric materials 206, 210 has a range of about 2nm to 4nm, for example, about 3nm. In some embodiments, the cap layer 171 is a metal layer, such as a titanium layer. The cap layer 171 can be formed by any suitable process, such as a CVD process using TiCl4 as a precursor. TiCl4 as a precursor may have a greater affinity for metal and nitride surfaces than oxide surfaces.

[0098] like FIG. 19A to FIG. 19C As shown, the sacrificial dielectric layer 164 and a portion of the contact etch stop layer (CESL) 162 are removed. The cap layer 171 serves as a mask layer to protect the gate electrode layer 172, the gate dielectric layer 170, the gate spacer 138, and the dielectric materials 206, 210. With the cap layer 171, there is no need to use a pattern mask layer when removing the sacrificial dielectric layer 164 and a portion of the contact etch stop layer (CESL) 162. As described above, the first interlayer dielectric (ILD) layer 163 is substantially denser than the sacrificial dielectric layer 164, and the etching rate of the sacrificial dielectric layer 164 is substantially faster than the etching rate of the first interlayer dielectric (ILD) layer 163. As a result, when removing the sacrificial dielectric layer 164, the first interlayer dielectric (ILD) layer 163 can serve as an etching stop layer. The sacrificial dielectric layer 164 and a portion of the contact etch stop layer (CESL) 162 may be removed by one or more etching processes, such as dry etching, wet etching, or a combination thereof. The one or more etching processes will not have a substantial effect on the cap layer 171. Fig.19CAs shown, the sacrificial dielectric layer 164 and a portion of the contact etch stop layer (CESL) 162 are removed to expose the top portions of the source / drain (S / D) regions 146n, 146p. As described above, in some embodiments, the etching rate of the sacrificial dielectric layer 164 is substantially faster than the etching rate of the dielectric materials 206, 210. Therefore, during the removal of the sacrificial dielectric layer 164 and a portion of the contact etch stop layer (CESL) 162, the capping layer 171 may or may not be used. In other words, the sacrificial dielectric layer 164 and the capping layer 171 may be used alone or together to protect the dielectric materials 206, 210.

[0099] Figure 20A-Figure 23A According to some embodiments, Figure 6 AA line is a schematic cross-sectional view of different stages of manufacturing the semiconductor device structure 100. Figure 20B-Figure 23B According to some embodiments, Figure 6 BB line is a schematic cross-sectional view of different stages of manufacturing a semiconductor device structure 100. FIG. 20A to FIG. 23A and FIG. 20B to FIG. 23B Shown in FIG. 19A to FIG. 19C The semiconductor device structure 100 with dielectric materials 206, 210 is shown at a manufacturing stage. Fig. 20A and Fig. 20B As shown, the capping layer 171 is selectively formed on the gate electrode layer 172, the gate spacer 138 and the dielectric materials 206 and 210. For clarity, FIG. 20A to FIG. 24A and FIG. 20B to FIG. 24B The gate dielectric layer 170 is omitted. Fig. 10C As described above, in some embodiments, the upper surface of the first interlayer dielectric (ILD) layer 163 is located at the height of the portion of the source / drain (S / D) region 146n, 146p having the largest dimension along the Y direction. In some embodiments, a portion of the first interlayer dielectric (ILD) layer 163 may be removed during the removal of the sacrificial dielectric layer 164 and a portion of the contact etch stop layer (CESL) 162. In this way, Fig. 20B As shown, the source / drain (S / D) regions 146n, 146p having the largest size along the Y direction may be exposed. The substrate 101 may also include an insulating material 118. For clarity, Fig. 20B , Fig. 21B , Fig. 22B , Fig. 23B and Fig.27B Not shown in the figure.

[0100] Next, if Fig.21A and Fig. 21BAs shown, a silicide layer 180 is formed on the source / drain (S / D) regions 146n, 146p. The silicide layer 180 can be formed by any suitable method. In some embodiments, a metal layer (e.g., a titanium layer) is first deposited on the cap layer 171, the gate spacer 138, the source / drain (S / D) regions 146n, 146p, and the first interlayer dielectric (ILD) layer 163. The portion of the metal layer in contact with the source / drain (S / D) regions 146n, 146p reacts during the deposition of the metal layer or during a thermal process after the deposition of the metal layer to form the silicide layer 180. Then, a selective etching process is performed to remove the metal layer formed on the cap layer 171, the gate spacer 138, and the first interlayer dielectric (ILD) layer 163. The selective etching process does not substantially affect the silicide layer 180, the gate spacer 138, and the first interlayer dielectric (ILD) layer 163. In some embodiments, during the selective etching, a portion of the capping layer 171 may be removed. In some embodiments, the silicide layer 180 may be formed by other suitable processes.

[0101] like Fig. 20B As described above, the source / drain (S / D) regions 146n, 146p are exposed with a portion having a maximum size along the Y direction. Therefore, the silicide layer 180 is formed on the exposed portion of the source / drain (S / D) regions 146n, 146p. Fig. 21B As shown, each silicide layer 180 covers the top portion of the source / drain (S / D) regions 146n, 146p. In some embodiments, the entire upper surface of each source / drain (S / D) region 146n, 146p is covered by the silicide layer 180.

[0102] Next, if Fig.22A and Fig. 22BAs shown, another contact etch stop layer (CESL) 184 is formed on the silicide layer 180 and the first interlayer dielectric (ILD) layer 163 and a second interlayer dielectric (ILD) layer 186. The contact etch stop layer (CESL) 184 may include the same material as the contact etch stop layer (CESL) 162, and the second interlayer dielectric (ILD) layer 186 may include the same material as the sacrificial dielectric layer 164. In some embodiments, the second interlayer dielectric (ILD) layer 186 is cured at a temperature ranging from about 350 degrees Celsius to 500 degrees Celsius. If the curing temperature of the second interlayer dielectric (ILD) layer 186 is greater than about 500 degrees Celsius, the material of the gate electrode layer 172 may be negatively affected by the high temperature. Thus, in some embodiments, the semiconductor device structure 100 includes a first interlayer dielectric (ILD) layer 163, a contact etch stop layer (CESL) 184 disposed on the first interlayer dielectric (ILD) layer 163, and a second interlayer dielectric (ILD) layer 186 disposed on the contact etch stop layer (CESL) 184 and different from the first interlayer dielectric (ILD) layer 163. The first and second interlayer dielectric (ILD) layers 163 and 186 may include the same material but have different densities because the first and second interlayer dielectric (ILD) layers 163 and 186 are cured at different temperatures. Fig. 22B As shown, the first interlayer dielectric (ILD) layer 163 surrounds the bottom portion of the source / drain (S / D) regions 146n, 146p, and the second interlayer dielectric (ILD) layer 186 surrounds the top portion of the source / drain (S / D) regions 146n, 146p. In some embodiments, after forming the second interlayer dielectric (ILD) layer 186, a planarization process (e.g., a CMP process) is performed to expose the gate electrode layer 172 and the dielectric materials 206, 210. The cap layer 171 can be removed by this planarization process.

[0103] Next, if Fig.23A and Fig. 23BAs shown, a conductive contact 188 is formed in the second interlayer dielectric (ILD) layer 186 and the contact etch stop layer (CESL) 184. The conductive contact 188 may include a conductive material, such as TiN, W, Ru, Mo, Co, Cu, or other suitable conductive materials. In some embodiments, if the conductive contact 188 includes a material that is easily diffused, a selective barrier layer (not shown) is used to prevent the diffusion of the conductive contact 188. An opening is formed in the second interlayer dielectric (ILD) layer 186 and the contact etch stop layer (CESL) 184 using a patterned mask (not shown). When forming the opening, the patterned mask protects the material of the dielectric material 206, 210. Then, the conductive contact 188 is deposited in the opening. A planarization process (e.g., a CMP process) may be performed to remove the portion of the conductive contact 188 formed on the dielectric material 206, 210, the second interlayer dielectric (ILD) layer 186, and the gate electrode layer 172. Thus, in some embodiments, the upper surface of the conductive contact 188 is substantially coplanar with the upper surfaces of the dielectric materials 206, 210 and the upper surface of the second interlayer dielectric (ILD) layer 186, such as Fig.23A and Fig. 23B shown.

[0104] like FIG. 20A to FIG. 23B As described above, the silicide layer 180 is formed before forming the opening for the conductive contact 216, and is formed on a larger portion of the source / drain (S / D) regions 146n, 146p than the conductive contact 216. In other words, the dimension of each silicide layer 180 extending along the Y direction is substantially larger than the dimension of the corresponding conductive contact 188 extending along the Y direction. The larger silicide layer 180 can form a reduced source / drain (S / D) contact resistance (Rcsd). Furthermore, by using the sacrificial dielectric layer 164 and / or the cap layer 171, the dielectric materials 206, 210 are not substantially affected. In addition, the cap layer 171 also protects the gate spacer 138.

[0105] FIG. 24A to FIG. 27B A process of forming the silicide layer 180 according to an alternative embodiment is shown. Figure 24A-Figure 25A An alternative embodiment is shown along Figure 6 Schematic cross-sectional view of different stages of manufacturing semiconductor device structure along line AA. Figure 24B-Figure 25B An alternative embodiment is shown along Figure 6 Schematic cross-sectional view of different stages of fabricating semiconductor device structure on the BB line. Figure 24C-Figure 25C An alternative embodiment is shown along Figure 6 Schematic cross-sectional view of different stages of CC line fabrication of semiconductor device structure.

[0106] FIG. 24A to FIG. 24C The semiconductor device structure 100 is shown after forming a sacrificial dielectric layer 164. FIG. 10A to FIG. 10C The manufacturing stage of the semiconductor device structure 100 shown in FIG. Next, the process of forming the dielectric materials 206 and 210 is not performed, but a gate replacement process is performed. FIG. 25A to FIG. 25C As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed, and a gate structure 174 is formed.

[0107] Next, if Fig.26 As shown, dielectric materials 206 and 210 are formed. Dielectric materials 206 and 210 can be formed by FIG. 11A to FIG. 15 The same process as described above is used. Fig. 11B The cut polysilicon gate (CPG) process may be a cut metal gate (CMG) process. The gate electrode layer 172 is cut and separated by the dielectric material 206, but the sacrificial gate electrode layer 134 is not cut. Furthermore, the sacrificial gate electrode layer 134 and the first semiconductor layer 106 and the second semiconductor layer 108 portions disposed below the sacrificial gate electrode layer 134 are not removed, but the gate structure 174 and the first semiconductor layer 106 portion surrounded by the gate structure 174 are removed. The dielectric material 210 replaces the removed gate structure 174 and the first semiconductor layer 106 portion.

[0108] After performing a gate replacement process to form the gate structure 174, FIG. 18A to FIG. 23B In some embodiments, a capping layer 171 is selectively deposited on the gate electrode layer 172, the gate spacer 138, and the dielectric materials 206, 210. The sacrificial dielectric layer 164 and a portion of the contact etch stop layer (CESL) 162 are then removed to expose the top portions of the source / drain (S / D) regions 146n, 146p, as shown in FIG. Fig.27A and Fig.27B Then, a silicide layer 180, a contact etch stop layer (CESL) 184, a second interlayer dielectric (ILD) layer 186, and a conductive contact 188 are formed. The process of forming the silicide layer 180, the contact etch stop layer (CESL) 184, the second interlayer dielectric (ILD) layer 186, and the conductive contact 188 may be the same as FIG. 20A to FIG. 23B Same process as described above.

[0109] Embodiments of the present disclosure provide a semiconductor device structure 100 including a silicide layer 180 whose dimension along the Y direction is substantially larger than the dimension of a conductive contact 188 along the Y direction. Furthermore, the semiconductor device structure 100 may include first and second interlayer dielectric (ILD) layers 163, 186 surrounding source / drain (S / D) regions 146n, 146p. Some embodiments may achieve a number of benefits. For example, a larger silicide layer 180 may form a reduced source / drain (S / D) contact resistance.

[0110] One embodiment provides a semiconductor device structure. The semiconductor device structure includes: a source / drain region disposed on a substrate, a first interlayer dielectric layer surrounding a first portion of the source / drain region, a second interlayer dielectric layer different from the first interlayer dielectric layer surrounding a second portion of the source / drain region, a silicide layer disposed on the source / drain region, and a conductive contact disposed on the source / drain region. The conductive contact is disposed in the second interlayer dielectric layer.

[0111] In some embodiments, the first interlayer dielectric layer and the second interlayer dielectric layer have different densities. In some embodiments, the size of the silicide layer in one direction is substantially larger than the size of the conductive contact in this direction. Furthermore, the first interlayer dielectric layer has an upper surface that is lower than the height of the portion of the source / drain region having the largest size in this direction. In some embodiments, the semiconductor device structure further includes one or more semiconductor layers in contact with the source / drain region. Furthermore, the semiconductor device structure further includes a gate electrode layer disposed on the one or more semiconductor layers and surrounding the one or more semiconductor layers.

[0112] Another embodiment provides a semiconductor device structure. The semiconductor device structure includes: a source / drain region disposed on a substrate, a first contact etch stop layer contacting a bottom of the source / drain region, a first interlayer dielectric layer contacting the first contact etch stop layer, a silicide layer contacting a top of the source / drain region, a second contact etch stop layer different from the first contact etch stop layer and contacting the first contact etch stop layer, the silicide layer and the first interlayer dielectric layer, and a second interlayer dielectric layer contacting the second contact etch stop layer.

[0113] In some embodiments, the semiconductor device structure further comprises a conductive contact disposed in the second interlayer dielectric layer. In some embodiments, the second contact etch stop layer is disposed between the first interlayer dielectric layer and the second interlayer dielectric layer. Furthermore, the first contact etch stop layer is disposed between the first interlayer dielectric layer and the source / drain region. In some embodiments, the dimension of the silicide layer in one direction is substantially larger than the dimension of the conductive contact in this direction. Furthermore, the first interlayer dielectric layer has an upper surface that is lower than the height of the portion of the source / drain region having the largest dimension in this direction.

[0114] Another embodiment provides a method for forming a semiconductor device structure. The method includes: depositing a first interlayer dielectric layer to bury a source / drain region; curing the first interlayer dielectric layer at a first temperature; removing a portion of the first interlayer dielectric layer to expose a portion of the source / drain region; depositing a sacrificial dielectric layer on the first interlayer dielectric layer; curing the sacrificial dielectric layer at a second temperature substantially lower than the first temperature; and removing the sacrificial dielectric layer to expose the portion of the source / drain region.

[0115] In some embodiments, the first temperature is approximately in the range of 550 degrees Celsius to 700 degrees Celsius. Furthermore, the second temperature is approximately in the range of 350 degrees Celsius to 500 degrees Celsius. In some embodiments, the above method also includes depositing a first contact etch stop layer on the source / drain region, wherein the first interlayer dielectric layer is deposited on the first contact etch stop layer. Furthermore, the above method also includes removing a portion of the first contact etch stop layer after removing the sacrificial dielectric layer. Furthermore, the above method also includes forming a silicide layer on the exposed portion of the source / drain region. Furthermore, the above method also includes depositing a second contact etch stop layer on the silicide layer, the first interlayer dielectric layer and the first contact etch stop layer. In addition, the above method also includes depositing a second interlayer dielectric layer on the second contact etch stop layer.

[0116] The above briefly describes the characteristic components of several embodiments of the utility model, so that those skilled in the art can more easily understand the types of the present disclosure. Any person skilled in the art should understand that the present disclosure can be easily used as a basis for the change or design of other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Any person skilled in the art can also understand that structures equivalent to the above do not depart from the spirit and scope of protection of the present disclosure, and can be changed, replaced and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, characterized in that: include: a source / drain region disposed on a substrate; a first interlayer dielectric layer surrounding a first portion of the source / drain region; a second interlayer dielectric layer, different from the first interlayer dielectric layer, surrounding a second portion of the source / drain region; a silicide layer disposed on the source / drain region; and A conductive contact is disposed on the source / drain region, wherein the conductive contact is disposed in the second interlayer dielectric layer.

2. The semiconductor device structure according to claim 1, wherein: The size of the silicide layer in one direction is larger than the size of the conductive contact in the same direction.

3. The semiconductor device structure according to claim 2, wherein: The first interlayer dielectric layer has an upper surface which is lower than the height of the portion of the source / drain region having the largest size in the direction.

4. The semiconductor device structure according to claim 1 or 2, wherein: The semiconductor device structure further includes one or more semiconductor layers in contact with the source / drain region.

5. A semiconductor device structure, characterized in that: include: a source / drain region disposed on a substrate; a first contact etch stop layer in contact with a bottom of the source / drain region; a first interlayer dielectric layer in contact with the first contact etch stop layer; a silicide layer in contact with a top portion of the source / drain region; a second contact etch stop layer, different from the first contact etch stop layer and contacting the first contact etch stop layer, the silicide layer and the first interlayer dielectric layer; and A second interlayer dielectric layer contacts the second contact etching stop layer.

6. The semiconductor device structure according to claim 5, wherein: The invention also comprises a conductive contact which is arranged in the second interlayer dielectric layer.

7. The semiconductor device structure according to claim 5 or 6, characterized in that: The second contact etching stop layer is arranged between the first interlayer dielectric layer and the second interlayer dielectric layer.

8. The semiconductor device structure according to claim 7, wherein: The first contact etching stop layer is arranged between the first interlayer dielectric layer and the source / drain region.

9. The semiconductor device structure according to claim 6, wherein: The size of the silicide layer in one direction is larger than the size of the conductive contact in the same direction.

10. The semiconductor device structure according to claim 9, wherein: The first interlayer dielectric layer has an upper surface which is lower than the height of the portion of the source / drain region having the largest size in the direction.

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