Integrated chip

Abstract

The integrated chip provided by the embodiment of the utility model comprises a first source electrode / drain electrode region and a second source electrode / drain electrode region which are arranged in a semiconductor substrate and are separated from each other in the side direction along the top surface of the substrate. A gate dielectric layer is over the substrate and extends laterally between the first source / drain region and the second source / drain region. A thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. The trench isolation layer extends along the gate dielectric layer. A first sidewall of the trench isolation layer extends along a first sidewall of the gate dielectric layer. The gate layer is located right above the gate dielectric layer and located between the first source / drain region and the second source / drain region. A first sidewall of the gate layer is located directly above the gate dielectric layer and laterally retracts from the first sidewall of the gate dielectric layer.

Description

Technical Field

[0001] The embodiment of the utility model relates to an integrated chip. Background Art

[0002] Modern integrated chips (ICs) include millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). Depending on the application of the IC, integrated chips may use many different types of semiconductor devices. For example, many integrated chips include high voltage (HV) transistor devices. High voltage transistor devices are often used in power electronic devices because they can handle high breakdown voltages (e.g., greater than about 25 volts). Utility Model Content

[0003] According to one embodiment of the utility model, an integrated chip including a semiconductor substrate includes the following structure. A first source / drain region and a second source / drain region are located in the semiconductor substrate and are spaced apart laterally along the top surface of the semiconductor substrate. A gate dielectric layer is located above the semiconductor substrate and extends laterally between the first source / drain region and the second source / drain region. The thickness of the gate dielectric layer along the first sidewall of the gate dielectric layer is less than the average thickness of the gate dielectric layer. A trench isolation layer extends along the gate dielectric layer on the opposite side of the gate dielectric layer. The first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. The gate layer is located directly above the gate dielectric layer and between the first source / drain region and the second source / drain region. The first sidewall of the gate layer is located directly above the gate dielectric layer and is retracted laterally from the first sidewall of the gate dielectric layer.

[0004] According to one embodiment of the utility model, an integrated chip including a semiconductor substrate and a first high voltage (HV) well region located in the semiconductor substrate includes the following structure. The first HV well region has a first doping type. The second HV well region is located in the semiconductor substrate and is located laterally next to the first HV well region. The second HV well region has a second doping type different from the first doping type. The first source / drain region is located in the first HV well region and along the top surface of the semiconductor substrate. The first source / drain region has a second doping type. The second source / drain region is located in the second HV well region, along the top surface of the semiconductor substrate, and is laterally spaced apart from the first source / drain region in a first direction. The second source / drain region has a second doping type. A gate dielectric layer is located above the first HV well region, above the second HV well region, and laterally between the first source / drain region and the second source / drain region. The gate dielectric layer has a first gate dielectric sidewall and a second gate dielectric sidewall extending in a first direction and laterally spaced apart in a second direction different from the first direction. The trench isolation layer extends on opposite sides of the gate dielectric layer in a first direction. The trench isolation layer has a first isolation sidewall extending along the first gate dielectric sidewall in the first direction and a second isolation sidewall extending along the second gate dielectric sidewall in the first direction. The first isolation sidewall and the second isolation sidewall are laterally spaced apart in the second direction. The gate layer is located directly above the gate dielectric layer and between the first source / drain region and the second source / drain region. The gate layer has a first gate sidewall and a second gate sidewall extending in the first direction and laterally spaced apart in the second direction. The metal field plate is located directly above the gate layer and coupled to the gate layer. The first gate sidewall and the second gate sidewall are located directly above the gate dielectric layer and are laterally spaced apart from the first isolation sidewall and the second isolation sidewall, respectively, in the second direction.

[0005] According to an embodiment of the utility model, an integrated chip includes the following structure. A semiconductor substrate having a trench, wherein the trench is bounded by a first sidewall of the semiconductor substrate and a second sidewall of the semiconductor substrate, and wherein the trench surrounds an active area of ​​the semiconductor substrate. A trench isolation layer in the trench, wherein a first sidewall of the trench isolation layer extends along the first sidewall of the semiconductor substrate and a second sidewall of the trench isolation layer extends along the second sidewall of the semiconductor substrate. A first high voltage (HV) well region in the semiconductor substrate, the first high voltage well region having a first doping type. A second high voltage well region in the semiconductor substrate next to the first high voltage well region, the second high voltage well region having a second doping type different from the first doping type. A gate dielectric layer, above the first high voltage well region, above the second high voltage well region, and laterally between the first sidewall of the trench isolation layer and the second sidewall of the trench isolation layer, the gate dielectric layer having a first sidewall extending along the first sidewall of the trench isolation layer and a second sidewall extending along the second sidewall of the trench isolation layer, wherein a thickness of the gate dielectric layer along the first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. A gate layer above the gate dielectric layer, the first sidewall of the gate layer being located directly above the gate dielectric layer and laterally retracted from the first sidewall of the gate dielectric layer. A first source / drain region in the first high voltage well region, the first source / drain region having the second doping type. A second source / drain region in the second high voltage well region, the second source / drain region having the second doping type. A metal field plate, directly above the gate layer and coupled to the gate layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1C Views showing some embodiments of an integrated chip including a high voltage (HV) transistor device including a gate layer that is set back from a sidewall of a gate dielectric layer.

[0008] FIG. 2A to FIG. 2C Show Figure 1A A view of some embodiments of an integrated chip is shown in which a body region is located in a first HV well region.

[0009] FIG. 3A to FIG. 3C Show Figure 1AA view of some embodiments of an integrated chip is shown in which a second source / drain region surrounds a first source / drain region.

[0010] FIG. 4A to FIG. 4C Show Figure 1A A view of some embodiments of an integrated chip is shown in which the HV transistor device further includes a third HV well region.

[0011] Figure 5A , Figure 5B , FIG. 5C to FIG. 15A , Fig. 15B , Fig. 15C Diagrams showing some embodiments of a method of forming an integrated chip including a high voltage (HV) transistor device including a gate layer that is set back from a sidewall of a gate dielectric layer.

[0012] Fig.16 A flow chart illustrating some embodiments of a method of forming an integrated chip including a high voltage (HV) transistor device including a gate layer that is set back from a sidewall of a gate dielectric layer. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the utility model. The specific examples of components and configurations described below are for simplifying the disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly in contact. In addition, the disclosure may repeat the figure numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms, such as "under," "beneath," "lower," "over," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of a component in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] A high voltage (HV) transistor device includes a first source / drain region and a second source / drain region in a semiconductor substrate. The second source / drain region is laterally spaced from the first source / drain region. A gate dielectric layer overlies the substrate and is laterally located between the first source / drain region and the second source / drain region. A trench isolation layer surrounds the first source / drain region, the second source / drain region, and the gate dielectric layer. Sidewalls of the trench isolation layer extend along sidewalls of the gate dielectric layer. A gate layer is located on the gate dielectric layer and extends over the sidewalls of the gate dielectric layer and over the trench isolation layer.

[0016] In some devices, the thickness of the gate dielectric layer decreases along the sidewalls of the gate dielectric layer where the gate dielectric layer interfaces with the trench isolation layer. Because the gate layer extends over the sidewalls of the gate dielectric layer where the thickness of the gate dielectric layer decreases, the minimum distance between the gate layer and the substrate may be reduced. As a result, the reliability of the HV transistor device may be reduced. For example, the gate oxide integrity (GOI) and / or breakdown voltage of the HV transistor device may be reduced.

[0017] In various embodiments disclosed herein, the sidewalls of the gate layer are retracted from the sidewalls of the gate dielectric layer and the sidewalls of the trench isolation layer to improve the reliability of the HV transistor device. For example, the sidewalls of the gate layer are located directly above the gate dielectric layer and are laterally offset from the sidewalls of the gate dielectric layer. Since the sidewalls of the gate layer are retracted from the sidewalls of the gate dielectric layer, the gate layer does not extend over the portion of the gate dielectric layer where the thickness is reduced. Therefore, the minimum distance between the gate layer and the substrate can be increased. Therefore, the reliability of the HV transistor device can be improved.

[0018] Figure 1A A first cross-sectional view 100 a of some embodiments of an integrated chip including a high voltage (HV) transistor device including a gate layer 116 that is set back from the sidewalls of a gate dielectric layer 112 is shown. Figure 1B Show Figure 1A A second cross-sectional view 100b of some embodiments of an integrated chip is shown. Figure 1C Show Figure 1A and Figure 1B A top view 100c of some embodiments of an integrated chip is shown.

[0019] In some embodiments, Figure 1A The cross-sectional view 100a may span Figure 1C The line A-A' is intercepted, and / or Figure 1C The top view 100c can be across Figure 1A In some embodiments, Figure 1B The cross-sectional view 100b may span Figure 1C The line B-B' is intercepted, and / or Figure 1C The top view 100c can be across Figure 1B In some embodiments, Figure 1A The cross-sectional view 100a of FIG. 1 is shown in an xz plane formed by a first direction 101x such as an x-axis and a third direction 101z such as a z-axis, Figure 1B The cross-sectional view 100b is shown in a yz plane formed by a second direction 101y such as the y-axis and a third direction 101z such as the z-axis, and Figure 1C The top view 100c is shown in an xy plane formed by a first direction 101x, such as an x-axis, and a second direction 101y, such as a y-axis.

[0020] The integrated chip includes a semiconductor substrate 102. A first high voltage (HV) well region 104 is positioned in the substrate 102. The first HV well region 104 has a first doping type. A second HV well region 106 is positioned next to the first HV well region 104 in the substrate 102. The second HV well region 106 has a second doping type different from the first doping type. A first source / drain region 108 is positioned in the first HV well region 104. A second source / drain region 110 is positioned in the second HV well region 106. The first source / drain region 108 and the second source / drain region 110 have a second doping type. The source / drain region may refer to a source or a drain individually or collectively depending on the context. In some embodiments, the first doping type is p-type and the second doping type is n-type. In some other embodiments, the first doping type is n-type and the second doping type is p-type.

[0021] The second source / drain region 110 is laterally spaced apart from the first source / drain region in a first direction (e.g., along a first direction 101x such as an x-axis). The substrate 102 has an upper surface 102a and a pair of sidewalls (e.g., a first sidewall 102b and a second sidewall 102c) located on opposite sides of the upper surface 102a. The upper surface 102a and the sidewalls 102b, 102c extend from the first source / drain region 108 to the second source / drain region 110 in the first direction. The sidewalls 102b, 102c are laterally spaced apart in a second direction (e.g., along a second direction 101y such as a y-axis) that is different from the first direction (e.g., substantially perpendicular to the first direction).

[0022] The channel region 118 extends laterally from the first source / drain region 108 along the upper surface 102a of the substrate 102 to the interface between the first HV well region 104 and the second HV well region 106. The drift region 134 extends from the second source / drain region 110 along the upper surface of the substrate 102 to the interface between the first HV well region 104 and the second HV well region 106.

[0023] A gate dielectric layer 112 is positioned above the first HV well region 104 and the second HV well region 106. The gate dielectric layer 112 extends laterally between the first source / drain region 108 and the second source / drain region 110. The gate dielectric layer 112 has a bottom surface 112a and a pair of sidewalls (e.g., a first sidewall 112b and a second sidewall 112c) located on opposite sides of the bottom surface 112a. The sidewalls 112b, 112c extend in a first direction (e.g., along a first direction 101x such as an x-axis) and are laterally spaced apart in a second direction (e.g., along a second direction 101y such as a y-axis). The bottom surface 112a of the gate dielectric layer 112 extends from the first source / drain region 108 along the upper surface 102a of the substrate 102 to the second source / drain region 110.

[0024] A trench isolation layer 114 (e.g., a shallow trench isolation (STI) layer) laterally surrounds the first source / drain region 108, the second source / drain region 110, and the gate dielectric layer 112 in a closed path (e.g., a circular path). In some embodiments, the trench isolation layer 114 defines an active region (e.g., an oxide defined (OD) region) of the HV transistor device. The trench isolation layer 114 extends along the gate dielectric layer 112 on opposite sides of the gate dielectric layer 112. For example, the trench isolation layer 114 has a first sidewall 114b and a second sidewall 114c extending along the first sidewall 112b and the second sidewall 112c of the gate dielectric layer in a first direction, respectively. The first sidewall 114b of the trench isolation layer 114 is laterally spaced apart from the second sidewall 114c of the trench isolation layer 114 in a second direction (e.g., 101y).

[0025] A gate layer 116 is positioned directly above the gate dielectric layer 112 and laterally between the first source / drain region 108 and the second source / drain region 110. The gate layer 116 has a first sidewall 116b and a second sidewall 116c extending in a first direction (e.g., 101x) and laterally spaced apart in a second direction (e.g., 101y). The first sidewall 116b and the second sidewall 116c are located directly above the gate dielectric layer 112 and the upper surface 102a of the substrate 102.

[0026] In some embodiments, the thickness of the gate dielectric layer 112 (e.g., the thickness along a third direction 101z such as the z-axis) decreases along the sidewalls 112b, 112c of the gate dielectric layer 112, where the gate dielectric layer 112 interfaces with the trench isolation layer 114. For example, in some embodiments, the thickness of the gate dielectric layer 112 along the sidewalls 112b, 112c of the gate dielectric layer 112 is substantially less than the average thickness of the gate dielectric layer 112. Therefore, in embodiments of the present disclosure, the gate layer 116 is set back from the sidewalls 112b, 112c of the gate dielectric layer 112 (where the thickness of the gate dielectric layer 112 decreases). For example, the first sidewall 116b of the gate layer 116 is located directly above the gate dielectric layer 112 and is laterally offset (e.g., spaced apart) from the first sidewall 112b of the gate dielectric layer 112 in the second direction. Similarly, the second sidewall 116 c of the gate layer 116 is directly above the gate dielectric layer 112 and is laterally offset (eg, spaced apart) from the second sidewall 112 c of the gate dielectric layer 112 in the second direction.

[0027] By offsetting the sidewalls 116b, 116c of the gate layer 116 from the corresponding sidewalls 112b, 112c of the gate dielectric layer 112, the gate layer 116 does not extend directly over the sidewalls 112b, 112c of the gate dielectric layer 112 where the thickness of the gate dielectric layer 112 is reduced. Therefore, the minimum distance between the gate layer 116 and the substrate 102 can be increased. Therefore, the reliability of the HV transistor device can be improved. For example, the gate oxide integrity (GOI) and / or the breakdown voltage of the HV transistor device can be improved. In addition, because the gate layer 116 does not extend directly over the sidewalls 112b, 112c of the gate dielectric layer 112, the electric field at the edge of the substrate where the sidewalls 102b, 102c meet the upper surface 102a can be reduced. Therefore, the GOI can be further improved.

[0028] In addition, the gate layer 116 has a third sidewall 116d and a fourth gate sidewall 116e extending between the first sidewall 116b and the second sidewall 116c in the second direction and spaced apart laterally in the first direction. The third sidewall 116d is located directly above the gate dielectric layer 112 and the second HV well region 106. The trench isolation layer 114 does not extend directly below the third sidewall 116d of the gate layer 116 located between the first source / drain region 108 and the second source / drain region 110. Instead, the gate dielectric layer 112 extends continuously from the first source / drain region 108 to the second source / drain region 110.

[0029] Since the trench isolation layer 114 does not extend directly under the third sidewall 116d of the gate layer 116, the thickness of the gate dielectric layer 112 directly under the third sidewall 116d of the gate layer 116 may not be reduced. Therefore, the minimum distance between the gate layer 116 and the substrate 102 may not be reduced. Therefore, the GOI of the gate layer 116 may be prevented from being reduced along the third sidewall 116d. In addition, since the trench isolation layer 114 does not extend directly between the first source / drain region 108 and the second source / drain region 110, the current passing through the HV transistor device may be increased.

[0030] A dielectric structure 120 including one or more dielectric layers is positioned above the substrate 102. A first metal interconnect 128 is coupled to the first source / drain region 108 via a first source / drain contact 122. A second metal interconnect 132 is coupled to the second source / drain region 110 via a second source / drain contact 126. A metal field plate 130 is positioned directly above the gate layer 116 and is coupled to the gate layer 116 via a gate contact 124. The metal field plate 130 covers the gate layer 116. For example, the metal field plate 130 extends from directly above the gate layer 116 to beyond the perimeter of the gate layer 116 (e.g., beyond the sidewalls 116b, 116c, 116d). Specifically, the metal field plate 130 extends beyond the third sidewall 116d of the gate layer located directly above the second HV well region 106 and the drift region 134. In some embodiments, the metal field plate 130 extends directly above the second source / drain region 110 .

[0031] By including the metal field plate 130 above the gate layer 116 and the drift region 134, the electric field distribution in the HV well regions 104, 106 can be improved. For example, the peak electric field in the drift region 134 can be reduced. Thus, the breakdown voltage of the HV transistor device can be improved.

[0032] In some embodiments, a lateral distance 136 between the first sidewall 116b of the gate layer 116 and the first sidewall 112b of the gate dielectric layer 112 is large enough so that the first sidewall 116b of the gate layer 116 is laterally spaced apart from a first portion of the gate dielectric layer 112 where the thickness is reduced (e.g., along the first sidewall 112b of the gate dielectric layer 112). Similarly, a lateral distance 138 between the second sidewall 116c of the gate layer 116 and the second sidewall 112c of the gate dielectric layer 112 is large enough so that the second sidewall 116c of the gate layer 116 is laterally spaced apart from a second portion of the gate dielectric layer 112 where the thickness is reduced (e.g., along the second sidewall 112c of the gate dielectric layer 112). If the distances 136, 138 are too small, the gate layer 116 may extend over the portion of the gate dielectric layer 112 where the thickness is reduced, and thus the GOI of the HV transistor device may be reduced.

[0033] In some embodiments, the thickness of the gate dielectric layer 112 is in a range of 900 angstroms to 500 angstroms, in a range of 800 angstroms to 600 angstroms, or some other suitable value. In some embodiments, because the gate layer 116 does not extend directly over the sidewalls 112b, 112c of the gate dielectric layer 112, the average thickness of the gate dielectric layer 112 may be reduced (e.g., relative to a gate dielectric layer having an increased average thickness to compensate for the reduced thickness along the sidewalls). As a result, the current through the HV transistor device may be further increased.

[0034] Figure 2A Show Figure 1A A first cross-sectional view 200 a of some embodiments of an integrated chip is shown in which a body region 210 is located in a first HV well region 104 .

[0035] Figure 2B Show Figure 2A A second cross-sectional view 200b of some embodiments of an integrated chip is shown.

[0036] Figure 2C Show Figure 2A and Figure 2B A top view 200c of some embodiments of an integrated chip is shown.

[0037] In some embodiments, Figure 2A The cross-sectional view 200a may span Figure 2C The line C-C' is intercepted, and / or Figure 2C The top view 200c can be across Figure 2A In some embodiments, Figure 2B The cross-sectional view 200b may span Figure 2C The line D-D' is intercepted, and / or Figure 2C The top view 200c can be across Figure 2B The line D-D' is intercepted.

[0038] The body region 210 has a first doping type. The body region 210 is laterally spaced apart from the first source / drain region 108 in a first direction (e.g., along 101x). The trench isolation layer 114 extends directly between the first source / drain region 108 and the body region 210. The first HV well region 104 laterally surrounds the second HV well region 106 in a closed path (e.g., an annular path). The body region 210 extends along the first HV well region 104 and laterally surrounds the source / drain regions 108, 110 in a closed path (e.g., an annular path). The trench isolation layer 114 surrounds the body region 210 in a closed path (e.g., annular path).

[0039] In some embodiments, a lightly doped (LD) source / drain region 208 having a second doping type is positioned in the first HV well region 104 below the first source / drain region 108. In some embodiments, the LD source / drain region 208 extends along the bottom of the first source / drain region 108 and the bottom surface of the gate dielectric layer 112. In some embodiments, the LD source / drain region 208 extends directly below the gate layer 116. The channel region 118 extends between the LD source / drain region 208 and the interface between the first HV well region 104 and the second HV well region 106. In some embodiments, a well region 212 having a first doping type is positioned in the first HV well region 104 below the LD source / drain region 208.

[0040] A third metal interconnect 222 is positioned above the body region 210 and coupled to the body region 210 via the body contact 220. In some embodiments, a silicide region 218 is formed along the body region 210, wherein the body contact 220 is coupled to the body region 210. Similarly, silicide regions 214, 216 are formed along the source / drain regions 108, 110, wherein the source / drain contacts 122, 126 are coupled to the source / drain regions 108, 110, respectively.

[0041] In some embodiments, a peripheral HV well region 204 having the second doping type is positioned in substrate 102 on a first side of first HV well region 104. Additionally, a peripheral HV well region 206 having the second doping type is positioned in substrate 102 on a second side of first HV well region 104.

[0042] The first HV well region 104 has a first doping type. The second HV well region 106 has a second doping type. The source / drain regions 108, 110 have a second doping type. In some embodiments (e.g., where the first doping type is n-type), the substrate 102 has a p-type doping type and the integrated chip further includes a deep well region 202 with n-type doping in the substrate 102 below the HV well regions 104, 106. For example, the deep well region 202 extends along the bottom of the first HV well region 104 and the second HV well region 106. In some other embodiments (e.g., where the first doping type is p-type), the substrate 102 has p-type doping and the integrated chip does not have a deep well region 202.

[0043] In some embodiments, FIG. 2A to FIG. 2C The transistor device shown in FIG. 1 may be referred to as an asymmetric metal-oxide-semiconductor field effect transistor (MOSFET).

[0044] Figure 3A Show Figure 1A A first cross-sectional view 300 a of some embodiments of an integrated chip is shown in which the second source / drain region 110 surrounds the first source / drain region 108 . Figure 3B Show Figure 3A A second cross-sectional view 300b of some embodiments of an integrated chip is shown. Figure 3C Show Figure 3A and Figure 3B A top view 300c of some embodiments of an integrated chip is shown.

[0045] In some embodiments, Figure 3A The cross-sectional view 300a may span Figure 3C The line E-E' is intercepted, and / or Figure 3C The top view 300c can be across Figure 3A In some embodiments, Figure 3B The cross-sectional view 300b may span Figure 3C The line F-F' is intercepted, and / or Figure 3C The top view 300c can be across Figure 3B The line F-F' is intercepted.

[0046] In some embodiments, the substrate 102 has p-type doping, the deep well region 202 has n-type doping, the first HV well region 104 has p-type doping, the second HV well region 106 has n-type doping, the source / drain regions 108 , 110 have n-type doping, the body region 210 has p-type doping, and the LD source / drain region 208 has n-type doping.

[0047] The second HV well region 106 surrounds the first HV well region 104 in a closed path (e.g., a circular path). The second source / drain region 110 extends along the second HV well region 106 and laterally surrounds the first source / drain region 108 and the body region 210 in a closed path (e.g., a circular path). The trench isolation layer 114 extends directly between the second source / drain region 110 and the body region 210. The deep well region 202 is disposed in the substrate 102 below the HV well regions 104, 106. The deep well region 202, the second HV well region 106, and the second source / drain region 110 isolate the first HV well region 104, the first source / drain region 108, and the body region 210 from adjacent transistor devices (not shown). Therefore, FIG. 3A to FIG. 3C The transistor arrangement shown in may be referred to as an isolated MOSFET.

[0048] In some embodiments, the first source / drain region 108 and the body region 210 are laterally located beside each other (e.g., in direct contact with each other), and the metal line 304 is coupled to both the first source / drain region 108 and the body region 210 via the body / source / drain contact 302. In some embodiments, a silicide region 306 is positioned in both the first source / drain region 108 and the body region 210.

[0049] Figure 4A Show Figure 1A A first cross-sectional view 400 a of some embodiments of an integrated chip is shown in which the HV transistor device further includes a third HV well region 402 . Figure 4B Show Figure 4A A second cross-sectional view 400b of some embodiments of an integrated chip is shown. Figure 4C Show Figure 4A and Figure 4B A top view 400c of some embodiments of an integrated chip is shown.

[0050] In some embodiments, Figure 4A The cross-sectional view 400a may span Figure 4C The line G-G' is intercepted, and / or Figure 4C The top view 400c can be across Figure 4A In some embodiments, Figure 4B The cross-sectional view 400b may span Figure 4C The line H-H' is intercepted, and / or Figure 4C The top view 400c can be across Figure 4B The line H-H' is intercepted.

[0051] The integrated chip includes a first HV well region 104 having a first doping type, a second HV well region 106 having a second doping type, and a third HV well region 402 having the first doping type. The second HV well region 106 extends directly between the first HV well region 104 and the third HV well region 402. In addition, the second HV well region 106 laterally surrounds both the first HV well region 104 and the third HV well region 402 in a closed path (e.g., a double annular path).

[0052] The first source / drain region 108 has a first doping type and is located in the first HV well region 104. The second source / drain region 110 has a first doping type and is located in the third HV well region 402. The channel region 118 extends from the interface between the first HV well region 104 and the second HV well region 106 along the bottom surface of the gate dielectric layer 112 to the interface between the second HV well region 106 and the third HV well region 402. In some embodiments, the first drift region 134 extends from the first source / drain region 108 to the interface between the first HV well region 104 and the second HV well region 106, and the second drift region 134 extends from the second source / drain region 110 to the interface between the third HV well region 402 and the second HV well region 106.

[0053] The body region 210 has a second doping type and is located in the second HV well region 106. The body region 210 extends along the second HV well region 106 and laterally surrounds both the source / drain regions 108, 110 in a closed path (e.g., a circular path). The trench isolation layer 114 extends directly between the first source / drain region 108 and the body region 210. In addition, the trench isolation layer 114 extends directly between the second source / drain region 110 and the body region 210.

[0054] In some embodiments, the metal field plate 130 is coupled to the gate layer 116 by a first gate contact 404 and a second gate contact 406 arranged on opposite sides of the gate layer 116. In some embodiments, a metal line 408 is coupled to the body region 210 on a first side of the transistor device by a first body contact 410, and another metal line 412 is coupled to the body region 210 on a second side of the transistor device by a second body contact 414. In some embodiments, the peripheral HV well regions 204, 206 are located on opposite sides of the second HV well region 106. The peripheral HV well regions 204, 206 have a first doping type.

[0055] In some embodiments, the transistor device is substantially symmetrical about a center line (not shown) extending between the first HV well region 104 and the third HV well region 402 in the second direction (eg, along 101y). FIG. 4A to FIG. 4C The transistor arrangement shown may be referred to as a symmetric MOSFET.

[0056] Figure 5A , Figure 5B , FIG. 5C to FIG. 15A , Fig. 15B , Fig. 15C Views 500a, 500b, 500c to 1500a, 1500b, 1500c of some embodiments illustrate methods of forming an integrated chip including a high voltage (HV) transistor device including a gate layer that is set back from the sidewalls of a gate dielectric layer. Figure 5A , Figure 5B , FIG. 5C to FIG. 15A , Fig. 15B , Fig. 15C is described with respect to a method, however, it should be understood that Figure 5A , Figure 5B , FIG. 5C to FIG. 15A , Fig. 15B , Fig. 15C The structure disclosed in is not limited to this method, but can exist as a structure independent of the method. In some embodiments, FIG. 5A to FIG. 15A The cross-sectional views 500a to 1500a can be respectively along FIG. 5C to FIG. 15C The line I-I' is intercepted, and FIG. 5B to FIG. 15B The cross-sectional views 500b to 1500b can be respectively along FIG. 5C to FIG. 15C The line J-J' is intercepted.

[0057] In some embodiments, Figure 5A 500a, Figure 5B The cross-sectional view 500b and Figure 5C As shown in the top view 500c of FIG. 1 , the semiconductor substrate 102 is etched to form a trench 504 in the substrate 102. The trench 504 is bounded by the sidewalls and the upper surface of the substrate 102. In some embodiments, the etching may bound the active area of ​​the substrate 102.

[0058] In some embodiments, a mask layer 502 is formed over the substrate and etching is performed according to the mask layer 502. In some embodiments, the mask layer 502 includes a photoresist layer, a hard mask layer, or some other suitable layer. In some embodiments, etching includes a dry etching process (e.g., a plasma etching process, a reactive ion etching process, an ion beam etching process, etc.) or some other suitable process. In some embodiments, the mask layer 502 is removed during and / or after etching. In some embodiments, the substrate 102 includes silicon or some other suitable material.

[0059] like Fig. 6A 600a, Figure 6B The cross-sectional view 600b and Figure 6C As shown in the top view 600c, on the substrate 102 and the trench (for example, Figure 5A , Figure 5B , Figure 5CIn some embodiments, the trench isolation layer 114 is deposited in a substrate 102 (shown as 504). In some embodiments, the trench isolation layer 114 surrounds the active area of ​​the substrate 102. In some embodiments, the trench isolation layer 114 includes a dielectric such as, for example, silicon dioxide or some other suitable material. In some embodiments, the trench isolation layer 114 is deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable process.

[0060] In addition, a planarization process is performed on the trench isolation layer 114. In some embodiments, the planarization process may include, for example, chemical mechanical planarization (CMP) or some other suitable process.

[0061] like Fig. 7A 700a, Figure 7B The cross-sectional view 700b and Figure 7C As shown in the top view 700 c of FIG. 1 , the substrate 102 is etched to form a gate dielectric recess 704 along the top surface of the substrate 102 and between the sidewalls of the trench isolation layer 114 . In some embodiments, the etching extends into the trench isolation layer 114 .

[0062] In some embodiments, a hard mask layer 702 is formed over the substrate 102 and etching is performed based on the hard mask layer 702. In some embodiments, the hard mask layer 702 is etched based on a photoresist layer to define the hard mask layer 702 before etching the substrate 102 based on the hard mask layer 702. In some embodiments, the hard mask layer 702 includes silicon nitride, plasma enhanced oxide, or some other suitable material. In some embodiments, etching includes a dry etching process or some other suitable process.

[0063] like Fig. 8A 800a, Figure 8B The cross-sectional view 800b and Figure 8CAs shown in the top view 800c of FIG. 1 , a first HV well region 104 and a second HV well region 106 are formed in the substrate 102 and are located laterally next to each other. In some embodiments, the second HV well region 106 is surrounded by the first HV well region 104. The first HV well region 104 has a first doping type and the second HV well region 106 has a second doping type different from the first doping type. In some embodiments, the first HV well region 104 and the second HV well region 106 are formed in the substrate 102 by an ion implantation process (e.g., as shown by arrows 802) or some other suitable process. In some embodiments, during the formation of the HV well regions 104, 106, the hard mask layer 702 remains in place.

[0064] In some embodiments, the substrate has p-type doping. In addition, in some embodiments (e.g., where the first doping type is n-type), before forming the first HV well region 104 in the substrate 102, a deep well region 202 having n-type doping is formed in the substrate 102. For example, the deep well region 202 can be formed in the substrate 102 by an ion implantation process or some other suitable process. In some other embodiments (e.g., where the first doping type is p-type), the substrate 102 does not have a deep well region 202.

[0065] In some embodiments, peripheral HV well regions 204, 206 are formed in the substrate on opposite sides of the first HV well region 104. Figure 8C The peripheral HV wells 204, 206 are not shown in the top view 800c of FIG.

[0066] like Fig.9A The cross-sectional view 900a, Fig. 9B The cross-sectional view 900b and Fig. 9C As shown in the top view 900c, on the substrate 102 in the gate dielectric recess (eg, Fig. 8A , Figure 8B , Figure 8C In some embodiments, the gate dielectric layer 112 is formed in a thermal oxide growth process in which a thermal oxide layer is grown in a recess above the substrate 102. In some embodiments, the hard mask layer 702 remains in place during the formation of the gate dielectric layer 112. In some embodiments, the exposed portions of the substrate 102 are oxidized during the thermal oxide growth process. In some embodiments, the hard mask layer 702 is removed after the thermal oxide growth process. In some embodiments, the gate dielectric layer 112 comprises silicon dioxide or some other suitable material.

[0067] In some embodiments, the thermal oxide growth process may behave differently along the trench isolation layer 114 than along the substrate 102. Therefore, the thickness of the gate dielectric layer 112 along the trench isolation layer 114 (e.g., along the sidewalls 114b, 114c) may be substantially less than the average thickness of the gate dielectric layer 112. Therefore, the minimum distance between the substrate 102 and the top surface of the gate dielectric layer 112 may decrease along the sidewalls 112b, 112c of the gate dielectric layer 112.

[0068] like Fig. 10A 1000a, Fig. 10B The cross-sectional view 1000b and Fig. 10C As shown in the top view 1000c of FIG. 1 , a gate layer 116 is deposited on the substrate 102, the gate dielectric layer 112, and the trench isolation layer 114. In some embodiments, the gate layer 116 includes polysilicon, metal, or some other suitable material. In some embodiments, the gate layer 116 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0069] like Fig.11A 1100a, Fig. 11B The cross-sectional view 1100b and Fig. 11C As shown in the top view 1100c of FIG. 1 , the gate layer 116 is etched to define the gate layer 116. For example, as a result of the etching, the gate layer 116 has a first sidewall 116b and a second sidewall 116c that are located directly above the gate dielectric layer 112 and laterally offset (e.g., retracted) from the sidewalls 112b, 112c of the gate dielectric layer 112 (where the gate dielectric layer 112 has a reduced thickness). By etching the gate layer 116 so that the sidewalls 116b, 116c of the gate layer 116 are located directly above the gate dielectric layer 112 and laterally retracted from the sidewalls 112b, 112c of the gate dielectric layer 112, the gate layer 116 does not extend over the region where the thickness of the gate dielectric layer 112 is reduced. Therefore, the reliability of the device can be improved.

[0070] In some embodiments, a mask layer 1102 is formed over the gate layer 116 and etching is performed according to the mask layer 1102. The mask layer 1102 has sidewalls that are located directly above the gate dielectric layer 112 and laterally offset from the sidewalls 112b, 112c of the gate dielectric layer 112 so that the gate layer 116 has similar features after etching. In some embodiments, the mask layer 1102 includes a photoresist layer, a hard mask layer, or some other suitable layer. In some embodiments, etching includes a dry etching process or some other suitable process. In some embodiments, the mask layer 1102 is removed during and / or after etching.

[0071] like Fig. 12A1200a, Fig. 12B The cross-sectional view 1200b and Fig. 12C As shown in the top view 1200c of FIG. 1 , a first source / drain region 108 is formed in the first HV well region 104. In addition, a second source / drain region 110 is formed in the second HV well region 106. In some embodiments, the source / drain region 110 has a second doping type. In addition, a body region 210 is formed in the first HV well region 104. In some embodiments, the body region 210 has a first doping type. In some embodiments, the source / drain regions 108, 110 and the body region 210 are formed by an ion implantation process (e.g., as shown by arrows 1202) or some other suitable process.

[0072] In some embodiments, before forming the first source / drain region 108 in the first HV well region 104 , a lightly doped (LD) source / drain region 208 is formed in the first HV well region 104 (eg, by an ion implantation process), and then the first source / drain region 108 is formed over the LD source / drain region 208 .

[0073] like Fig.13A 1300a, Fig. 13B The cross-sectional view 1300b and Fig. 13C As shown in the top view 1300c of FIG. 1 , a first dielectric layer 140 is deposited on the substrate 102, and contacts 122, 124, 126, 220 are formed in the first dielectric layer 140. For example, the first source / drain contact 122 is formed on the first source / drain region 108 and directly contacts the first source / drain region 108. The second source / drain contact 126 is formed on the second source / drain region 110 and directly contacts the second source / drain region 110. The body contact 220 is formed on the body region 210 and directly contacts the body region 210. The gate contact 124 is formed on the gate layer 116 and directly contacts the gate layer 116.

[0074] In some embodiments, the first dielectric layer 140 includes silicon dioxide or some other suitable material. In some embodiments, the first dielectric layer 140 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process. In some embodiments, the contacts 122, 124, 126, 220 are formed in the first dielectric layer 140 by etching the first dielectric layer 140, depositing a contact material (e.g., tungsten, etc.) on the etched first dielectric layer 140, and performing a planarization process (e.g., CMP, etc.) on the contact material.

[0075] like Fig.14A 1400a, Fig. 14B The cross-sectional view 1400b and Fig. 14CAs shown in the top view 1400c of FIG. 1 , a second dielectric layer 142 is deposited on the first dielectric layer 140 and on the contacts 122, 124, 126, 220. In some embodiments, the second dielectric layer 142 comprises silicon dioxide or some other suitable material. In some embodiments, the second dielectric layer 142 is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0076] In addition, the second dielectric layer 142 is etched to form interconnect openings 1406, 1408, 1410 and a field plate opening 1404 in the second dielectric layer and over the contacts 122, 126, 220, 124. For example, a first interconnect opening 1406 is formed in the second dielectric layer 142 directly over the first source / drain contact 122, a second interconnect opening 1408 is formed in the second dielectric layer 142 directly over the second source / drain contact 126, and a third interconnect opening 1410 is formed in the second dielectric layer 142 directly over the body contact 220. In addition, a field plate opening 1404 is formed in the second dielectric layer 142 directly over the gate contact 124. In some embodiments, a mask layer 1402 is formed over the second dielectric layer 142 and etching is performed based on the mask layer 1402.

[0077] The sidewall of the second dielectric layer 142 that bounds the field plate opening 1404 is located directly above the second HV well region 106 and is laterally spaced apart from the third sidewall 116d of the gate layer 116 in a first direction (e.g., along the first direction 101x such as the x-axis). Fig.15A , Fig. 15B , Fig. 15C As shown in FIG130 , the metal field plate will extend beyond the third sidewall 116 d of the gate layer 116 and be located directly above the second HV well region 106 (eg, directly above the drift region 134 ). Therefore, the breakdown voltage of the device can be improved.

[0078] like Fig.15A 1500a, Fig. 15B The cross-sectional view 1500b and Fig. 15C As shown in the top view 1500c of FIG. 1500, the field plate opening (eg, Fig.14A , Fig. 14B , Fig. 14C In addition, a metal field plate 130 is formed in the interconnect opening (e.g., Fig.14A , Fig. 14B , Fig. 14CIn some embodiments, the metal field plate 130 and the metal interconnects 128, 132, 222 are formed in the second dielectric layer 142 (see 1406, 1408, 1410). In some embodiments, the metal field plate 130 and the metal interconnects 128, 132, 222 are formed by depositing a metal (e.g., copper, aluminum, etc.) on the second dielectric layer 142 and in the interconnect openings. In addition, a planarization process is performed on the metal. In some embodiments, the metal field plate 130 includes a plurality of metal segments extending in a first direction (e.g., along a first direction 101x such as an x-axis), the plurality of metal segments are spaced apart in a second direction (e.g., along a second direction 101y such as a y-axis), and are connected together by connecting segments extending in the second direction.

[0079] Fig.16 A flow chart of some embodiments of a method 1600 for forming an integrated chip including a high voltage (HV) transistor device, the HV transistor device including a gate layer that is retracted from the sidewall of the gate dielectric layer. Although method 1600 is shown and described below as a series of actions or events, it should be understood that the order in which such actions or events are shown should not be interpreted as having a limiting meaning. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, not all of the actions shown may be necessary to implement one or more aspects or embodiments described herein. In addition, one or more of the actions illustrated herein may be performed in one or more separate actions and / or stages.

[0080] At block 1602, a substrate is etched to form a trench in the substrate that laterally surrounds an active area of ​​the substrate. Figure 5A A cross-sectional view 500a of some embodiments corresponding to block 1602 is shown, Figure 5B A cross-sectional view 500b of some embodiments corresponding to block 1602 is shown, and Figure 5C A top view 500c of some embodiments corresponding to block 1602 is shown.

[0081] At block 1604, a trench isolation layer is deposited in the trench. Fig. 6A A cross-sectional view 600a of some embodiments corresponding to block 1604 is shown, Figure 6B A cross-sectional view 600b of some embodiments corresponding to block 1604 is shown, and Figure 6C A top view 600c of some embodiments corresponding to block 1604 is shown.

[0082] At block 1606, the substrate is etched to form recesses in the substrate between sidewalls of the trench isolation layer. Fig. 7A A cross-sectional view 700a of some embodiments corresponding to block 1606 is shown, Figure 7BA cross-sectional view 700b of some embodiments corresponding to block 1606 is shown, and Figure 7C A top view 700c of some embodiments corresponding to block 1606 is shown.

[0083] At block 1608 , a first high voltage (HV) well region having a first doping type is formed in the substrate below the recess. Fig. 8A A cross-sectional view 800a of some embodiments corresponding to block 1608 is shown, Figure 8B A cross-sectional view 800b of some embodiments corresponding to block 1608 is shown, and Figure 8C A top view 800c of some embodiments corresponding to block 1608 is shown.

[0084] At block 1610 , a second HV well region having a second doping type is formed in the substrate beside the first HV well region and below the recess. Fig. 8A A cross-sectional view 800a of some embodiments corresponding to block 1610 is shown, Figure 8B A cross-sectional view 800b of some embodiments corresponding to block 1610 is shown, and Figure 8C A top view 800c of some embodiments corresponding to block 1610 is shown.

[0085] At block 1612 , a gate dielectric layer is formed in the recess between the sidewalls of the trench isolation layer. Fig.9A A cross-sectional view 900a of some embodiments corresponding to block 1612 is shown, Fig. 9B A cross-sectional view 900b of some embodiments corresponding to block 1612 is shown, and Fig. 9C A top view 900c of some embodiments corresponding to block 1612 is shown.

[0086] At block 1614, a gate layer is deposited over the gate dielectric layer. Fig. 10A A cross-sectional view 1000a of some embodiments corresponding to block 1614 is shown, Fig. 10B A cross-sectional view 1000b of some embodiments corresponding to block 1614 is shown, and Fig. 10C A top view 1000c of some embodiments corresponding to block 1614 is shown.

[0087] At block 1616 , the gate layer is etched such that sidewalls of the gate layer are directly above the gate dielectric layer and are laterally set back from the sidewalls of the gate dielectric layer. Fig.11A A cross-sectional view 1100a of some embodiments corresponding to block 1616 is shown, Fig. 11B A cross-sectional view 1100b of some embodiments is shown corresponding to block 1616, and Fig. 11C A top view 1100c of some embodiments corresponding to block 1616 is shown.

[0088] At block 1618 , a first source / drain region having a second doping type is formed in the first HV well region. Fig. 12A A cross-sectional view 1200a of some embodiments is shown corresponding to block 1618, Fig. 12B A cross-sectional view 1200b of some embodiments is shown corresponding to block 1618, and Fig. 12C A top view 1200c of some embodiments corresponding to block 1618 is shown.

[0089] At block 1620 , a second source / drain region having a second doping type is formed in the second HV well region. Fig. 12A A cross-sectional view 1200a of some embodiments corresponding to block 1620 is shown, Fig. 12B A cross-sectional view 1200b of some embodiments is shown corresponding to block 1620, and Fig. 12C A top view 1200c of some embodiments corresponding to block 1620 is shown.

[0090] At block 1622 , a metal field plate coupled to the gate layer is formed directly above the gate layer, the metal field plate extending beyond a sidewall of the gate layer toward the second source / drain region. Fig.15A A cross-sectional view 1500a of some embodiments corresponding to block 1622 is shown, Fig. 15B A cross-sectional view 1500b of some embodiments corresponding to block 1622 is shown, and Fig. 15C A top view 1500c of some embodiments corresponding to block 1622 is shown.

[0091] Therefore, the disclosed embodiments relate to a high voltage (HV) transistor device and method of forming the HV transistor device, the device including a gate layer that is laterally recessed from the sidewalls of an underlying gate dielectric layer to improve device reliability.

[0092] Therefore, in some embodiments, the present disclosure relates to an integrated chip including a semiconductor substrate. A first source / drain region and a second source / drain region are located in the semiconductor substrate and are spaced apart laterally along the top surface of the semiconductor substrate. A gate dielectric layer is located above the semiconductor substrate and extends laterally between the first source / drain region and the second source / drain region. The thickness of the gate dielectric layer along the first sidewall of the gate dielectric layer is less than the average thickness of the gate dielectric layer. A trench isolation layer extends along the gate dielectric layer on the opposite side of the gate dielectric layer. The first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. The gate layer is located directly above the gate dielectric layer and between the first source / drain region and the second source / drain region. The first sidewall of the gate layer is located directly above the gate dielectric layer and is retracted laterally from the first sidewall of the gate dielectric layer.

[0093] In some embodiments, the method further includes: a metal field plate located directly above the gate layer and coupled to the gate layer.

[0094] In some embodiments, the metal field plate extends beyond the periphery of the gate layer toward the second source / drain region.

[0095] In some embodiments, the first sidewall of the trench isolation layer extends along a first sidewall of the semiconductor substrate, and the first sidewall of the gate layer is laterally retracted from the first sidewall of the semiconductor substrate and the first sidewall of the trench isolation layer.

[0096] In some embodiments, the first sidewall of the semiconductor substrate is spaced apart from the second sidewall of the semiconductor substrate, wherein the upper surface of the semiconductor substrate extends between the first sidewall of the semiconductor substrate and the second sidewall of the semiconductor substrate, and wherein the first sidewall of the gate layer is located directly above the upper surface of the semiconductor substrate.

[0097] In some embodiments, the gate dielectric layer extends laterally from the first source / drain region to the second source / drain region.

[0098] In some embodiments, the first source / drain region is laterally spaced apart from the second source / drain region in a first direction, wherein the first sidewall of the gate dielectric layer, the first sidewall of the trench isolation layer, and the first sidewall of the gate layer extend in the first direction, and wherein the first sidewall of the gate layer is laterally spaced apart from the first sidewall of the gate dielectric layer in a second direction different from the first direction.

[0099] In some embodiments, the gate dielectric layer has a second sidewall extending along the second sidewall of the trench isolation layer in the first direction, wherein the second sidewall of the gate dielectric layer is laterally spaced apart from the first sidewall of the gate dielectric layer in the second direction, wherein the gate layer has a second sidewall extending in the first direction and laterally spaced apart from the first sidewall of the gate layer in the second direction, and wherein the second sidewall of the gate layer is spaced apart from the second sidewall of the gate dielectric layer in the second direction.

[0100] In some embodiments, it further includes: a first high voltage (HV) well region located in the semiconductor substrate, wherein the first source / drain region is located in the first high voltage well region, wherein the first high voltage well region has a first doping type and the first source / drain region has a second doping type different from the first doping type; and a second high voltage well region located in the semiconductor substrate next to the first high voltage well region, wherein the second source / drain region is located in the second high voltage well region, and wherein the second high voltage well region and the second source / drain region have the second doping type.

[0101] In other embodiments, the disclosure relates to an integrated chip including a semiconductor substrate and a first high voltage (HV) well region located in the semiconductor substrate. The first HV well region has a first doping type. The second HV well region is located in the semiconductor substrate and is laterally adjacent to the first HV well region. The second HV well region has a second doping type different from the first doping type. A first source / drain region is located in the first HV well region and along a top surface of the semiconductor substrate. The first source / drain region has a second doping type. The second source / drain region is located in the second HV well region, along the top surface of the semiconductor substrate, and laterally spaced apart from the first source / drain region in a first direction. The second source / drain region has a second doping type. A gate dielectric layer is located above the first HV well region, above the second HV well region, and laterally between the first source / drain region and the second source / drain region. The gate dielectric layer has a first gate dielectric sidewall and a second gate dielectric sidewall extending in a first direction and laterally spaced apart in a second direction different from the first direction. The trench isolation layer extends on opposite sides of the gate dielectric layer in a first direction. The trench isolation layer has a first isolation sidewall extending along the first gate dielectric sidewall in the first direction and a second isolation sidewall extending along the second gate dielectric sidewall in the first direction. The first isolation sidewall and the second isolation sidewall are laterally spaced apart in the second direction. The gate layer is located directly above the gate dielectric layer and between the first source / drain region and the second source / drain region. The gate layer has a first gate sidewall and a second gate sidewall extending in the first direction and laterally spaced apart in the second direction. The metal field plate is located directly above the gate layer and coupled to the gate layer. The first gate sidewall and the second gate sidewall are located directly above the gate dielectric layer and are laterally spaced apart from the first isolation sidewall and the second isolation sidewall, respectively, in the second direction.

[0102] In some embodiments, the drift region located in the semiconductor substrate extends laterally from the first high voltage well region along the second high voltage well region to the second source / drain region, and wherein the metal field plate extends in the first direction from directly above the gate layer to directly above the drift region.

[0103] In some embodiments, the gate layer has a third gate sidewall and a fourth gate sidewall extending in the second direction and spaced apart laterally in the first direction, wherein the fourth gate sidewall is located directly above the first high voltage well region and the third gate sidewall is located directly above the second high voltage well region, and wherein the metal field plate extends in the first direction from directly above the gate layer to laterally exceed the third gate sidewall.

[0104] In some embodiments, a lateral distance between the first gate sidewall and the first gate dielectric sidewall is greater than an average thickness of the gate dielectric layer.

[0105] In some embodiments, the gate dielectric layer extends laterally from the first source / drain region to the second source / drain region.

[0106] In some embodiments, the semiconductor substrate has a first semiconductor sidewall and a second semiconductor sidewall on opposite sides of the semiconductor upper surface, wherein the first semiconductor sidewall and the second semiconductor sidewall extend along the first isolation sidewall and the second isolation sidewall, respectively, in the first direction, wherein the first semiconductor sidewall is laterally spaced apart from the second semiconductor sidewall in the second direction, and wherein the first gate sidewall and the second gate sidewall are located directly above the semiconductor upper surface and are laterally spaced apart from the first semiconductor sidewall and the second semiconductor sidewall, respectively, in the second direction.

[0107] In some embodiments, a thickness of the gate dielectric layer along the first isolation sidewall and the second isolation sidewall is less than an average thickness of the gate dielectric layer.

[0108] In yet other embodiments, the disclosure relates to a method for forming an integrated chip. The method includes etching a semiconductor substrate to form a trench in the semiconductor substrate. The trench is bounded by a first sidewall of the semiconductor substrate and a second sidewall of the semiconductor substrate. The trench surrounds an active area of ​​the semiconductor substrate. A trench isolation layer is deposited in the trench. The first sidewall of the trench isolation layer extends along the first sidewall of the semiconductor substrate and the second sidewall of the trench isolation layer extends along the second sidewall of the semiconductor substrate. A first high voltage (HV) well region is formed in the semiconductor substrate. The first HV well region has a first doping type. A second HV well region is formed in the semiconductor substrate next to the first HV well region. The second HV well region has a second doping type different from the first doping type. A gate dielectric layer is formed above the first HV well region, above the second HV well region, and laterally between the first sidewall of the trench isolation layer and the second sidewall of the trench isolation layer. The gate dielectric layer has a first sidewall extending along the first sidewall of the trench isolation layer and a second sidewall extending along the second sidewall of the trench isolation layer. The thickness of the gate dielectric layer along the first side wall of the gate dielectric layer is less than the average thickness of the gate dielectric layer. A gate layer is deposited on the gate dielectric layer. The gate layer is etched so that the first side wall of the gate layer is located directly above the gate dielectric layer and is laterally retracted from the first side wall of the gate dielectric layer. A first source / drain region is formed in the first HV well region. The first source / drain region has a second doping type. A second source / drain region is formed in the second HV well region. The second source / drain region has a second doping type. A metal field plate coupled to the gate layer is formed directly above the gate layer.

[0109] In some embodiments, it further includes: before forming the first high voltage well region in the semiconductor substrate, etching the semiconductor substrate located between the first sidewall of the trench isolation layer and the second sidewall of the trench isolation layer to form a groove in the semiconductor substrate, wherein the gate dielectric layer is formed in the groove, and wherein forming the gate dielectric layer includes performing a thermal oxide growth process.

[0110] In some embodiments, the first source / drain region is laterally spaced apart from the second source / drain region in a first direction, wherein the first sidewall of the gate dielectric layer, the first sidewall of the trench isolation layer, and the first sidewall of the gate layer extend in the first direction, and wherein the first sidewall of the gate layer is laterally retracted from the first sidewall of the gate dielectric layer in a second direction different from the first direction.

[0111] In some embodiments, the metal field plate extends beyond the gate layer toward the second source / drain region and is located directly above the second high voltage well region.

[0112] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated chip, characterized in that include: Semiconductor substrate; a first source / drain region and a second source / drain region located in the semiconductor substrate and laterally spaced apart along a top surface of the semiconductor substrate; a gate dielectric layer located on the semiconductor substrate and extending laterally between the first source / drain region and the second source / drain region, wherein a thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer; a trench isolation layer extending along the gate dielectric layer on an opposite side of the gate dielectric layer, wherein a first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer; as well as A gate layer is located directly above the gate dielectric layer and between the first source / drain region and the second source / drain region, wherein a first sidewall of the gate layer is located directly above the gate dielectric layer and is laterally retracted from the first sidewall of the gate dielectric layer.

2. The integrated chip according to claim 1, characterized in that Also includes: A metal field plate is located directly above the gate layer and coupled to the gate layer.

3. The integrated chip according to claim 1, characterized in that The first sidewall of the trench isolation layer extends along a first sidewall of the semiconductor substrate, and wherein the first sidewall of the gate layer is laterally retracted from the first sidewall of the semiconductor substrate and the first sidewall of the trench isolation layer.

4. The integrated chip according to claim 1, characterized in that The first sidewall of the semiconductor substrate is spaced apart from the second sidewall of the semiconductor substrate, wherein the upper surface of the semiconductor substrate extends between the first sidewall of the semiconductor substrate and the second sidewall of the semiconductor substrate, and wherein the first sidewall of the gate layer is located directly above the upper surface of the semiconductor substrate.

5. The integrated chip according to claim 1, characterized in that The gate dielectric layer extends laterally from the first source / drain region to the second source / drain region.

6. The integrated chip according to claim 1, characterized in that The first source / drain region is laterally spaced apart from the second source / drain region in a first direction, wherein the first sidewall of the gate dielectric layer, the first sidewall of the trench isolation layer, and the first sidewall of the gate layer extend in the first direction, and wherein the first sidewall of the gate layer is laterally spaced apart from the first sidewall of the gate dielectric layer in a second direction different from the first direction.

7. An integrated chip, characterized in that include: Semiconductor substrate; a first high voltage (HV) well region located in the semiconductor substrate, the first high voltage well region having a first doping type; A second high voltage well region, located in the semiconductor substrate and laterally adjacent to the first high voltage well region, the second high voltage well region having a second doping type different from the first doping type; a first source / drain region located in the first high voltage well region and along the top surface of the semiconductor substrate, the first source / drain region having the second doping type; a second source / drain region located in the second high voltage well region, along the top surface of the semiconductor substrate, and laterally spaced apart from the first source / drain region in a first direction, the second source / drain region having the second doping type; a gate dielectric layer located above the first high voltage well region, above the second high voltage well region and laterally between the first source / drain region and the second source / drain region, the gate dielectric layer having a first gate dielectric sidewall and a second gate dielectric sidewall extending in the first direction and laterally spaced apart in a second direction different from the first direction; a trench isolation layer extending on opposite sides of the gate dielectric layer in the first direction, the trench isolation layer having a first isolation sidewall extending along the first gate dielectric sidewall in the first direction and a second isolation sidewall extending along the second gate dielectric sidewall in the first direction, wherein the first isolation sidewall is laterally spaced apart from the second isolation sidewall in the second direction; a gate layer located directly above the gate dielectric layer and between the first source / drain region and the second source / drain region, the gate layer having a first gate sidewall and a second gate sidewall extending in the first direction and laterally spaced apart in the second direction; as well as a metal field plate located directly above the gate layer and coupled to the gate layer, The first gate sidewall and the second gate sidewall are located directly above the gate dielectric layer and are laterally spaced apart from the first isolation sidewall and the second isolation sidewall in the second direction, respectively.

8. The integrated chip according to claim 7, characterized in that The drift region in the semiconductor substrate extends laterally from the first high voltage well region along the second high voltage well region to the second source / drain region, and the metal field plate extends in the first direction from directly above the gate layer to directly above the drift region.

9. An integrated chip, characterized in that include: a semiconductor substrate having a trench, wherein the trench is bounded by a first sidewall of the semiconductor substrate and a second sidewall of the semiconductor substrate, and wherein the trench surrounds an active area of ​​the semiconductor substrate; a trench isolation layer in the trench, wherein a first sidewall of the trench isolation layer extends along the first sidewall of the semiconductor substrate and a second sidewall of the trench isolation layer extends along the second sidewall of the semiconductor substrate; a first high voltage (HV) well region in the semiconductor substrate, the first high voltage well region having a first doping type; a second high voltage well region in the semiconductor substrate next to the first high voltage well region, the second high voltage well region having a second doping type different from the first doping type; a gate dielectric layer, above the first high voltage well region, above the second high voltage well region and laterally between the first sidewall of the trench isolation layer and the second sidewall of the trench isolation layer, the gate dielectric layer having a first sidewall extending along the first sidewall of the trench isolation layer and a second sidewall extending along the second sidewall of the trench isolation layer, wherein a thickness of the gate dielectric layer along the first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer; a gate layer above the gate dielectric layer, wherein a first sidewall of the gate layer is located directly above the gate dielectric layer and is laterally recessed from the first sidewall of the gate dielectric layer; a first source / drain region in the first high voltage well region, the first source / drain region having the second doping type; a second source / drain region in the second high voltage well region, the second source / drain region having the second doping type; as well as A metal field plate is directly above the gate layer and coupled to the gate layer.

10. The integrated chip according to claim 9, characterized in that The first source / drain region is laterally spaced apart from the second source / drain region in a first direction, wherein the first sidewall of the gate dielectric layer, the first sidewall of the trench isolation layer, and the first sidewall of the gate layer extend in the first direction, and wherein the first sidewall of the gate layer is laterally retracted from the first sidewall of the gate dielectric layer in a second direction different from the first direction.

Images