Semiconductor structure

Abstract

A semiconductor structure includes a photodiode in a substrate, a superabsorbent structure on the photodiode, an array of a plurality of nanoscale structures at least partially surrounding the superabsorbent structure. The array of nanoscale structures is substantially separated at fixed intervals. An array of nanoscale structures on photodiodes of a pixel array improves quantum efficiency of short wavelength light, such as green and blue light. The nanoscale structures may be used without a high-absorbing structure (e.g., when the pixel array is only configured to visible light), or may at least partially surround the high-absorbing structure (e.g., when the pixel array is simultaneously configured to visible light and near-infrared light). In addition to this, an array of nano-scale structures may be formed using photolithography such that the nano-scale structures are substantially separated at fixed intervals. Therefore, the quantum efficiency of the pixel array can be better improved compared with that of a nano-scale structure array formed by a random (or similar random) process (such as directed self-assembly).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure having an array of nanoscale structures. Background Art

[0002] Complementary metal oxide semiconductor (CMOS) image sensor (CIS) devices utilize light-sensitive CMOS circuits to convert light energy into electrical energy. The light-sensitive CMOS circuits may include photodiodes formed in a silicon substrate. When the photodiode is exposed to light, an electric charge is induced in the photodiode (called photocurrent). The photodiode may be coupled to a switching transistor, which is used to sample the charge of the photodiode. Color can be determined by placing a filter on the light-sensitive CMOS circuit.

[0003] The light received by the pixel sensors of a CMOS image sensor device is generally based on the three primary colors: red, green, and blue (R, G, B). The pixel sensors that sense each color of light can be defined by the use of color filters, which allow wavelengths of light of a specific color to pass through to the photodiode. Some pixel sensors may include near infrared (NIR) filters, which block visible light and allow near infrared light to pass through to the photodiode. Utility Model Content

[0004] One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a photodiode in a substrate. The semiconductor structure includes a highly absorptive structure on the photodiode and is configured to reflect infrared light toward the photodiode. The semiconductor structure includes an array of a plurality of nanoscale structures at least partially surrounding the highly absorptive structure and is configured to reflect visible light toward the photodiode. The array of nanoscale structures is generally spaced apart at regular intervals.

[0005] Another aspect of the present disclosure is to provide a semiconductor structure. The semiconductor structure includes a substrate; a plurality of pixel sensors in the substrate, wherein each of the pixel sensors includes a photodiode; an isolation structure surrounding the pixel sensors; a high absorption structure on the photodiode, wherein the high absorption structure extends from a top surface of the substrate into the substrate toward the photodiode; and a plurality of nanoscale structures on the photodiode and between the isolation structure and the high absorption structure, wherein the high absorption structure is at least partially surrounded by the nanoscale structure.

[0006] Another aspect of the present disclosure is to provide a semiconductor structure. The semiconductor structure includes a photodiode in a substrate. The semiconductor structure includes an array of multiple nanoscale structures on the photodiode and is configured to reflect visible light toward the photodiode, and the array of nanoscale structures is substantially separated by a fixed interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is better understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[0008] Figure 1 is a schematic diagram illustrating an exemplary environment in which the system and / or method described in the present disclosure may be implemented;

[0009] Figure 2 is a diagram illustrating an exemplary pixel array described in the present disclosure;

[0010] FIG. 3A to FIG. 3C is a schematic diagram illustrating an exemplary semiconductor structure described in the present disclosure;

[0011] FIG. 4A to FIG. 4M is a schematic diagram illustrating an exemplary embodiment of the present disclosure;

[0012] FIG. 5A to FIG. 5D is a schematic diagram illustrating an exemplary embodiment of the present disclosure;

[0013] Figure 6 It is a diagram of the disclosure Figure 1 a schematic diagram of exemplary elements of one or more devices;

[0014] Figure 7 is a flow chart illustrating an exemplary process of fabricating a semiconductor structure according to the present disclosure.

[0015]

Explanation of symbols

[0016] 100: Environment

[0017] 102:Semiconductor process tools / deposition tools

[0018] 104:Semiconductor process tools / exposure tools

[0019] 106:Semiconductor process tools / development tools

[0020] 108:Semiconductor process tools / etching tools

[0021] 110:Semiconductor process tools / planarization tools

[0022] 112:Semiconductor process tools / electroplating tools

[0023] 114:Semiconductor process tools / photoresist removal tools

[0024] 116:Semiconductor process tools / annealing tools

[0025] 118: Wafer / die transfer tool

[0026] 200: Pixel array

[0027] 202: Pixel sensor

[0028] 204: Deep Trench Isolation Structure

[0029] 300: Pixel Array

[0030] 302a, 302b: Pixel sensor

[0031] 304: Base material

[0032] 306: Photodiode

[0033] 308: Isolation Structure

[0034] 310: Anti-reflective coating

[0035] 312a: Metal layer

[0036] 312b: Dielectric layer

[0037] 314: Transmission Gate

[0038] 316: Highly absorbent structure

[0039] 318: Etching stop layer

[0040] 320,320a,320b,320c,320d,320e,320f: Nanoscale structures

[0041] 330,360: Pixel array

[0042] 332: Porosity

[0043] 334: Top surface

[0044] 400: Example

[0045] 402: Hard mask layer

[0046] 404: First Material

[0047] 406: Second Material

[0048] 408: Third Material

[0049] 410: Photoresist layer

[0050] 412a, 412b, 412c, 412d, 412e: nanoscale holes

[0051] 414: Groove

[0052] 450: Section view

[0053] 500: Example

[0054] 550: Section view

[0055] 600: Device

[0056] 610: Bus

[0057] 620: Processor

[0058] 630: Memory

[0059] 640: Input component

[0060] 650: Output component

[0061] 660: Communication Components

[0062] 700: Craftsmanship

[0063] 710,720,730,740,750,760,770,780,790: Blocks

[0064] AA:Line

[0065] d1,d2: depth

[0066] w1,w2,w3,w4: width DETAILED DESCRIPTION

[0067] The following disclosure provides many different embodiments or examples to implement different features of the novel invention. The specific examples of components and configurations described below are intended to simplify the disclosure. These are of course only examples and are not intended to be limiting. For example, the description of a first feature formed on or above a second feature includes embodiments in which the first feature and the second feature are in direct contact, and also includes embodiments in which other features are formed between the first feature and the second feature, so that the first feature and the second feature are not in direct contact. In addition, the disclosure repeats component symbols and / or letters in various specific examples. The purpose of this repetition is to simplify and clarify the description and does not indicate a relationship between the various discussed embodiments and / or configurations.

[0068] Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., are used to facilitate description of the relationship of parts or features illustrated in the drawings to other parts or features. Spatially relative terms encompass different orientations of the elements in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in the present disclosure may be interpreted so.

[0069] A pixel array (e.g., a back side illumination (BSI) complementary metal oxide semiconductor (CMOS) image sensor and / or other types of CMOS image sensors) is configured to detect visible light (e.g., light having a wavelength range of about 380 nm to about 750 nm), near infrared (NIR) light (e.g., light having a wavelength range of about 700 nm to about 1400 nm), or a combination thereof. In order to improve the quantum efficiency (QE) of the pixel array, a high absorption (HA) structure may be formed on the photodiode of the pixel array. In particular, the angled walls of the high absorption structure may be modified or change the direction of the refractive interface of the pixel array. The change in direction results in a smaller angle of refraction relative to a planar portion of the incident light at the same incident angle. Thus, the high absorption structure is directed toward the photodiode at a larger angle of incident light. The high absorption structure particularly improves the quantum efficiency of long wavelength light, such as red light and near infrared light.

[0070] Some embodiments described in the present disclosure provide techniques and apparatus for forming an array of nanoscale structures on a photodiode of a pixel array. Because the nanoscale structures are smaller than highly absorbing structures, the nanoscale structures improve the quantum efficiency of short wavelength light, such as green and blue light. The nanoscale structures can be used without highly absorbing structures (e.g., when the pixel array is configured only for visible light), or can at least partially surround highly absorbing structures (e.g., when the pixel array is configured for both visible light and near infrared light).

[0071] In addition, the array of nanoscale structures can be formed using photolithography so that the nanoscale structures are substantially spaced apart at regular intervals, thereby improving the quantum efficiency of the pixel array compared to if the array of nanoscale structures is formed using a random (or quasi-random) process such as directed self-assembly (DSA).

[0072] Figure 1 1 is a schematic diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, the environment 100 may include a plurality of semiconductor process tools 102 to 116 and a wafer / die transfer tool 118. The plurality of semiconductor process tools 102 to 116 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, a photoresist removal tool 114, an annealing tool 116, and / or other types of semiconductor process tools. The tools included in the exemplary environment 100 may be included in a semiconductor cleaning chamber, a semiconductor wafer foundry, a semiconductor process facility, and / or a manufacturing facility, among other examples.

[0073] Deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices that can be used to deposit various materials on a substrate. In some embodiments, deposition tool 102 includes a spin coating tool that can be used to deposit a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma enhanced atomic layer deposition (PEALD) tool, or other types of chemical vapor deposition tools. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other types of PVD tools. In some embodiments, the exemplary environment 100 includes a plurality of deposition tools 102 .

[0074] The exposure tool 104 is a semiconductor processing tool that can expose the photoresist layer to a radiation source, such as an ultraviolet (UV) light source [e.g., a deep UV light source, an extreme UV (EUV) light source, and / or the like], an X-ray light source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns used to form one or more semiconductor devices, can include patterns used to form one or more structures of a semiconductor device, can include patterns used to etch various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, an exposure machine, or a similar type of exposure tool.

[0075] The developing tool 106 is a semiconductor process tool that can develop the photoresist layer that has been exposed to the radiation source to develop the pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portion of the photoresist layer. In some embodiments, the developing tool 106 dissolves the exposed portion or the unexposed portion of the photoresist layer through the use of a chemical developer to develop the pattern.

[0076] The etching tool 108 is a semiconductor processing tool that can etch various types of substrates, wafers, or materials of semiconductor devices. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 can utilize plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which includes utilizing an ionized gas to etch the one or more portions isotropically or directionally.

[0077] The planarization tool 110 is a semiconductor process tool that can grind or planarize the layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or other types of planarization tools that can grind or planarize layers or surfaces of deposited or plated materials. The planarization tool 110 can combine chemical and mechanical forces (such as chemical etching and abrasive-free grinding) to grind or planarize the surface of the semiconductor device. The planarization tool 110 can use abrasives and corrosive chemical polishing liquids in combination with a polishing pad and a retaining ring (e.g., typically having a diameter larger than the semiconductor device). The polishing pad and the semiconductor device can be pressed together by a powered polishing head and held in place by a retaining ring. The powered polishing head can rotate on different rotation axes to remove material and equalize the irregular surface morphology of the semiconductor device to flatten or planarize the semiconductor device.

[0078] The electroplating tool 112 is a semiconductor processing tool that can electroplate a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the electroplating tool 112 can include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0079] The photoresist removal tool 114 is a semiconductor processing tool that can remove the remaining portion of the photoresist layer from the substrate after the etching tool 108 removes the portion of the substrate. For example, the photoresist removal tool 114 can use chemical strippers and / or other techniques to remove the photoresist layer from the substrate.

[0080] The annealing tool 116 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices that can heat a semiconductor substrate or a semiconductor device. For example, the annealing tool 116 may include a rapid thermal annealing (RTA) tool or other type of annealing tool that can heat a semiconductor substrate to cause a reaction between two or more materials or gases or to cause material decomposition. In another specific example, the annealing tool 116 may be configured to heat (e.g., increase or increase its temperature) a structure or layer (or portion thereof) to reflow the structure or layer, or crystallize the structure or layer to remove defects such as pores or seams. In another specific example, the annealing tool 116 may be configured to heat (e.g., increase or increase its temperature) a layer (or portion thereof) to bond two or more semiconductor devices.

[0081] The wafer / die transfer tool 118 may be included in a cluster tool or other type of tool including multiple process chambers, and is configured to transfer substrates and / or semiconductor devices between multiple process chambers, between a process chamber and a buffer area, between a process chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or between a process chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some embodiments, the wafer / die transfer tool 118 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-clean process tool (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations).

[0082] In some embodiments, one or more of the semiconductor process tools 102 to the semiconductor process tools 116 and / or the wafer / die transfer tool 118 can perform one or more semiconductor process operations described herein. For example, the semiconductor process tools 102 to the semiconductor process tools 116 and / or the wafer / die transfer tool 118 can form a hard mask layer on a substrate including a photodiode, deposit a first material having a first rectangular pattern on the hard mask layer, deposit a second material along the sidewalls of the first rectangular pattern, remove the first material so that the second material remains in the second rectangular pattern, deposit a third material along the sidewalls of the second rectangular pattern, remove the second material so that the third material remains in the third rectangular pattern, etch the hard mask layer to extend the third rectangular pattern into the hard mask layer, remove the third material so that the hard mask layer remains in the third rectangular pattern, perform a lithography operation using the hard mask layer to form an array of nanoscale holes in the substrate and / or form an array of nanoscale structures by depositing a dielectric material in the array of nanoscale holes, and other examples.

[0083] Figure 1 The number and arrangement of devices shown are provided as one or more specific examples. In practice, there may be additional devices, fewer devices, different devices, or different Figure 1 The device configuration shown. Furthermore, Figure 1 Two or more of the devices shown may be used in a single device, or Figure 1The single device shown may be used in a variety of distributed devices. For example, deposition tool 102 may include electroplating tool 112. Additionally or alternatively, one set of devices (e.g., one or more devices) of example environment 100 may perform one or more functions performed by another set of devices of example environment 100.

[0084] Figure 2 2 is an illustration of an exemplary pixel array 200 (or a portion thereof) described herein. Pixel array 200 may be included in an image sensor, such as a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0085] Figure 2 FIG. 2 shows a top view of the pixel array 200. Figure 2 As shown, the pixel array 200 may include a plurality of pixel sensors 202. Figure 2 As shown, the pixel sensors 202 may be arranged in a grid. In some embodiments, the pixel sensors 202 are square (eg, Figure 2 In some embodiments, the pixel sensor 202 includes other shapes, such as a circle, an octagon, a diamond, and / or other shapes.

[0086] Pixel sensor 202 may be configured to sense and / or accumulate incident light (e.g., light directed toward pixel array 200). For example, pixel sensor 202 may absorb and accumulate photons of incident light. Photons accumulated in a photodiode may generate a charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a greater intensity or brightness, while a smaller amount of charge may correspond to a lower intensity or brightness).

[0087] The pixel sensors 202 may be electrically and optically isolated by a deep trench isolation (DTI) structure 204 included in the pixel array 200. The DTI structure 204 may include a plurality of interconnect trenches filled with a dielectric material, such as an oxide material. The DTI structure 204 may be included around the periphery of the pixel sensors 202 such that the DTI structure 204 surrounds the pixel sensors 202, such as Figure 2 . Furthermore, the trench of the deep trench isolation structure 204 can extend into the substrate, wherein the pixel sensor 202 is formed to surround the photodiode and other structures of the pixel sensor 202 in the substrate. As described above, the pixel array 200 can be included in a BSI CMOS image sensor. In these embodiments, the deep trench isolation structure 204 can include a back side deep trench isolation (BDTI) structure with a high aspect ratio, which is formed from the back side of the pixel array 200.

[0088] Pixel array 200 may be electrically connected to a back-end-of-line (BEOL) metal stack (not shown) of an image sensor. The BEOL metal stack may electrically connect pixel array 200 to a control circuit that may be used to measure the amount of incident light accumulated in pixel sensor 202 and convert the measured value into an electrical signal.

[0089] As mentioned above, Figure 2 is provided as a specific example. Figure 2 Other specific examples may be different from those described.

[0090] Figure 3A is a schematic diagram of an exemplary pixel array 300 described in the present disclosure. Each pixel of the exemplary pixel array 300 has two photodiodes. Figure 3A The exemplary pixel array 300 in FIG. 1 may include or may be included in the pixel array 200 (or a portion thereof). In some embodiments, the pixel array 300 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0091] like Figure 3A As shown, pixel array 300 may include a plurality of adjacent pixel sensors, such as pixel sensor 302a and pixel sensor 302b. In some embodiments, pixel sensor 302a and pixel sensor 302b are configured as square pixel sensors 202 included in pixel array 200. In some embodiments, pixel sensor 302a and pixel sensor 302b are configured as octagonal pixel sensors and / or square pixel sensors. In some embodiments, pixel sensor 302a and pixel sensor 302b include additional or other shapes of pixel sensors or combinations thereof.

[0092] Pixel sensor 302a and pixel sensor 302b may be formed in substrate 304, wherein substrate 304 may include a semiconductor die substrate, a semiconductor wafer, or other types of substrates in which semiconductor pixels may be formed. In some embodiments, substrate 304 is made of silicon (Si), materials including silicon, III-V compound semiconductor materials such as gallium arsenide (GaAs), silicon on insulator (SOI), or other types of semiconductor materials that can generate charges from incident light photons.

[0093] Each of pixel sensor 302a and pixel sensor 302b may include a photodiode 306. Photodiode 306 may include a region of substrate 304 doped with various types of ions to form a pn junction or a PIN junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) portion, and an n-type portion). For example, substrate 304 is doped with n-type dopants to form a first portion (e.g., an n-type portion) of photodiode 306, and is doped with p-type dopants to form a second portion (e.g., a p-type portion) of photodiode 306. Photodiode 306 is configured to absorb photons of incident light. The absorption of photons causes photodiode 306 to accumulate charge (referred to as a photocurrent) due to the photoelectric effect. Thereby, photons strike photodiode 306, which causes photodiode 306 to emit electrons. The emission of electrons causes the generation of electron-hole pairs, wherein the electrons migrate toward the cathode of photodiode 306 and the holes migrate toward the anode, thereby generating a photocurrent.

[0094] Isolation structures 308 may be included in substrate 304 between adjacent pixel sensors. Isolation structures 308 may provide optical isolation by blocking or preventing light from diffusing or escaping from one of the pixel sensors to another of the pixel sensors, thereby reducing crosstalk between adjacent pixel sensors. Isolation structures 308 may include trenches or deep trench isolation structures (e.g., deep trench isolation structures 204) covered or laid with an antireflective coating (ARC) 310 and filled with an oxide layer (e.g., on the ARC 310). Isolation structures 308 may be formed in a grid layout, wherein isolation structures 308 extend around pixel sensors 302a and pixel sensors 302b in pixel array 300 and are staggered in various locations of pixel array 300. In some embodiments, as Figure 3A As shown, the isolation structure 308 may surround multiple groups of pixel sensors (eg Figure 3A ). Instead, refer to Figure 3B As described above, the isolation structure 308 may surround each pixel sensor individually.

[0095] An anti-reflective coating 310 may be included in the isolation structure 308 and on the substrate 304 above the photodiode 306. The anti-reflective coating 310 may include a suitable material to reduce reflection of incident light projected toward the photodiode 306. For example, the anti-reflective coating 310 may include a nitrogen-containing material.

[0096] Metal layer 312a may be included on and / or over isolation structure 308. Metal layer 312a may include a metallization material such as tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), other conductive materials, and / or alloys including one or more of the foregoing. Metal layer 312a may be etched such that a mesh structure is formed between pixel sensor 302a and pixel sensor 302b and over isolation structure 308. The mesh structure may include a plurality of interconnecting posts of metal layer 312a. The mesh structure may surround pixel sensor 302a and pixel sensor 302b and may be configured to provide additional crosstalk reduction and / or mitigation in conjunction with isolation structure 308.

[0097] In some embodiments, the mesh structure may additionally or alternatively include a dielectric layer 312b. Thus, in one embodiment, the mesh structure may include a hybrid structure having a metal layer 312a and a dielectric layer 312b. The dielectric layer 312b may include an oxide material, such as silicon oxide (SiO x ) (such as silicon dioxide (SiO2)), silicon nitride (SiN x ), Silicon Carbide (SiC x ), titanium nitride (TiN x ), Tantalum Nitride (TaN x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ) or aluminum oxide (AlO x ) or other dielectric materials that may be combined with the isolation structure 308 to provide additional crosstalk reduction and / or mitigation.

[0098] Each of pixel sensor 302a and pixel sensor 302b may include a transmission gate 314 to control the transmission of photocurrent between photodiode 306 and a drain region (not shown). Transmission gate 314 may be energized (e.g., by applying a voltage or current to transmission gate 314) to cause a conductive channel to form between photodiode 306 and the drain region (and / or drain extension region). The conductive channel may be removed or closed by de-energizing transmission gate 314, which blocks and / or prevents photocurrent from flowing between photodiode 306 and the drain region (and / or drain extension region). Thus, transmission gate 314 facilitates electronic communication between pixel sensor 302a and pixel sensor 302b and a BEOL metal stack (not shown) that is used to measure the amount of incident light accumulated within pixel sensor 302a and pixel sensor 302b and convert this measurement into an electrical signal.

[0099] Pixel array 300 may further include a high absorption structure 316 in substrate 304. High absorption structure 316 may be located near the center of the periphery or inner boundary of isolation structure 308 so that high absorption structure 316 is located above and / or over photodiode 306. High absorption structure 316 may include a shallow trench filled with a dielectric material, such as silicon oxide (SiO x The high absorbency structure 316 may include a structure having angled walls so that the structure has a generally pyramidal appearance (eg, approximately triangular in cross-sectional view, such as Figure 3A As shown, and in the top view, it is approximately polygonal, for example, approximately rectangular, as shown Figure 3C As shown, or a nearly triangular shape). As described in the present disclosure, a "pyramid shape" may refer to a structure having a multi-sided base connected to a point as a vertex or to a smaller polygon. High absorption structure 316 may extend from the top surface of substrate 304 into substrate 304 toward photodiode 306.

[0100] The high absorption structure 316 can increase the absorption of incident light (thereby increasing the quantum efficiency of the pixel array) by modifying or changing the direction of the refractive interface of a portion of the top surface of the substrate 304. This change in direction results in a smaller angle of refraction relative to a planar portion of the incident light at the same incident angle. Therefore, the high absorption structure 316 is directed toward the pixel sensors 302a and 302b at a larger angle of incident light than if the high absorption structure 316 were not included in the pixel array 300.

[0101] In some embodiments, an etch stop layer (ESL) 318 can prevent over-etching of the substrate 304. The etch stop layer includes a material that is resistant (or at least partially resistant) to a particular type of dry etching and / or wet etching. The etch stop layer can include a material that is resistant to an etchant that can otherwise be used to etch other layers near the etch stop layer. Selecting this material provides etch selectivity and can cause the etch stop layer to remain unetched (or largely unetched) while other layers are etched. For example, the etch stop layer 318 can include a nitride (e.g., aluminum nitride (AlN) and / or silicon nitride (SiN)) and / or an oxide (e.g., silicon oxynitride (SiO x N y ), aluminum oxynitride (AlON) and / or silicon oxide (SiO x )). In some embodiments, the etch stop layer 318 includes a plurality of etch stop layers stacked together and configured to serve as a single etch stop layer.

[0102] The pixel array 300 may further include nanoscale structures 320 (e.g., nanoscale structures 320a, nanoscale structures 320b, nanoscale structures 320c, nanoscale structures 320d, nanoscale structures 320e, and nanoscale structures 320f) in the substrate 304. As used herein, "nanoscale" means that the size (e.g., width and / or height) is less than about 100 nm. The nanoscale structures 320 may be located around or within the inner boundary of the isolation structure 308, and are generally physically smaller than the deep trench isolation structure 308. The nanoscale structures 320 may be filled with a dielectric material, such as silicon oxide (SiO x In some embodiments, nanoscale structures 320 are filled with a combination of materials that act as dielectrics. Nanoscale structures 320 are configured to reduce the amount of incident light reflected by the top surface of substrate 304 and are configured to refract incident light toward photodiode 306 toward substrate 304.

[0103] High absorption structure 316 improves the quantum efficiency of pixel array 300 for light with longer wavelengths, such as red light (e.g., incident light with a wavelength of approximately 650 nm) and near infrared light (e.g., incident light in the near infrared wavelength range). Since nanoscale structure 320 is smaller than high absorption structure 316, nanoscale structure 320 improves the quantum efficiency for light with shorter wavelengths, such as green light (e.g., incident light with a wavelength of approximately 550 nm) and blue light (e.g., incident light with a wavelength of approximately 450 nm).

[0104] Figure 3B 3 is a schematic diagram of an exemplary pixel array 330 of the present disclosure. The exemplary pixel array 330 has one photodiode per pixel instead of two photodiodes per pixel. Figure 3B The exemplary pixel array 330 in FIG. 1 may include or may be included in the pixel array 200 (or a portion thereof). In some embodiments, the pixel array 330 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0105] Figure 3B The exemplary pixel array 330 is similar to Figure 3A 300. Figure 3B As shown, the isolation structure 308 surrounds each photodiode 306 individually, rather than in groups. Figure 3B As shown, isolation structure 308 includes apertures 332 within each trench to further reduce crosstalk between adjacent pixel sensors.

[0106] Further Figure 3BAs shown, each trench within the isolation structure 308 may have a depth (e.g., represented by d1) relative to the top surface 334 of the substrate 304. The depth d1 ranges from about 3 micrometers (μm) to about 5 μm. Providing a depth of at least 3 μm provides electrical isolation between adjacent pixel sensors to reduce optical crosstalk. Providing a depth of no more than 5 μm allows the photodiode to remain undamaged during the formation of the isolation structure 308. In addition, each of the photodiodes 306 may have a depth (e.g., represented by d2) relative to the top surface 334 of the substrate 304. The depth d1 ranges from about 5 micrometers (μm) to about 7 μm. Using a depth of at least 5 μm allows the bulk silicon of the substrate 304 to perform photoelectron conversion of incoming photons into current. Using a depth of no more than 7 μm allows the pixel array 330 to be minimized for inclusion in an electronic package. Therefore, a ratio of a depth d1 of the isolation structure 308 from the top surface 334 to a depth d2 of the photodiode 306 from the top surface 334 ranges from about 0.5 to about 0.8.

[0107] Figure 3C 3 is a schematic diagram of an exemplary pixel array 360 described in the present disclosure. Exemplary pixel array 360 is similar to exemplary pixel array 330, but exemplary pixel array 360 is shown in a top view rather than a cross-sectional view. Figure 3C The exemplary pixel array 360 in FIG. 3 may include or may be included in the pixel array 200 (or a portion thereof). In some embodiments, the pixel array 360 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0108] Compared to Figure 3A and Figure 3B A cross-sectional view of Figure 3C is a top view. Figure 3C As shown, the top layer of the isolation structure (eg Figure 3C Each photodiode (or a group of photodiodes) is surrounded by a metal layer 312a in the embodiment or a dielectric layer 312b in other embodiments. On each photodiode is a highly absorbing structure 316, and the highly absorbing structure 316 is at least partially surrounded by an array of nanoscale structures 320.

[0109] Further Figure 3CAs shown, nanoscale structures 320 are generally spaced apart at fixed intervals. As used herein, "fixed interval" means that the distance between adjacent structures in the array is approximately equal (e.g., within a 1%, 10% or similar error range) to the distance between other adjacent structures in the same array. Additionally or alternatively, "fixed interval" means that the distance between adjacent structures in a row is approximately equal (e.g., within a 1%, 10% or similar error range) to the distance between other adjacent structures in the same row. The array of nanoscale structures 320 is generally spaced apart at fixed intervals because the nanoscale structures 320 are patterned by photolithography, as described with reference to FIG. FIG. 4A to FIG. 4M as described, rather than by a random (or quasi-random) process.

[0110] As mentioned above, FIG. 3A to FIG. 3C is provided as a specific example. FIG. 3A to FIG. 3C Other specific examples may be different from those described.

[0111] FIG. 4A to FIG. 4M is a schematic diagram illustrating an exemplary embodiment 400 of the present disclosure. Exemplary embodiment 400 may be an exemplary process for forming pixel array 300. Exemplary embodiment 400 may include a patterning technique for forming an array of nanoscale structures 320 of pixel array 300. FIG. 4A to FIG. 4M The nanoscale structures 320 obtained by the patterning technique are generally separated by a fixed interval.

[0112] FIG. 4A to FIG. 4J 4 is a top view of a pixel array of the exemplary embodiment 400 and a cross-sectional view 450 along line AA. Figure 4A As shown, exemplary processes for forming a pixel array may be performed with respect to substrate 304 .

[0113] As described above, substrate 304 may include a semiconductor die substrate, a semiconductor wafer, a stacked semiconductor wafer, or other types of substrates in which semiconductor pixels may be formed. For example, substrate 304 is made of silicon (Si) (e.g., a silicon substrate), a material including silicon, a III-V compound semiconductor material (e.g., gallium arsenide (GaAs)), silicon on insulator (SOI), or other types of semiconductor materials that can generate charges from incident light photons. In some embodiments, substrate 304 is composed of a doped material (e.g., a p-doped material or an n-doped material) such as doped silicon.

[0114] In addition, the substrate 304 may have a photodiode formed therein. The photodiode is not shown in FIG. FIG. 4A to FIG. 4M308 because the photodiode will be deeper in the substrate 304 than shown in the figure. In addition, an isolation structure (such as a deep trench isolation structure) can be included in the substrate 304 and at least partially surround the photodiode. The isolation structure 308 is not shown in FIG. FIG. 4A to FIG. 4M , because the isolation structure surrounds the portion of the substrate 304 shown in the figure.

[0115] like Figure 4A As shown, a hard mask layer 402 may be formed on the substrate 304. For example, the deposition tool 102 may form the hard mask layer 402 on and / or above the front surface of the substrate 304 (e.g., on the top surface of the substrate 304). The hard mask layer 402 may include a metal material, an oxide material (e.g., silicon oxide (SiO x )) and / or other types of dielectric materials. In some embodiments, the hard mask layer 402 may include a high dielectric constant (high-k) material. Specific examples of high-k dielectric materials include high dielectric constant metal oxides, such as hafnium oxide (HfO x ), aluminum oxide (Al x O y )、ZrO x ), magnesium oxide (MgO x ), yttrium oxide (Y x O y ), Tantalum Oxide (Ta x O y ), titanium oxide (TiO x ), lanthanum oxide (La x O y ), barium oxide (BaO x ) or other types of high-k metal oxides. In some embodiments, the deposition tool 102 may form the hard mask layer 402 using a spin coating technique, a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, and / or other deposition techniques.

[0116] Further Figure 4A As shown, first material 404 may be formed on hard mask layer 402. For example, deposition tool 102 may form first material 404 on and / or over the front surface of substrate 304 (e.g., on hard mask layer 402). First material 404 may include metal (e.g., titanium nitride (TiN), tungsten (W), and / or aluminum (Al), among other examples) and / or other materials that may be etched separately from hard mask layer 402 (e.g., by using different etchants and / or different etching techniques). In some embodiments, deposition tool 102 may form first material 404 using spin coating techniques, chemical vapor deposition techniques, physical vapor deposition techniques, atomic layer deposition techniques, and / or other deposition techniques.

[0117] like Figure 4B4. As shown, a portion of first material 404 is removed. For example, deposition tool 102 may form a photoresist layer on and / or over the front surface of first material 404, exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and development tool 106 may develop and remove a portion of the photoresist layer to expose the pattern. Thus, etching tool 108 may etch a portion of first material 404. For example, etching tool 108 may use a wet etching technique, a dry etching technique, a plasma-assisted etching technique, and / or other types of etching techniques to etch a portion of first material 404. After etching tool 108 removes a portion of first material 404, photoresist removal tool 114 may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0118] Further Figure 4B As shown, the first material 404 may remain in the first rectangular pattern. In the exemplary embodiment 400, the first rectangular pattern is shorter along the direction parallel to the line AA than the direction perpendicular to the line AA. In some embodiments, the first rectangular pattern of the first material 404 may include a structure having a width (e.g., represented by w1). The width w1 ranges from about 50 nm to about 80 nm. Providing a width of at least 50 nm provides for the deposition of the second material 406 (e.g., referring to Figure 4C Providing a width of no more than 80 nm allows the formation of nanoscale structures (e.g., see Figure 4M In addition, adjacent structures of the first rectangular pattern may be separated from each other by a width (e.g., denoted by w2). The width w2 ranges from about 60 nm to about 120 nm. Providing a width of at least 60 nm allows the formation of nanoscale structures separated from each other (e.g., referring to Figure 4M Providing a width of no more than 120 nm allows the formation of sufficiently dense nanoscale structures (e.g., see Figure 4M Thus, the ratio of the width w1 of the first material 404 to the width w2 between the portions of the first material 404 is in the range of about 0.4 to about 0.8.

[0119] like Figure 4C As shown, the second material 406 may be formed on the first rectangular pattern. For example, the deposition tool 102 may form the second material 406 on and / or over the front surface of the substrate 304 (e.g., on the first material 404). The second material 406 may include a nitride (e.g., silicon nitride (Si3N4), and other examples therein) and / or other materials that may be selectively deposited on the first material 404. Thus, as Figure 4CAs shown, the second material 406 is deposited on the top surface and sidewalls of the first rectangular pattern, but not on the exposed surface of the hard mask layer 402. In addition, the second material 406 may include a material that can be etched separately from the hard mask layer 402 (e.g., by using different etchants and / or different etching techniques). In some embodiments, the deposition tool 102 may form the second material 406 using a spin coating technique, a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, and / or other deposition techniques.

[0120] like Figure 4D 4. As shown, a portion of the second material 406 is removed. For example, the deposition tool 102 may form a photoresist layer on and / or over the front surface of the second material 406, the exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and the development tool 106 may develop and remove a portion of the photoresist layer to expose the pattern. Thus, the etching tool 108 may etch a portion of the second material 406. For example, the etching tool 108 may use a wet etching technique, a dry etching technique, a plasma-assisted etching technique, and / or other types of etching techniques to etch a portion of the second material 406. After the etching tool 108 removes the portion of the second material 406, the photoresist removal tool 114 may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0121] Alternatively, the etching tool 108 may perform an anisotropic etching cycle (eg, using plasma or other types of dry etching) to remove the portion of the second material 406 on the top surface of the first rectangular pattern. Thus, the second material 406 remains only on the sidewalls of the first rectangular pattern.

[0122] like Figure 4E As shown, first material 404 is removed. For example, deposition tool 102 may form a photoresist layer on and / or over the front surface of first material 404, exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and development tool 106 may develop and remove a portion of the photoresist layer to expose the pattern. Thus, etching tool 108 may etch first material 404. For example, etching tool 108 may use a wet etching technique, a dry etching technique, a plasma-assisted etching technique, and / or other types of etching techniques to etch first material 404. After etching tool 108 removes first material 404, photoresist removal tool 114 may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0123] Alternatively, the etching tool 108 may perform an isotropic etching cycle (e.g., using dry etching or wet etching) to remove the first material 404. For example, the second material 406 may be selected to be resistant to the etchant and / or etching technique used to remove the first material 404. Therefore, the second material 406 remains in the second rectangular pattern. In the exemplary embodiment 400, the second rectangular pattern is shorter along the direction parallel to line AA than in the direction perpendicular to line AA. In some embodiments, the second rectangular pattern of the second material 406 may include a structure having a width (e.g., represented by w3). The width w3 ranges from about 10 nm to about 40 nm. Providing a width of at least 10 nm provides for the deposition of the third material 408 (e.g., referring to Figure 4F Providing a width of no more than 40 nm allows the formation of nanoscale structures (e.g., see Figure 4M In addition, adjacent structures of the second rectangular pattern may be separated from each other by a width (e.g., denoted by w4). The width w4 ranges from about 30 nm to about 120 nm. Providing a width of at least 30 nm allows the formation of nanoscale structures separated from each other (e.g., referring to Figure 4M Providing a width of no more than 120 nm allows the formation of sufficiently dense nanoscale structures (e.g., see Figure 4M As described above, the quantum efficiency of the pixel array for visible light is improved. Therefore, the ratio of the width w3 of the second material 406 to the width w4 between the portions of the second material 406 is in the range of about 0.1 to about 0.3.

[0124] like Figure 4F As shown, the third material 408 may be formed on the second rectangular pattern. For example, the deposition tool 102 may form the third material 408 on and / or above the front surface of the substrate 304 (e.g., on the second material 406). The third material 408 may include a metal material, an oxide material, and / or other materials that may be selectively deposited on the second material 406. Figure 4F As shown, the third material 408 is deposited on the top surface and sidewalls of the second rectangular pattern, but not on the exposed surface of the hard mask layer 402. In addition, the third material 408 may include a material that can be etched separately from the hard mask layer 402 (e.g., by using different etchants and / or different etching techniques). In some embodiments, the deposition tool 102 may form the third material 408 using a spin coating technique, a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, and / or other deposition techniques.

[0125] like Figure 4GAs shown, a portion of third material 408 is removed. For example, deposition tool 102 may form a photoresist layer on and / or over the front side surface of third material 408, exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and development tool 106 may develop and remove a portion of the photoresist layer to expose the pattern. Thus, etching tool 108 may etch a portion of third material 408. For example, etching tool 108 may use a wet etching technique, a dry etching technique, a plasma assisted etching technique, and / or other types of etching techniques to etch a portion of third material 408. After etching tool 108 removes a portion of third material 408, photoresist removal tool 114 may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0126] Alternatively, the etching tool 108 may perform an anisotropic etching cycle (eg, using plasma or other types of dry etching) to remove portions of the third material 408 on the top surface of the second rectangular pattern. Thus, the third material 408 remains only on the sidewalls of the second rectangular pattern.

[0127] like Figure 4H 4. As shown, the second material 406 is removed. For example, the deposition tool 102 may form a photoresist layer on and / or over the front surface of the second material 406, the exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and the development tool 106 may develop and remove a portion of the photoresist layer to expose the pattern. Thus, the etching tool 108 may etch the second material 406. For example, the etching tool 108 may use a wet etching technique, a dry etching technique, a plasma-assisted etching technique, and / or other types of etching techniques to etch the second material 406. After the etching tool 108 removes the second material 406, the photoresist removal tool 114 may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0128] Alternatively, the etching tool 108 may perform an isotropic etching cycle (e.g., using dry etching or wet etching) to remove the second material 406. For example, the third material 408 may be selected to be resistant to the etchant and / or etching technique used to remove the second material 406. Therefore, the third material 408 remains in the third rectangular pattern. In the exemplary embodiment 400, the third rectangular pattern is shorter along the direction parallel to line AA than in the direction perpendicular to line AA. In some embodiments, the third rectangular pattern of the third material 408 may include a structure having a width (e.g., represented by w3). The width w3 ranges from about 10 nm to about 40 nm. Providing a width of at least 10 nm allows the formation of sufficiently large nanoscale structures (e.g., see Figure 4MProviding a width of no more than 40 nm allows the formation of nanoscale structures (e.g., see Figure 4M In addition, adjacent structures of the third rectangular pattern may be separated from each other by a width (e.g., denoted by w3). The width w3 ranges from about 10 nm to about 40 nm. Providing a width of at least 10 nm allows the formation of nanoscale structures separated from each other (e.g., referring to Figure 4M Providing a width of no more than 40 nm allows the formation of sufficiently dense nanoscale structures (e.g., see Figure 4M As described above), the quantum efficiency of the pixel array for visible light is improved. Therefore, the ratio of the width of the second material 406 to the width between the portions of the second material 406 is in the range of about 0.1 to about 0.3. For example, the width of the third material 408 is approximately equal to the width between the portions of the third material 408, such as Figure 4H shown.

[0129] like Fig. 4I As shown, a portion of the hard mask layer 402 is removed. For example, the deposition tool 102 may form a photoresist layer on and / or over the front surface of the hard mask layer 402, the exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and the development tool 106 may develop and remove a portion of the photoresist layer to expose the pattern. Thus, the etching tool 108 may etch a portion of the hard mask layer 402. For example, the etching tool 108 may use a wet etching technique, a dry etching technique, a plasma assisted etching technique, and / or other types of etching techniques to etch a portion of the hard mask layer 402. After the etching tool 108 removes the portion of the hard mask layer 402, the photoresist removal tool 114 may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0130] Alternatively, the etching tool 108 may perform an anisotropic etching cycle (e.g., using plasma or other types of dry etching) to remove portions of the hard mask layer 402 that are not beneath the remaining portions of the third material 408. For example, the third material 408 may be selected to be resistant to the etchant and / or etching technique used to remove the hard mask layer 402. Thus, the third rectangular pattern extends into the hard mask layer 402. In some embodiments, the third rectangular pattern also extends into the substrate 304. For example, the etching tool 108 may perform etching until a threshold is met (e.g., by performing an etching cycle for a period of time that includes a time threshold). Alternatively, an etch stop layer may be located between the hard mask layer 402 and the substrate 304 to prevent etching of the substrate 304.

[0131] like Figure 4JAs shown, the third material 408 is removed. For example, the deposition tool 102 may form a photoresist layer on and / or over the front surface of the third material 408, the exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and the development tool 106 may develop and remove a portion of the photoresist layer to expose the pattern. Thus, the etching tool 108 may etch the third material 408. For example, the etching tool 108 may use a wet etching technique, a dry etching technique, a plasma assisted etching technique, and / or other types of etching techniques to etch the third material 408. After the etching tool 108 removes the third material 408, the photoresist removal tool 114 may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0132] Alternatively, the etching tool 108 may perform an isotropic etching cycle (e.g., using dry etching or wet etching) to remove the third material 408. For example, the hard mask layer 402 may be selected to be resistant to the etchant and / or etching technique used to remove the third material 408. Therefore, the hard mask layer 402 remains in the third rectangular pattern.

[0133] like Figure 4K As shown, the photoresist layer 410 is formed on the substrate 304. For example, the deposition tool 102 can form the photoresist layer 410 on and / or over the front surface of the substrate 304 (eg, on the exposed surface of the hard mask layer 402 and the substrate 304). Figure 4K As shown, the exposure tool 104 can expose the photoresist layer 410 to a radiation source to form a pattern on the photoresist layer 410, and the development tool 106 can develop and remove a portion of the photoresist layer 410 to expose the pattern. For example, the pattern can separate the third rectangular pattern so that the exposed portion of the substrate 304 has a substantially square cross-section (e.g., in a top view). As described herein, "square" means a polygon with four substantially equal sides (e.g., within a 1%, 10% or similar error range).

[0134] In some embodiments, Figure 4K As shown, the pattern of the photoresist layer 410 may extend along the boundary of the corresponding isolation structure (not shown). Therefore, the isolation structure is formed before the nano-scale structure 320a to the nano-scale structure 320e. Alternatively, the isolation structure may be formed after the nano-scale structure 320a to the nano-scale structure 320e.

[0135] Figure 4L and Figure 4M A top view of a pixel array and a cross-sectional view 450 along line AA of the exemplary embodiment 400 are shown. Figure 4LAs shown, a portion of the substrate 304 is removed. For example, the etching tool 108 may use a wet etching technique, a dry etching technique, a plasma-assisted etching technique, and / or other types of etching techniques to etch the substrate 304. The etching tool 108 may etch the exposed portion of the substrate 304 according to the pattern of the photoresist layer 410. As a result, an array of nanoscale holes (e.g., nanoscale holes 412a, nanoscale holes 412b, nanoscale holes 412c, nanoscale holes 412d, and nanoscale holes 412e) is formed in the substrate 304.

[0136] Further Figure 4L As shown, after the etching tool 108 removes a portion of the substrate 304, the photoresist removal tool 114 can remove the remaining portion of the photoresist layer 410 (eg, using chemical strippers, plasma ashing, and / or other techniques). Figure 4L As shown, the hard mask layer 402 is removed. For example, the etching tool 108 may etch the hard mask layer 402 using a wet etching technique, a dry etching technique, a plasma assisted etching technique, and / or other types of etching techniques.

[0137] like Figure 4M As shown, nanoscale holes 412a to 412e are filled with dielectric material to form an array of nanoscale structures 320a to 320e. The deposition tool 102 may deposit the dielectric material using spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other deposition techniques. In some embodiments, the dielectric material overflows from the nanoscale holes 412a to 412e, and the planarization tool 110 removes the dielectric material outside the nanoscale holes 412a to 412e using chemical mechanical planarization.

[0138] Since the array of nanoscale holes 412a-412e is small, nanoscale structure 320 refracts visible light toward a photodiode (not shown) of the pixel sensor. Therefore, the array of nanoscale structures 320a-320e increases the quantum efficiency of the pixel sensor for visible light.

[0139] As mentioned above, FIG. 4A to FIG. 4M is provided as a specific example. FIG. 4A to FIG. 4M Other specific examples may be different from those described above. For example, in some embodiments, the first material 404 is patterned to have smaller widths w1 and w2. Therefore, the rectangular pattern of the second material 406 can extend into the hard mask layer 402, and the nano-scale structures 320a to 320d can still be obtained without depositing the third material 408.

[0140] FIG. 5A to FIG. 5Dis a schematic diagram illustrating an exemplary embodiment 500 of the present disclosure. Exemplary embodiment 500 may be an exemplary process for forming pixel array 300. Exemplary embodiment 500 may include a patterning technique for forming an array of nanoscale structures 320 of pixel array 300. FIG. 5A to FIG. 5C The nanoscale structures 320 obtained by the patterning technique are generally separated by a fixed interval.

[0141] Figure 5A 5 is a top view of a pixel array of the exemplary embodiment 500 and a cross-sectional view 550 along line AA. Figure 5A As shown, an exemplary process for forming a pixel array with respect to a substrate 304 and a patterned hard mask layer 402 may be performed. The hard mask layer 402 may refer to FIG. 4A to FIG. 4J As described above, it is patterned.

[0142] like Figure 5B As shown, the photoresist layer 410 is formed on the substrate 304. For example, the deposition tool 102 can form the photoresist layer 410 on and / or over the front surface of the substrate 304 (eg, on the exposed surface of the hard mask layer 402 and the substrate 304). Figure 5B As shown, the exposure tool 104 can expose the photoresist layer 410 to a radiation source to form a pattern on the photoresist layer 410, and the developing tool 106 can develop and remove a portion of the photoresist layer 410 to expose the pattern. For example, the pattern can separate the third rectangular pattern of the hard mask layer 402, so that the exposed portion of the substrate 304 has a substantially square cross-section (e.g., in a top view). In addition, as Figure 4B As shown, the pattern may provide a substrate for a highly absorbent structure 316 .

[0143] In some embodiments, Figure 5B As shown, the pattern of the photoresist layer 410 may extend along the boundary of the corresponding isolation structure (not shown). Therefore, the isolation structure is formed before the nano-scale structure 320. Alternatively, the isolation structure may be formed after the nano-scale structure 320.

[0144] Figure 5C and Figure 5D A top view of a pixel array and a cross-sectional view 550 along line AA of the exemplary embodiment 500 are shown. Figure 5CAs shown, a portion of the substrate 304 is removed. For example, the etching tool 108 may use a wet etching technique, a dry etching technique, a plasma-assisted etching technique, and / or other types of etching techniques to etch the substrate 304. The etching tool 108 may etch the exposed portion of the substrate 304 according to the pattern of the photoresist layer 410. As a result, an array of nanoscale holes (e.g., nanoscale holes 412a, nanoscale holes 412b, nanoscale holes 412c, nanoscale holes 412d, and nanoscale holes 412e) is formed in the substrate 304.

[0145] Further Figure 5C As shown, after the etching tool 108 removes a portion of the substrate 304, the photoresist removal tool 114 can remove the remaining portion of the photoresist layer 410 (eg, using chemical strippers, plasma ashing, and / or other techniques). Figure 5C As shown, the hard mask layer 402 is removed. For example, the etching tool 108 may use wet etching techniques, dry etching techniques, plasma assisted etching techniques and / or other types of etching techniques to etch the hard mask layer 402. Figure 5C As shown, a generally tapered recess 414 may be formed (eg, using another photolithography cycle to etch a portion of the substrate 304 corresponding to the tapered recess 414).

[0146] like Figure 5D As shown, nanoscale holes 412a to 412e are filled with dielectric material to form an array of nanoscale structures 320a to 320d. The deposition tool 102 may deposit the dielectric material using spin coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other deposition techniques. In addition, the tapered groove 414 is filled with dielectric material to form a high absorption structure 316. In some embodiments, the dielectric material overflows from the nanoscale holes 412a to 412e and the tapered groove 414, and the planarization tool 110 removes the dielectric material outside the nanoscale holes 412a to 412e and the tapered groove 414 using chemical mechanical planarization technology.

[0147] In the exemplary embodiment 500, the array of nanoscale structures 320a-320d and the highly absorbent structure 316 comprise the same dielectric material (or combination of materials as dielectrics). Instead, the array of nanoscale structures 320a-320d is filled with a first dielectric material (or combination of materials) prior to a subsequent photolithography cycle to form the tapered recess 414. Thus, the tapered recess 414 is filled with a second dielectric material (or combination of materials) such that the array of nanoscale structures 320a-320d and the highly absorbent structure 316 are formed of different materials (or combinations of materials).

[0148] The highly absorbing structure 316 refracts near infrared light toward the photodiode (not shown) of the pixel sensor. Therefore, the highly absorbing structure 316 increases the quantum efficiency of the pixel sensor for near infrared light. In addition, since the array of nanoscale holes 412a to 412d is relatively small, the nanoscale structures 320a to 320d refract visible light toward the photodiode (not shown) of the pixel sensor. Therefore, the array of nanoscale structures 320a to 320d increases the quantum efficiency of the pixel sensor for visible light.

[0149] As mentioned above, FIG. 5A to FIG. 5D is provided as a specific example. FIG. 5A to FIG. 5D Other specific examples of may be different from those described above. For example, as shown in FIG. 4A to FIG. 4M As described above, in some embodiments, the first material 404 is patterned to have smaller widths w1 and w2. Therefore, the rectangular pattern of the second material 406 can extend into the hard mask layer 402, and the nano-scale structures 320a to 320d can still be produced without depositing the third material 408.

[0150] Figure 6 is a schematic diagram illustrating exemplary components of the apparatus 600 described herein. In some embodiments, one or more of the semiconductor process tool 102 to the semiconductor process tool 116 and / or the wafer / die transfer tool 118 may include one or more apparatuses 600 and / or one or more components of the apparatus 600. Figure 6 As shown, device 600 may include a bus 610 , a processor 620 , a memory 630 , an input component 640 , an output component 650 , and / or a communication component 660 .

[0151] Bus 610 includes one or more components that enable wired and / or wireless communication between components of device 600. Bus 610 may be connected to Figure 6 The processor 620 may be a computer program product or a processor that is coupled together, for example, by operational coupling, communicative coupling, electrical coupling, and / or electrical coupling. The processor 620 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable logic gate array, an application specific integrated circuit, and / or other types of process elements. The processor 620 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, the processor 620 may include one or more processors that may be programmed to perform one or more operations or processes described elsewhere in the present disclosure.

[0152] The memory 630 may include volatile and / or non-volatile memory. For example, the memory 630 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 630 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 630 may be a non-transitory computer-readable medium. The memory 630 may store information, instructions, and / or software (e.g., one or more software applications) related to the operation of the device 600. In some embodiments, the memory 630 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 620), for example, via a bus 610.

[0153] Input component 640 enables device 600 to receive input, such as user input and / or sensor input. For example, input component 640 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a converter, a sensor, a global positioning system sensor, a global satellite navigation system sensor, an accelerometer, a gyroscope and / or a brake. Output component 650 enables device 600 to provide output, such as through a screen, a loudspeaker and / or a light emitting diode. Communication component 660 enables device 600 to communicate with other devices through a wired connection and / or a wireless connection. For example, communication component 660 may include a receiver, a transmitter, a transceiver, a modem, a network interface card and / or an antenna.

[0154] Device 600 may perform one or more operations or processes described in the present disclosure. For example, a non-transitory computer-readable medium (e.g., memory 630) may store a set of instructions (e.g., one or more instructions or program codes) executed by processor 620. Processor 620 may perform one or more operations or processes described in the present disclosure. In some embodiments, a set of instructions executed by one or more processors 620 causes one or more processors 620 and / or device 600 to perform one or more operations or processes described in the present disclosure. In some embodiments, fixed-wire circuits may replace or be combined with instructions to perform one or more operations or processes described in the present disclosure. In addition or alternatively, processor 620 is configured to perform one or more operations or processes described in the present disclosure. Therefore, the embodiments described in the present disclosure are not limited to any particular combination of fixed-wire circuits and software.

[0155] Figure 6 The number and configuration of components shown are provided for illustration only. Device 600 may include additional components, fewer components, different components, or different Figure 6Additionally or alternatively, one or more components of device 600 may perform one or more functions described as being performed by another set of components of device 600.

[0156] Figure 7 FIG. 7 is a flow chart of an exemplary process 700 for forming nanoscale structures of a pixel sensor. In some embodiments, Figure 7 One or more process blocks of are performed by one or more semiconductor process tools (e.g., one or more of semiconductor process tools 102 to semiconductor process tools 116). In addition or alternatively, Figure 7 One or more process blocks may be performed by one or more components of the apparatus 600 , such as the processor 620 , the memory 630 , the input component 640 , the output component 650 , and / or the communication component 660 .

[0157] like Figure 7 As shown, process 700 may include forming a hard mask layer on a substrate including a photodiode (block 710). For example, one or more of semiconductor process tools 102 to 116 may form hard mask layer 402 on substrate 304 including photodiode 306, as described herein.

[0158] Further Figure 7 As shown, process 700 may include depositing a first material in a first rectangular pattern on the hard mask layer (block 720). For example, one or more of semiconductor process tools 102 to 116 may deposit a first material 404 in a first rectangular pattern on the hard mask layer 402 as described herein.

[0159] Further Figure 7 As shown, process 700 may include depositing a second material along sidewalls of the first rectangular pattern (block 730). For example, one or more of semiconductor process tools 102-116 may deposit second material 406 along sidewalls of the first rectangular pattern as described herein.

[0160] Further Figure 7 As shown, the process 700 may include removing the first material so that the second material remains in the second rectangular pattern (block 740). For example, one or more of the semiconductor process tools 102 to 116 may remove the first material 404 so that the second material 406 remains in the second rectangular pattern, as described in the present disclosure.

[0161] Further Figure 7As shown, the process 700 may include depositing a third material along sidewalls of the second rectangular pattern (block 750). For example, one or more of the semiconductor process tools 102-116 may deposit the third material 408 along sidewalls of the second rectangular pattern as described herein.

[0162] Further Figure 7 As shown, the process 700 may include removing the second material so that the third material remains in the third rectangular pattern (block 760). For example, one or more of the semiconductor process tools 102 to 116 may remove the second material 406 so that the third material 408 remains in the third rectangular pattern, as described in the present disclosure.

[0163] Further Figure 7 As shown, the process 700 may include etching the hard mask layer to extend the third rectangular pattern into the hard mask layer (block 770). For example, one or more of the semiconductor process tools 102 to the semiconductor process tools 116 may etch the hard mask layer 402 to extend the third rectangular pattern into the hard mask layer 402 as described herein.

[0164] Further Figure 7 As shown, the process 700 may include removing the third material so that the hard mask layer remains in the third rectangular pattern (block 780). For example, one or more of the semiconductor process tools 102 to the semiconductor process tools 116 may remove the third material 408 so that the hard mask layer 402 remains in the third rectangular pattern, as described in the present disclosure.

[0165] Further Figure 7 As shown, process 700 may include performing a lithography operation using a hard mask layer to form an array of a plurality of nanoscale holes in a substrate, and forming an array of a plurality of nanoscale structures by depositing a dielectric material in the array of nanoscale holes (block 790). For example, one or more of semiconductor process tools 102 to semiconductor process tools 116 may perform a lithography operation using a hard mask layer 402 to form an array of nanoscale holes 412a to 412e in substrate 304, and forming an array of nanoscale structures 320 by depositing a dielectric material in the array of nanoscale holes 412a to 412e, as described herein.

[0166] The process 700 may include additional embodiments, such as any single embodiment or any combination of the embodiments described below and / or in combination with one or more other processes described elsewhere in this disclosure.

[0167] In a first embodiment, the width of the first material 404 is about 50 nm to about 80 nm.

[0168] In the second embodiment, alone or in combination with the first embodiment, the width of the second material 406 is about 10 nm to about 40 nm.

[0169] In the third embodiment, alone or in combination with one or more of the first and second embodiments, the width of the third material 408 is about 10 nm to about 40 nm.

[0170] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, the step of performing a lithography operation further includes performing a lithography operation to etch a pyramid recess 414 into the substrate 304 .

[0171] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the process 700 includes forming a high absorption structure 316 by depositing additional dielectric material according to the pyramidal recesses 414 .

[0172] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the lithography operation includes forming a photoresist layer 410 ; patterning an array of nanoscale holes 412 a to 412 e using the photoresist layer 410 , and removing the photoresist layer 410 .

[0173] In a seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, the process 700 includes removing the third material 408 after forming the array of nanoscale holes 412 a to 412 e .

[0174] In an eighth embodiment, alone or in combination with one or more of the first to seventh embodiments, the first material includes metal.

[0175] In a ninth embodiment, alone or in combination with one or more of the first to eighth embodiments, the second material includes nitride.

[0176] In a tenth embodiment, alone or in combination with one or more of the first to ninth embodiments, the third material includes metal or oxide.

[0177] Although Figure 7 Example blocks of process 700 are shown. In some embodiments, process 700 includes additional blocks, fewer blocks, different blocks, or blocks different from those in the process 700. Figure 7 The block configuration is depicted. Additionally or alternatively, two or more blocks of process 700 may be performed simultaneously.

[0178] In this way, forming an array of nanoscale structures improves the quantum efficiency of short wavelength light, such as green and blue light, at the photodiodes of the pixel array. The nanoscale structures can be used without highly absorptive structures (e.g., when the pixel array is configured for visible light only), or can at least partially surround highly absorptive structures (e.g., when the pixel array is configured for both visible light and near infrared light). In addition, the array of nanoscale structures can be formed using photolithography so that the nanoscale structures are separated by substantially fixed intervals. Therefore, the quantum efficiency of the pixel array can be improved compared to if the array of nanoscale structures is formed using a random (or quasi-random) process (e.g., directed self-assembly).

[0179] As detailed above, some embodiments described in the present disclosure provide a semiconductor structure. The semiconductor structure includes a photodiode in a substrate. The semiconductor structure includes a highly absorptive structure on the photodiode and is configured to reflect infrared light toward the photodiode. The semiconductor structure includes an array of nanoscale structures at least partially surrounding the highly absorptive structure and is configured to reflect visible light toward the photodiode. The array of nanoscale structures is generally spaced apart at regular intervals.

[0180] As described in detail above, some embodiments described in the present disclosure provide a method. The method includes forming a hard mask layer on a substrate including a photodiode. The method includes depositing a first material in a first rectangular pattern on the hard mask layer. The method includes depositing a second material along the sidewalls of the first rectangular pattern. The method includes removing the first material so that the second material remains in the second rectangular pattern. The method includes depositing a third material along the sidewalls of the second rectangular pattern. The method includes removing the second material so that the third material remains in the third rectangular pattern. The method includes etching the hard mask layer to extend the third rectangular pattern into the hard mask layer. The method includes removing the third material so that the hard mask layer remains in the third rectangular pattern. The method includes performing a lithography operation using the hard mask layer to form an array of nanoscale holes in the substrate. The method includes forming an array of nanoscale structures by depositing a dielectric material in the array of nanoscale holes.

[0181] As described in detail above, some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a photodiode in a substrate. The semiconductor structure includes an array of nanoscale structures on the photodiode and is configured to reflect visible light toward the photodiode, and the array of nanoscale structures is substantially separated by a fixed interval.

[0182] Depending on the context, "satisfying a threshold" as used in the present disclosure may mean a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc.

[0183] One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a photodiode in a substrate. The semiconductor structure includes a highly absorptive structure on the photodiode and is configured to reflect infrared light toward the photodiode. The semiconductor structure includes an array of nanoscale structures at least partially surrounding the highly absorptive structure and is configured to reflect visible light toward the photodiode. The array of nanoscale structures is generally spaced apart at regular intervals.

[0184] In some embodiments, each of the nanoscale structures has a width of substantially 10 nanometers (nm) to 40 nm.

[0185] In some embodiments, each of the nanoscale structures is substantially square in cross-section.

[0186] In some embodiments, the distance between each of the nanoscale structures and an adjacent one of the nanoscale structures is substantially 10 nm to 40 nm.

[0187] In some embodiments, the high absorbency structure has a substantially pyramidal appearance.

[0188] In some embodiments, the semiconductor structure further includes an isolation structure surrounding the photodiode, wherein a ratio of a depth of the isolation structure from the top of the substrate to a depth of the photodiode from the top of the substrate is substantially 0.5 to 0.8.

[0189] Another aspect of the present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a hard mask layer on a substrate including a photodiode; depositing a first material in a first rectangular pattern on the hard mask layer; depositing a second material along the sidewalls of the first rectangular pattern; removing the first material so that the second material remains in the second rectangular pattern; depositing a third material along the sidewalls of the second rectangular pattern; removing the second material so that the third material remains in the third rectangular pattern; etching the hard mask layer to extend the third rectangular pattern into the hard mask layer; removing the third material so that the hard mask layer remains in the third rectangular pattern; performing a lithography operation using the hard mask layer to form an array of nanoscale holes in the substrate; and forming an array of nanoscale structures by depositing a dielectric material in the array of nanoscale holes.

[0190] In some embodiments, the width of the first material is substantially 50 nm to 80 nm.

[0191] In some embodiments, the width of the second material is substantially 10 nm to 40 nm.

[0192] In some embodiments, the width of the third material is substantially 10 nm to 40 nm.

[0193] In some embodiments, the step of performing a lithography operation further comprises performing a lithography operation to etch a pyramid-shaped pattern into the substrate.

[0194] In some embodiments, the method further includes forming a highly absorbing structure by depositing additional dielectric material according to a pyramidal profile pattern.

[0195] In some embodiments, the step of performing the lithography operation includes forming a photoresist layer; patterning an array of nanoscale holes using the photoresist layer; and removing the photoresist layer.

[0196] In some embodiments, the method further comprises removing the third material after forming the array of nanoscale holes.

[0197] In some embodiments, the first material comprises a metal.

[0198] In some embodiments, the second material includes a nitride.

[0199] In some embodiments, the third material includes a metal or an oxide.

[0200] Another aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a photodiode in a substrate. The semiconductor structure includes an array of multiple nanoscale structures on the photodiode and is configured to reflect visible light toward the photodiode, and the array of nanoscale structures is substantially separated by a fixed interval.

[0201] In some embodiments, the nanoscale structures are filled with a dielectric material.

[0202] In some embodiments, the semiconductor structure further includes an isolation structure surrounding the photodiode, wherein a ratio of a depth of the isolation structure from the top of the substrate to a depth of the photodiode from the top of the substrate is substantially 0.5 to 0.8.

[0203] Another aspect of the present disclosure is to provide a semiconductor structure. The semiconductor structure includes a substrate; a plurality of pixel sensors in the substrate, wherein each of the pixel sensors includes a photodiode; an isolation structure surrounding the pixel sensors; a high absorption structure on the photodiode, wherein the high absorption structure extends from a top surface of the substrate into the substrate toward the photodiode; and a plurality of nanoscale structures on the photodiode and between the isolation structure and the high absorption structure, wherein the high absorption structure is at least partially surrounded by the nanoscale structure.

[0204] In some embodiments, the distances between two adjacent nanoscale structures are substantially the same.

[0205] The above summarizes the features of many embodiments, so that those with ordinary knowledge in the art can better understand the aspects of the present disclosure. Those with ordinary knowledge in the art should understand that other processes and structures can be designed or modified based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments described. Those with ordinary knowledge in the art should also understand that equivalent structures do not deviate from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: Include: a photodiode in a substrate; a highly absorbing structure on the photodiode, wherein the highly absorbing structure is configured to reflect infrared light toward the photodiode; as well as An array of a plurality of nanoscale structures at least partially surrounds the highly absorptive structure, wherein the array of the plurality of nanoscale structures is configured to reflect visible light toward the photodiode, and the array of the plurality of nanoscale structures is separated by a fixed interval.

2. The semiconductor structure according to claim 1, wherein: Each of the plurality of nanoscale structures has a width of 10 nanometers to 40 nanometers.

3. The semiconductor structure according to claim 1 or 2, characterized in that: Each of the plurality of nanoscale structures has a square cross-section.

4. The semiconductor structure according to claim 1 or 2, characterized in that: Wherein a distance between each of the plurality of nanoscale structures and an adjacent one of the plurality of nanoscale structures is 10 nanometers to 40 nanometers.

5. The semiconductor structure according to claim 1 or 2, characterized in that: The high absorption structure has a pyramidal shape.

6. The semiconductor structure according to claim 1 or 2, characterized in that: Also includes: An isolation structure surrounds the photodiode, wherein a ratio of a depth of the isolation structure from a top of the substrate to a depth of the photodiode from the top of the substrate is 0.5 to 0.

8.

7. A semiconductor structure, characterized in that: Include: a substrate; a plurality of pixel sensors in the substrate, wherein each of the plurality of pixel sensors comprises a photodiode; an isolation structure surrounding the plurality of pixel sensors; a high absorption structure on the photodiode, wherein the high absorption structure extends from a top surface of the substrate into the substrate toward the photodiode; as well as A plurality of nanoscale structures are located on the photodiode and between the isolation structure and the high absorption structure, wherein the high absorption structure is at least partially surrounded by the plurality of nanoscale structures.

8. The semiconductor structure according to claim 7, wherein: The distances between two adjacent nanoscale structures are the same.

9. A semiconductor structure, characterized in that: Include: a photodiode in a substrate; as well as An array of a plurality of nanoscale structures is disposed on the photodiode, wherein the array of the plurality of nanoscale structures is configured to reflect visible light toward the photodiode, and the array of the plurality of nanoscale structures is separated by a fixed interval.

10. The semiconductor structure according to claim 9, wherein: Also includes: An isolation structure surrounds the photodiode, wherein a ratio of a depth of the isolation structure from a top of the substrate to a depth of the photodiode from the top of the substrate is 0.5 to 0.8.

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