Semiconductor device

Abstract

The utility model relates to a semiconductor device. The semiconductor device includes an active region protruding from a substrate and disposed between portions of an isolation structure. The semiconductor device includes a gate stack disposed on a channel region of the active region. The semiconductor device includes a source / drain feature over a source / drain region of the active region, where the source / drain feature has a recess extending below a top surface of the substrate. The semiconductor device includes a backside silicide layer on a bottom surface of the source / drain feature. The semiconductor device includes a backside via on a bottom surface of the backside silicide layer, with a top surface of the backside via below a bottommost portion of the gate stack.

Description

Technical Field

[0001] The present disclosure relates to semiconductor technology, and more particularly to a semiconductor device with a backside via. Background Art

[0002] The integrated circuit industry has experienced exponential growth. Technological advances in semiconductor manufacturing processes have resulted in generations of integrated circuits, each with smaller and more complex circuits than the previous one. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per unit of chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be produced using a process) has decreased. In general, this miniaturization is limited only by the ability to lithographically define integrated circuit features as geometry size continues to decrease.

[0003] As feature sizes continue to decrease, some integrated circuit components (such as source / drain metal contacts and power line connections) may be moved to the back side of the wafer. Moving these components can achieve better spacing management while optimizing power consumption. To achieve this, the source / drain components formed on the front side of the substrate must be electrically connected to the back side power rails through back side vias (or back side metal contacts). These back side vias need to have low resistance, low capacitance, and low leakage current to improve device performance. In some cases, leakage current becomes a problem when the back side vias are not properly insulated. For example, current leakage may occur through the back side substrate material. This leakage must be minimized to avoid any coupling or shorting between the metal gate and the source / drain metal contacts.

[0004] Thus, while existing methods of making backside vias are generally adequate for their intended purposes, they have not been completely satisfactory in all respects. Utility Model Content

[0005] The present disclosure relates to a semiconductor device. The semiconductor device includes an active region protruding from a substrate and disposed between multiple portions of an isolation structure. The semiconductor device includes a gate stack disposed on a channel region of the active region. The semiconductor device includes a source / drain component above a source / drain region of the active region, wherein the source / drain component has an entrenched portion extending below a top surface of the substrate. The semiconductor device includes a backside silicide layer on a bottom surface of the source / drain component. The semiconductor device includes a backside via on a bottom surface of the backside silicide layer, wherein a top surface of the backside via is below a bottommost portion of the gate stack.

[0006] In some embodiments, the source / drain feature has a lightly doped outer layer and a heavily doped inner layer, and the backside via is in electrical contact with the heavily doped inner layer by directly contacting the backside silicide layer.

[0007] In some embodiments, a width of the backside via along a longitudinal direction of the active region is smaller than a width of the source / drain feature.

[0008] In some embodiments, the semiconductor device further comprises: a silicon nitride cap on a first portion of the bottom surface of the source / drain component, wherein the backside via is disposed on a second portion of the bottom surface of the source / drain component.

[0009] In some embodiments, the semiconductor device further comprises: a silicon nitride barrier layer on a plurality of sidewalls of the backside via.

[0010] In some embodiments, the source / drain component is a first source / drain component, and the semiconductor device further includes: a second source / drain component above a second source / drain region of the active region; and a backside dielectric cap on a bottom surface of the second source / drain component, wherein the bottom surface of the first source / drain component is below the bottom surface of the second source / drain component.

[0011] In some embodiments, the semiconductor device further comprises: a front-side via on the source / drain component.

[0012] In some embodiments, the semiconductor device further comprises: an interconnect layer on the front-side via and the gate stack.

[0013] In some embodiments, a bottom layer of the gate stack has a thickness, and the top surface of the backside via is vertically spaced a distance from the bottom layer of the gate stack, wherein the distance is not less than the thickness.

[0014] In some embodiments, the semiconductor device further comprises: a second backside via on a bottom surface of a second source / drain component, wherein the backside via extends along a longitudinal direction of the active region to contact the second backside via. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present disclosure. It should also be noted that the accompanying drawings only illustrate typical embodiments of the present disclosure and should not be considered as limiting the scope thereof. The present disclosure can also be applied to other embodiments.

[0016] Figure 1A to Figure 1BA flowchart of a method for forming a semiconductor device having a backside via partially or completely is shown according to various embodiments of the present disclosure.

[0017] FIG. 2A to FIG. 2B A three-dimensional schematic diagram and a top view schematic diagram of a semiconductor working object are depicted, wherein the AA' line and the BB' line cross-cut the source / drain regions of the working object.

[0018] FIG. 3A to FIG. 23A According to an embodiment of the present disclosure, a diagram is shown in FIG. FIG. 2A to FIG. 2B The A-A' line cuts and according to Figure 1A to Figure 1B A schematic cross-sectional view of a semiconductor device manufactured by the method.

[0019] FIG. 3B to FIG. 4B , FIG. 10B to FIG. 11B ,as well as FIG. 15B to FIG. 23B According to an embodiment of the present disclosure, a diagram is shown in FIG. FIG. 2A to FIG. 2B The B-B' line cutting and according to Figure 1A to Figure 1B A schematic cross-sectional view of a semiconductor device manufactured by the method.

[0020] Fig.23C According to an embodiment of the present disclosure, a cross-sectional view of a semiconductor device having a back-side via cut along line AA′ is shown.

[0021] Fig.23D According to an embodiment of the present disclosure, a cross-sectional view of a semiconductor device having a back-side via cut along line BB′ is shown.

[0022] Figure 24 to Figure 25 According to another embodiment of the present disclosure, a cross-sectional schematic diagram of a semiconductor device with a backside via is depicted.

[0023] FIG. 26A to FIG. 26B A flowchart of a method for forming a semiconductor device having a backside via partially or completely is shown according to various embodiments of the present disclosure.

[0024] FIG. 27A to FIG. 27B A three-dimensional schematic diagram and a top view schematic diagram of a semiconductor working object are depicted, wherein the AA' line and the BB' line cross-cut the source / drain regions of the working object.

[0025] FIG. 28A to FIG. 47A According to an embodiment of the present disclosure, a diagram is shown in FIG. FIG. 27A to FIG. 27B The A-A' line cuts and according to FIG. 26A to FIG. 26B A schematic cross-sectional view of a semiconductor device manufactured by the method.

[0026] FIG. 28B to FIG. 29B , FIG. 32B to FIG. 35B ,as well as Figures 39B to 47B According to an embodiment of the present disclosure, a diagram is shown in FIG. FIG. 27A to FIG. 27B The B-B' line cutting and according to FIG. 26A to FIG. 26B A schematic cross-sectional view of a semiconductor device manufactured by the method.

[0027] Fig.47C According to an embodiment of the present disclosure, a cross-sectional view of a semiconductor device having a back-side via cut along line AA′ is shown.

[0028] Fig.47D According to an embodiment of the present disclosure, a cross-sectional view of a semiconductor device having a back-side via cut along line BB′ is shown.

[0029] Figures 48 to 51 According to another embodiment of the present disclosure, a cross-sectional schematic diagram of a semiconductor device with a backside via is depicted.

[0030] The reference numerals are described as follows:

[0031] 100 / 1000: Method

[0032] 102 / 104 / 106 / 107 / 108 / 109 / 110 / 112 / 114 / 116 / 118 / 120 / 122 / 124 / 126 / 128: Operation

[0033] 200: Semiconductor devices

[0034] 202: Base

[0035] 202a: Protrusion

[0036] 204: Semiconductor stacking

[0037] 204a: first semiconductor layer

[0038] 204b: Second semiconductor layer

[0039] 205: Suspended semiconductor channel

[0040] 206: Isolation Structure

[0041] 208: Virtual gate structure

[0042] 209: Virtual Gate Stack

[0043] 211: Gate spacer

[0044] 212: Deep groove

[0045] 214: Air gap

[0046] 216: Internal spacer

[0047] 250: Semiconductor workpieces

[0048] 275: Gate trench

[0049] 285: Front groove

[0050] 291: Metal filling layer

[0051] 292: Front metal contact

[0052] 295: Dorsal groove

[0053] 308: Metal Gate Structure

[0054] 309: Gate electrode

[0055] 311: Gate dielectric layer

[0056] 390: Backside silicide components

[0057] 391: Back metal filling layer

[0058] 392 / 392a / 392b / 392c / 392d / 392e / 392f: Back metal contact / back vias

[0059] 393: Barrier layer

[0060] 500: Dielectric layer

[0061] 600: Directed plasma treatment

[0062] 700: Dielectric components

[0063] 800: (Epitaxial) Source / Drain Components

[0064] 800a: Inner heavily doped layer

[0065] 800b: External lightly doped layer

[0066] 900: Interlayer dielectric layer

[0067] 1002: Interconnect layer

[0068] 1212a: First groove

[0069] 1212b: Second groove

[0070] 1800a: First source / drain component

[0071] 1800b: Second source / drain component

[0072] CR: Channel area

[0073] d1 / d1' / d2 / d3 / d3': distance

[0074] SDR: Source / Drain Region

[0075] t1 / t1': thickness DETAILED DESCRIPTION

[0076] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first element is formed on a second element, an embodiment in which the first and second elements are in direct contact may be included, and an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0077] Furthermore, spatially relative terms such as "under", "below", "lower", "above", "higher" and the like may be used to facilitate description of the relationship between one component or parts and another component or parts in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0078] In addition, when "approximately", "approximately", etc. are used to describe a number or a range of numbers, such terms are intended to cover numbers within a reasonable range, including the number, such as within + / -10% of the number, or other values ​​understood by those skilled in the art. For example, the term "about 5 nanometers" can cover a size range of 4.5 nanometers to 5.5 nanometers.

[0079] Various embodiments of the present disclosure are related to semiconductor devices with backside vias (also called backside contacts). In order to reduce the size of the device and reduce power consumption, certain power connection components (such as vias) are moved to the back side of the substrate. However, as the device components are miniaturized, the spacing between the metal gate and the adjacent source / drain components becomes smaller, so the backside vias connected to the source / drain components may be too close to the metal gate, resulting in current leakage problems between the gate and the backside vias. In order to prevent leakage and the possibility of short circuits between the gate and the source / drain connection, various embodiments of the present disclosure provide solutions for better insulating the backside vias from surrounding components. For example, the formation of the backside vias is deeper into the substrate to increase the spacing between the backside vias and the metal gate. As another example, a backside dielectric cover is used as a part of forming the backside vias. As another example, the backside vias are surrounded by an interlayer dielectric (ILD) layer.

[0080] To illustrate various aspects of the present disclosure, methods for forming semiconductor devices are discussed below. The embodiments shown in the present disclosure use a gate-all-around (GAA) field-effect transistor (FET), but the present disclosure is not limited thereto. A GAA FET refers to a transistor having a gate stack (gate electrode and gate dielectric layer) surrounding the transistor channel, such as a vertically stacked all-around gate horizontal nanowire or nanosheet metal-oxide-semiconductor field-effect transistor (MOSFET) device. Those skilled in the art to which the present disclosure pertains should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments described herein.

[0081] Figure 1A to Figure 1BA flow chart of a method 100 for forming a semiconductor device having a backside via in part or in whole is depicted according to various embodiments of the present disclosure. In operation 102, the method 100 receives or provides a workpiece, which includes a semiconductor stack having a staggered first semiconductor layer and a second semiconductor layer, and the semiconductor stack extends above an isolation structure above a substrate. In operation 104, the method 100 forms a dummy gate structure (including a dummy gate stack and a gate spacer) above a channel region of the semiconductor stack, the channel region being defined by an area below the dummy gate stack, and adjacent to the channel region is a source / drain region where a source / drain component will be formed. In operation 106, the method 100 forms a deep trench in the source / drain region (i.e., adjacent to the channel region), the deep trench exposing a side surface of the semiconductor stack. In operation 108, the method 100 forms an inner spacer in the channel region. In operation 110, the method 100 forms a dielectric component on a bottom surface of the deep trench. In operation 112, the method 100 forms a source / drain component in the deep trench. At operation 114, the method 100 forms an ILD layer over the source / drain components. At operation 116, the method 100 forms a suspended semiconductor channel by removing the dummy gate stack from the dummy gate structure and removing the second semiconductor layer. At operation 118, the method 100 forms a metal gate structure over the channel region, each metal gate structure also surrounding each suspended semiconductor channel in the respective channel region. At operation 120, the method 100 forms a front side metal contact over the source / drain components. At operation 122, the method 100 forms an interconnect (or an interconnect layer with an interconnect component) over the front side contact. At operation 124, the method 100 flips the work piece and thins the substrate from the back side. At operation 126, the method 100 etches the work piece from the back side to form a back side trench, which exposes the bottom surface of one of the source / drain components. At operation 128, method 100 forms a backside conductive feature (i.e., a backside via or a backside metal contact) in the backside trench and on the exposed bottom surface of one of the source / drain features. Method 100 may perform further steps to complete the fabrication of the semiconductor device. The present disclosure contemplates additional processes, additional steps may be provided before, during, and / or after the various steps / processes described in method 100, and some of the steps may be replaced or deleted.

[0082] Method 100 is described below from FIG. 2A to FIG. 2B The description begins with a three-dimensional schematic diagram and a top view of a semiconductor workpiece 250, wherein lines AA' and BB' intersect source / drain regions SDR in the x and y directions, respectively. Workpiece 250 shows an initial semiconductor device 200, which will be further processed according to various embodiments of the present disclosure.

[0083] The following will be combined FIG. 3A to FIG. 23AA schematic cross-sectional view of the semiconductor device 200 depicted in the xz plane and FIG. 3B to FIG. 4B , FIG. 10B to FIG. 11B ,as well as FIG. 15B to FIG. 23B The method 100 is further described with reference to schematic cross-sectional views of a semiconductor device 200 depicted in the yz plane. These illustrations depict various schematic views of a semiconductor device 200 at various stages of manufacture and manufactured according to embodiments of the present disclosure. For the sake of clarity, these illustrations have been simplified to better understand the disclosed concepts of the present disclosure. Additional components may be added to the device 200, and some of the components described below may be replaced, modified, or deleted in other embodiments of the device 200.

[0084] The semiconductor device 200 may be an integrated circuit (IC) chip, a system on chip (SoC) or a portion thereof, and may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), fin-like field effect transistors (FinFETs), nanosheet FETs, nanowire FETs, other types of multi-gate FETs, MOSFETs, complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal-oxide semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. In some embodiments, the device is included in a non-volatile memory, such as non-volatile random access memory (NVRAM), flash memory, electrically erasable programmable read only memory (EEPROM), electrically programmable read-only memory (EPROM), other suitable memory types, or a combination of the foregoing.

[0085] At operation 102 , the method 100 receives a work object 250 of a semiconductor device 200 , an embodiment of which is shown in FIG. FIG. 2A to FIG. 2B . The work object 250 may include a substrate 202 and a semiconductor stack 204 protruding from the substrate 202. The semiconductor stack 204 protrudes above an isolation structure 206 disposed above the substrate 202. The isolation structure 206 provides isolation between adjacent semiconductor stacks 204 and may be a shallow trench isolation (STI) layer. In operation 104, the method 100 forms a dummy gate structure 208 above a channel region CR of the semiconductor stack 204. The channel region is defined by a portion of the semiconductor stack 204 beneath the dummy gate structure 208. Adjacent to the channel region is a source / drain region SDR of the semiconductor stack 204. The semiconductor stack 204 extends longitudinally in the x-direction, while the dummy gate structure 208 extends longitudinally in the y-direction. It is worth noting that forming the dummy gate structure 208 is a separate step from forming the semiconductor stack 204. However, for the sake of simplicity, FIG. 2A to FIG. 2B The received workpiece 250 is shown to have been formed with a dummy gate structure 208 .

[0086] Still reference FIG. 2A to FIG. 2B , respective AA' lines cross several dummy gate structures 208 along the semiconductor stack 204 in the x-direction (the longitudinal direction of the semiconductor stack). Respective BB' lines cross the source / drain region SDR of the semiconductor stack 204 in the y-direction (the longitudinal direction of the dummy gate structure 208) and cross portions of the isolation structure 206 surrounding the semiconductor stack 204. The AA' lines and the BB' lines are used to illustrate schematic cross-sectional views of various components formed in the source / drain region SDR.

[0087] FIG. 3A to FIG. 23A The diagram shows the cutting process along the A-A' line at each manufacturing stage and the Figure 1A to Figure 1B A schematic cross-sectional view of a semiconductor device 200 manufactured by a method of FIG. 3B to FIG. 4B , FIG. 10B to FIG. 11B ,as well as FIG. 15B to FIG. 23B Describe the manufacturing process at each stage FIG. 2A to FIG. 2B The B-B' line cutting and according to Figure 1A to Figure 1B Schematic cross-sectional view of a semiconductor device 200 manufactured by a method.

[0088] like Figure 3AAs shown, the semiconductor stack 204 is disposed on the substrate 202. The substrate 202 may be a silicon (Si) substrate or a substrate having other semiconductor materials such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe) or diamond. The semiconductor stack 204 may also be referred to as an active region. The semiconductor stack 204 includes an alternating first semiconductor layer 204a and a second semiconductor layer 204b. The first semiconductor layer 204a has a material composition different from that of the second semiconductor layer 204b. For example, the first semiconductor layer 204a is made of silicon, and the second semiconductor layer 204b is made of silicon germanium. The first semiconductor layer 204a may have the same material composition as the substrate 202. The dummy gate structure 208 is disposed above the channel region CR of the semiconductor stack 204. Each dummy gate structure 208 includes a dummy gate stack 209 and a gate spacer 211 on the sidewall of the dummy gate stack 209. The dummy gate stack 209 may be made of polysilicon, and the gate spacer 211 may be made of silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride or a suitable dielectric material. The source / drain region SDR extends between adjacent dummy gate structures 208 .

[0089] Reference now Figure 3B, each semiconductor stack 204 extends over an isolation structure 206 above the substrate 202. The substrate 202 may include a protrusion 202a that protrudes above the top surface of the isolation structure 206, and the semiconductor stack 204 may extend from the top surface of the protrusion 202a. Each protrusion 202a is interposed by the isolation structure 206, so that the isolation structure 206 interfaces with the top surface of the substrate 202 and the side surface of the protrusion 202a. The isolation structure 206, which may be an STI layer, provides isolation between adjacent semiconductor stacks 204. In an exemplary process, the dielectric material for the isolation structure 206 is deposited on the workpiece 250 using chemical vapor deposition (CVD), subatmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (FCVD), physical vapor deposition (PVD), spin coating, and / or other suitable processes, and then the deposited dielectric material is planarized and recessed until the semiconductor stack 204 rises above the isolation structure 206. The dielectric material for the isolation structure 206 may include silicon oxide, silicon oxynitride, fluorinated silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials.

[0090] At operation 106, method 100 forms deep trenches 212 in source / drain regions SDR adjacent to channel region CR of device 200, an embodiment of which is shown in FIG. FIG. 4A to FIG. 4B . The deep trench 212 may also be referred to as a source / drain trench (recess) and has sidewalls defined by the remaining portion of the semiconductor stack 204. The deep trench 212 may be formed by a dry etching process, a wet etching process, other suitable etching processes, or a combination of the foregoing. In some embodiments, the etching process is a multi-step etching process, for example: the etching process may include alternative etchants to individually and alternately remove the semiconductor layer 204a and the semiconductor layer 204b. In some embodiments, the parameters of the etching process are configured to selectively etch the semiconductor stack 204, while minimally (to no) etching of the dummy gate structure 208 (i.e., the dummy gate stack 209 and the gate spacer 211). In some embodiments, a lithography process is performed to form a patterned mask layer covering the dummy gate structure 208 and / or a portion of the isolation structure 206, and the etching process uses the patterned mask layer as an etching mask when forming the deep trench 212.

[0091] refer to Figure 4A , the deep trench 212 extends into the substrate 202, passing through the bottommost semiconductor layer 204b of the semiconductor stack 204. As shown in the figure, the distance d1 represents the etching distance between the bottommost semiconductor layer 204b and the bottommost surface of the deep trench 212, and the ratio of the distance d1 to the thickness t1 of one of the first semiconductor layer 204a or the second semiconductor layer 204b can be in the range of 2 to 5, the distance d1 can be in the range of 20 to 50 nanometers, and the thickness t1 can be in the range of 5 to 15 nanometers. Fig.23C As will be explained in more detail, sufficient distance d1 is necessary to ensure proper spacing and insulation between the subsequently formed backside via and the bottommost portion of the subsequently formed gate structure. In some embodiments, the etch distance d1 must also take into account the subsequently formed dielectric features in the deep trench 212, which will be etched away in subsequent process steps. However, excessive spacing, such as a ratio of d1 to t1 greater than 5, is also undesirable because it will unnecessarily expand the device footprint. As long as the benefits of gate to backside via isolation are achieved, any excessive spacing (e.g., d1 / t1 greater than 5) will only create additional cost and space, and therefore, the etch distance d1 should not be too shallow or too deep. Reference Figure 4B , the deep trench 212 may extend below the top surface of the isolation structure 206 , but not below the bottom surface of the isolation structure 206 .

[0092] At operation 108 , the method 100 forms inner spacers 216 in the channel region CR along sidewalls of the semiconductor layer 204 b by any suitable process. Figure 5A as well as Fig. 6A The exemplary process steps for forming the inner spacer 216 are shown. First, Figure 5A As shown, a side etching process is performed to selectively etch the sidewall of the second semiconductor layer 204b without etching (or substantially etching) the first semiconductor layer 204a. In other words, the side etching process is configured to laterally etch (e.g., along the x-direction) the semiconductor layer 204b, thereby reducing the length of the semiconductor layer 204b along the x-direction. The side etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination of the foregoing. After the side etching process is performed, an air gap 214 is formed under each first semiconductor layer 204a, and then, as shown in FIG. Fig. 6A As shown, an inner spacer 216 is formed in each air gap 214. The inner spacer 216 is disposed directly below the gate spacer 211 and may be substantially vertically aligned with the gate spacer 211 along the z-direction.

[0093] The inner spacers 216 may be formed by a spacer deposition process and a spacer etching process. For example, a spacer deposition process is performed to form a portion of the dummy gate structure 208 and to define the deep trench 212 (eg, Figure 5A A spacer layer is formed on the semiconductor layer 204a, the semiconductor layer 204b, and the substrate 202. The spacer deposition process may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), metal-organic chemical vapor deposition (MOCVD), reduced pressure chemical vapor deposition (RPCVD), plasma-assisted chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), atmospheric pressure chemical vapor deposition (APCVD), electroplating, other suitable methods, or a combination of the foregoing processes. The spacer layer partially (and in some embodiments, completely) fills the deep trench 212. The spacer deposition process is configured to ensure that the spacer layer fills the air gap 214 between the semiconductor layer 204a and between the semiconductor layer 204a and the substrate 202 below the gate spacer 211. A spacer etching process is then performed that selectively etches the spacer layer to form a gate spacer such as Fig. 6A , while the semiconductor layer 204a, the dummy gate stack 209, and the gate spacer 211 are etched minimally (or even absently). The spacer layer (i.e., the inner spacer 216) includes a material different from the semiconductor layer 204a and the gate spacer 211 to achieve a desired etch selectivity during the gate spacer etching process. In some embodiments, the spacer layer includes a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or carbon oxynitride silicon). In some embodiments, the spacer layer includes a low-k dielectric material.

[0094] In operation 110 , the method 100 forms a dielectric feature 700 on a bottom surface of the deep trench 212 . 7A to 9A Exemplary process steps for forming dielectric component 700 are shown. First, referring to Fig. 7A , a dielectric layer 500 is conformally deposited in the deep trench 212 and above the dummy gate structure 208. The dielectric layer 500 may be deposited by an ALD process, and the dielectric layer 500 is disposed along the bottom and side surface of the deep trench 212. The dielectric layer 500 may include silicon nitride. Fig. 8A , performing a directional plasma treatment 600 on the bottom horizontal surface of the dielectric layer 500 in the deep trench 212, the directional plasma treatment 600 may include a nitrogen plasma surface treatment, and the treated bottom horizontal surface of the dielectric layer 500 may contain more nitrogen than the untreated sidewall portion of the dielectric layer 500. Third, referring to Fig. 9A , selectively etching away the untreated dielectric layer 500 on the sidewalls of the deep trench 212, which can be accomplished by a wet etching sidewall removal process, which can be an isotropic process using hydrofluoric acid (HF), so that the remaining portion of the dielectric layer 500 is a dielectric component 700 that only covers the bottom surface of the deep trench 212, and the dielectric component 700 can have a thickness of 2 to 5 nanometers in the z direction. The dielectric component 700 can also be referred to as a dielectric cover or cap layer. FIG. 23C to FIG. 23D The advantages of such a dielectric cover are described in more detail.

[0095] At operation 112 , the method 100 epitaxially grows source / drain features 800 in the deep trench 212 and on the dielectric features 700 , an embodiment of which is shown in FIG. Fig. 10A as well as Fig. 10B. The source / drain component 800 may include an n-type source / drain component corresponding to an n-type GAA transistor region or a p-type source / drain component corresponding to a p-type GAA transistor region. The source / drain component 800 may be formed by an epitaxial process using a CVD deposition technique (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum chemical vapor deposition (UHV-CVD)), molecular beam epitaxy, other suitable epitaxial growth processes, or a combination of the foregoing. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the substrate 202 and / or the semiconductor stack 204 (particularly the semiconductor layer 204a), and the epitaxial source / drain component 800 is doped with n-type dopants and / or p-type dopants. In some embodiments, for n-type GAA transistors, the epitaxial source / drain features 800 include silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming silicon:carbon epitaxial source / drain features, silicon:phosphorus epitaxial source / drain features, or silicon:carbon:phosphorus epitaxial source / drain features). In some embodiments, for p-type GAA transistors, the epitaxial source / drain features 800 include silicon germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming silicon:germanium:boron epitaxial source / drain features).

[0096] In some embodiments, the epitaxial source / drain components 800 include materials and / or dopants that achieve a desired tensile stress and / or compressive stress in the respective channel regions CR. In some embodiments, the epitaxial source / drain components 800 are doped during deposition by adding impurities to the raw materials of the epitaxial process (i.e., in situ). In some embodiments, the epitaxial source / drain components 800 are doped by an ion implantation process after the deposition process. In some embodiments, an annealing process (e.g., rapid thermal annealing (RTA) and / or laser annealing) is performed to activate the epitaxial source / drain components 800 and / or other source / drain regions (e.g., heavily doped source / drain regions and / or lightly doped source / drain (LDD) regions). In some embodiments, the epitaxial source / drain features 800 are formed in separate process sequences, including, for example, masking the p-type GAA transistor region when forming the epitaxial source / drain features 800 in the n-type GAA transistor region and masking the n-type GAA transistor region when forming the epitaxial source / drain features 800 in the p-type GAA transistor region.

[0097] In some embodiments, Fig. 10AAs shown, an epitaxial source / drain component 800 is formed to include more than one epitaxial layer. Specifically, each epitaxial source / drain component 800 includes an inner heavily doped layer 800a and an outer lightly doped layer (or multiple layers) 800b. In one embodiment, the outer lightly doped layer 800b is first epitaxially grown in the deep trench 212 from the semiconductor layer 204a and the side surface of the substrate 202, and then the inner heavily doped layer 800a is epitaxially grown from the outer lightly doped layer 800b to fill the deep trench 212. The outer lightly doped layer 800b may have a thickness of 2 to 5 nanometers in the x-direction, and the inner heavily doped layer 800a fills the remaining space in the deep trench 212. It should be noted that the dielectric component 700 may directly interface with the inner heavily doped layer 800a. The source / drain component 800 may be grown to a height above the topmost first semiconductor layer 204a and be located between the gate spacers 211 of different dummy gate structures 208. As shown Fig. 10B As shown, source / drain features 800 are grown over the isolation structure 206 and over the dielectric features 700. It should be noted that in the cross-sectional schematic diagram, only the inner heavily doped layer 800a is present.

[0098] At operation 114 , the method 100 forms an ILD layer 900 over the source / drain features 800 and the isolation structure 206 , an example of which is shown in FIG. Fig.11A as well as Fig. 11B .like Fig.11A As shown, the ILD layer 900 also fills the space between adjacent dummy gate structures 208. The ILD layer 900 can be formed by a deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods or combinations thereof). In some embodiments, the ILD layer 900 is formed by a flowable chemical vapor deposition (FCVD) process, which includes, for example, depositing a flowable material (such as a liquid compound) on the device 200 and converting the flowable material into a solid material by a suitable technique (such as thermal annealing and / or ultraviolet radiation treatment). The ILD layer 900 includes a dielectric material, including, for example, silicon oxide, silicon nitride, silicon oxynitride, an oxide formed by tetraethylorthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), (Dow Chemical, Midland, Michigan) and / or combinations thereof. In the described embodiments, the ILD layer 900 is a dielectric layer including a low-k dielectric material (generally referred to as a low-k dielectric layer), and the ILD layer 900 may include a multilayer structure including a plurality of dielectric materials. In some embodiments, a contact etch stop layer (CESL) is disposed between the ILD layer 900 and the isolation structure 206, the epitaxial source / drain features 800, and the gate spacer 211. The CESL includes a material different from the ILD layer 900, such as a dielectric material different from the ILD layer 900, for example, in the case where the ILD layer 900 includes a low-k dielectric material, the CESL includes silicon and nitrogen, such as silicon nitride or silicon oxynitride. After the deposition of the ILD layer 900 and / or the CESL, a chemical mechanical polishing or planarization (CMP) process and / or other planarization processes may be performed until the top (or top surface) of the dummy gate stack 209 is reached (exposed).

[0099] At operation 116 , the method 100 forms the suspended semiconductor channel 205 by removing the dummy gate stack layer 209 from the dummy gate structure 208 and removing the second semiconductor layer 204 b . Fig. 12A as well as Fig.13A Exemplary process steps involved in operation 116 are depicted.

[0100] First, if Fig. 12AAs shown, the dummy gate stack 209 is removed by a suitable etching process, thereby generating a gate trench 275 and exposing the semiconductor stack 204. The etching process is designed with an etchant to selectively remove the dummy gate stack 209. In the described embodiment, the etching process completely removes the dummy gate stack 209 to expose the surfaces of the semiconductor layer 204a and the semiconductor layer 204b in the xz plane, and the etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination of the foregoing. In some embodiments, the etching process is a multi-step etching process, for example: the etching process may include alternative etchants to individually remove various layers of the dummy gate stack 209, such as the dummy gate electrode layer, the dummy gate dielectric layer, and / or the hard mask layer. In some embodiments, the etching process is configured to selectively etch the dummy gate stack 209, while etching other components of the device 200 (such as the ILD layer 900, the gate spacer 211, the semiconductor layer 204a, and the semiconductor layer 204b) is minimal (to no). In some embodiments, a photolithography process is performed to form a patterned mask layer covering the ILD layer 900 and / or the gate spacer 211 , and the etching process uses the patterned mask layer as an etching mask.

[0101] Secondly, if Fig.13AAs shown, the second semiconductor layer 204b (exposed by the gate trench 275) is selectively removed from the channel region CR to form the suspended semiconductor channel 205. In other words, the remaining portion of the semiconductor layer 204a now becomes the suspended semiconductor channel 205. In the described embodiment, the etching process selectively etches the semiconductor layer 204b, while the etching of the semiconductor layer 204a is minimal (to no etching), and in some embodiments, the etching of the gate spacer 211 and / or the inner spacer 216 is minimal (to no etching). Various etching parameters may be adjusted to achieve selective etching of the semiconductor layer 204b, such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source power, radio-frequency (RF) bias, RF bias power, etchant flow rate, other suitable etching parameters, or a combination of the foregoing, for example: the etchant is selected to etch the material of the semiconductor layer 204b (silicon germanium in the embodiment shown) at a higher rate than the material of the semiconductor layer 204a (silicon in the embodiment shown) (i.e., the etchant has a high etching selectivity relative to the material of the semiconductor layer 204b). The etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination of the foregoing. In some embodiments, a dry etching process (such as a reactive ion etching (RIE) process) utilizes a fluorine-containing gas (such as sulfur hexafluoride (SF6)) to selectively etch the semiconductor layer 204b. In some embodiments, the ratio of fluorine-containing gas to oxygen-containing gas (e.g., oxygen (O2)), etching temperature, and / or RF power can be adjusted to selectively etch silicon germanium (or silicon). In some embodiments, the wet etching process uses an etching solution including ammonium hydroxide (NH4OH) and water (H2O) to selectively etch the semiconductor layer 204b. In some embodiments, the chemical vapor etching process uses hydrochloric acid (HCl) to selectively etch the semiconductor layer 204b.

[0102] In operation 118, the method 100 forms a metal gate structure 308 (also referred to as a gate stack) above the channel region CR and surrounding each suspended semiconductor channel 205, an embodiment of which is shown in FIG. Fig.14A. Each gate structure 308 includes a gate dielectric layer 311 and a gate electrode 309 disposed on the gate dielectric layer 311. In some embodiments, the gate dielectric layer 311 includes an interface layer and a high dielectric constant dielectric layer disposed on the interface layer, and the gate electrode 309 may include one or more conductive materials, such as a cap layer, a work function metal layer, a blocking layer, a metal fill layer and / or other suitable conductive material layers. The work function layer (if present) may be the same or different and may be an n-type work function layer or a p-type work function layer, depending on the corresponding GAA transistor type. The gate dielectric layer 311 includes a high dielectric constant dielectric material, such as a material with a dielectric constant greater than silicon oxide (dielectric constant ≈ 3.9). The gate electrode 309 may be formed by a CVD process or a PVD process of depositing a metal fill layer, which fills the remaining portion of the gate trench 275 and above the gate dielectric layer 311. The metal fill layer includes a suitable conductive material, such as aluminum (Al), tungsten (W) and / or copper (Cu). The metal filling layer may additionally or collectively include other metals, metal oxides, metal nitrides, other suitable materials, or a combination of the foregoing, or the metal filling layer may be formed using another suitable deposition process, such as ALD, CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, spin coating, electroplating, other deposition processes, or a combination of the foregoing.

[0103] A planarization process is performed to remove excess gate material from the semiconductor device 200, such as a CMP process is performed until the top surface of the ILD layer 900 is reached (exposed), so that the top surface of the metal gate structure 308 is substantially flush with the top surface of the ILD layer 900 after the CMP process. As a result, the semiconductor device 200 now forms a GAA transistor with a gate structure 308 surrounding the respective channel layer 205 (now no longer suspended), wherein the gate structure 308 is disposed between the respective channel layers 205 along the z-direction and between the respective source / drain features 800 along the x-direction. In addition, the metal gate structure 308 is separated from the source / drain features 800 by the gate spacer 211 and the inner spacer 216.

[0104] At operation 120 , the method 100 forms a front side metal contact 292 over the source / drain features 800 . FIG. 15A to FIG. 17A as well as FIG. 15B to FIG. 17B The exemplary process steps for forming the front metal contact 292 are shown. First, Fig.15A as well as Fig. 15BAs shown, a front trench 285 is formed through the ILD layer 900 to expose the top surface of the epitaxial source / drain feature 800. The trench can be formed by any suitable etching process. In some embodiments, the front trench 285 extends into the source / drain feature 800 to a certain depth so that the source / drain feature 800 has a dipped top surface. The additional extension is to ensure that the subsequent metal contact feature has an appropriate surface contact area. Next, the metal contact feature is deposited into the front trench 285. The metal contact feature includes a silicide feature 290 ( Fig.16A as well as Fig. 16B ) and a metal filling layer 291 ( Fig.17A as well as Fig. 17B ) to form the front metal contact 292 ( Fig.15A as well as Fig. 15B ). The silicide feature 290 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. The metal fill layer 291 above the silicide feature 290 may include titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta), or molybdenum (Mo). Forming the front side metal contact 292 may include a CMP process for removing excess metal. The front side metal contact 292 may also be referred to as a front side via, which may be connected to additional front side metal lines or traces.

[0105] At operation 122 , method 100 forms an interconnect (or interconnect layer) 1002 over front side metal contact 292 and metal gate structure 308 , such as Fig.18A as well as Fig.18B. The interconnect layer 1002 includes electrically coupling various devices (e.g., p-type GAA transistors and / or n-type GAA transistors, transistors, resistors, capacitors and / or inductors of the device 200) and / or components (e.g., gate structures and / or epitaxial source / drain components of p-type GAA transistors and / or n-type GAA transistors) so that the various devices and / or components can operate in a manner specified by the design requirements of the device 200. The interconnect layer 1002 includes a combination of dielectric layers and conductive layers (e.g., metal layers), which are configured to form various interconnect structures, and the conductive layers are configured to form vertical interconnect components (e.g., device-level contacts and / or vias) and / or horizontal interconnect components (e.g., wires). Vertical interconnect components typically connect horizontal interconnect components in different layers (or different planes) of the interconnect layer. During operation, interconnect layer 1002 is configured to route signals between devices and / or elements of device 200 and / or distribute signals (eg, clock signals, voltage signals, and / or ground signals) to devices and / or elements of device 200 .

[0106] At operation 124, the method 100 turns over the workpiece 250 of the semiconductor device 200 so that the back side of the substrate 202 faces upward, an embodiment of which is shown in FIG. Fig.19A as well as Fig.19B To keep the directional labels consistent, the vertically upward axis is now shown as the -Z direction due to the flipping. After flipping the workpiece 250, operation 124 may include a CMP process to thin the substrate 202. After thinning, as shown in FIG. Fig.19B As shown, the isolation structure 206 may be exposed from the back side so that it is coplanar with the protruding portion 202a of the substrate 202. In some embodiments, the thinning of the substrate 202 includes thinning the isolation structure 206 from the back side, and it should be noted that the thinning does not expose the dielectric component 700. In a further embodiment (not shown), the backside substrate 202 is removed by a silicon removal process, followed by a silicon oxide deposition process, and thus, the substrate 202 may be replaced by a silicon oxide layer (also referred to as a backside ILD layer), for example: a selective wet etching process targets the substrate 202 without etching other surrounding components, and then a silicon oxide deposition (or silicon nitride plus silicon oxide double layer) process is performed, followed by a CMP process.

[0107] At operation 126, the method 100 etches the workpiece 250 from the back side to form a back side trench 295 that exposes the bottom surface of one of the source / drain features 800, an example of which is shown in FIG. Fig. 20A as well as Fig. 20B The backside trench 295 may be formed by an etching process similar to that used to form the frontside trench 285. Fig. 20AAs shown, the backside trench 295 is formed by etching through the thinned substrate 202 and one of the dielectric features 700 to expose the heavily doped inner layer 800a of one of the source / drain features 800. Fig. 20B As shown, the backside trench 295 is formed by etching through the protruding portion 202 a of the substrate 202 and the isolation structure 206 .

[0108] In operation 128, the method 100 forms a backside conductive feature 392 (ie, a backside via) in the backside trench 295 and on the exposed bottom surface of one of the source / drain features 800, an example of which is shown in FIG. Fig.23A as well as Fig. 23B .

[0109] Reference now Fig.21A as well as Fig.21B In some embodiments, before forming the back conductive component 392, a back barrier layer 393 is first formed along the sidewalls of the back trench 295. The barrier layer 393 is a dielectric barrier layer formed by a suitable process, the process including deposition and anisotropic etching (e.g., plasma etching) to remove the barrier layer deposited on the bottom surface of the trench. The barrier layer may include silicon nitride, silicon oxynitride, other suitable dielectric materials, or a combination thereof.

[0110] refer to Fig.23A as well as Fig. 23B , and then a backside metal contact component is deposited into the backside trench 295, the backside metal contact component including a backside silicide component 390 ( Fig.22A as well as Fig. 22B ) and the back metal filling layer 391 ( Fig.23A as well as Fig. 23B ) to form a backside metal contact 392 together. The backside silicide component 390 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi) or other suitable compounds. The backside metal filling layer 391 above the backside silicide component 390 may include titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta) or molybdenum (Mo). Forming the backside metal contact 392 may include a CMP process for removing excess metal. The backside metal contact 392 may also be referred to as a backside via, which can be connected to additional backside metal lines or traces.

[0111] Reference now Fig.23C as well as Fig.23D, for illustration and description of the related components, the workpiece 250 is flipped back to the xz and yz axes. As shown, the backside metal contact 392 (or backside via) is vertically spaced from the metal gate structure 308 by a distance d1'. Since the dielectric component 700 is etched away to expose the bottom of the source / drain component 800, the distance d1' is less than the etching distance d1 (see Figure 4A ), specifically, the distance d1' is the spacing between the bottommost gate portion of the metal gate structure 308 and the topmost surface of the backside metal contact 392, the bottommost gate portion of the metal gate structure 308 being below the bottommost channel layer 205 and above the top surface of the substrate 202. The ratio of the distance d1' to the thickness t1' is in the range of 1 to 3, and the thickness t1' is similar to the thickness t1 (see Figure 4A ), which is Fig.23C d1′ corresponds to the thickness of the gate portion of the metal gate structure 308 between the channel layer 205, the inner spacer 216, or the channel layer 205. The distance d1′ can be in the range of 5 to 30 nanometers, and the thickness t1′ can be in the range of 5 to 15 nanometers, but d1′ must be at least equal to or greater than t1′ to ensure a minimum ratio of d1′ to t1′, for example: if the thickness t1′ of the inner spacer 216 or the channel layer 205 is 5 nanometers, then the distance d1′ must also be at least 5 nanometers, because sufficient distance d1′ is required to ensure proper spacing and insulation between the backside via 392 and the bottom of the metal gate structure. The additional spacing prevents unnecessary current leakage and the possibility of shorting between the gate and the source / drain features, however, too large a spacing (such as a ratio of d1′ to t1′ greater than 3) is also undesirable because it will unnecessarily expand the device footprint. As long as the benefits of gate-to-backside via isolation are achieved, any excessive spacing (e.g., d1′ / t1′ greater than 3) will only generate additional cost and space. It should be noted that in the yz plane, the top surface of the backside via 392 may extend into the inner heavily doped layer 800 a of the source / drain feature 800 such that the top surface of the backside via 392 is above the top surface of the isolation structure 206 .

[0112] Still refer to Fig.23C as well as Fig.23D, one of the source / drain features 800 is connected to the backside via 392, while the other of the source / drain features 800 is not connected. For the source / drain features 800 that are not connected to the backside via 392, the dielectric cap 700 provides appropriate insulation to prevent stray conduction between those source / drain features 800 and other metal connections on the backside. Another advantage of the dielectric cap 700 is that it acts as an etch stop layer for proper etch height when forming the backside trench 295 and the backside via 392. Since the distance between the backside via 392 and the metal gate structure 308 is very sensitive, without the dielectric cap 700, it will be difficult to control the distance d1' and undesirable over-etching may occur. Using the dielectric cap 700, the appropriate distance d1' can be controlled to ensure the benefit of proper isolation between the metal gate structure 308 and the backside via 392.

[0113] The method 100 may perform further steps to complete the fabrication of the semiconductor device 200. Additional operations may be provided before, during, and after the method 100, such as forming another backside contact under another of the source / drain features 800. Furthermore, for additional embodiments of the method 100, some of the operations described may be moved, replaced, or eliminated, such as: Figure 24 to Figure 25 According to another embodiment of the present disclosure, a cross-sectional view of a semiconductor device 200 having a backside via 392 is shown.

[0114] Fig.24 Draw and Fig.23A The semiconductor workpiece 250 is substantially similar to the workpiece shown in FIG. 2 , except that the backside via 392 a is enlarged in the x-direction to have a greater width in the x-direction than the source / drain feature 800 . Fig.25 Draw and Fig.23A The semiconductor workpiece shown is substantially similar to the semiconductor workpiece 250, except that the backside vias 392b are via rails that contact the plurality of source / drain features 800 by extending longitudinally in the x-direction.

[0115] FIG. 26A to FIG. 26B1 is a flowchart of a method 1000 for forming a semiconductor device 200 having a backside via in part or in whole according to various embodiments of the present disclosure. Method 1000 is similar to method 100, and similar operation steps are not repeated for the sake of brevity. The difference between method 1000 and method 1000 is that method 1000 does not only form a deep trench 212, but forms a first trench (shallow trench) of a first depth and a second trench (deep trench) of a second depth, wherein the second trench is similar to the deep trench 212 described in method 100, specifically, in operation 107, method 1000 performs a first etch to form a first trench having a first depth adjacent to the channel region CR, and in operation 109, method 1000 performs a second etch on some of the first trenches to form a second trench of a second depth. The other operation steps substantially reflect the operations in the above-mentioned method 100. However, it should be noted that the formation of different components now corresponds to the first trench and the second trench.

[0116] The following will be combined FIG. 28A to FIG. 47A Depicted along Fig.27A as well as Fig.27B A schematic cross-sectional view of the semiconductor device 200 cut along the AA′ line and FIG. 28B to FIG. 29B , FIG. 32B to FIG. 35B ,as well as Figures 39B to 47B Depicted along Fig.27A as well as Fig.27B The method 1000 is further described with reference to the schematic cross-sectional views of the semiconductor device 200 cut along the BB' line. These figures depict various schematic views of the semiconductor device 200 at various stages of manufacture and manufactured according to embodiments of the present disclosure. The differences between the method 1000 and the method 100 will now be described in more detail. FIG. 27A to FIG. 47A , FIG. 27B to FIG. 29B , FIG. 32B to FIG. 35B ,as well as Figures 39B to 47B .

[0117] At operation 107, the method 1000 performs a first etch to form a first trench 1212a in the source / drain region SDR adjacent to the channel region CR of the device 200, an embodiment of which is shown in FIG. FIG. 29A to FIG. 29B. The first trench 1212a may also be referred to as a first source / drain trench (recess) and has sidewalls defined by the remaining portion of the semiconductor stack 204. The first trench 1212a may be formed by a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process, for example: the etching process may include alternative etchants to individually and alternately remove the semiconductor layer 204a and the semiconductor layer 204b. In some embodiments, the parameters of the etching process are configured to selectively etch the semiconductor stack 204, while minimally (to no) etching of the dummy gate structure 208 (i.e., the dummy gate stack 209 and the gate spacer 211). In some embodiments, a lithography process is performed to form a patterned mask layer covering the dummy gate structure 208 and / or a portion of the isolation structure 206, and the etching process uses the patterned mask layer as an etching mask.

[0118] refer to Fig.29A , the first groove 1212a (similar to Figure 4A The deep trench 212 in the first trench 1212a extends into the substrate 202 through the bottommost semiconductor layer 204b of the semiconductor stack 204. As shown in the figure, the distance d2 represents the etching distance between the bottommost semiconductor layer 204b and the bottommost surface of the first trench 1212a. It should be noted that the distance d2 is less than the distance d1 (see Figure 4A The ratio of the distance d2 to the thickness t1 of one of the first semiconductor layer 204a or the second semiconductor layer 204b can be in the range of 0 to 2, the distance d2 can be in the range of 5 to 20 nanometers, and the thickness t1 can be in the range of 5 to 15 nanometers. The distance d2 does not need to be very deep, as long as the side surface of the bottommost semiconductor layer 204b is exposed, and referring to FIG. 34A, the subsequent source / drain feature 800 in the first trench 1212a contacts the bottommost internal spacer 216. In some embodiments, the distance d2 is the thickness of the dielectric feature 700 to be deposited into the first trench 1212a. In other embodiments, the distance d2 is approximately the same as the thickness t1. Now referring to FIG. Fig.29B In some embodiments, when the distance d2 is not so deep, the first trench 1212a does not extend below the top surface of the isolation structure 206, and thus, many protrusions 202a of the substrate 202 remain after the first etching to form the first trench 1212a.

[0119] In operation 108, method 1000 forms inner spacers 216 in substantially the same manner as method 100, except that trenches 1212a are shallower in this step (see FIG. 30A to FIG. 31A In an alternative embodiment, operation 108 may be performed after operation 109, that is, the inner spacer 216 is formed after the first trench 1212a and the second trench 1212b are formed.

[0120] At operation 109 , the method 1000 performs a second etch to form a second trench 1212 b having a second depth deeper than the first trench 1212 a . Fig.32A as well as Fig.32B An embodiment is shown in which a second trench 1212b is formed adjacent to the first trench 1212a. The second trench 1212b may also be referred to as a second source / drain trench (recess) and is formed by further etching one or more first trenches 1212a. The second etching process may be performed using a lithography and patterning process similar to the first etching process.

[0121] Still refer to Fig.32A The second groove 1212b is similar in structure to Figure 4A The second trench 1212b has an etch distance d3 that is approximately equal to the etch distance d1. As shown, d3 is the distance between the bottom inner spacer 216 or the first semiconductor layer 204a or the second semiconductor layer 204b and the bottom surface of the second trench 1212b. The etch distance d3 is greater than the etch distance d2, and the ratio of the distance d3 to d2 can be in the range of 2 to 3, the distance d3 can be in the range of 20 to 50 nanometers, and the distance d2 can be in the range of 5 to 20 nanometers. The reason for the etch distance d3 is similar to that corresponding to Figure 4A The reason for the etching distance d1 is the same. Fig.32B In some embodiments, the first trench 1212 a does not extend below the top surface of the isolation structure 206 , but the second trench 1212 b extends below the top surface of the isolation structure 206 .

[0122] Referring back to method 1000, the remaining operations 110 to 128 are similar to the operations of method 100, and the intermediate process steps are as follows: FIG. 33A to FIG. 47B , FIG. 33B to FIG. 35B ,as well as Figures 39B to 47B As shown, the difference here is that the first source / drain feature 1800a is formed in the first trench 1212a, and the second source / drain feature 1800b is formed in the second trench 1212b. In addition, as shown in FIG. Fig.47A as well as Fig.47B As shown, the backside contact (or via) 392 is formed only under the second source / drain feature 1800 b.

[0123] Reference now Fig.47C as well as Fig.47DAfter operation 128 of method 1000, work object 250 is flipped back to the xz and yz axes for illustration and description of the related components. As shown, the backside metal contact 392 (or backside via) is vertically spaced from the metal gate structure 308 by a distance d3'. Since the dielectric component 700 is etched away to expose the bottom of the source / drain component 1800b, the distance d3' is less than the etching distance d3 (see Fig.32A ), specifically, the distance d3' is the spacing between the bottommost gate portion of the metal gate structure 308 and the topmost surface of the backside metal contact 392, the bottommost gate portion of the metal gate structure 308 being below the bottommost channel layer 205 and above the top surface of the substrate 202. The ratio of the distance d3' to the thickness t1' is in the range of 1 to 3, and the thickness t1' is similar to the thickness t1 (see Fig.32A ), which is Fig.47C d3′ corresponds to the thickness of the gate portion of the metal gate structure 308 between the channel layer 205, the inner spacer 216, or the channel layer 205. The distance d3′ can be in the range of 5 to 30 nanometers, and the thickness t1′ can be in the range of 5 to 15 nanometers, but d3′ must be at least equal to or greater than t1′ to ensure a minimum ratio of d3′ to t1′, for example, if the thickness t1′ of the inner spacer 216 or the channel layer 205 is 5 nanometers, then the distance d3′ must also be at least 5 nanometers, because sufficient distance d3′ is required to ensure proper spacing and insulation between the backside via 392 and the bottom of the metal gate structure. The additional spacing prevents unnecessary current leakage and the possibility of shorting between the gate and the source / drain features, however, too large a spacing (such as a ratio of d3′ to t1′ greater than 3) is also undesirable because it will unnecessarily expand the device footprint. As long as the benefits of gate-to-backside via isolation are achieved, any excessive spacing (e.g., d3′ / t1′ greater than 3) will only generate additional cost and space. It should be noted that in the yz plane, the top surface of the backside via 392 may extend into the inner heavily doped layer 800 a of the epitaxial source / drain feature 800 such that the top surface of the backside via 392 is above the top surface of the isolation structure 206 .

[0124] Still refer to Fig.47C as well as Fig.47D, only the second source / drain component 1800b is connected to the backside via 392 because they have a sufficient spacing d3' to isolate the backside via 392 from the gate structure 308. On the other hand, the first source / drain component 1800a is not connected to the backside via 392 because the spacing is not enough to isolate it from the gate structure 308. The remaining dielectric cap 700 provides appropriate insulation to prevent stray conduction between the first source / drain component 1800a and other metal connections on the back side. The first source / drain component 1800a with a shallower depth into the substrate 202 is also beneficial for further separation and isolation from other backside metal components. For the second source / drain component 1800b, the etched dielectric cap 700 acts as an etch stop layer for appropriate etching height when forming the backside trench 295 and the backside via 392. Since the distance between the backside via 392 and the metal gate structure 308 is very sensitive, without the dielectric cap 700, it will be difficult to control the distance d3' and undesirable over-etching may occur. Using the dielectric cap 700, the appropriate distance d3' can be controlled to ensure the benefit of proper isolation between the metal gate structure 308 and the backside via 392. It should be noted that the bottommost portion of the second source / drain feature 1800b (i.e., the portion in contact with the backside via 392) is below the bottommost portion of the first source / drain feature 1800a. In some embodiments, the bottommost portion of the second source / drain feature 1800b is also below the bottommost portion of the dielectric cap 700.

[0125] Method 1000 may perform further steps to complete the fabrication of semiconductor device 200. Additional operations may be provided before, during, and after method 1000, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of method 1000, such as: Figures 48 to 51 FIG. 1 is another embodiment of the present disclosure according to the method 1000 , and depicts a cross-sectional view of a semiconductor device 200 with a backside via.

[0126] Fig.48 Draw and Fig.47A , except that the backside via 392c is enlarged to have a larger width in the x-direction than the second source / drain component 1800b in the x-direction. In some embodiments, the backside via 392c is a via rail that connects the plurality of second source / drain components 1800b without connecting to the first source / drain component 1800a, which is possible because of the height difference between the first source / drain components 1800a and 1800b in the z-direction, and therefore, when viewed along the -z direction, the backside via 392c can cover the first source / drain component 1800a.

[0127] Fig.49Draw and Fig.47A , except that the width of the backside via 392d in the x-direction is less than the width of the second source / drain feature 1800b in the x-direction. It should be noted that in this embodiment, a portion of the dielectric feature 700 remains even after the backside trench 295 is etched and filled. Fig.50 The embodiment shown is similar to Fig.49 , except for the backside via 392e which is not lined with a barrier layer 393 . Fig.51 The embodiment shown is similar to Fig.50 , except that the back side guide hole 392f has an overlapping offset. Figures 49 to 51 As shown, the present disclosure contemplates backside vias with or without a barrier layer as well as having portions of dielectric features 700 remaining even after the backside vias are formed.

[0128] Although not limiting, various embodiments of the present disclosure provide advantages for semiconductor devices with backside vias. One illustrative advantage is that the backside vias are formed to be sufficiently separated from the metal gate structure on the backside, which separation prevents unwanted current leakage between the source / drain components and the metal gate. Another illustrative advantage is the use of a dielectric cap when forming the backside vias, thereby providing an appropriate etching distance. Another illustrative advantage is the use of a dielectric cap as an insulating layer for source / drain components without backside vias, thereby isolating these source / drain components from other metal components on the backside. Another illustrative advantage is the formation of source / drain components with different depths to control the formation of backside vias or backside via rails.

[0129] One aspect of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes receiving a workpiece, the workpiece having an active region extending from a substrate, the active region being surrounded by an isolation structure, and multiple portions of the active region protruding above the top surface of the isolation structure. The method includes forming a gate stack above a channel region of the active region and forming a first source / drain trench adjacent to the channel region and extending in the substrate below the top surface of the isolation structure. The method includes forming a first epitaxial source / drain component in the first source / drain trench. The method includes forming a first front side metal contact above the first epitaxial source / drain component. The method includes forming a first back side trench, the first back side trench exposing the bottom surface of the first epitaxial source / drain component and forming a first back side conductive component in the first back side trench and on the bottom surface exposed by the first epitaxial source / drain component, wherein the top surface of the first back side conductive component is below the bottommost surface of the gate stack.

[0130] In one embodiment, the method further includes forming a second source / drain trench adjacent to the channel region and extending below the top surface of the isolation structure. The method further includes forming a second epitaxial source / drain feature in the second source / drain trench and forming a second front side metal contact above the second epitaxial source / drain feature.

[0131] In yet another embodiment, the method further includes forming a second backside trench, the second backside trench exposing a bottom surface of the second epitaxial source / drain component; and forming a second backside conductive component in the second backside trench and on the exposed bottom surface of the second epitaxial source / drain component, wherein a top surface of the second backside conductive component is formed below the bottommost surface of the gate stack. In another embodiment, the first backside trench further exposes the bottom surface of the second epitaxial source / drain component, wherein the first backside conductive component extends in a direction to also be formed on the exposed bottom surface of the second epitaxial source / drain component.

[0132] In one embodiment, the method further includes forming a second source / drain trench adjacent to the channel region, wherein forming the first source / drain trench includes selectively etching the first source / drain trench deeper than the second source / drain trench.

[0133] In one embodiment, before forming the first epitaxial source / drain component, a dielectric component is formed on a bottom surface of the first source / drain trench, and forming the dielectric component includes conformally depositing a dielectric layer into the first source / drain trench, performing a plasma treatment on a top surface of the dielectric layer, and selectively etching away the dielectric layer on multiple sidewalls of the first source / drain trench.

[0134] In yet another embodiment, forming the first backside trench comprises etching through the dielectric feature in the first source / drain trench. In yet another embodiment, after forming the first backside conductive feature, a portion of the dielectric feature remains above the bottom surface of the first epitaxial source / drain feature.

[0135] In one embodiment, forming the first backside conductive component comprises forming a dielectric barrier layer along a plurality of sidewalls of the first backside trench. In one embodiment, the first epitaxial source / drain component has a lightly doped outer layer and a heavily doped inner layer, and the first backside conductive component is in direct contact with the heavily doped inner layer of the first epitaxial source / drain component.

[0136] Another aspect of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes receiving a semiconductor stack having a plurality of first semiconductor layers and a plurality of second semiconductor layers interlaced, wherein the semiconductor stack extends over an isolation structure above a substrate. The method includes performing a first etching process on a plurality of first source / drain regions and a plurality of second source / drain regions of the semiconductor stack to form a plurality of first source / drain trenches exposing a plurality of side surfaces of the semiconductor stack. The method includes performing a second etching process only on the second source / drain region of the semiconductor stack to form a plurality of second source / drain trenches, the second source / drain trenches being deeper into the substrate than the first source / drain trenches. The method includes forming a plurality of first dielectric components on a plurality of bottom surfaces of the first source / drain trenches. After forming the first source / drain component, a plurality of first source / drain components and a plurality of second source / drain components are formed in the first source / drain trenches and the second source / drain trenches, respectively. The method includes removing the second semiconductor layer from the semiconductor stack to form a plurality of suspended semiconductor channels in a channel region of the semiconductor stack. The method includes forming a metal gate structure above the channel region and surrounding each of the suspended semiconductor channels to form a plurality of wrapped semiconductor channels. And the method includes forming a plurality of backside source / drain trenches by etching from the back side of the substrate to expose a plurality of bottom surfaces of the second source / drain components, each of the exposed bottom surfaces being located below a bottommost portion of the metal gate structure, the bottommost portion of the metal gate structure surrounding a bottommost portion of the wrapped semiconductor channels.

[0137] In one embodiment, the method further comprises forming a backside via on a bottom surface of one of the second source / drain features. In another embodiment, before forming the first source / drain feature and the second source / drain feature, a plurality of second dielectric features are formed in the second source / drain trenches, wherein forming the backside source / drain trenches comprises etching through the second dielectric features in the second source / drain trenches.

[0138] In one embodiment, forming the metal gate structure includes forming a dummy gate stack above the channel region of the semiconductor stack. Before performing the second etching process, a plurality of sidewalls of each of the second semiconductor layer in the first source / drain trench are side-etched to form a plurality of air gaps. The method of forming a portion of the metal gate structure also includes forming a plurality of inner spacers in the air gaps, removing the dummy gate stack to expose a plurality of side surfaces of the semiconductor stack, and after removing the second semiconductor layer, replacing the dummy gate stack and the removed second semiconductor layer with a metal gate component.

[0139] Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes an active region protruding from a substrate and disposed between multiple portions of an isolation structure. The semiconductor device includes a gate stack disposed on a channel region of the active region. The semiconductor device includes a source / drain component above a source / drain region of the active region, wherein the source / drain component has an entrenched portion extending below a top surface of the substrate. The semiconductor device includes a backside silicide layer on a bottom surface of the source / drain component. The semiconductor device includes a backside via on a bottom surface of the backside silicide layer, wherein a top surface of the backside via is below a bottommost portion of the gate stack.

[0140] In one embodiment of the semiconductor device, the source / drain feature has a lightly doped outer layer and a heavily doped inner layer, and the backside via is in electrical contact with the heavily doped inner layer by directly contacting the backside silicide layer.

[0141] In one embodiment of the semiconductor device, the width of the backside via in the longitudinal direction of the active region is smaller than the width of the source / drain component. In another embodiment, the semiconductor device further comprises a silicon nitride cap on a first portion of the bottom surface of the source / drain component, wherein the backside via is disposed on a second portion of the bottom surface of the source / drain component.

[0142] In one embodiment, the semiconductor device further comprises a silicon nitride barrier layer on a plurality of sidewalls of the backside via.

[0143] In one embodiment of the semiconductor device, the source / drain component is a first source / drain component, and the semiconductor device further includes a second source / drain component above a second source / drain region of the active region, and a backside dielectric cap on a bottom surface of the second source / drain component, wherein the bottom surface of the first source / drain component is below the bottom surface of the second source / drain component.

[0144] The above summarizes the components of several embodiments so that those skilled in the art to which the present disclosure belongs can more easily understand the concepts of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: an active region protruding from a substrate and disposed between a plurality of portions of an isolation structure; a gate stack disposed on a channel region of the active region; a source / drain feature over a source / drain region of the active region, wherein the source / drain feature has a recess extending below a top surface of the substrate; a backside silicide layer on a bottom surface of the source / drain feature; as well as A backside via is on the bottom surface of the backside silicide layer, wherein a top surface of the backside via is below a bottommost portion of the gate stack.

2. The semiconductor device according to claim 1, wherein The source / drain component has a lightly doped outer layer and a heavily doped inner layer, and the back-side via is in electrical contact with the heavily doped inner layer by directly contacting the back-side silicide layer.

3. The semiconductor device according to claim 1, wherein The width of the back-side via along a longitudinal direction of the active region is smaller than the width of the source / drain component.

4. The semiconductor device according to claim 1 or 3, wherein: Also includes: A silicon nitride cap is on a first portion of the bottom surface of the source / drain component, wherein the backside via is disposed on a second portion of the bottom surface of the source / drain component.

5. The semiconductor device according to claim 1, wherein: Also includes: A silicon nitride barrier layer is formed on the sidewalls of the backside via.

6. The semiconductor device according to claim 1, wherein: The source / drain component is a first source / drain component, and the semiconductor device further includes: a second source / drain feature over a second source / drain region of the active region; and A backside dielectric cap is on a bottom surface of the second source / drain feature, wherein the bottom surface of the first source / drain feature is below the bottom surface of the second source / drain feature.

7. The semiconductor device according to claim 1, wherein: Also includes: A front side via is formed on the source / drain feature.

8. The semiconductor device according to claim 7, wherein: Also includes: An interconnect layer is on the front side via and the gate stack.

9. The semiconductor device according to claim 1, wherein: A bottom layer of the gate stack has a thickness, and the top surface of the back-side via is vertically spaced a distance from the bottom layer of the gate stack, wherein the distance is not less than the thickness.

10. The semiconductor device according to claim 1, wherein Also includes: A second backside via is provided on a bottom surface of a second source / drain component, wherein the backside via extends along a longitudinal direction of the active region to contact the second backside via.

Images