AURORA transmission circuit based on high-capacity FPGA

Abstract

The utility model discloses an AURORA transmission circuit based on a large-capacity FPGA, which comprises an FPGA chip D51 and an FPGA chip D88, the FPGA chip D51 and the FPGA chip D88 are connected through an AURORA transmission protocol, an AE45 pin of the FPGA chip D51 is electrically connected with a K29 pin of the FPGA chip D88 through a capacitor C957, an AE46 pin of the FPGA chip D51 is electrically connected with a K30 pin of the FPGA chip D88 through a capacitor C958, and the AE45 pin of the FPGA chip D51 is electrically connected with a K30 pin of the FPGA chip D88 through a capacitor C958. And an AD43 pin of the FPGA chip D51 is electrically connected with a J31 pin of the FPGA chip D88 through a capacitor C959. According to the AURORA transmission circuit based on the large-capacity FPGA disclosed by the utility model, the FPGA chip D51 and the FPGA chip D88 realize high transmission rate and capability through an AURORA transmission protocol, and the AURORA transmission circuit based on the large-capacity FPGA has the advantages of fast transmission, high practicability, wide application range and the like.

Description

Technical Field

[0001] The utility model belongs to the technical field of FPGA protocol transmission, and in particular relates to an AURORA transmission circuit based on a large-capacity FPGA. Background Art

[0002] Based on the continuous changes in market requirements and design concepts, the capacity requirements for FPGA boards are becoming larger and larger. As a result, the design requirements for various parts of FPGA boards are constantly increasing. Some existing transmission protocols between PFGA chips (data transmission between master and slave chips) have low transmission rates and poor transmission capabilities, which cannot meet the transmission requirements of high transmission rates and capabilities.

[0003] Therefore, further improvements are made to the above problems. Utility Model Content

[0004] The main purpose of the utility model is to provide an AURORA transmission circuit based on a large-capacity FPGA. The AURORA transmission protocol is used between the FPGA chip D51 and the FPGA chip D88 to achieve high transmission rate and capacity. It has the advantages of fast transmission, high practicality and wide range of use.

[0005] To achieve the above purpose, the utility model provides an AURORA transmission circuit based on a large-capacity FPGA, including an FPGA chip D51 and an FPGA chip D88, wherein the FPGA chip D51 and the FPGA chip D88 are connected via an AURORA transmission protocol, wherein:

[0006] The AE45 pin of the FPGA chip D51 is electrically connected to the K29 pin of the FPGA chip D88 via a capacitor C957, the AE46 pin of the FPGA chip D51 is electrically connected to the K30 pin of the FPGA chip D88 via a capacitor C958, the AD43 pin of the FPGA chip D51 is electrically connected to the J31 pin of the FPGA chip D88 via a capacitor C959, the AD44 pin of the FPGA chip D51 is electrically connected to the J32 pin of the FPGA chip D88 via a capacitor C960, and the FPGA chip D51 is electrically connected to the J33 pin of the FPGA chip D88 via a capacitor C961. The AC45 pin of the FPGA chip D1 is electrically connected to the H29 pin of the FPGA chip D88 through the capacitor C961, the AC46 pin of the FPGA chip D51 is electrically connected to the H30 pin of the FPGA chip D88 through the capacitor C962, the AB43 pin of the FPGA chip D51 is electrically connected to the G31 pin of the FPGA chip D88 through the capacitor C963, and the AB44 pin of the FPGA chip D51 is electrically connected to the G32 pin of the FPGA chip D88 through the capacitor C964; the AA45 pin of the FPGA chip D51 is electrically connected to the H29 pin of the FPGA chip D88 through the capacitor C961, the AC46 pin of the FPGA chip D51 is electrically connected to the H30 pin of the FPGA chip D88 through the capacitor C962, the AB43 pin of the FPGA chip D51 is electrically connected to the G31 pin of the FPGA chip D88 through the capacitor C963, and the AB44 pin of the FPGA chip D51 is electrically connected to the G32 pin of the FPGA chip D88 through the capacitor C964; The capacitor C1057 is electrically connected to the F29 pin of the FPGA chip D88, the AA46 pin of the FPGA chip D51 is electrically connected to the F30 pin of the FPGA chip D88 via the capacitor C1058, the Y43 pin of the FPGA chip D51 is electrically connected to the D29 pin of the FPGA chip D88 via the capacitor C1059, the Y44 pin of the FPGA chip D51 is electrically connected to the D30 pin of the FPGA chip D88 via the capacitor C1060, the W45 pin of the FPGA chip D51 is electrically connected to the The B29 pin of the FPGA chip D88 is electrically connected, the W46 pin of the FPGA chip D51 is electrically connected to the B30 pin of the FPGA chip D88 through the capacitor C1062, the V43 pin of the FPGA chip D51 is electrically connected to the A31 pin of the FPGA chip D88 through the capacitor C1063, and the V44 pin of the FPGA chip D51 is electrically connected to the A32 pin of the FPGA chip D88 through the capacitor C1064 (R0-7_P / R0-7_N represents 8 high-speed receiving pipelines, each of which can provide a 25G transmission rate);

[0007] The AE40 pin of the FPGA chip D51 is electrically connected to the L31 pin of the FPGA chip D88 via capacitor C1712, the AE41 pin of the FPGA chip D51 is electrically connected to the L32 pin of the FPGA chip D88 via capacitor C1713, the AD38 pin of the FPGA chip D51 is electrically connected to the K33 pin of the FPGA chip D88 via capacitor C1714, the AD39 pin of the FPGA chip D51 is electrically connected to the K34 pin of the FPGA chip D88 via capacitor C1715, and the FPGA chip The AC40 pin of D51 is electrically connected to the H33 pin of the FPGA chip D88 via a capacitor C1716, the AC41 pin of the FPGA chip D51 is electrically connected to the H34 pin of the FPGA chip D88 via a capacitor C1717, the AB38 pin of the FPGA chip D51 is electrically connected to the F33 pin of the FPGA chip D88 via a capacitor C1718, and the AB39 pin of the FPGA chip D51 is electrically connected to the F34 pin of the FPGA chip D88 via a capacitor C1719; the AA40 pin of the FPGA chip D51 is electrically connected to the H34 pin of the FPGA chip D88 via a capacitor C1717. The pin is electrically connected to the E31 pin of the FPGA chip D88 through a capacitor C1720, the AA41 pin of the FPGA chip D51 is electrically connected to the E32 pin of the FPGA chip D88 through a capacitor C1721, the Y38 pin of the FPGA chip D51 is electrically connected to the D33 pin of the FPGA chip D88 through a capacitor C1722, the Y39 pin of the FPGA chip D51 is electrically connected to the D34 pin of the FPGA chip D88 through a capacitor C1723, and the W40 pin of the FPGA chip D51 is electrically connected to the D35 pin of the FPGA chip D88 through a capacitor C1724. It is electrically connected to the C31 pin of the FPGA chip D88, the W41 pin of the FPGA chip D51 is electrically connected to the C32 pin of the FPGA chip D88 through capacitor C1725, the V38 pin of the FPGA chip D51 is electrically connected to the B33 pin of the FPGA chip D88 through capacitor C1726, and the V39 pin of the FPGA chip D51 is electrically connected to the B34 pin of the FPGA chip D88 through capacitor C1727 (T0-7_P / T0-7_N represents 8 high-speed transmission pipelines, each of which can provide 25G transmission rate).

[0008] As a further preferred technical solution of the above technical solution, the AG36 pin and the AG37 pin (also including AU36 / 37, etc.) of the FPGA chip D51 are used to provide a clock, and the clock is 125 MHz.

[0009] As a further preferred technical solution of the above technical solution, the B42 pin of the FPGA chip D51 is connected to the first power supply terminal (VCC1.2) and the B43 pin of the FPGA chip D51 is connected to the first power supply terminal through resistor R585 (used for voltage correction of the GTH transceiver of the FPGA chip).

[0010] As a further preferred technical solution of the above technical solution, the FPGA chip D51 also includes a first filter capacitor circuit.

[0011] As a further preferred technical solution of the above technical solution, the FPGA chip D88 also includes a second filter capacitor circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The utility model is a circuit diagram of an FPGA chip D51 of an AURORA transmission circuit based on a large-capacity FPGA.

[0013] Figure 2 The utility model is a circuit diagram of an FPGA chip D88 of an AURORA transmission circuit based on a large-capacity FPGA.

[0014] Figure 3 This is a first filter capacitor circuit diagram of an AURORA transmission circuit based on a large-capacity FPGA of the utility model.

[0015] Figure 4 The utility model discloses a second filter capacitor circuit diagram of an AURORA transmission circuit based on a large-capacity FPGA. DETAILED DESCRIPTION

[0016] The following description is used to disclose the utility model so that those skilled in the art can implement the utility model. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the utility model defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the utility model.

[0017] The utility model discloses an AURORA transmission circuit based on a large-capacity FPGA. The specific embodiments of the utility model are further described below in conjunction with preferred embodiments.

[0018] In the embodiments of the present invention, those skilled in the art will note that the capacitors and the like involved in the present invention may be regarded as prior art.

[0019] Preferred embodiments.

[0020] like Figure 1-4As shown, the utility model discloses an AURORA transmission circuit based on a large-capacity FPGA, including an FPGA chip D51 and an FPGA chip D88, wherein the FPGA chip D51 and the FPGA chip D88 are connected via an AURORA transmission protocol, wherein:

[0021] The AE45 pin of the FPGA chip D51 is electrically connected to the K29 pin of the FPGA chip D88 via a capacitor C957, the AE46 pin of the FPGA chip D51 is electrically connected to the K30 pin of the FPGA chip D88 via a capacitor C958, the AD43 pin of the FPGA chip D51 is electrically connected to the J31 pin of the FPGA chip D88 via a capacitor C959, the AD44 pin of the FPGA chip D51 is electrically connected to the J32 pin of the FPGA chip D88 via a capacitor C960, and the FPGA chip D51 is electrically connected to the J33 pin of the FPGA chip D88 via a capacitor C961. The AC45 pin of the FPGA chip D1 is electrically connected to the H29 pin of the FPGA chip D88 through the capacitor C961, the AC46 pin of the FPGA chip D51 is electrically connected to the H30 pin of the FPGA chip D88 through the capacitor C962, the AB43 pin of the FPGA chip D51 is electrically connected to the G31 pin of the FPGA chip D88 through the capacitor C963, and the AB44 pin of the FPGA chip D51 is electrically connected to the G32 pin of the FPGA chip D88 through the capacitor C964; the AA45 pin of the FPGA chip D51 is electrically connected to the H29 pin of the FPGA chip D88 through the capacitor C961, the AC46 pin of the FPGA chip D51 is electrically connected to the H30 pin of the FPGA chip D88 through the capacitor C962, the AB43 pin of the FPGA chip D51 is electrically connected to the G31 pin of the FPGA chip D88 through the capacitor C963, and the AB44 pin of the FPGA chip D51 is electrically connected to the G32 pin of the FPGA chip D88 through the capacitor C964; The capacitor C1057 is electrically connected to the F29 pin of the FPGA chip D88, the AA46 pin of the FPGA chip D51 is electrically connected to the F30 pin of the FPGA chip D88 via the capacitor C1058, the Y43 pin of the FPGA chip D51 is electrically connected to the D29 pin of the FPGA chip D88 via the capacitor C1059, the Y44 pin of the FPGA chip D51 is electrically connected to the D30 pin of the FPGA chip D88 via the capacitor C1060, the W45 pin of the FPGA chip D51 is electrically connected to the The B29 pin of the FPGA chip D88 is electrically connected, the W46 pin of the FPGA chip D51 is electrically connected to the B30 pin of the FPGA chip D88 through the capacitor C1062, the V43 pin of the FPGA chip D51 is electrically connected to the A31 pin of the FPGA chip D88 through the capacitor C1063, and the V44 pin of the FPGA chip D51 is electrically connected to the A32 pin of the FPGA chip D88 through the capacitor C1064 (R0-7_P / R0-7_N represents 8 high-speed receiving pipelines, each of which can provide a 25G transmission rate);

[0022] The AE40 pin of the FPGA chip D51 is electrically connected to the L31 pin of the FPGA chip D88 via capacitor C1712, the AE41 pin of the FPGA chip D51 is electrically connected to the L32 pin of the FPGA chip D88 via capacitor C1713, the AD38 pin of the FPGA chip D51 is electrically connected to the K33 pin of the FPGA chip D88 via capacitor C1714, the AD39 pin of the FPGA chip D51 is electrically connected to the K34 pin of the FPGA chip D88 via capacitor C1715, and the FPGA chip The AC40 pin of D51 is electrically connected to the H33 pin of the FPGA chip D88 via a capacitor C1716, the AC41 pin of the FPGA chip D51 is electrically connected to the H34 pin of the FPGA chip D88 via a capacitor C1717, the AB38 pin of the FPGA chip D51 is electrically connected to the F33 pin of the FPGA chip D88 via a capacitor C1718, and the AB39 pin of the FPGA chip D51 is electrically connected to the F34 pin of the FPGA chip D88 via a capacitor C1719; the AA40 pin of the FPGA chip D51 is electrically connected to the H34 pin of the FPGA chip D88 via a capacitor C1717. The pin is electrically connected to the E31 pin of the FPGA chip D88 through a capacitor C1720, the AA41 pin of the FPGA chip D51 is electrically connected to the E32 pin of the FPGA chip D88 through a capacitor C1721, the Y38 pin of the FPGA chip D51 is electrically connected to the D33 pin of the FPGA chip D88 through a capacitor C1722, the Y39 pin of the FPGA chip D51 is electrically connected to the D34 pin of the FPGA chip D88 through a capacitor C1723, and the W40 pin of the FPGA chip D51 is electrically connected to the D35 pin of the FPGA chip D88 through a capacitor C1724. It is electrically connected to the C31 pin of the FPGA chip D88, the W41 pin of the FPGA chip D51 is electrically connected to the C32 pin of the FPGA chip D88 through capacitor C1725, the V38 pin of the FPGA chip D51 is electrically connected to the B33 pin of the FPGA chip D88 through capacitor C1726, and the V39 pin of the FPGA chip D51 is electrically connected to the B34 pin of the FPGA chip D88 through capacitor C1727 (T0-7_P / T0-7_N represents 8 high-speed transmission pipelines, each of which can provide 25G transmission rate).

[0023] Specifically, the AG36 pin and the AG37 pin (also including AU36 / 37, etc.) of the FPGA chip D51 are used to provide a clock, and the clock is 125 MHz.

[0024] More specifically, the B42 pin of the FPGA chip D51 is connected to the first power supply terminal (VCC1.2) and the B43 pin of the FPGA chip D51 is connected to the first power supply terminal (used for voltage correction of the GTH transceiver of the FPGA chip) through a resistor R585.

[0025] Furthermore, the FPGA chip D51 also includes a first filtering capacitor circuit.

[0026] Furthermore, the FPGA chip D88 also includes a second filtering capacitor circuit.

[0027] It is worth mentioning that the technical features such as capacitors involved in this utility model patent application should be regarded as prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected by conventional methods in the field and should not be regarded as the invention point of this utility model patent. This utility model patent will not be further elaborated.

[0028] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present utility model should be included in the protection scope of the present utility model.

Claims

1. An AURORA transmission circuit based on a large-capacity FPGA, characterized in that: It includes an FPGA chip D51 and an FPGA chip D88, wherein the FPGA chip D51 and the FPGA chip D88 are connected via the AURORA transmission protocol, wherein: The AE45 pin of the FPGA chip D51 is electrically connected to the K29 pin of the FPGA chip D88 via a capacitor C957, the AE46 pin of the FPGA chip D51 is electrically connected to the K30 pin of the FPGA chip D88 via a capacitor C958, the AD43 pin of the FPGA chip D51 is electrically connected to the J31 pin of the FPGA chip D88 via a capacitor C959, and the AD44 pin of the FPGA chip D51 is electrically connected to the J32 pin of the FPGA chip D88 via a capacitor C960. The AC45 pin of the FPGA chip D51 is electrically connected to the H29 pin of the FPGA chip D88 via a capacitor C961, the AC46 pin of the FPGA chip D51 is electrically connected to the H30 pin of the FPGA chip D88 via a capacitor C962, the AB43 pin of the FPGA chip D51 is electrically connected to the G31 pin of the FPGA chip D88 via a capacitor C963, and the AB44 pin of the FPGA chip D51 is electrically connected to the G32 pin of the FPGA chip D88 via a capacitor C964; The AA45 pin of the FPGA chip D51 is electrically connected to the F29 pin of the FPGA chip D88 via a capacitor C1057, the AA46 pin of the FPGA chip D51 is electrically connected to the F30 pin of the FPGA chip D88 via a capacitor C1058, the Y43 pin of the FPGA chip D51 is electrically connected to the D29 pin of the FPGA chip D88 via a capacitor C1059, and the Y44 pin of the FPGA chip D51 is electrically connected to the D30 pin of the FPGA chip D88 via a capacitor C1060. , the W45 pin of the FPGA chip D51 is electrically connected to the B29 pin of the FPGA chip D88 through the capacitor C1061, the W46 pin of the FPGA chip D51 is electrically connected to the B30 pin of the FPGA chip D88 through the capacitor C1062, the V43 pin of the FPGA chip D51 is electrically connected to the A31 pin of the FPGA chip D88 through the capacitor C1063, and the V44 pin of the FPGA chip D51 is electrically connected to the A32 pin of the FPGA chip D88 through the capacitor C1064; The AE40 pin of the FPGA chip D51 is electrically connected to the L31 pin of the FPGA chip D88 via a capacitor C1712, the AE41 pin of the FPGA chip D51 is electrically connected to the L32 pin of the FPGA chip D88 via a capacitor C1713, the AD38 pin of the FPGA chip D51 is electrically connected to the K33 pin of the FPGA chip D88 via a capacitor C1714, the AD39 pin of the FPGA chip D51 is electrically connected to the K34 pin of the FPGA chip D88 via a capacitor C1715. The AC40 pin of the FPGA chip D51 is electrically connected to the H33 pin of the FPGA chip D88 via a capacitor C1716, the AC41 pin of the FPGA chip D51 is electrically connected to the H34 pin of the FPGA chip D88 via a capacitor C1717, the AB38 pin of the FPGA chip D51 is electrically connected to the F33 pin of the FPGA chip D88 via a capacitor C1718, and the AB39 pin of the FPGA chip D51 is electrically connected to the F34 pin of the FPGA chip D88 via a capacitor C1719. The AA40 pin of the FPGA chip D51 is electrically connected to the E31 pin of the FPGA chip D88 via a capacitor C1720, the AA41 pin of the FPGA chip D51 is electrically connected to the E32 pin of the FPGA chip D88 via a capacitor C1721, the Y38 pin of the FPGA chip D51 is electrically connected to the D33 pin of the FPGA chip D88 via a capacitor C1722, the Y39 pin of the FPGA chip D51 is electrically connected to the D34 pin of the FPGA chip D88 via a capacitor C1723. The W40 pin of the FPGA chip D51 is electrically connected to the C31 pin of the FPGA chip D88 through the capacitor C1724, the W41 pin of the FPGA chip D51 is electrically connected to the C32 pin of the FPGA chip D88 through the capacitor C1725, the V38 pin of the FPGA chip D51 is electrically connected to the B33 pin of the FPGA chip D88 through the capacitor C1726, and the V39 pin of the FPGA chip D51 is electrically connected to the B34 pin of the FPGA chip D88 through the capacitor C1727.

2. The AURORA transmission circuit based on a large-capacity FPGA according to claim 1, characterized in that: The AG36 pin and the AG37 pin of the FPGA chip D51 are used to provide a clock, and the clock is 125 MHz.

3. The AURORA transmission circuit based on a large-capacity FPGA according to claim 2 is characterized in that: The B42 pin of the FPGA chip D51 is connected to the first power supply terminal and the B43 pin of the FPGA chip D51 is connected to the first power supply terminal through a resistor R585.

4. The AURORA transmission circuit based on a large-capacity FPGA according to claim 3 is characterized in that: The FPGA chip D51 also includes a first filtering capacitor circuit.

5. The AURORA transmission circuit based on a large-capacity FPGA according to claim 4 is characterized in that: The FPGA chip D88 also includes a second filtering capacitor circuit.

Images