Mainboard system and electronic equipment
By storing multiple types of firmware in the same storage module in the motherboard system of electronic equipment, the problems of large firmware storage space and high cost in the existing technology are solved, and lower-cost and more efficient firmware storage is achieved, which is suitable for thinness and lightness. and integrated development needs.
Patent Information
- Application Number
- CN202420830694.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-19
- Publication Date
- 2025-01-21
- Estimated Expiration
- 2034-04-19
AI Technical Summary
In existing electronic devices, the firmware of each processor is stored in different storage modules, resulting in large space and high cost of motherboards, making it difficult to achieve the development trend of lightweight and integrated.
Design a motherboard system in which the BIOS firmware, EC firmware of the embedded controller, PD firmware of the PD controller and Thunderbolt interface firmware of the Thunderbolt interface chip are all stored in the same storage module. The CPU, embedded controller, PD control The processor and Thunderbolt interface chip can read their respective firmware from the storage module according to the set strategy.
By reducing the number of storage modules required to store firmware, the cost is reduced and the occupation of motherboard space is reduced, which is in line with the development trend of thinness, lightness and integration.
Smart Images
Figure CN222380111U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of computers, and in particular to a motherboard system and an electronic device. Background Art
[0002] Electronic devices include multiple processors, and different processors have their own firmware. The firmware of different processors is stored in corresponding storage modules, such as read-only memory, for the processor to retrieve. For example, BIOS firmware, PD (power delivery controller) firmware, EC (embedded controller) firmware, etc. are stored in different memories, which not only occupies the motherboard space, but also has high costs, which does not conform to the development trend of electronic devices to be thinner and more integrated. Utility Model Content
[0003] The present disclosure provides a mainboard system and an electronic device to at least solve the above technical problems existing in the prior art.
[0004] According to a first aspect of the present disclosure, there is provided a motherboard system, comprising:
[0005] Motherboard;
[0006] CPU, arranged on the main board;
[0007] A thunderbolt interface chip, provided on the mainboard and connected to the CPU, wherein the thunderbolt interface chip is connected to at least one thunderbolt interface;
[0008] An embedded controller, arranged on the mainboard and connected to the CPU;
[0009] A PD controller, disposed on the mainboard, the PD controller is connected to the CPU, the Thunderbolt interface chip and the embedded controller;
[0010] A storage module is arranged on the mainboard, the storage module is connected to the CPU, the Thunderbolt interface chip and the embedded controller, and the storage module stores BIOS firmware, EC firmware of the embedded controller, PD firmware of the PD controller and Thunderbolt interface firmware of the Thunderbolt interface chip.
[0011] In one possible implementation, the storage module is a SPI ROM, and the CPU, the Thunderbolt interface chip, and the embedded controller are respectively connected to the storage module via a SPI bus.
[0012] In one possible implementation, there is a first distance between the CPU and the storage module, a second distance between the embedded controller and the storage module, and a third distance between the Thunderbolt interface chip and the storage module, and the first distance, the second distance, and the third distance are all less than a first threshold.
[0013] In one possible implementation, it also includes a bus controller, which is used to set the other two interfaces connected to the SPI bus to a high-impedance state when one of the CPU, the Thunderbolt interface chip and the embedded controller obtains the corresponding firmware from the storage module via the SPI bus.
[0014] In one possible implementation, the CPU, the Thunderbolt interface chip, and the embedded controller respectively obtain the firmware from the storage module in a time-sharing manner through the SPI bus, and the timing of the SPI bus is configured as follows:
[0015] The embedded controller obtains the corresponding firmware through the SPI bus before the Thunderbolt interface chip obtains the corresponding firmware through the SPI bus, and the Thunderbolt interface chip obtains the corresponding firmware through the SPI bus before the CPU obtains the corresponding firmware through the SPI bus.
[0016] In one possible implementation, the embedded controller is connected to the PD controller via an I2C bus, and the embedded controller is configured to: obtain the EC firmware required by the embedded controller and the PD firmware required by the PD controller from the storage module via the SPI bus, and the embedded controller transmits the PD firmware stored in the internal storage unit of the embedded controller to the PD controller via the I2C bus, wherein the PD firmware is encapsulated in the EC firmware.
[0017] In one possible implementation, the embedded controller maps the EC firmware encapsulated with the PD firmware from the storage module to the internal storage unit of the embedded controller through a mirror code.
[0018] In one possible implementation, the PD controller is connected to the lightning interface chip via an I2C bus, and the PD controller is configured to: based on detecting a first signal indicating that a device is connected to the lightning interface, the PD controller pulls up the level of a power enable pin of the lightning interface chip to power on the lightning interface chip;
[0019] The Thunderbolt interface chip is configured to: based on power being turned on, the Thunderbolt interface chip obtains the Thunderbolt interface firmware through the SPI bus.
[0020] In one possible implementation, the Thunderbolt interface chip includes a retimer controller, and the PD controller is connected to the retimer controller via an I2C bus.
[0021] According to a second aspect of the present disclosure, an electronic device is provided, comprising the mainboard system described in the embodiment of the present disclosure.
[0022] In the motherboard system disclosed in the present invention, the BIOS firmware, the EC firmware of the embedded controller, the PD firmware of the PD controller and the Thunderbolt interface firmware of the Thunderbolt interface chip are all stored in the same storage module. The CPU, embedded controller, PD controller and Thunderbolt interface chip can read their respective firmware from the storage module according to the set strategy, thereby reducing the storage modules required to store the firmware, reducing the cost, and reducing the space occupied by the motherboard, which is in line with the development trend of lightweight and integration.
[0023] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which:
[0025] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.
[0026] Figure 1 A schematic structural diagram of a mainboard system according to an embodiment of the present disclosure is shown.
[0027] Explanation of the numbers in the figure: 1-mainboard, 2-CPU, 3-embedded controller, 4-PD controller, 5-storage module, 6-Thunderbolt interface chip. DETAILED DESCRIPTION
[0028] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.
[0029] See also Figure 1The embodiment of the present disclosure provides a motherboard system, including a motherboard 1, a CPU 2, a thunderbolt interface chip 6, an embedded controller 3, a PD controller 4 and a storage module 5. The CPU 2, the embedded controller 3, the PD controller 4 and the storage module 5 are all arranged on the motherboard 1. The thunderbolt interface chip 6 is connected to the CPU 2, and the thunderbolt interface chip 6 is connected to at least one thunderbolt interface; the embedded controller 3 is connected to the CPU 2; the PD controller 4 is connected to the CPU 2, the thunderbolt interface chip 6 and the embedded controller 3; the storage module 5 is connected to the CPU 2, the thunderbolt interface chip 6 and the embedded controller 3, and the storage module 5 stores BIOS firmware, EC firmware of the embedded controller 3, PD firmware of the PD controller 4 and thunderbolt interface firmware of the thunderbolt interface chip 6.
[0030] In the motherboard system of the embodiment of the present disclosure, the BIOS firmware, the EC firmware of the embedded controller 3, the PD firmware of the PD controller 4 and the Thunderbolt interface firmware of the Thunderbolt interface chip 6 are all stored in the same storage module 5. The CPU 2, the embedded controller 3, the PD controller 4 and the Thunderbolt interface chip 6 can read their respective firmware from the storage module 5 according to the set strategy, thereby reducing the storage modules 5 required to store the firmware, reducing the cost, and reducing the space occupied by the motherboard 1, which is in line with the development trend of lightweight and integration.
[0031] In the disclosed embodiment, the storage module 5 includes but is not limited to ROM (read-only memory) and Flash (non-volatile storage medium), ROM includes EPROM (erasable programmable read-only memory) and EEPROM (electrically erasable programmable read-only memory) and other read-only memories. Flash includes NOR Flash and NAND Flash.
[0032] A BIOS chip is generally provided on the mainboard 1 of the electronic device. In the embodiment of the present disclosure, the BIOS chip can be used as a storage module 5 for storing various firmware, thereby reducing the configuration of other storage modules 5.
[0033] In one embodiment, see Figure 1 , CPU2, thunderbolt interface chip 6 and embedded controller 3 are connected to storage module 5 through SPI bus respectively, and storage module 5 is SPI ROM. CPU2, thunderbolt interface chip 6 and embedded controller 3 can be directly connected to storage module 5 through SPI bus without conversion circuit.
[0034] In one possible implementation, there is a first distance between the CPU 2 and the storage module 5, there is a second distance between the embedded controller 3 and the storage module 5, there is a third distance between the lightning interface chip 6 and the storage module 5, and the first distance, the second distance, and the third distance are all less than the first threshold. The first distance, the second distance, and the third distance are all less than the first threshold, which can make the SPI routing between the CPU 2, the lightning interface chip 6, the embedded controller 3, and the storage module 5 more reasonable, meet the routing length requirements of the three branches, and easily meet the requirements of relevant design specifications.
[0035] The storage unit can be set at the center position between the CPU 2, the thunderbolt interface chip 6 and the embedded controller 3, so that the first distance, the second distance and the third distance meet the equal length condition. The difference between the first distance, the second distance and the third distance and the fourth distance is less than the second threshold, and the first distance, the second distance and the third distance meet the equal length condition. The fourth distance is the distance where the first distance, the second distance and the third distance are equal, and the second threshold can be, for example, 0.1mm, 0.3mm, 0.5mm, 1mm, etc.
[0036] In one possible implementation, the motherboard system of the embodiment of the present disclosure further includes a bus controller, and the bus controller is used to set the remaining two interfaces connected to the SPI bus to a high impedance state when one of the CPU2, the thunderbolt interface chip 6, and the embedded controller 3 obtains the corresponding firmware from the storage module 5 via the SPI bus. When one of the CPU2, the thunderbolt interface chip 6, and the embedded controller 3 obtains the corresponding firmware from the storage module 5 via the SPI bus, the bus controller sets the remaining two interfaces connected to the SPI bus to a high impedance state, which can prevent the remaining two processors from being affected.
[0037] In one possible implementation, CPU2, thunderbolt interface chip 6 and embedded controller 3 respectively obtain firmware from storage module 5 in time-division through SPI bus, and the timing of SPI bus is configured as follows: the timing of embedded controller 3 obtaining corresponding firmware through SPI bus is earlier than that of thunderbolt interface chip 6 obtaining corresponding firmware through SPI bus, and the timing of thunderbolt interface chip 6 obtaining corresponding firmware through SPI bus is earlier than that of CPU2 obtaining corresponding firmware through SPI bus. CPU2, PD controller 4, thunderbolt interface chip 6 and embedded controller 3 obtain their respective firmware according to preset strategies. Storage module 5 is respectively connected to CPU2, thunderbolt interface chip 6 and embedded controller 3 through SPI bus, and SPI bus can control the order and timing of CPU2, thunderbolt interface chip 6 and embedded controller 3 reading their respective firmware through chip select signal. In the implementation of the present disclosure, the timing of SPI bus refers to that when the three SPI branches connecting storage module 5 to CPU2, thunderbolt interface chip 6 and embedded controller 3 all have the need to read firmware, they are read in the above order, and if the processor with the highest priority does not have the need to read firmware, the corresponding firmware is read by other processors with the lowest priority in the order of priority.
[0038] In the embodiment of the present disclosure, the PD controller 4 is not directly connected to the storage module 5 , and the PD firmware required by the PD controller 4 can be obtained from the storage module 5 through the embedded controller 3 .
[0039] In one embodiment, see Figure 1 , the embedded controller 3 is connected to the PD controller 4 via the I2C bus, and the embedded controller 3 is configured to: obtain the EC firmware required by the embedded controller 3 and the PD firmware required by the PD controller 4 from the storage module 5 via the SPI bus, and the embedded controller 3 transmits the PD firmware stored in the internal storage unit of the embedded controller 3 to the PD controller 4 via the I2C bus. When the mainboard 1 of the electronic device is powered on for the first time, the BIOS firmware, EC firmware, PD firmware and Thunderbolt interface firmware are all stored in the storage module 5, and the embedded controller 3 needs to obtain the EC firmware first so that the electronic device can run smoothly. In the embodiment of the present disclosure, the PD firmware is encapsulated in the EC firmware. When the embedded controller 3 obtains the EC firmware from the storage module 5 via the SPI bus, the PD firmware is read together with the EC firmware to the internal storage unit of the EC, and the PD firmware encapsulated in the EC firmware is stored together in the internal storage unit of the EC, and then the controller 3 transmits the PD firmware to the PD controller 4. After the power is turned on for the first time, the EC firmware encapsulated with the PD firmware is stored in the internal storage unit of the EC. Before the corresponding firmware is updated or before the EC loses power, there is no need to obtain it from the storage module 5 again via the SPI bus, and the PD controller 4 can obtain the PD firmware from the EC.
[0040] In one possible implementation, the embedded controller 3 maps the EC firmware encapsulated with the PD firmware and the PD firmware from the storage module 5 to the internal storage unit of the embedded controller 3 through the mirror code.
[0041] In one embodiment, the PD controller 4 is connected to the lightning interface chip 6 via the I2C bus, and the PD controller 4 is configured to: based on the detection of the first signal indicating that a device is connected to the lightning interface, the PD controller 4 pulls up the level of the power enable pin of the lightning interface chip 6 to power on the lightning interface chip 6. After the PD controller 4 obtains the PD firmware, it can detect whether a device is connected to the lightning interface. If it is detected that a device is connected to the lightning interface, the PD controller 4 can power on the lightning interface chip 6 by pulling up the level of the power enable pin of the lightning interface chip 6. If no device is connected to the lightning interface, the PD controller 4 can keep the power enable pin of the lightning interface chip 6 at a low level.
[0042] The lightning interface chip 6 is configured as follows: upon powering on, the lightning interface chip 6 obtains the lightning interface firmware through the SPI bus. When the power start pin of the lightning interface chip 6 receives an enable signal, the lightning interface chip 6 can be powered on. When the lightning interface chip 6 is powered on, the lightning interface firmware is obtained from the storage module 5 through the SPI bus. If the power enable pin of the lightning interface chip 6 remains at a low level, the lightning interface chip 6 is not powered on, and the lightning interface chip 6 does not obtain the lightning interface firmware.
[0043] In one embodiment, the lightning interface chip 6 includes a retimer controller, and the PD controller 4 is connected to the retimer controller via an I2C bus. The lightning interface chip 6 is integrated with the retimer controller. Of course, in other exemplary embodiments, the retimer controller can also be replaced by other controllers.
[0044] In the disclosed embodiment, the embedded controller 3, the PD controller 4 and the Thunderbolt interface chip 6 can be configured by their respective firmware, so that in different situations, each controller can obtain its own firmware according to its own timing.
[0045] An embodiment of the present disclosure provides an electronic device, including a mainboard system of the embodiment of the present disclosure.
[0046] The electronic device of the embodiments of the present disclosure may be a mobile phone, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a virtual reality (VR) device, an artificial intelligence device, a wearable device, a vehicle-mounted device, etc.
[0047] Application scenario 1
[0048] After surface mounting, the mainboard system is powered on for the first time, and the power adapter or battery is connected. After the PD controller 4 and the embedded controller 3 are powered on, the embedded controller 3 first maps the EC firmware encapsulated with the PD firmware from the SPI ROM directly to the internal Flash of the embedded controller 3 through the SPI bus through the mirror code; the embedded controller 3 then transmits the PD firmware to the PD controller 4 through the I2C bus; at this time, the PD controller 4 detects whether an external device is connected to the Thunderbolt interface. If the PD controller 4 recognizes that a device is inserted into the Thunderbolt interface, the level of the power enable pin of the Thunderbolt interface chip 6 is controlled to power on the Thunderbolt interface chip 6. After that, the Thunderbolt interface chip 6 obtains the Thunderbolt interface firmware from the SPI ROM through the SPI bus; then, CPU2 obtains the BIOS firmware, initializes it, and starts the normal boot process.
[0049] In this case, the time when the Thunderbolt interface chip 6 obtains the Thunderbolt interface firmware is controlled by the chip select signal between the PD controller 4 obtaining the PD firmware and the CPU 2 obtaining the BIOS firmware, which does not affect the normal boot process. The three branches connected to the SPI ROM obtain the firmware from the SPI ROM separately in time sequence.
[0050] Application scenario 2
[0051] After the motherboard system is powered on for the first time, in normal use, as long as the PD firmware and EC firmware are not updated, the branch of the embedded controller 3 connecting to the SPI ROM will not be used again, see application scenario 1, because the EC firmware and PD firmware have been stored in the Flash inside the embedded controller 3 after the first power-on. When the user does not connect the battery, or the battery is out of power, or other reasons cause the embedded controller 3 to lose power, the user connects the power adapter or battery, and after the PD controller 4 and the EC controller are powered on, the embedded controller 3 first transmits the PD firmware to the PD controller 4 through the I2C bus; then, the PD controller 4 detects whether there is an external device connected to the Thunderbolt interface. If the PD controller 4 recognizes that a device is plugged into the Thunderbolt interface, it will control the level of the power enable pin of the Thunderbolt interface chip 6. After the Thunderbolt interface chip 6 is powered on, the Thunderbolt interface chip 6 obtains the Thunderbolt interface firmware from the SPI ROM through the SPI bus. After that, the CPU2 obtains the BIOS firmware, performs initialization, and starts the normal boot process.
[0052] In this case, the Thunderbolt interface chip 6 branch is still enabled first, and then CPU2 obtains the BIOS firmware.
[0053] Application scenario three
[0054] After the user boots up and enters the operating system, the external device is connected to the Thunderbolt interface, or other situations where the embedded controller 3 is not powered off and the PD controller 4 does not need to re-acquire the firmware can be regarded as the same situation. At this time, the PD controller 4 recognizes that an external device is connected to the Thunderbolt interface, and the PD controller 4 will control the level of the power enable pin of the Thunderbolt interface chip 6. After the Thunderbolt interface chip 6 is powered on, the Thunderbolt interface chip 6 obtains the Thunderbolt interface firmware from the SPI ROM through the SPI bus.
[0055] In this case, since the other two branches do not need to obtain firmware, of the three branches connected to the SPI ROM, only the Thunderbolt interface chip 6 is in use.
[0056] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of this disclosure can be achieved, and this document is not limited here.
[0057] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0058] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A motherboard system, characterized in that: include: Motherboard; CPU, arranged on the main board; A thunderbolt interface chip, provided on the mainboard and connected to the CPU, wherein the thunderbolt interface chip is connected to at least one thunderbolt interface; An embedded controller, arranged on the mainboard and connected to the CPU; A PD controller, disposed on the mainboard, the PD controller is connected to the CPU, the Thunderbolt interface chip and the embedded controller; A storage module is arranged on the mainboard, the storage module is connected to the CPU, the Thunderbolt interface chip and the embedded controller, and the storage module stores BIOS firmware, EC firmware of the embedded controller, PD firmware of the PD controller and Thunderbolt interface firmware of the Thunderbolt interface chip.
2. The motherboard system according to claim 1, characterized in that: The storage module is a SPI ROM, and the CPU, the thunderbolt interface chip and the embedded controller are respectively connected to the storage module via a SPI bus.
3. The motherboard system according to claim 2, characterized in that: There is a first distance between the CPU and the storage module, a second distance between the embedded controller and the storage module, and a third distance between the Thunderbolt interface chip and the storage module. The first distance, the second distance, and the third distance are all less than a first threshold.
4. The motherboard system according to claim 2, characterized in that: It also includes a bus controller, which is used to set the other two interfaces connected to the SPI bus to a high-impedance state when one of the CPU, the Thunderbolt interface chip and the embedded controller obtains the corresponding firmware from the storage module through the SPI bus.
5. The motherboard system according to claim 2, characterized in that: The CPU, the Thunderbolt interface chip, and the embedded controller obtain firmware from the storage module in a time-sharing manner through the SPI bus, and the timing of the SPI bus is configured as follows: The embedded controller obtains the corresponding firmware through the SPI bus before the Thunderbolt interface chip obtains the corresponding firmware through the SPI bus, and the Thunderbolt interface chip obtains the corresponding firmware through the SPI bus before the CPU obtains the corresponding firmware through the SPI bus.
6. The motherboard system according to claim 5, characterized in that: The embedded controller is connected to the PD controller via the I2C bus, and the embedded controller is configured to: obtain the EC firmware required by the embedded controller and the PD firmware required by the PD controller from the storage module via the SPI bus, and the embedded controller transmits the PD firmware stored in the internal storage unit of the embedded controller to the PD controller via the I2C bus, wherein the PD firmware is encapsulated in the EC firmware.
7. The motherboard system according to claim 6, characterized in that: The embedded controller maps the EC firmware encapsulated with the PD firmware from the storage module to the internal storage unit of the embedded controller through a mirror code.
8. The motherboard system according to claim 6, characterized in that: The PD controller is connected to the lightning interface chip via an I2C bus, and the PD controller is configured to: based on detecting a first signal indicating that a device is connected to the lightning interface, the PD controller pulls up the level of a power enable pin of the lightning interface chip to power on the lightning interface chip; The Thunderbolt interface chip is configured to: based on power being turned on, the Thunderbolt interface chip obtains the Thunderbolt interface firmware through the SPI bus.
9. The motherboard system according to claim 8, characterized in that: The thunderbolt interface chip includes a retimer controller, and the PD controller is connected to the retimer controller via an I2C bus.
10. An electronic device, characterized in that: A mainboard system comprising any one of claims 1-9.