Semiconductor structure and stitched die

Abstract

A semiconductor structure and a sewed die are provided. The semiconductor structure includes a first semiconductor die including a first contact pad; a second semiconductor die including a second contact pad; and a stitching die over the first semiconductor die and the second semiconductor die and including a third contact pad connected to the first contact pad and a fourth contact pad connected to the second contact pad. The apparatus also includes a cooling structure over the seamed die. The stitched die includes a first surface including a first dielectric layer in direct contact with the cooling structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures and stitched dies. Background Art

[0002] Stitching dies are used to interconnect multiple semiconductor dies to facilitate communication between the semiconductor dies. Utility Model Content

[0003] In some embodiments, a semiconductor structure includes: a first semiconductor die including a first contact pad; a second semiconductor die including a second contact pad; a stitching die located above the first semiconductor die and the second semiconductor die and including a third contact pad connected to the first contact pad and a fourth contact pad connected to the second contact pad. The device also includes a cooling structure located above the stitching die. The stitching die includes a first surface including a first dielectric layer directly contacting the cooling structure.

[0004] In some embodiments, a semiconductor structure includes a stitching die, a first semiconductor die, and a second semiconductor die. The stitching die includes a dielectric layer, a first conductive structure, and a second conductive structure. The first conductive structure is in the dielectric layer and extends to a first surface of the dielectric layer, and the second conductive structure is in the dielectric layer and extends to the first surface of the dielectric layer. The stitching die is bonded to the first semiconductor die and the second semiconductor die. The first semiconductor die includes a third conductive structure, and the second semiconductor die includes a fourth conductive structure. The first conductive structure contacts the third conductive structure, and the second conductive structure contacts the fourth conductive structure.

[0005] In some embodiments, a stitched die includes a dielectric layer having a first exposed surface and a second exposed surface, a first conductive structure, and a second conductive structure. The first conductive structure is embedded in the dielectric layer and extends to the first exposed surface but not to the second exposed surface. The second conductive structure is embedded in the dielectric layer and extends to the first exposed surface but not to the second exposed surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, the various aspects of the present disclosure are best understood from the following detailed description. It should be understood that the elements and / or structures of the accompanying drawings are not necessarily drawn to scale. Therefore, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1A to 1C are drawings of semiconductor stitching structures at various stages of fabrication according to some embodiments;

[0008] Figure 2 is a cross-sectional view illustrating a portion of a semiconductor structure according to some embodiments;

[0009] FIG. 3A to FIG. 3Dis a diagram illustrating a semiconductor package at various manufacturing stages according to some embodiments;

[0010] FIG. 4A to FIG. 4D is a diagram illustrating a semiconductor package at various manufacturing stages according to some embodiments;

[0011] Figure 5A and Figure 5B is a top view of a semiconductor package according to some embodiments.

[0012]

Explanation of symbols

[0013] 100:Structure

[0014] 105: substrate layer

[0015] 110: Base dielectric layer

[0016] 115: Interlayer dielectric layer

[0017] 115A: Interlayer dielectric layer

[0018] 115B: Interlayer dielectric layer

[0019] 115N: Interlayer dielectric layer

[0020] 120: Etching stop layer

[0021] 125A, 125B, 125C, 125D: Conductive contact

[0022] 130A, 130B, 130C, 130D: Conductive contact

[0023] 135A, 135B, 135C, 135D: Conductive contact

[0024] 130V:Through hole part

[0025] 130L: Line section

[0026] 135V:Through hole part

[0027] 135L: Line section

[0028] 140: passivation layer

[0029] 145A, 145B: Conductive contact pads

[0030] 150: Dielectric layer

[0031] 155: Hybrid bonding layer

[0032] 160A, 160B: Conductive contact pads

[0033] 160V:Through hole part

[0034] 160P: Contact pad

[0035] 160O: offset structure

[0036] 170: Stitching grain

[0037] 175: Exposed Surface

[0038] 180: Exposed surface

[0039] 200:Structure

[0040] 205: substrate layer

[0041] 210A: Device

[0042] 210B: Device

[0043] 215A, 215B: Gate dielectric layer

[0044] 220A, 220B: Gate electrode

[0045] 225A, 225B: Source / drain region

[0046] 230A, 230B: Sidewall spacers

[0047] 235A, 235B: Gate covering layer

[0048] 240: Shallow Trench Isolation Structure

[0049] 245: Dielectric layer

[0050] 250A, 250B: Conductive contact

[0051] 255: Device layer

[0052] 260: Dielectric layer

[0053] 260A: Dielectric layer

[0054] 260B: Dielectric layer

[0055] 260C: Dielectric layer

[0056] 260N: Dielectric layer

[0057] 265: Etching stop layer

[0058] 270A, 270B, 270C, 270D: Conductive structure

[0059] 275: Passivation layer

[0060] 280A, 280B: Conductive contact pads

[0061] 285: Grain

[0062] 285A, 285B, 285C, 285D: Grain

[0063] 290: Top surface

[0064] 295: Back

[0065] 300: Encapsulation

[0066] 305: Base

[0067] 310: Dielectric layer

[0068] 315: Hybrid bonding layer

[0069] 320A,320B: Conductive contact pads

[0070] 325: Bonding layer

[0071] 330A,330B: Conductive structure

[0072] 335A,335B: Conductive structure

[0073] 340: Dielectric layer

[0074] 345: Cooling structure

[0075] 350,355,360: Sealing ring

[0076] 400: Encapsulation

[0077] 405: Base

[0078] 410: Dielectric layer

[0079] 430A, 430B: Conductive structure

[0080] 435A, 435B: Conductive structure

[0081] 440: Dielectric layer

[0082] 445: Cooling structure

[0083] 450,455,460: Sealing ring

[0084] 500: Encapsulation

[0085] 505: Base

[0086] S: Spacing DETAILED DESCRIPTION

[0087] The following disclosure provides many different embodiments or implementations for implementing different features of the provided subject matter. In order to simplify the disclosure, specific embodiments of the components and arrangements are described below. Of course, these are merely embodiments and are not meant to be limiting. For example, in the description below, the description of forming a first feature above or on a second feature may include an embodiment in which the first and second features are directly in contact with each other, and may also include an embodiment in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, in various examples, the disclosure may reuse reference numbers and / or words. This repetition is for the purpose of simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0088] Additionally, spatially relative terms such as "below," "below," "lower," "above," "higher," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures for convenience. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein should be interpreted accordingly.

[0089] Provided herein are one or more techniques for forming semiconductor structures and the resulting structures formed thereby. According to some embodiments, the present application relates to a semiconductor structure and a method for manufacturing the same. According to some embodiments, stitched die are used to interconnect multiple semiconductor die to facilitate communication between semiconductor die and allow vertical arrangement of semiconductor die, such as stacked die. In some embodiments, the stitched die includes a conductive structure formed in one or more dielectric layers. One or more dielectric layers and the conductive structure are formed on a substrate layer of the semiconductor layer. The substrate layer is removed to expose one of the one or more dielectric layers. Using a hybrid bonding process, the stitched die is bonded to the semiconductor die of the underlying layer, and a cooling structure is formed on the exposed dielectric layer of the stitched die. Removing the substrate layer of the stitched die allows the cooling structure to be located closer to the semiconductor die of the underlying layer, thereby improving cooling efficiency and potentially improving processing performance.

[0090] Figures 1A to 1C FIG. 1 is a diagram illustrating a semiconductor stitching structure 100 at various stages of manufacture according to some embodiments. Figure 1AAccording to some embodiments, the semiconductor stitching structure 100 is formed on a substrate layer 105. The substrate layer 105 includes at least one of an epitaxial layer, a single crystal semiconductor material (such as but not limited to at least one of Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb or InP), a silicon-on-insulator (SOI) structure, a wafer or a die formed from a wafer. In some embodiments, the substrate layer 105 includes at least one of crystalline silicon or other suitable materials. Other structures and / or configurations of the substrate layer 105 are within the scope of the present disclosure.

[0091] In some embodiments, a base dielectric layer 110 is formed on the substrate layer 105. In some embodiments, the base dielectric layer 110 includes silicon dioxide or a low-k dielectric material. In some embodiments, the base dielectric layer 110 includes one or more layers of low-k dielectric material. The k value of the low-k dielectric material is less than about 3.9. In some embodiments, the material used for the base dielectric layer 110 includes at least one of Si, O, C or H, such as SiCOH, SiOC, oxygen-doped SiC (oxygen-doped SiC; ODC), nitrogen-doped SiC (nitrogen-doped SiC; NDC), plasma-enhanced oxide (plasma-enhanced oxide; PEOX) or other suitable materials. In some embodiments, the low-k dielectric material is further characterized or classified as ultra low-k (ULK), extra low-k (ELK) or extreme low-k (XLK), where this classification is generally based on the k value. For example, ULK generally refers to a material having a k value between about 2.7 and about 2.4, ELK generally refers to a material having a k value between about 2.3 and about 2.0, and XLK generally refers to a material having a k value less than about 2.0. Organic materials, such as polymers, may be used for the base dielectric layer 110. In some embodiments, the base dielectric layer 110 includes one or more layers of a carbon-containing material, an organic silicate glass, a porogen-containing material, or a combination thereof. In some embodiments, the base dielectric layer 110 includes nitrogen. In some embodiments, the base dielectric layer 110 is formed by using, for example, at least one of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), spin coating technology, or some other suitable process.

[0092] In some embodiments, the semiconductor stitching structure 100 includes one or more interlayer dielectric layers 115 formed on the base dielectric layer 110. According to some embodiments, the one or more interlayer dielectric layers 115 include a first interlayer dielectric layer 115A, a second interlayer dielectric layer 115B, and an Nth interlayer dielectric layer 115N. Any number of interlayer dielectric layers 115 is contemplated. One of the interlayer dielectric layers 115 may include a standard dielectric material with a medium or low dielectric constant, such as silicon dioxide. In some embodiments, as described for the base dielectric layer 110, at least one of the interlayer dielectric layers 115 includes a dielectric material with a relatively low dielectric constant. The interlayer dielectric layer 115 is formed in a variety of ways, such as by thermal growth, chemical growth, atomic layer deposition (ALD), CVD, PECVD, or some other suitable process. In some embodiments, one or more interlayer dielectric layers 115 include ULK or ELK dielectric materials in the lower portion, one or more interlayer dielectric layers 115 include low-k dielectric materials in the middle portion, and one or more interlayer dielectric layers 115 include standard-k dielectric materials, such as doped or undoped silicon glass, in the upper portion.

[0093] In some embodiments, the semiconductor stitching structure 100 includes one or more etch stop layers 120 to separate the interlayer dielectric layers 115. In some embodiments, the etch stop layers 120 stop the etching process between the interlayer dielectric layers 115. According to some embodiments, the etch stop layers 120 include a dielectric material having an etching selectivity different from that of the interlayer dielectric layers 115. In some embodiments, at least one etch stop layer 120 includes SiN, SiCN, SiCO, CN, etc., alone or in combination. The etch stop layers 120 are formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, or some other suitable process.

[0094] In some embodiments, the semiconductor stitching structure 100 includes one or more conductive contacts 125A, 125B, 125C, 125D formed in the interlayer dielectric layer 115A. The conductive contacts 125A, 125B, 125C, 125D are formed in a variety of ways, such as by a single damascene process, a dual damascene process, a trench silicide process, or some other suitable process. In some embodiments, the conductive contacts 125A, 125B, 125C, 125D include a barrier layer, a seed layer, a metal fill layer, or other suitable layer. The metal fill layer may include tungsten, aluminum, copper, cobalt, or other suitable materials. Other structures and configurations of the conductive contacts 125A, 125B, 125C, 125D are within the scope of the present disclosure.

[0095] In some embodiments, the semiconductor stitching structure 100 includes one or more conductive contacts 130A, 130B, 130C, 130D formed in the interlayer dielectric layer 115B. In some embodiments, the conductive contacts 130A, 130B, 130C, 130D extend through the interlayer dielectric layer 115B. In some embodiments, some of the conductive contacts 130A, 130B, 130C, 130D include a via portion 130V and a line portion 130L. The line portion 130L has an axial length extending out of the page. In some embodiments, the conductive contacts 130A, 130B, 130C, 130D include a barrier layer, a seed layer, a metal fill layer, or other suitable layers. The metal fill layer may include tungsten, aluminum, copper, cobalt, or other suitable materials. Other structures and devices of the conductive contacts 130A, 130B, 130C, 130D are included within the scope of the present disclosure.

[0096] In some embodiments, the semiconductor stitching structure 100 includes one or more conductive contacts 135A, 135B, 135C, 135D formed in the interlayer dielectric layer 115N. In some embodiments, the conductive contacts 135A, 135B, 135C, 135D extend through the interlayer dielectric layer 115N. In some embodiments, some of the conductive contacts 135A, 135B, 135C, 135D include a via portion 135V and a line portion 135L. The line portion 135L has an axial length extending out of the page. In some embodiments, the conductive contacts 135A, 135B, 135C, 135D include a barrier layer, a seed layer, a metal fill layer, or other suitable layers. The metal fill layer may include tungsten, aluminum, copper, cobalt, or other suitable materials. Other structures and devices of the conductive contacts 135A, 135B, 135C, 135D are included within the scope of the present disclosure.

[0097] Conductive contacts 125A, 130A, 135A define a seal ring for semiconductor stitching structure 100. Conductive contacts 125B, 130B, 135B and conductive contacts 125D, 130D, 135D define a conductive structure with external contacts, and conductive contacts 125C, 130C, 135C define a conductive structure without external contacts.

[0098] In some embodiments, a passivation layer 140 is formed on the uppermost interlayer dielectric layer 115N. The passivation layer 140 may include one or more layers. In some embodiments, the passivation layer 140 includes a polymer layer such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), an inorganic-organic hybrid material such as Or some other suitable passivation material. The passivation layer 140 serves as a mechanical protection and stress buffer layer. In some embodiments, a precursor of the passivation layer 140 is deposited by spin coating and / or other suitable techniques. In the passivation layer 140, conductive contact pads 145A, 145B are formed to contact the conductive contacts 135A, 135C below, respectively. In some embodiments, the conductive contact pads 145A, 145B include a barrier layer, a seed layer, a metal filling layer or other suitable layers. The metal filling layer may include tungsten, aluminum, copper, cobalt or other suitable materials. The conductive contact pads 145A, 145B may be formed by forming a groove in the passivation layer 140, forming the material of the conductive contact pads 145A, 145B in the groove, and performing a planarization process to remove part of the material outside the groove.

[0099] Reference Figure 1B According to some embodiments, a dielectric layer 150 and a hybrid bonding layer 155 are formed over the passivation layer 140, and conductive contact pads 160A, 160B are formed in the dielectric layer 150 and the hybrid bonding layer 155. In some embodiments, as described for the base dielectric layer 110, the dielectric layer 150 includes a dielectric material with a relatively low dielectric constant. The dielectric layer 150 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, or some other suitable process. In some embodiments, the hybrid bonding layer 155 includes a standard k dielectric material, such as silicon dioxide, doped or undoped silicon glass, SiON, or some other dielectric material. Some conductive contact pads 160A, 160B may include a through hole portion 160V and a contact pad 160P. In some embodiments, the conductive contact pads 160A, 160B include a barrier layer, a seed layer, a metal filling layer, or other suitable layers. The metal filling layer may include tungsten, aluminum, copper, cobalt, or other suitable materials. One or more of the conductive contact pads 160A, 160B may include an offset structure 160O that provides a lateral offset from a substantially linear stack of conductive contacts (e.g., conductive contacts 125D, 130D, 135D, 145B) in the conductive contact structure. In some embodiments, the conductive contact pads 160A, 160B include a barrier layer, a seed layer, a metal fill layer, or other suitable layer. The metal fill layer may include tungsten, aluminum, copper, cobalt, or other suitable material. The conductive contact pads 160A, 160B may be formed by forming recesses in the dielectric layer 150 and the hybrid bonding layer 155, forming the material of the conductive contact pads 160A, 160B in the recesses, and performing a planarization process to remove portions of the material outside the recesses. Other structures and configurations of the conductive contact pads 160A, 160B are contemplated within the scope of the present disclosure.

[0100] Reference Figure 1C, according to some embodiments, the substrate layer 105 is removed. In some embodiments, the semiconductor stitching structure 100 is inverted and a planarization process is performed to remove the substrate layer 105. The planarization process may terminate in response to exposing the base dielectric layer 110 or after a predetermined period of time. A semiconductor wafer including a plurality of semiconductor stitching structures 100 may be cut to provide a stitching die 170 having a first exposed surface 175 including a dielectric material (e.g., the base dielectric layer 110) and a second exposed surface 180 including a dielectric material (e.g., the hybrid bonding layer 155). In some embodiments, the stitching die 170 has a thickness of at least about 0.5 microns and includes at least two metallization layers to reduce the likelihood of stress-induced cracks.

[0101] Figure 2 is a cross-sectional view of a portion of a semiconductor structure 200 according to some embodiments. According to some embodiments, Figure 1C The semiconductor stitching structure 100 is used to interconnect Figure 2 In one embodiment, the semiconductor structure 200 is formed on a substrate layer 205, and the substrate layer 205 includes at least one of an epitaxial layer, a single crystal semiconductor material (such as but not limited to at least one of Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb, or InP), a silicon-on-insulator (SOI) structure, a wafer, or a grain formed from a wafer. In some embodiments, the substrate layer 205 includes at least one of crystalline silicon or other suitable materials. Other structures and / or configurations of the substrate layer 205 are included within the scope of the present disclosure.

[0102] According to some embodiments, the semiconductor structure 200 includes a first device 210A and a second device 210B formed on or in a substrate layer 205. In some embodiments, the first device 210A and the second device 210B each include a gate dielectric layer 215A, 215B, a gate electrode 220A, 220B, a source / drain region 225A, 225B, a sidewall spacer 230A, 230B, a gate cap layer 235A, 235B, etc. According to some embodiments, a gate replacement process is used to form the gate dielectric layer 215A, 215B and the gate electrode 220A, 220B. A sacrificial gate structure including a sacrificial gate dielectric layer, a sacrificial gate electrode layer (e.g., a polysilicon layer), and a hard mask layer is formed. In some embodiments, a patterning process is performed to pattern a hard mask layer corresponding to a pattern of a gate structure to be formed, and an etching process is performed using the patterned hard mask layer to etch the sacrificial gate electrode layer and the sacrificial gate dielectric layer to define the sacrificial gate structure. In some embodiments, after the etching process, the remaining portion of the hard mask layer forms a capping layer over the remaining portion of the sacrificial gate electrode layer. The sacrificial gate structure is subsequently replaced by a replacement gate dielectric layer, such as gate dielectric layers 215A, 215B, and a replacement gate electrode, such as gate electrodes 220A, 220B.

[0103] In some embodiments, the gate dielectric layers 215A, 215B include a high-k dielectric material. As used herein, the term "high-k dielectric" refers to a material having a dielectric constant k greater than or equal to about 3.9 (the k value of SiO2). The high-k dielectric material can be any suitable material. Examples of high-k dielectric materials include, but are not limited to, Al2O3, HfO2, ZrO2, La2O3, TiO2, SrTiO3, LaAlO3, Y2O3, Al2O x N y , HfO x N y 、ZrOxNy、La2O x N y 、TiO x N y 、SrTiO x N y 、LaAlO x N y 、Y2O x N y 、SiON、SiN x, silicates thereof, and alloys thereof. Each value of x is independently from 0.5 to 3, and each value of y is independently from 0 to 2. In some embodiments, the gate electrodes 220A, 220B include a barrier layer, one or more work function material layers, a seed layer, a metal filling layer, or other suitable layers. In some embodiments, the metal filling layer includes tungsten, aluminum, copper, cobalt, or other suitable materials. In some embodiments, the gate dielectric layer 215A, 215B and one or more layers including the gate electrodes 220A, 220B are deposited by at least one of ALD, physical vapor deposition (PVD), CVD, LPCVD, ALCVD, ultrahigh vacuum CVD (ultrahigh vacuumCVD; UHVCVD), reduced pressure CVD (reduced pressure CVD; RPCVD), molecular beam epitaxy (molecular beamepitaxy; MBE), or other suitable techniques. In some embodiments, the gate electrodes 220A, 220B are recessed and the gate cap layers 235A, 235B are formed in the recesses.

[0104] In some embodiments, the sidewall spacers 230A, 230B are formed adjacent to the gate dielectric layer 215A, 215B and the gate electrode 220A, 220B. In some embodiments, the sidewall spacers 230A, 230B are formed by depositing a spacer layer over the sacrificial gate structure and performing an anisotropic etching process to remove horizontal portions of the spacer layer. In some embodiments, the sidewall spacers 230A, 230B include silicon nitride or other suitable materials.

[0105] In some embodiments, after forming the sacrificial gate structure, source / drain regions 225A, 225B are formed in the substrate layer 205. For example, in some embodiments, portions of the substrate layer 205 are doped by an implantation process to form the source / drain regions 225A, 225B. In some embodiments, an etching process is performed to recess the substrate layer 205 adjacent to the sidewall spacers 230A, 230B, and an epitaxial growth process is performed to form the source / drain regions 225A, 225B.

[0106] In one embodiment, one or more shallow trench isolation (STI) structures 240 are formed within the substrate layer 205. In some embodiments, the STI structure 240 is formed by forming at least one mask layer over the substrate layer 205. In some embodiments, the at least one mask layer includes an oxide material layer over the substrate layer 205 and a nitride material layer over the oxide material layer and / or one or more other suitable layers. At least a portion of the at least one mask layer is removed to define an etching mask to be used as a template to etch the substrate layer 205 to form a trench. In the trench, a dielectric material is formed to define the STI structure 240. In some embodiments, the STI structure 240 includes multiple layers, such as an oxide liner, a nitride liner formed on the oxide liner, an oxide filling material formed on the nitride liner, and / or other suitable materials. Other structures and / or configurations of the STI structure 240 are included within the scope of the present disclosure.

[0107] In some embodiments, the devices 210A, 210B are formed using the same materials and layer thicknesses. In some embodiments, different materials and / or thicknesses may be used due to different voltage domains. For example, the materials and / or thicknesses of the gate dielectric layers 215A, 215B may be different from each other. In some embodiments, the materials of the gate electrodes 220A, 220B may also be different. Other structures and configurations of the devices 210A, 210B are encompassed within the scope of the present disclosure. For example, the devices 210A, 210B may be fin field effect transistor (finFET) devices, nanosheet devices, nanowire devices, or some other suitable devices.

[0108] In some embodiments, a dielectric layer 245 is formed over the devices 210A, 210B. In some embodiments, the dielectric layer 245 includes silicon dioxide or a low-k dielectric material. In some embodiments, the dielectric layer 245 is formed by using at least one of, for example, CVD, PECVD, LPCVD, ALCVD, spin coating technology, or some other suitable process.

[0109] In some embodiments, the semiconductor structure 200 includes one or more conductive contacts 250A, 250B formed in the dielectric layer 245. The conductive contacts 250A, 250B are formed in a variety of ways, such as by a single damascene process, a dual damascene process, a trench silicide process, or some other suitable process. In some embodiments, the conductive contacts 250A, 250B contact the gate electrodes 220A, 220B, and additional contacts (not shown) are formed to contact the source / drain regions 225A, 225B at different locations along the axial length of the devices 210A, 210B (e.g., into or out of the paper). In some embodiments, the conductive contacts 250A, 250B include a barrier layer, a seed layer, a metal fill layer, or other suitable layers. In some embodiments, the metal fill layer includes tungsten, aluminum, copper, cobalt, or other suitable materials. In some embodiments, the devices 210A, 210B, the conductive contacts 250A, 250B, and the dielectric layer 245 define a device layer 255 of the semiconductor structure 200. Other structures and configurations of the conductive contacts 250A, 250B are contemplated within the scope of the present disclosure.

[0110] In some embodiments, the semiconductor structure 200 includes one or more dielectric layers 260 formed above the device layer 255. According to some embodiments, the one or more dielectric layers 260 include a second dielectric layer 260A, a third dielectric layer 260B, a fourth dielectric layer 260C, and an nth dielectric layer 260N. Any number of dielectric layers 260 is contemplated. In some embodiments, at least one of the dielectric layers 260 includes a standard dielectric material (e.g., SiO2) having a medium or low dielectric constant. In some embodiments, as described for dielectric layer 245, at least one of the dielectric layers 260 includes a dielectric material having a relatively low dielectric constant. The dielectric layer 260 is formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, or some other suitable process. In some embodiments, one or more dielectric layers 260 include ULK or ELK dielectric materials in the lower portion, one or more dielectric layers 260 include low-k dielectric materials in the middle portion, and one or more dielectric layers 260 include standard-k dielectric materials, such as doped or undoped silicon glass, in the upper portion.

[0111] In some embodiments, the semiconductor structure 200 includes one or more etch stop layers 265 separating the dielectric layers 260. In some embodiments, the etch stop layers 265 stop the etching process between the dielectric layers 260. According to some embodiments, the etch stop layers 265 include a dielectric material having a different etching selectivity than the dielectric layers 260. In some embodiments, at least one of the etch stop layers 265 includes SiN, SiCN, SiCO, CN, etc., alone or in combination. The etch stop layers 265 are formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, or some other suitable process.

[0112] In some embodiments, the semiconductor structure 200 includes one or more conductive structures 270A, 270B, 270C, 270D. The conductive structures 270A, 270B, 270C, 270D may be constructed using the same techniques as described above. Figure 1A The conductive structures 270A, 270B, 270C, 270D are formed by similar techniques described. In some embodiments, the conductive structures 270A, 270B, 270C, 270D extend through their respective dielectric layers 260. The combination of a particular dielectric layer 260 and the related portions of the conductive structures 270A, 270B, 270C, 270D in the particular dielectric layer 260 defines a metallization layer, such as metallization layers "M0", "M1", "M2" and "Mx". The conductive structures 270A, 270B are structures for contacting the underlying devices 210A, 210B, respectively. When multiple dies are stacked, the conductive structure 270C is a through silicon via (TSV) for contacting the underlying dies. The conductive structure 270D is a sealing ring of the semiconductor structure 200.

[0113] In some embodiments, a passivation layer 275 is formed on the topmost dielectric layer 260N. The passivation layer 275 may include one or more layers. In some embodiments, the passivation layer 275 includes a polymer layer such as polyimide, BCB, PBO, an inorganic-organic hybrid material such as ORMOCER or some other suitable passivation material. The passivation layer 275 is used as a mechanical protection and stress buffer layer. In some embodiments, the precursor of the passivation layer 275 is deposited by spin coating and / or other suitable techniques. In the passivation layer 275, conductive contact pads 280A, 280B are formed to contact the underlying conductive structures 270A, 270B respectively. In some embodiments, the conductive contact pads 280A, 280B include a barrier layer, a seed layer, a metal filling layer or other suitable layers. The metal filling layer may include tungsten, aluminum, copper, cobalt or other suitable materials. Conductive contact pads 280A, 280B may be formed by forming a recess in passivation layer 275, forming a material of conductive contact pads 280A, 280B in the recess, and performing a planarization process to remove a portion of the material outside the recess. A semiconductor wafer including a plurality of semiconductor structures 200 may be cut to provide semiconductor grains 285 having a top surface 290 and a back surface 295.

[0114] FIG. 3A to FIG. 3D A semiconductor package 300 is shown at various stages of fabrication according to some embodiments. Figure 3A According to some embodiments, the first semiconductor die 285A and the second semiconductor die 285B are mounted to the substrate 305 in a top-up configuration. Figure 2 . In some embodiments, the substrate 305 includes one or more additional semiconductor die arranged in a stack, wherein the first semiconductor die 285A and the second semiconductor die 285B represent the top semiconductor die in the stack. In some embodiments, the substrate 305 is a circuit board or an interposer. The substrate 305 can be a bonding layer, such as SiO2 or SiON, and the first semiconductor die 285A and the second semiconductor die 285B use a process of applying pressure and heat to promote bonding to the bonding layer. In an embodiment using a bonding process, for example, before the semiconductor structure 200 is segmented, the bonding layer can also be formed on the first semiconductor die 285A and the second semiconductor die 285B. In some embodiments, the first semiconductor die 285A and the second semiconductor die 285B are mounted to the substrate 305 by solder balls or other mounting arrangements. In some embodiments, the spacing S between the first semiconductor die 285A and the second semiconductor die 285B is at least 1.5 microns to allow PnP variations.

[0115] Reference Figure 3BAccording to some embodiments, a dielectric layer 310 and a hybrid bonding layer 315 are formed above the first semiconductor grain 285A and the second semiconductor grain 285B, and conductive contact pads 320A, 320B are formed in the dielectric layer 310 and the hybrid bonding layer 315. In some embodiments, as described for the base dielectric layer 110, silicon dioxide, a molding material, or some other dielectric material, the dielectric layer 310 includes a dielectric material with a relatively low dielectric constant. The dielectric layer 310 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, or some other suitable process. In some embodiments, the hybrid bonding layer 315 includes a standard k dielectric material, such as silicon dioxide, doped or undoped silicon glass, SiON, or some other dielectric material. The conductive contact pads 320A, 320B may include a barrier layer, a seed layer, a metal filling layer, or other suitable layers. The metal filling layer may include tungsten, aluminum, copper, cobalt, or other suitable materials.

[0116] Reference Figure 3C According to some embodiments, stitching die 170 is bonded to first semiconductor die 285A and second semiconductor die 285B. The bonding process applies heat and pressure to stitching die 170, first semiconductor die 285A and second semiconductor die 285B to bond between hybrid bonding layer 155 and hybrid bonding layer 315 of stitching die 170 to form bonding layer 325, and to bond between conductive structures 330A, 330B in stitching die 170 and conductive structures 335A, 335B in first semiconductor die 285A and second semiconductor die 285B. The number of conductive structures interconnecting stitching die 170 with first semiconductor die 285A and second semiconductor die 285B can vary. Stitching die 170 facilitates communication between first semiconductor die 285A and second semiconductor die 285B. In some embodiments, conductive structures 335A, 335B can be used as alignment guides for placing stitching die 170. In some embodiments, the stitching die 170 is designed such that the seal ring 350 of the stitching die 170 is spaced at least 0.5 microns from the seal rings 355 , 360 of the first and second semiconductor dies 285A and 285B to avoid stacking of the seal rings 350 , 355 , 360 .

[0117] Reference Figure 3DAccording to some embodiments, a dielectric layer 340 and a cooling structure 345 are formed over the stitching die 170, the first semiconductor die 285A, and the second semiconductor die 285B. In some embodiments, the dielectric layer 340 includes a dielectric material having a relatively low dielectric constant as described for the base dielectric layer 110, silicon dioxide, a molding material, or some other dielectric material. The dielectric layer 340 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, or some other suitable process. In some embodiments, the cooling structure 345 includes a metal layer, a heat sink, a heat sink structure, a base of a cooling fan, or some other cooling structure. In some embodiments, removing the substrate layer 105 from the semiconductor stitching structure 100 helps position the cooling structure 345 closer to the first semiconductor die 285A and the second semiconductor die 285B. In some embodiments, the cooling structure 345 directly contacts the base dielectric layer 110 on the exposed surface 175 of the stitching die 170.

[0118] FIG. 4A to FIG. 4D A semiconductor package 400 is depicted at various stages of fabrication according to some embodiments. Figure 4A According to some embodiments, the first semiconductor die 285A and the second semiconductor die 285B are mounted to the substrate 405 in a back-side-up arrangement. Figure 2 The first semiconductor die 285A and the second semiconductor die 285B are oriented so that the back surface 295 faces upward.

[0119] Reference Figure 4B According to some embodiments, a dielectric layer 410 is formed over the first semiconductor grain 285A and the second semiconductor grain 285B. In some embodiments, the dielectric layer 410 includes a dielectric material having a relatively low dielectric constant as described for the base dielectric layer 110, silicon dioxide, a molding material, or some other dielectric material. The dielectric layer 410 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, or some other suitable process.

[0120] Reference Figure 4C, according to some embodiments, the stitching die 170 is bonded to the first semiconductor die 285A and the second semiconductor die 285B. The bonding process applies heat and pressure to the stitching die 170, the first semiconductor die 285A and the second semiconductor die 285B, resulting in bonding between the hybrid bonding layer 155 of the stitching die 170 and the substrate layer 205 of the first semiconductor die 285A and the second semiconductor die 285B, and bonding between the conductive structures 430A, 430B in the stitching die 170 and the conductive structures 435A, 435B in the first semiconductor die 285A and the second semiconductor die 285B. The number of conductive structures interconnecting the stitching die 170 with the first semiconductor die 285A and the second semiconductor die 285B can vary. In some embodiments, the conductive structures 435A, 435B can be used as alignment guides for placing the stitching die 170. The stitching die 170 facilitates communication between the first semiconductor die 285A and the second semiconductor die 285B. In some embodiments, the stitching die 170 is designed such that the seal ring 450 of the stitching die 170 is spaced at least 0.5 microns from the seal rings 455 , 460 of the first semiconductor die 285A and the second semiconductor die 285B to avoid stacking of the seal rings 450 , 455 , 460 .

[0121] Reference Figure 4D According to some embodiments, a dielectric layer 440 and a cooling structure 445 are formed over the stitching die 170, the first semiconductor die 285A, and the second semiconductor die 285B. In some embodiments, the dielectric layer 440 includes a dielectric material having a relatively low dielectric constant, as described for the base dielectric layer 110, silicon dioxide, a molding material, or some other dielectric material. The dielectric layer 440 can be formed in a variety of ways, such as by thermal growth, chemical growth, ALD, CVD, PECVD, or some other suitable process. In some embodiments, the cooling structure 445 includes a metal layer, a heat sink, a heat sink structure, a base of a cooling fan, or some other cooling structure. In some embodiments, removing the substrate layer 105 from the semiconductor stitching structure 100 helps to position the cooling structure 445 closer to the first semiconductor die 285A and the second semiconductor die 285B. In some embodiments, the cooling structure 445 directly contacts the base dielectric layer 110 on the exposed surface 175 of the stitching die 170.

[0122] Figure 5A and 5B is a top view of a semiconductor package 500 according to some embodiments. Figure 5A, stitching die 170 interconnects two semiconductor dies 285A, 285B. As described above, semiconductor dies 285A, 285B are mounted to a substrate 505, such as an underlying semiconductor die, a circuit board, an interposer, or some other substrate. Figure 5B , stitching die 170 interconnects four semiconductor dies 285A, 285B, 285C, 285D. Semiconductor dies 285A, 285B, 285C, 285D are mounted to substrate 505. The number of semiconductor dies 285 interconnected by stitching die 170 may vary.

[0123] The stitching die 170 facilitates communication between the semiconductor die 285 and the die stack to provide a combined processing complex having a reduced footprint compared to a single semiconductor die having the same number of functional devices. The removal of the substrate layer 105 of the stitching die 170 allows the cooling structures 345, 445 to be positioned closer to the underlying semiconductor die 285, thereby improving cooling efficiency and potentially improving processing performance.

[0124] In some embodiments, a semiconductor structure includes: a first semiconductor die including a first contact pad; a second semiconductor die including a second contact pad; a stitching die located above the first semiconductor die and the second semiconductor die and including a third contact pad connected to the first contact pad and a fourth contact pad connected to the second contact pad. The device also includes a cooling structure located above the stitching die. The stitching die includes a first surface including a first dielectric material (or first dielectric layer) directly contacting the cooling structure.

[0125] In some embodiments, the stitched die includes a second surface, relative to the first surface, the second surface includes a second dielectric material (or a second dielectric layer), the third contact pad is embedded in the second dielectric material, the first semiconductor die includes a third surface, the third surface includes a third dielectric material (or a third dielectric layer), the first contact pad is embedded in the third dielectric material, and the second dielectric material is bonded to the third dielectric material.

[0126] In some embodiments, the stitching die includes a passivation layer and a conductive contact. The passivation layer is located below the second dielectric material. The conductive contact extends through the passivation layer and contacts the third contact pad.

[0127] In some embodiments, the first semiconductor die includes a substrate layer and a conductive contact. The substrate layer is formed below the third dielectric material. The conductive contact extends through the substrate layer and contacts the first contact pad.

[0128] In some embodiments, the first semiconductor die includes a substrate layer, an interlayer dielectric layer, and a conductive contact. The interlayer dielectric layer is formed on the substrate layer. The conductive contact extends through the interlayer dielectric layer and contacts the first contact pad.

[0129] In some embodiments, the first semiconductor die includes a first seal ring, and the stitching die includes a second seal ring laterally offset from the first seal ring.

[0130] In some embodiments, the semiconductor structure further includes a molding material laterally located between the first semiconductor die and the second semiconductor die and laterally adjacent to the stitching die, wherein the cooling structure is located on the molding material.

[0131] In some embodiments, a method of manufacturing a semiconductor structure includes forming a stitching die by forming a dielectric layer over a first substrate layer, forming a first conductive structure in the dielectric layer and extending to a first surface of the dielectric layer, forming a second conductive structure in the dielectric layer and extending to the first surface of the dielectric layer, and removing the first substrate layer to expose the second surface of the dielectric layer. The stitching die is bonded to a first semiconductor die including a third conductive structure and a second semiconductor die including a fourth conductive structure. The first conductive structure contacts the third conductive structure, and the second conductive structure contacts the fourth conductive structure.

[0132] In some embodiments, the method further includes forming a cooling structure on the second surface of the dielectric layer of the stitched die.

[0133] In some embodiments, forming the cooling structure includes forming the cooling structure to directly contact the second surface of the dielectric layer of the stitching die.

[0134] In some embodiments, the method also includes forming a first bonding layer above the first semiconductor grain and the second semiconductor grain; forming a first contact pad in the first bonding layer that contacts the third conductive structure; and bonding a second bonding layer of the stitched grain to the first bonding layer, wherein the dielectric layer includes the second bonding layer.

[0135] In some embodiments, the dielectric layer forming the stitched grain includes forming an interlayer dielectric layer; forming a passivation layer on the interlayer dielectric layer; and forming the second bonding layer on the passivation layer, wherein the first conductive structure extends through at least a portion of the interlayer dielectric layer, through the passivation layer, and through the second bonding layer.

[0136] In some embodiments, the method further includes orienting the first semiconductor die in a backside-up orientation before bonding the stitching die to the first semiconductor die, wherein the first semiconductor die includes a second substrate layer and the third conductive structure extends through the substrate layer.

[0137] In some embodiments, the method further includes orienting the first semiconductor die in a top-up direction before bonding the stitched die to the first semiconductor die, wherein the first semiconductor die includes a second substrate layer and an interlayer dielectric layer on the substrate layer, and the third conductive structure extends through the interlayer dielectric layer.

[0138] In some embodiments, the method further includes orienting the stitching die such that a seal ring in the stitching die is laterally offset from a seal ring in the first semiconductor die.

[0139] In some embodiments, the method further includes forming a molding material, wherein the molding material is laterally positioned between the first semiconductor die and the second semiconductor die and laterally adjacent to the stitching die; and forming a cooling structure on the molding material to directly contact the second surface of the dielectric layer of the stitching die.

[0140] In some embodiments, a stitched die includes a dielectric layer having a first exposed surface and a second exposed surface, a first conductive structure, and a second conductive structure. The first conductive structure is embedded in the dielectric layer and extends to the first exposed surface but not to the second exposed surface. The second conductive structure is embedded in the dielectric layer and extends to the first exposed surface but not to the second exposed surface.

[0141] In some embodiments, the dielectric layer includes an interlayer dielectric layer and a passivation layer. The passivation layer is located on the interlayer dielectric layer.

[0142] In some embodiments, the dielectric layer includes a bonding layer disposed on the passivation layer.

[0143] In some embodiments, the stitching die further includes a sealing ring disposed in the dielectric layer.

[0144] In some embodiments, a semiconductor structure includes a stitching die, a first semiconductor die, and a second semiconductor die. The stitching die includes a dielectric layer, a first conductive structure, and a second conductive structure. The first conductive structure is in the dielectric layer and extends to a first surface of the dielectric layer, and the second conductive structure is in the dielectric layer and extends to the first surface of the dielectric layer. The stitching die is bonded to the first semiconductor die and the second semiconductor die. The first semiconductor die includes a third conductive structure, and the second semiconductor die includes a fourth conductive structure. The first conductive structure contacts the third conductive structure, and the second conductive structure contacts the fourth conductive structure.

[0145] In some embodiments, the semiconductor structure further includes a cooling structure on a second surface of the dielectric layer of the stitched die.

[0146] The features of multiple embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the various embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

[0147] Although the subject matter has been described in language specific to structural features or methodological acts, it is understood that the subject matter of the appended patent claims is not necessarily limited to the above-mentioned specific features or acts. Rather, the above-mentioned specific features and acts are disclosed as exemplary forms to implement the patent claims.

[0148] Various operation implementations are provided herein. The order of some or all of the operations described should not be interpreted to mean that these operations must be in order. Alternative sequencing will have the advantages described herein. In addition, it should be understood that not all operations must be presented in each implementation provided herein.

[0149] In addition, "exemplary" is used herein to represent embodiments, examples, illustrations, etc., and is not necessarily advantageous. "Or" as used in this application tends to represent an inclusive "or" rather than an exclusive "or". In addition, unless otherwise specified or clearly pointed to the singular form from the context, "a" and "an" used in this application are generally interpreted as meaning "one or more". In addition, at least one of A and B and / or similar, generally means A or B or both A and B. In addition, when "including", "having", "has", "have" or their variations are used in the detailed description or patent application, these terms tend to be included in the term "including" in a similar manner.

[0150] In addition, although the disclosure has been shown and described with respect to one or more embodiments, considerable changes and modifications will occur based upon the reading and understanding of this specification and the accompanying drawings. The disclosure includes all such modifications and variations and is limited only by the claims.

Claims

1. A semiconductor structure, characterized in that: include: a first semiconductor die including a first contact pad; a second semiconductor die including a second contact pad; a stitching die over the first semiconductor die and the second semiconductor die and including a third contact pad connected to the first contact pad and a fourth contact pad connected to the second contact pad; and a cooling structure located above the stitched die, wherein: The stitched die includes a first surface including a first dielectric layer directly contacting the cooling structure.

2. The semiconductor structure according to claim 1, wherein: in: The stitching die includes a second surface, opposite to the first surface, The second surface includes a second dielectric layer, The third contact pad is embedded in the second dielectric layer, The first semiconductor grain includes a third surface, and the third surface includes a third dielectric layer. The first contact pad is embedded in the third dielectric layer, and The second dielectric layer is bonded to the third dielectric layer.

3. The semiconductor structure according to claim 2, wherein: The stitched grain comprises: a passivation layer disposed below the second dielectric layer; and A conductive contact extends through the passivation layer and contacts the third contact pad.

4. The semiconductor structure according to claim 2, characterized in that The first semiconductor crystal grain comprises: a substrate layer formed below the third dielectric layer; and A conductive contact extends through the substrate layer and contacts the first contact pad.

5. The semiconductor structure according to claim 2, wherein: The first semiconductor crystal grain comprises: a substrate layer; an interlayer dielectric layer formed on the substrate layer; and A conductive contact extends through the interlayer dielectric layer and contacts the first contact pad.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: in: The first semiconductor die includes a first sealing ring; and The stitched die includes a second seal ring laterally offset from the first seal ring.

7. A semiconductor structure, characterized in that: include: A stitched die comprising: a dielectric layer; a first conductive structure located in the dielectric layer, wherein the first conductive structure extends to a first surface of the dielectric layer; and a second conductive structure located in the dielectric layer, wherein the second conductive structure extends to the first surface of the dielectric layer; and A first semiconductor die and a second semiconductor die are bonded to the stitching die, wherein the first semiconductor die includes a third conductive structure, the second semiconductor die includes a fourth conductive structure, the first conductive structure contacts the third conductive structure, and the second conductive structure contacts the fourth conductive structure.

8. The semiconductor structure according to claim 7, wherein: Also includes: A cooling structure is on a second surface of the dielectric layer of the stitched die.

9. A stitched die, characterized in that: include: a dielectric layer having a first exposed surface and a second exposed surface; a first conductive structure embedded in the dielectric layer and extending to the first exposed surface but not extending to the second exposed surface; as well as A second conductive structure is embedded in the dielectric layer and extends to the first exposed surface but does not extend to the second exposed surface.

10. The stitched die according to claim 9, wherein: Also includes: A sealing ring is located in the dielectric layer.

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