Differential hysteresis comparator circuit and chip

Abstract

The utility model provides a differential hysteresis comparator circuit and a chip. The differential hysteresis comparator circuit comprises an operational amplifier, a reference current source, a current mirror circuit and a voltage clamping circuit. The first voltage is converted into current through the first resistor, the second voltage is converted into current through the second resistor, the current input to the positive and negative input ends of the operational amplifier is forcibly equal due to the virtual short characteristic of the operational amplifier, and the current to be compared is output to the reference current source for comparison through the current mirror circuit. According to the embodiment, the output voltage of the operational amplifier is limited in a set range through the voltage clamping circuit, when the input voltage difference value (the value obtained by subtracting the first voltage from the second voltage) changes the output polarity, the voltage value needing to be established by the output voltage of the operational amplifier is reduced, and the establishing speed is increased.

Description

Technical Field

[0001] The present application relates to the technical field of comparators, and in particular to a differential hysteresis comparator circuit and chip. Background Art

[0002] When the input signal of the differential hysteresis comparator changes, the output signal has a certain hysteresis and delay. Specifically, the differential hysteresis comparator has a hysteresis characteristic, that is, when the input voltage is higher than a certain threshold, the comparator outputs a high level; when the input voltage is lower than another threshold, the comparator outputs a low level; and between these two thresholds, the output of the comparator remains unchanged. This characteristic makes the differential hysteresis comparator less sensitive to small changes, thereby enhancing the system's anti-interference ability.

[0003] Specifically, in the existing differential hysteresis comparator, the difference in input voltage is converted into a corresponding current through a feedback loop and a resistor. The current is copied and compared with the reference current to determine whether the difference in input voltage is greater than the target value. The reference current and input resistance jointly determine the circuit threshold. When the input voltage difference is closer to the set threshold, the smaller the current difference is, the slower the establishment speed is. The farther the input voltage difference is from the threshold, the faster the speed is. In addition, when the difference in input voltage is less than 0V, the feedback loop in the circuit will be closed. When the input switches to be greater than the threshold at the next moment, it needs to be established from the closed state, resulting in a slow establishment. Utility Model Content

[0004] The purpose of the embodiments of the present application is to provide a differential hysteresis comparator circuit and chip to solve the problem of slow settling speed of the existing differential hysteresis comparator when switching the output polarity according to the difference of the input voltage.

[0005] A differential hysteresis comparator circuit provided in an embodiment of the present application includes: an operational amplifier, a reference current source, a current mirror circuit and a voltage clamp circuit;

[0006] The negative input terminal of the operational amplifier is connected to the first voltage through the first resistor, and the positive input terminal of the operational amplifier is connected to the second voltage through the second resistor; the positive input terminal of the operational amplifier is connected to the first terminal of the current mirror circuit, the negative input terminal of the operational amplifier is connected to the second terminal of the current mirror circuit, the output terminal of the operational amplifier is connected to the fourth terminal of the current mirror circuit through the voltage clamp circuit, and the third terminal of the current mirror circuit is connected to the reference current source;

[0007] The current mirror circuit is used to: enter a shutdown mode or an operating mode according to the output voltage of the operational amplifier; in the operating mode, obtain a current to be compared according to the first voltage and the second voltage, output the current to be compared to a reference current source, and compare the current to be compared with the reference current to obtain a comparison result;

[0008] The voltage clamp circuit is used to limit the output voltage of the operational amplifier to a set range.

[0009] In the above technical solution, the differential hysteresis comparator circuit includes an operational amplifier, a reference current source, a current mirror circuit and a voltage clamp circuit. The first voltage is converted into a current through a first resistor, and the second voltage is converted into a current through a second resistor. Due to the virtual short characteristic of the operational amplifier, the currents input to the positive and negative input terminals of the operational amplifier are forced to be equal, and the current to be compared is output to the reference current source for comparison through the current mirror circuit. In this embodiment, the output voltage of the operational amplifier is limited to a set range through a voltage clamp circuit. When the input voltage difference (the value of the second voltage minus the first voltage) changes the output polarity, the voltage value that the output voltage of the operational amplifier needs to establish is reduced, thereby improving the establishment speed.

[0010] In some optional implementations, the current mirror circuit includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube; the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube and the fifth MOS tube are PMOS tubes;

[0011] The gate of the first MOS tube is connected to the gate of the fifth MOS tube, the gate of the first MOS tube is connected to the drain of the first MOS tube, the drain of the first MOS tube is connected to the positive input terminal of the operational amplifier; the source of the fifth MOS tube is connected to the source of the fourth MOS tube, the drain of the fifth MOS tube is connected to the drain of the fourth MOS tube, the gate of the fourth MOS tube is connected to the negative input terminal of the operational amplifier, the drain of the fourth MOS tube is connected to the first terminal of the reference current source, and the second terminal of the reference current source is grounded. The source of the second MOS tube is connected to the power supply, the source of the third MOS tube is connected to the power supply, the gate of the second MOS tube and the gate of the third MOS tube are connected to the output terminal of the operational amplifier; the drain of the second MOS tube is connected to the source of the first MOS tube, and the drain of the third MOS tube is connected to the source of the fourth MOS tube.

[0012] In the above technical solution, when the input voltage difference (the value of the second voltage minus the first voltage) is less than 0V, the second MOS tube and the third MOS tube are turned off, the entire feedback loop is turned off, and the current mirror circuit enters the shutdown mode; when the input voltage difference is greater than 0V, the second MOS tube and the third MOS tube are turned on, and the current mirror circuit enters the working mode.

[0013] In some optional implementations, the voltage clamping circuit includes: a third resistor, a first current source, a sixth MOS transistor and a seventh MOS transistor;

[0014] A first end of the third resistor is connected to a power supply, a second end of the third resistor is connected to a source of a sixth MOS tube, a source of the sixth MOS tube is connected to a gate of the sixth MOS tube, a drain of the sixth MOS tube is connected to a first current source, a gate of the sixth MOS tube is connected to a gate of a seventh MOS tube, a source of the seventh MOS tube is connected to an output end of the operational amplifier, and a drain of the seventh MOS tube is grounded.

[0015] In the above technical solution, when the input voltage difference (the value of the second voltage minus the first voltage) is less than 0V, the gate voltage of the second MOS tube and the third MOS tube is pulled up to VDD-IB1×R3 by the output voltage of the operational amplifier, wherein VDD is the power supply voltage, IB1 is the current value of the first current source, and R3 is the resistance value of the third resistor. When the input voltage difference changes the output polarity at the next moment, the output voltage of the operational amplifier starts to build up from the upper limit VDD-IB1×R3. However, when the voltage clamping circuit is not provided, when the input voltage difference is less than 0V to the next moment when the input voltage difference changes the output polarity, the output voltage of the operational amplifier starts to build up from the upper limit VDD. Compared with the case where the voltage clamping circuit is not provided, this embodiment improves the building speed when the input voltage difference is less than 0V to the next moment when the input voltage difference changes the output polarity by limiting the upper limit of the output voltage of the operational amplifier.

[0016] In some optional implementations, the voltage clamping circuit includes: a second current source, a fourth resistor, an eighth MOS transistor and a ninth MOS transistor;

[0017] A first end of the second current source is connected to a power supply, a second end of the second current source is connected to a drain of an eighth MOS tube, a drain of the eighth MOS tube is connected to a gate of the eighth MOS tube, a gate of the eighth MOS tube is connected to a gate of a ninth MOS tube, a source of the eighth MOS tube is connected to a fourth resistor and then to ground, and a source of the ninth MOS tube is connected to an output end of the operational amplifier.

[0018] In the above technical solution, when the input voltage difference (the value of the second voltage minus the first voltage) is too large, the gate voltages of the second MOS tube and the third MOS tube are pulled down by the output voltage of the operational amplifier, and the output voltage lower limit of the operational amplifier is set at IB2×R4 through the voltage clamping circuit, where IB2 is the current value of the second current source, and R4 is the resistance value of the fourth resistor. When the input voltage difference changes the output polarity at the next moment, the voltage value to be established is reduced, thereby increasing the establishment speed.

[0019] In some optional implementations, the voltage clamping circuit includes: a third resistor, a fourth resistor, a first current source, a second current source, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor and a ninth MOS transistor;

[0020] A first end of the third resistor is connected to a power supply, a second end of the third resistor is connected to a source of a sixth MOS tube, a source of the sixth MOS tube is connected to a gate of the sixth MOS tube, a drain of the sixth MOS tube is connected to a first current source, a gate of the sixth MOS tube is connected to a gate of a seventh MOS tube, a source of the seventh MOS tube is connected to an output end of the operational amplifier, and a drain of the seventh MOS tube is grounded;

[0021] A first end of the second current source is connected to a power supply, a second end of the second current source is connected to a drain of an eighth MOS tube, a drain of the eighth MOS tube is connected to a gate of the eighth MOS tube, a gate of the eighth MOS tube is connected to a gate of a ninth MOS tube, a source of the eighth MOS tube is connected to a fourth resistor and then to ground, and a source of the ninth MOS tube is connected to an output end of the operational amplifier.

[0022] In the above technical solution, by setting the output voltage range of the operational amplifier to [IB2×R4, VDD-IB1×R3], the voltage value that needs to be established when the input voltage changes the output polarity is reduced, thereby improving the establishment speed.

[0023] In some optional embodiments, the current mirror circuit includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube; the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube and the fifth MOS tube are NMOS tubes; the gate of the first MOS tube is connected to the gate of the fifth MOS tube, the gate of the first MOS tube is connected to the drain of the first MOS tube, and the drain of the first MOS tube is connected to the positive input terminal of the operational amplifier; the source of the fifth MOS tube is connected to the source of the fourth MOS tube, the drain of the fifth MOS tube is connected to the drain of the fourth MOS tube, the gate of the fourth MOS tube is connected to the negative input terminal of the operational amplifier, the drain of the fourth MOS tube is connected to the second terminal of the reference current source, and the first terminal of the reference current source is connected to the power supply. The source of the second MOS tube is grounded, the source of the third MOS tube is grounded, the gate of the second MOS tube and the gate of the third MOS tube are connected to the output terminal of the operational amplifier; the drain of the second MOS tube is connected to the source of the first MOS tube, and the drain of the third MOS tube is connected to the source of the fourth MOS tube.

[0024] A differential hysteresis comparator chip provided in an embodiment of the present application includes a differential hysteresis comparator circuit as described in any one of the above items, a lead frame, and a plastic packaging material; the differential hysteresis comparator circuit is arranged on the lead frame, and the plastic packaging material is used to seal the differential hysteresis comparator circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A differential hysteresis comparator circuit module diagram provided in an embodiment of the present application;

[0027] Figure 2 A circuit structure diagram of a differential hysteresis comparator provided in the first embodiment of the present application;

[0028] Figure 3 A circuit structure diagram of a differential hysteresis comparator provided in the second embodiment of the present application;

[0029] Figure 4 A circuit structure diagram of a differential hysteresis comparator provided in the third embodiment of the present application;

[0030] Figure 5 A circuit structure diagram of a differential hysteresis comparator provided in the fourth embodiment of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0032] Please refer to Figure 1 , Figure 1 A differential hysteresis comparator circuit module diagram provided in an embodiment of the present application includes: an operational amplifier OP, a reference current source Iref, a current mirror circuit and a voltage clamp circuit.

[0033] Wherein, the negative input terminal of the operational amplifier OP is connected to the first voltage INN through the first resistor R1, and the positive input terminal of the operational amplifier OP is connected to the second voltage INP through the second resistor R2; the positive input terminal of the operational amplifier OP is connected to the first terminal of the current mirror circuit, the negative input terminal of the operational amplifier OP is connected to the second terminal of the current mirror circuit, the output terminal of the operational amplifier OP is connected to the fourth terminal of the current mirror circuit through the voltage clamp circuit, and the third terminal of the current mirror circuit is connected to the reference current source Iref;

[0034] The current mirror circuit is used to: enter a shutdown mode or an operating mode according to the output voltage of the operational amplifier OP; in the operating mode, obtain a current to be compared according to the first voltage INN and the second voltage INP, output the current to be compared to a reference current source Iref, and compare the current to be compared with the reference current Iref to obtain a comparison result;

[0035] The voltage clamp circuit is used to limit the output voltage of the operational amplifier OP within a set range.

[0036] In an embodiment of the present application, the differential hysteresis comparator circuit includes an operational amplifier OP, a reference current source Iref, a current mirror circuit and a voltage clamp circuit. The first voltage INN is converted into a current through a first resistor R1, and the second voltage INP is converted into a current through a second resistor R2. Due to the virtual short characteristic of the operational amplifier OP, the currents input to the positive and negative input terminals of the operational amplifier OP are forced to be equal, and the current to be compared is output to the reference current source Iref for comparison through the current mirror circuit. In this embodiment, the output voltage of the operational amplifier OP is limited to a set range through a voltage clamp circuit. When the input voltage difference (the value of the second voltage INP minus the first voltage INN) changes the output polarity, the voltage value that the output voltage of the operational amplifier OP needs to establish is reduced, thereby increasing the establishment speed.

[0037] Please refer to Figure 2 , Figure 2 A differential hysteresis comparator circuit structure diagram provided for the first embodiment of the present application.

[0038] The current mirror circuit of this embodiment includes a first MOS tube M1, a second MOS tube, a third MOS tube, a fourth MOS tube M4 and a fifth MOS tube M5; the first MOS tube M1, the second MOS tube, the third MOS tube, the fourth MOS tube M4 and the fifth MOS tube M5 are PMOS tubes.

[0039] Among them, the gate of the first MOS tube M1 is connected to the gate of the fifth MOS tube M5, the gate of the first MOS tube M1 is connected to the drain of the first MOS tube M1, and the drain of the first MOS tube M1 is connected to the positive input terminal of the operational amplifier OP; the source of the fifth MOS tube M5 is connected to the source of the fourth MOS tube M4, the drain of the fifth MOS tube M5 is connected to the drain of the fourth MOS tube M4, the gate of the fourth MOS tube M4 is connected to the negative input terminal of the operational amplifier OP, the drain of the fourth MOS tube M4 is connected to the first terminal of the reference current source Iref, and the second terminal of the reference current source Iref is grounded. The source of the second MOS tube M2 is connected to the power supply, the source of the third MOS tube M3 is connected to the power supply, the gate of the second MOS tube M2 and the gate of the third MOS tube M3 are connected to the output terminal of the operational amplifier OP; the drain of the second MOS tube M2 is connected to the source of the first MOS tube M1, and the drain of the third MOS tube M3 is connected to the source of the fourth MOS tube M4.

[0040] In the embodiment of the present application, when the input voltage difference (the value of the second voltage INP minus the first voltage INN) is less than 0V, the second MOS tube M2 and the third MOS tube M3 are turned off, the entire feedback loop is turned off, and the current mirror circuit enters the shutdown mode; when the input voltage difference is greater than 0V, the second MOS tube M2 and the third MOS tube M3 are turned on, and the current mirror circuit enters the working mode.

[0041] The voltage clamping circuit of this embodiment includes: a third resistor R3, a first current source IB1, a sixth MOS transistor M6 and a seventh MOS transistor M7;

[0042] A first end of the third resistor R3 is connected to a power supply, a second end of the third resistor R3 is connected to a source of a sixth MOS tube M6, a source of the sixth MOS tube M6 is connected to a gate of the sixth MOS tube M6, a drain of the sixth MOS tube M6 is connected to a first current source IB1, a gate of the sixth MOS tube M6 is connected to a gate of a seventh MOS tube M7, a source of the seventh MOS tube M7 is connected to an output end of the operational amplifier OP, and a drain of the seventh MOS tube M7 is grounded.

[0043] In the embodiment of the present application, when the input voltage difference (the value of the second voltage INP minus the first voltage INN) is less than 0V, the gate voltage of the second MOS tube M2 and the third MOS tube M3 is pulled up to VDD-IB1×R3 by the output voltage of the operational amplifier OP, wherein VDD is the power supply voltage, IB1 is the current value of the first current source IB1, and R3 is the resistance value of the third resistor. When the input voltage difference changes the output polarity at the next moment, the output voltage of the operational amplifier OP starts to build up from the upper limit VDD-IB1×R3. However, when the voltage clamping circuit is not set, when the input voltage difference is less than 0V to the next moment when the input voltage difference changes the output polarity, the output voltage of the operational amplifier OP starts to build up from the upper limit VDD. Compared with the case where the voltage clamping circuit is not set, this embodiment increases the speed of building up when the input voltage difference is less than 0V to the next moment when the input voltage difference changes the output polarity by limiting the upper limit of the output voltage of the operational amplifier OP.

[0044] Please refer to Figure 3 , Figure 3 A differential hysteresis comparator circuit structure diagram provided for the second embodiment of the present application.

[0045] The difference from the first embodiment is that the voltage clamping circuit of this embodiment includes: a second current source IB2, a fourth resistor R4, an eighth MOS transistor M8 and a ninth MOS transistor M9.

[0046] Wherein, a first end of the second current source IB2 is connected to a power supply, a second end of the second current source IB2 is connected to a drain of the eighth MOS tube M8, a drain of the eighth MOS tube M8 is connected to a gate of the eighth MOS tube M8, a gate of the eighth MOS tube M8 is connected to a gate of a ninth MOS tube M9, a source of the eighth MOS tube M8 is connected to a fourth resistor R4 and then to ground, and a source of the ninth MOS tube M9 is connected to an output end of the operational amplifier OP.

[0047] In the embodiment of the present application, when the input voltage difference (the value of the second voltage INP minus the first voltage INN) is too large, the gate voltages of the second MOS tube M2 and the third MOS tube M3 are pulled down by the output voltage of the operational amplifier OP, and the output voltage lower limit of the operational amplifier OP is set at IB2×R4 through the voltage clamping circuit, where IB2 is the current value of the second current source IB2, and R4 is the resistance value of the fourth resistor. When the input voltage difference changes the output polarity at the next moment, the voltage value that needs to be established is reduced, thereby increasing the establishment speed.

[0048] Please refer to Figure 4 , Figure 4 A differential hysteresis comparator circuit structure diagram provided for the third embodiment of the present application.

[0049] The difference from the first embodiment is that the voltage clamping circuit of this embodiment includes: a third resistor R3, a fourth resistor R4, a first current source IB1, a second current source IB2, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8 and a ninth MOS transistor M9.

[0050] Wherein, a first end of the third resistor R3 is connected to a power supply, a second end of the third resistor R3 is connected to a source of a sixth MOS transistor M6, a source of the sixth MOS transistor M6 is connected to a gate of the sixth MOS transistor M6, a drain of the sixth MOS transistor M6 is connected to a first current source IB1, a gate of the sixth MOS transistor M6 is connected to a gate of a seventh MOS transistor M7, a source of the seventh MOS transistor M7 is connected to an output end of the operational amplifier OP, and a drain of the seventh MOS transistor M7 is grounded;

[0051] A first end of the second current source IB2 is connected to a power supply, a second end of the second current source IB2 is connected to a drain of the eighth MOS tube M8, a drain of the eighth MOS tube M8 is connected to a gate of the eighth MOS tube M8, a gate of the eighth MOS tube M8 is connected to a gate of a ninth MOS tube M9, a source of the eighth MOS tube M8 is connected to the fourth resistor R4 and then to ground, and a source of the ninth MOS tube M9 is connected to an output end of the operational amplifier OP.

[0052] In the embodiment of the present application, by setting the output voltage range of the operational amplifier OP to [IB2×R4, VDD-IB1×R3], the voltage value that needs to be established when the input voltage changes the output polarity is reduced, thereby improving the establishment speed.

[0053] Please refer to Figure 5 , Figure 5 A circuit structure diagram of a differential hysteresis comparator provided in the fourth embodiment of the present application.

[0054] The difference from the third embodiment is that the current mirror circuit of this embodiment includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4 and a fifth MOS tube M5; the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the fourth MOS tube M4 and the fifth MOS tube M5 are NMOS tubes.

[0055] Among them, the gate of the first MOS tube M1 is connected to the gate of the fifth MOS tube M5, the gate of the first MOS tube M1 is connected to the drain of the first MOS tube M1, and the drain of the first MOS tube M1 is connected to the positive input terminal of the operational amplifier OP; the source of the fifth MOS tube M5 is connected to the source of the fourth MOS tube M4, the drain of the fifth MOS tube M5 is connected to the drain of the fourth MOS tube M4, the gate of the fourth MOS tube M4 is connected to the negative input terminal of the operational amplifier OP, the drain of the fourth MOS tube M4 is connected to the second end of the reference current source Iref, and the first end of the reference current source Iref is connected to the power supply.

[0056] The source of the second MOS tube M2 is grounded, the source of the third MOS tube M3 is grounded, the gate of the second MOS tube M2 and the gate of the third MOS tube M3 are connected to the output end of the operational amplifier OP; the drain of the second MOS tube M2 is connected to the source of the first MOS tube M1, and the drain of the third MOS tube M3 is connected to the source of the fourth MOS tube M4.

[0057] A differential hysteresis comparator chip provided in an embodiment of the present application includes a differential hysteresis comparator circuit as described in any one of the above items, a lead frame, and a plastic packaging material; the differential hysteresis comparator circuit is arranged on the lead frame, and the plastic packaging material is used to seal the differential hysteresis comparator circuit.

[0058] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0059] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0060] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0061] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0062] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A differential hysteresis comparator circuit, characterized in that: include: Operational amplifiers, reference current sources, current mirror circuits, and voltage clamp circuits; The negative input terminal of the operational amplifier is connected to a first voltage through a first resistor, and the positive input terminal of the operational amplifier is connected to a second voltage through a second resistor; the positive input terminal of the operational amplifier is connected to a first terminal of the current mirror circuit, the negative input terminal of the operational amplifier is connected to a second terminal of the current mirror circuit, the output terminal of the operational amplifier is connected to a fourth terminal of the current mirror circuit through the voltage clamp circuit, and the third terminal of the current mirror circuit is connected to the reference current source; The current mirror circuit is used to: enter a shutdown mode or a working mode according to the output voltage of the operational amplifier; in the working mode, obtain a current to be compared according to the first voltage and the second voltage, output the current to be compared to the reference current source, and compare the current to be compared with the reference current to obtain a comparison result; The voltage clamp circuit is used to limit the output voltage of the operational amplifier to a set range.

2. The differential hysteresis comparator circuit according to claim 1, characterized in that: The current mirror circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube; the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube and the fifth MOS tube are PMOS tubes; The gate of the first MOS tube is connected to the gate of the fifth MOS tube, the gate of the first MOS tube is connected to the drain of the first MOS tube, and the drain of the first MOS tube is connected to the positive input terminal of the operational amplifier; the source of the fifth MOS tube is connected to the source of the fourth MOS tube, the drain of the fifth MOS tube is connected to the drain of the fourth MOS tube, the gate of the fourth MOS tube is connected to the negative input terminal of the operational amplifier, the drain of the fourth MOS tube is connected to the first terminal of the reference current source, and the second terminal of the reference current source is grounded; The source of the second MOS tube is connected to a power supply, the source of the third MOS tube is connected to a power supply, the gate of the second MOS tube and the gate of the third MOS tube are connected to the output end of the operational amplifier; the drain of the second MOS tube is connected to the source of the first MOS tube, and the drain of the third MOS tube is connected to the source of the fourth MOS tube.

3. The differential hysteresis comparator circuit according to claim 2, characterized in that: The voltage clamping circuit includes: a third resistor, a first current source, a sixth MOS tube and a seventh MOS tube; A first end of the third resistor is connected to a power supply, a second end of the third resistor is connected to a source of the sixth MOS tube, a source of the sixth MOS tube is connected to a gate of the sixth MOS tube, a drain of the sixth MOS tube is connected to the first current source, a gate of the sixth MOS tube is connected to a gate of the seventh MOS tube, a source of the seventh MOS tube is connected to an output end of the operational amplifier, and a drain of the seventh MOS tube is grounded.

4. The differential hysteresis comparator circuit according to claim 2, wherein: The voltage clamping circuit includes: a second current source, a fourth resistor, an eighth MOS tube and a ninth MOS tube; A first end of the second current source is connected to a power supply, a second end of the second current source is connected to the drain of the eighth MOS tube, the drain of the eighth MOS tube is connected to the gate of the eighth MOS tube, the gate of the eighth MOS tube is connected to the gate of the ninth MOS tube, the source of the eighth MOS tube is connected to the fourth resistor and then grounded, and the source of the ninth MOS tube is connected to the output end of the operational amplifier.

5. The differential hysteresis comparator circuit according to claim 2, characterized in that: The voltage clamping circuit includes: a third resistor, a fourth resistor, a first current source, a second current source, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor and a ninth MOS transistor; The first end of the third resistor is connected to the power supply, the second end of the third resistor is connected to the source of the sixth MOS tube, the source of the sixth MOS tube is connected to the gate of the sixth MOS tube, the drain of the sixth MOS tube is connected to the first current source, the gate of the sixth MOS tube is connected to the gate of the seventh MOS tube, the source of the seventh MOS tube is connected to the output end of the operational amplifier, and the drain of the seventh MOS tube is grounded; A first end of the second current source is connected to a power supply, a second end of the second current source is connected to the drain of the eighth MOS tube, the drain of the eighth MOS tube is connected to the gate of the eighth MOS tube, the gate of the eighth MOS tube is connected to the gate of the ninth MOS tube, the source of the eighth MOS tube is connected to the fourth resistor and then grounded, and the source of the ninth MOS tube is connected to the output end of the operational amplifier.

6. The differential hysteresis comparator circuit according to claim 1, wherein: The current mirror circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube; wherein the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube and the fifth MOS tube are NMOS tubes; The gate of the first MOS tube is connected to the gate of the fifth MOS tube, the gate of the first MOS tube is connected to the drain of the first MOS tube, and the drain of the first MOS tube is connected to the positive input terminal of the operational amplifier; the source of the fifth MOS tube is connected to the source of the fourth MOS tube, the drain of the fifth MOS tube is connected to the drain of the fourth MOS tube, the gate of the fourth MOS tube is connected to the negative input terminal of the operational amplifier, the drain of the fourth MOS tube is connected to the second end of the reference current source, and the first end of the reference current source is connected to the power supply; The source of the second MOS tube is grounded, the source of the third MOS tube is grounded, the gate of the second MOS tube and the gate of the third MOS tube are connected to the output end of the operational amplifier; the drain of the second MOS tube is connected to the source of the first MOS tube, and the drain of the third MOS tube is connected to the source of the fourth MOS tube.

7. A differential hysteresis comparator chip, characterized in that: It comprises the differential hysteresis comparator circuit, a lead frame and a plastic packaging material as described in any one of claims 1 to 6; the differential hysteresis comparator circuit is arranged on the lead frame, and the plastic packaging material is used to seal the differential hysteresis comparator circuit.

Images