Semiconductor package

Abstract

A semiconductor package includes a substrate, a redistribution structure formed on the substrate, a first photonic wiring structure disposed on the redistribution structure, an optical interposer die disposed on the first photonic wiring structure, a second photonic wiring structure disposed on the first photonic wiring structure, an optical engine die disposed on the second photonic wiring structure, and a molding structure formed on the substrate. The second photonic wiring structure is disposed on the redistribution structure, the optical engine die is disposed on the second photonic wiring structure, and the molding structure is disposed between the first photonic wiring structure and the second photonic wiring structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package with an optical bridge. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using photolithography and etching processes to form circuit components and elements thereon. Many integrated circuits (ICs) are typically manufactured on a single semiconductor wafer, and the individual bare die on the wafer are separated by cutting along scribe lines between the integrated circuits. The individual bare die are typically packaged separately, such as in a multi-chip module or other type of package.

[0003] While existing packages and methods of making packages are generally adequate for their intended purposes, they are not completely satisfactory in all respects. Utility Model Content

[0004] The purpose of the present invention is to provide a semiconductor package to solve at least one of the above problems.

[0005] An embodiment of the present disclosure provides a semiconductor package, including a substrate, a redistribution structure, a first photonic wiring structure, an optical interposer die, a second photonic wiring structure, an optical engine die, and a molding structure. The redistribution structure is formed on the substrate, the first photonic wiring structure is arranged on the redistribution structure, the optical interposer die is arranged on the first photonic wiring structure, the second photonic wiring structure is arranged on the redistribution structure, the optical engine die is arranged on the second photonic wiring structure, and the molding structure is arranged between the first photonic wiring structure and the second photonic wiring structure.

[0006] According to one embodiment of the present invention, the first photonic wiring structure includes: a first dielectric structure; a first waveguide disposed in the first dielectric structure; and a reflective element disposed in the first dielectric structure.

[0007] According to one embodiment of the present invention, the second photonic wiring structure includes: a second dielectric structure; and a second waveguide, which is disposed in the second dielectric structure and optically coupled to the first waveguide.

[0008] According to one embodiment of the present invention, a third waveguide is formed in the redistribution structure, and the third waveguide is optically coupled to the first waveguide and the second waveguide.

[0009] According to one embodiment of the present invention, the optical interposer die and the optical engine die are arranged in a direction parallel to a surface of the substrate.

[0010] According to one embodiment of the present invention, the optical engine die includes a photonic die and an electrical die, the photonic die is arranged on the second photonic wiring structure, and the electrical die is arranged on the photonic die, wherein the photonic die and the electrical die have different widths.

[0011] According to one embodiment of the present invention, the optical interposer die covers the second photonic wiring structure and a portion of the molding structure.

[0012] According to one embodiment of the present invention, the molding structure is formed between the substrate and the optical engine die.

[0013] According to one embodiment of the present invention, the molded structure includes an optical adhesive.

[0014] According to one embodiment of the present invention, the first photonic wiring structure includes a reflector formed by a high-refractive coating film, and the substrate has a curved surface, and the curved surface and the reflector are arranged in a first direction perpendicular to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following detailed description is provided in conjunction with the accompanying drawings for complete disclosure. It should be noted that, in accordance with common practices in the industry, the illustrations are not necessarily drawn to scale. In fact, the size of the components may be arbitrarily enlarged or reduced for clarity of illustration.

[0016] Figures 1A to 1L is a schematic diagram of a method of forming an optical bridge according to some embodiments of the present disclosure.

[0017] Figures 2A to 2L is a schematic diagram of a method of forming an optical bridge according to some embodiments of the present disclosure.

[0018] FIG. 3A to FIG. 3E is a schematic diagram of forming a semiconductor package according to some embodiments of the present disclosure.

[0019] Figure 4 is a top view of a semiconductor package according to some embodiments of the present disclosure.

[0020] Figure 5 is a schematic diagram of a semiconductor package according to some embodiments of the present disclosure.

[0021] Figure 6 is a schematic diagram of a semiconductor package according to some embodiments of the present disclosure.

[0022] Figure 7 is a schematic diagram of a semiconductor package according to some embodiments of the present disclosure.

[0023] Fig. 8A is a schematic diagram of a semiconductor package according to some embodiments of the present disclosure.

[0024] Figure 8B is a top view of a semiconductor package according to some embodiments of the present disclosure.

[0025] Fig. 9A is a schematic diagram of a semiconductor package according to some embodiments of the present disclosure.

[0026] Fig. 9B is a top view of a semiconductor package according to some embodiments of the present disclosure.

[0027] FIG. 10A to FIG. 10D is a schematic diagram of a method of forming a semiconductor package according to some embodiments of the present disclosure.

[0028] The reference numerals are as follows:

[0029] 10: Substrate / optical interposer bare crystal

[0030] 10A, 10B, 10D: Surface

[0031] 10C: protrusion

[0032] 11A,11B:Substrate

[0033] 12,27,67: concave part

[0034] 12A: Bottom surface

[0035] 12B,66: Side wall

[0036] 20,21,22,23,28,29,60,61,62,63,68,69,336: oxide layer

[0037] 24,64: Open

[0038] 25: Bottom surface

[0039] 26: Side wall

[0040] 27A, 67A: First surface

[0041] 27B, 67B: Second surface

[0042] 30: Anti-reflection layer

[0043] 40: First waveguide / waveguide

[0044] 50: Reflective element

[0045] 52: High reflective coating

[0046] 62A: Oxide materials

[0047] 70,278: Dielectric layer

[0048] 80,242: Dielectric structure

[0049] 82: Anti-reflection layer

[0050] 100A, 100B, 100C, 100D, 100F, 100E: Optical bridge

[0051] 200A, 200B, 200C, 200D, 200E, 200F, 200G: semiconductor package

[0052] 210:Substrate

[0053] 220: Redistribution structure

[0054] 222: Insulation layer

[0055] 224,226,272,274,276,334,344,502,514: Conductive characteristics

[0056] 228: The Third Waveguide

[0057] 230,232: Molded structure

[0058] 240: Support substrate

[0059] 244: Anti-reflection layer

[0060] 250: Dielectric structure / fiber array unit

[0061] 252: protrusion

[0062] 254: Dielectric Materials

[0063] 260: Fiber Optic

[0064] 270:Joint layer

[0065] 300: Optical engine bare crystal

[0066] 300A, 300B: Optical engine bare die

[0067] 310,310A,310B: Bare crystal

[0068] 312,322: Device layer

[0069] 320: Photonic bare crystal

[0070] 320A,320B: Photon Bare Crystal

[0071] 330: Second photon wiring structure

[0072] 332: Second waveguide

[0073] 342: Conductive via

[0074] 350: Bare crystal

[0075] 360: Virtual bare crystal

[0076] 400: Light

[0077] 500: Packaging components

[0078] 510: Redistribution structure

[0079] 512: Insulation layer

[0080] 520: Dielectric materials

[0081] AA:Line

[0082] R1, R2: First photonic wiring structure DETAILED DESCRIPTION

[0083] The following disclosure provides many different embodiments or examples to implement the different features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present disclosure describes a first feature formed on or above a second feature, it means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, different examples in the following disclosure may reuse the same reference symbols and / or marks. These repetitions are for the purpose of simplification and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0084] In addition, spatially related terms such as "below," "below," "lower," "above," "higher," and similar terms are used to facilitate description of the relationship between one element or feature and another element or feature in the figure. In addition to the orientation shown in the drawings, these spatially related terms are intended to include different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein may be interpreted in the same manner.

[0085] The use of ordinal terms (such as "first", "second", etc.) in the claims to modify claim elements does not itself imply any priority, sequence, or order of one claim element relative to another claim element or the temporal order of the actions of performing a method, but is merely used as a marker to distinguish one claim element with a specific name from another element with the same name (but using ordinal terms) to distinguish the claim elements.

[0086] The terms "approximately" and "substantially" generally refer to + / -20% of the value, more generally + / -10% of the value, more generally + / -5% of the value, more generally + / -5% of the value, more generally + / -3% of the value, more generally + / -2% of the value, more generally + / -1% of the value, and even more generally + / -0.5% of the value. The values ​​disclosed herein are approximate values. When not specifically described, the numerical values ​​include the meaning of "approximately" or "substantially".

[0087] Other features and processes may also be included. For example, a test structure may be included to help verify the testing of a three-dimensional package or a three-dimensional integrated circuit device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate that allows testing of a three-dimensional package or a three-dimensional integrated circuit, the use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that incorporate intermediate verification of known good bare die to increase yield and reduce costs.

[0088] According to some embodiments of the present disclosure, the present disclosure provides a semiconductor package with an optical interposer die, which serves as an optical bridge for intra- and inter-package communications. The optical interposer die can alleviate photonic die area limitations and reduce costs. In addition, the optical interposer die does not have any active components, which enables it to be manufactured at higher temperatures and achieve better performance.

[0089] Figures 1A to 1L is a schematic diagram of a method of forming an optical bridge 100A according to some embodiments of the present disclosure. Figure 1AAs shown in , according to some embodiments, a substrate 10 having a surface 10A is provided. In some embodiments, the substrate 10 may be referred to as an optical interposer bare die 10. In some embodiments, the substrate 10 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 10 may include elementary semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elementary semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. In some embodiments, conductive features (e.g., conductive lines, pads, through holes) may be provided in the substrate 10.

[0090] exist Figure 1B According to some embodiments of the present disclosure, the substrate 10 is recessed until a new surface 10B and a protrusion 10C protruding from the surface 10B are formed. In some embodiments, the recessing process may include photolithography and etching processes. In some embodiments, the top surface of the protrusion 10C is a curved surface, which can be used as a curved surface of a lens mirror.

[0091] exist Figure 1C According to some embodiments of the present disclosure, an oxide layer 21 is formed on the substrate 10 to cover the surface 10B and the protrusion 10C. In some embodiments, the oxide layer 21 may be, for example, silicon oxide.

[0092] exist Figure 1D In the embodiment of the present invention, the oxide layer 21 is recessed to form an opening 24 in the oxide layer 21. In some embodiments, the recessing process may include photolithography and etching processes. In some embodiments, the opening 24 has a bottom surface 25 and sidewalls 26. In some embodiments, the oxide layer 21 is recessed to expose the protrusion 10C below, and the bottom surface 25 is the top surface of the protrusion 10C.

[0093] Then, in Figure 1E According to some embodiments of the present disclosure, an anti-reflection layer 30 is formed on the sidewall 26. In some embodiments, the bottom surface 25 is spaced apart from the anti-reflection layer 30.

[0094] In some embodiments of the present disclosure, the material of the anti-reflection layer 30 may include silicon oxide, silicon nitride, polymer, benzocyclobutene (BCB) or any suitable material. The anti-reflection layer 30 may reduce optical loss or reflection. Methods for forming the anti-reflection layer 30 include physical vapor deposition (PVD) processes, such as evaporation, radio frequency (RF) or DC sputtering; chemical vapor deposition (CVD) processes, such as atmospheric pressure, low pressure, plasma enhanced and high density plasma chemical vapor deposition; atomic layer deposition (ALD); ion beam deposition; and liquid-phase non-vacuum methods, such as sol-gel method and metal organic decomposition method; and / or any other suitable method known in the art.

[0095] exist Figure 1F According to some embodiments of the present disclosure, an oxide layer 23 is formed on the oxide layer 21 and in the opening 24. In some embodiments, the oxide layer 23 may be, for example, silicon oxide, etc. In some embodiments, the oxide layer 21 and the oxide layer 23 may have the same material.

[0096] Next, in Figure 1G In the process, a planarization process is performed to remove the oxide layer 23 and a portion of the oxide layer 21 to form the oxide layer 22. In some embodiments, the anti-reflection layer 30 is exposed from the oxide layer 22. In some embodiments, the planarization process may include chemical mechanical polishing (CMP), a mechanical grinding process, an etch-back process, a combination thereof, and the like.

[0097] exist Figure 1H In the embodiment of the present invention, an oxide layer 28 is formed on the oxide layer 22. In some embodiments, the oxide layer 28 may be, for example, silicon oxide. In some embodiments, a first waveguide 40 may be formed in the oxide layer 28. In some embodiments, the first waveguide 40 may be formed by forming a semiconductor material layer on the oxide layer 28 and then patterning the semiconductor material layer. In some embodiments, the first waveguide 40 is used as an optical transmitter or an optical receiver.

[0098] In some embodiments, the first waveguide 40 includes an elemental semiconductor material, a compound semiconductor material, or a semiconductor alloy. For example, the elemental semiconductor may include Si or Ge. The compound semiconductor and the semiconductor alloy may include SiGe, SiC, SiGeC, a III-V semiconductor, or a II-VI semiconductor, respectively. For example, the III-V semiconductor includes GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. II-VI semiconductors may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe , CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe.

[0099] Next, if Fig. 1I As shown in , according to some embodiments, the oxide layer 28 is recessed to form a recess 27. In some embodiments, the recess 27 has a first surface 27A and a second surface 27B. In some embodiments, the first surface 27A and the second surface 27B have different normal vectors. For example, according to some embodiments of the present disclosure, the first surface 27A may be substantially parallel to the surface 10B, and the second surface 27B and the surface 10B may have an angle of about 45 degrees. In some embodiments, the anti-reflective layer 30 at least partially overlaps the recess 27 in a direction perpendicular to the surface 10B. In some embodiments, the first surface 27A and the second surface 27B at least partially overlap the bottom surface 25 in a direction perpendicular to the surface 10B. In some embodiments, the recess process may include photolithography and etching processes.

[0100] Then, if Figure 1JAs shown in FIG. 2 , a high reflection coating (HRC) 52 is disposed on the oxide layer 28 and in the recess 27 to cover the first surface 27A and the second surface 27B. In some embodiments, the high reflection coating 52 may include one or more layers of materials such as metal (e.g., copper, etc.), titanium nitride, etc., or a combination thereof. In some embodiments, the high reflection coating 52 may include a periodic stack of dielectric layers, such as a stack of layers including silicon oxide, silicon nitride, etc.

[0101] exist Figure 1K In some embodiments, a planarization process is performed to remove the high reflective coating 52 outside the recess 27, and the high reflective coating 52 in the recess is retained as the reflective element 50. In some embodiments, the planarization process may include chemical mechanical polishing (CMP), a mechanical grinding process, an etch-back process, a combination thereof, etc. In some embodiments, the reflective element 50 may be a mirror coated with a high refractive material, and the high refractive material may include, for example, a metal (such as copper, etc.), titanium nitride, etc. or a combination thereof. In some embodiments, the mirror is arranged in a direction perpendicular to the bottom surface 25 of the substrate 10, for example, perpendicular to the surface 10A.

[0102] Then, if Figure 1L As shown in FIG. 1 , an oxide layer 29 is formed on the oxide layer 28 to form the optical bridge 100A. In some embodiments, the oxide layer 29 may be, for example, silicon oxide. In some embodiments, the oxide layer 22, the oxide layer 28, and the oxide layer 29 may include the same material. In some embodiments, the oxide layer 22, the oxide layer 28, and the oxide layer 29 may be collectively referred to as the oxide layer 20. In some embodiments, the oxide layer 20, the anti-reflection layer 30, the first waveguide 40, and the reflective element 50 may be referred to as the first photonic wiring structure R1.

[0103] Figures 2A to 2L is a schematic diagram of a method for forming an optical bridge 100B according to some embodiments of the present disclosure. Figure 2A As shown in , according to some embodiments, a substrate 10 is provided. In some embodiments, the substrate 10 may be referred to as an optical interposer bare die 10. In some embodiments, the substrate 10 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 10 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0104] like Figure 2B As shown in FIG. 1 , a recess 12 is formed on a surface 10D of a substrate 10. In some embodiments, the recess 12 may have a bottom surface 12A and a sidewall 12B. In some embodiments, the bottom surface 12A is a curved surface, which may serve as a curved surface of a lens reflector. In some embodiments, the process of forming the recess 12 may include photolithography and etching processes.

[0105] Next, in Figure 2C In the embodiment of the present invention, an oxide layer 61 is formed in the recess 12. In some embodiments, the oxide layer 61 may be, for example, silicon oxide, etc. In some embodiments, the oxide layer 61 may be formed by depositing an oxide layer on the substrate 10 and then performing a planarization process to remove excess material outside the recess 12. In some embodiments, the planarization process may include chemical mechanical polishing (CMP), a mechanical grinding process, an etch-back process, a combination thereof, etc.

[0106] Then, if Figure 2D As shown in FIG. 1 , an oxide layer 63 is disposed on the substrate 10. In some embodiments, the oxide layer 63 may be, for example, silicon oxide. Then, Figure 2E In some embodiments, an opening 64 is formed in the oxide layer 63 and the recess 12 to expose the bottom surface 12A and the sidewall 12B of the recess 12, and the oxide layer 61 is removed when the opening 64 is formed. In some embodiments, the process for forming the opening 64 may include photolithography and etching processes. In some embodiments, the opening 64 has a sidewall 66, and the sidewall 12B and the sidewall 66 extend continuously.

[0107] Next, if Figure 2F As shown in , according to some embodiments of the present disclosure, an anti-reflection layer 30 is formed on the sidewall 12B and the sidewall 66. In some embodiments, the material of the anti-reflection layer 30 may include silicon oxide, silicon nitride, polymer, benzocyclobutene or any suitable material. The anti-reflection layer 30 can reduce optical loss or reflection. Methods for forming the anti-reflection layer 30 include physical vapor deposition (PVD) processes, such as evaporation, radio frequency or DC sputtering; chemical vapor deposition (CVD) processes, such as atmospheric pressure, low pressure, plasma enhanced and high density plasma chemical vapor deposition; atomic layer deposition (ALD); ion beam deposition; and liquid phase non-vacuum methods, such as sol-gel method and metal organic decomposition method; and / or any other suitable method known in the art.

[0108] Next, in Figure 2GIn the embodiment of the present invention, an oxide material 62A is formed in the opening 64, and the oxide material 62A and the oxide layer 63 may be collectively referred to as an oxide layer 62. In some embodiments, forming the oxide material 62A in the opening 64 includes depositing an oxide covering the oxide layer 63 and in the opening 64, and then performing a planarization process to remove the oxide material above the oxide layer 63 and outside the opening 64. In some embodiments, the planarization process may include chemical mechanical polishing (CMP), a mechanical grinding process, an etch-back process, a combination thereof, and the like.

[0109] exist Figure 2H In the embodiment of the present invention, an oxide layer 68 is formed on the oxide layer 62. In some embodiments, the oxide layer 68 may be, for example, silicon oxide. In some embodiments, the first waveguide 40 may be formed in the oxide layer 68. In some embodiments, the first waveguide 40 may be formed by forming a semiconductor material layer on the oxide layer 68 and then patterning the semiconductor material layer. In some embodiments, the first waveguide 40 is used as an optical transmitter or an optical receiver.

[0110] Next, if Fig.2I As shown in , according to some embodiments, the oxide layer 68 is recessed to form a recess 67. In some embodiments, the recess 67 has a first surface 67A and a second surface 67B. In some embodiments, the first surface 67A and the second surface 67B have different normal vectors. For example, according to some embodiments of the present disclosure, the first surface 67A may be substantially parallel to the surface 10D, and the second surface 67B and the surface 10D may have an angle of about 45 degrees. In some embodiments, the anti-reflective layer 30 at least partially overlaps the recess 67 in a direction perpendicular to the surface 10D. In some embodiments, the first surface 67A and the second surface 67B at least partially overlap the bottom surface 12A in a direction perpendicular to the surface 10D. In some embodiments, the recess process may include photolithography and etching processes.

[0111] Then, if Figure 2J As shown in FIG. 5 , a high reflective coating (HRC) 52 is disposed on the oxide layer 68 and in the recess 67 to cover the first surface 67A and the second surface 67B. In some embodiments, the high reflective coating 52 may include one or more layers of materials such as metal (e.g., copper, etc.), titanium nitride, etc., or a combination thereof. In some embodiments, the high reflective coating 52 may include a periodic stack of dielectric layers, such as a stack of layers including silicon oxide, silicon nitride, etc.

[0112] exist Figure 2KIn some embodiments, a planarization process is performed to remove the high reflective coating 52 outside the recess 67, and the high reflective coating 52 in the recess is retained as the reflective element 50. In some embodiments, the planarization process may include chemical mechanical polishing (CMP), a mechanical grinding process, an etch-back process, a combination thereof, etc. In some embodiments, the reflective element 50 may be a reflector coated with a high refractive material, and the high refractive material may include, for example, a metal (such as copper, etc.), titanium nitride, etc. or a combination thereof. In some embodiments, the reflector is arranged in a direction perpendicular to the bottom surface 12A of the substrate 10, for example, perpendicular to the surface 10D.

[0113] Then, if Figure 2L As shown in FIG. 1 , an oxide layer 69 is formed on the oxide layer 68 to form the optical bridge 100B. In some embodiments, the oxide layer 69 may be, for example, silicon oxide. In some embodiments, the oxide layer 62, the oxide layer 68, and the oxide layer 69 may include the same material. In some embodiments, the oxide layer 62, the oxide layer 68, and the oxide layer 69 may be collectively referred to as the oxide layer 60. In some embodiments, the oxide layer 60, the anti-reflection layer 30, the first waveguide 40, and the reflective element 50 may be referred to as the first photonic wiring structure R2.

[0114] In some embodiments, the optical bridge 100A or the optical bridge 100B may allow light to pass through to adjust the optical path of an external optical signal. For example, light may pass through the bottom surface 12A or the bottom surface 25 and reach the reflective element 50. The reflective element 50 then reflects the light, changes its direction, and allows it to be transmitted to the waveguide 40. The waveguide 40 may then convey the light to other elements, which will be described later.

[0115] FIG. 3A to FIG. 3E FIG. 2 is a schematic diagram of forming a semiconductor package 200A according to some embodiments of the present disclosure. Figure 3A As shown in FIG. 2 , a redistribution structure 220 is formed on a substrate 210. In some embodiments, the substrate 210 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. The elemental semiconductor material may include, but is not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. The compound semiconductor material may include, but is not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The alloy semiconductor material may include, but is not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0116] In some embodiments, the redistribution structure 220 includes a plurality of insulating layers 222, conductive features 224, conductive features 226, and a third waveguide 228 surrounded by the insulating layer 222. The conductive features 224 may include conductive lines and / or conductive vias. The conductive features 226 may include conductive pads. In some embodiments, some conductive vias are stacked on each other. The upper conductive via is substantially aligned with the lower conductive via. In some embodiments, some conductive vias are staggered vias. The upper conductive via is not aligned with the lower conductive via. In some embodiments, the insulating layer 222 may be made of a polymer material, a ceramic material, a metal material, a semiconductor material, one or more other suitable materials or a combination thereof, or include a polymer material, a ceramic material, a metal material, a semiconductor material, one or more other suitable materials or a combination thereof. In some embodiments, the conductive features 224 and the conductive features 226 may be made of copper, aluminum, cobalt, nickel, gold, silver, tungsten, one or more other suitable materials or a combination thereof, or include copper, aluminum, cobalt, nickel, gold, silver, tungsten, one or more other suitable materials or a combination thereof.

[0117] In some embodiments, the third waveguide 228 may be formed by forming a semiconductor material layer and then patterning the semiconductor material layer. In some embodiments, the third waveguide 228 functions as an optical transmitter or an optical receiver.

[0118] Next, in Figure 3B According to some embodiments of the present disclosure, the optical bridge 100A, the optical engine die 300, and the die 350 may be disposed on the redistribution structure 220. In some embodiments, the optical bridge 100A may also be replaced by the optical bridge 100B described above.

[0119] In some embodiments, the optical engine die 300 includes an electrical die 310, a photonic die 320, and the optical engine die 300 is disposed on a second photonic wiring structure 330. In some embodiments, the second photonic wiring structure 330 is disposed on the redistribution structure 220, the photonic die 320 is disposed on the second photonic wiring structure 330, and the electrical die 310 is disposed on the photonic die 320. In some embodiments, the redistribution structure 220 is electrically connected to the second photonic wiring structure 330 through a conductive feature 226 disposed in the redistribution structure 220 and a conductive feature 334 disposed in an oxide layer 336, and then electrically connected to the electrical die 310 through a conductive via 342 penetrating the oxide layer 336 and the redistribution structure 220 to a conductive feature 344 between the electrical die 310 and the photonic die 320. In some embodiments, the oxide layer 336 may be, for example, silicon oxide. In some embodiments, the second waveguide 332 is disposed in the oxide layer 336. In some embodiments, second waveguide 332 may be formed by forming a semiconductor material layer and then patterning the semiconductor material layer. In some embodiments, second waveguide 332 functions as an optical transmitter or an optical receiver. In some embodiments, conductive features 334, conductive vias 342, and conductive features 344 may be made of or include copper, aluminum, cobalt, nickel, gold, silver, tungsten, one or more other suitable materials, or combinations thereof.

[0120] In some embodiments, the electrical die 310 may be an electronic integrated circuit (EIC) or the like that provides serializer / deserializer (SerDes) functions and has a device layer 312 that includes components for performing these functions. In this way, the electrical die 310 may function as part of an input / output interface (I / O interface) between optical signals and electrical signals within the semiconductor package 200A.

[0121] In some embodiments, the photon die 320 is configured to process, receive and / or transmit optical signals. Therefore, the photon die 320 is also referred to as an optical chip in some applications. An optical signal is an electromagnetic signal that exhibits characteristics that can be modeled by photons, and unlike an electrical signal, an electrical signal is a signal carried by an electric charge (e.g., an electron, a hole, or an ion). In an alternative embodiment, the photon die 320 also includes one or more active and / or passive components disposed in a device layer 322 therein and configured to process, receive and / or transmit an electrical signal converted by the laser die into / from an optical signal. In an alternative embodiment, the photonic integrated circuit (PIC) 130 also includes a light detection device such as a light sensor disposed in the device layer 322.

[0122] In some embodiments, the die 350 is electrically connected to the redistribution structure 220 . In some embodiments, the die 350 is a logic die (e.g., central processing units (CPUs), graphics processing units (GPUs), system-on-chips (SoCs), application processors (APs), microcontrollers, application-specific integrated circuit (ASIC) die, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a high bandwidth memory (HBM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die, etc.), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof.

[0123] In some embodiments, the optical bridge 100A and the optical engine die 300 are arranged in a direction parallel to the surface of the substrate 210. For example, the electrical die 310 and the photonic die 320 are arranged in a direction parallel to the surface of the substrate 10.

[0124] Then, in Figure 3C In some embodiments of the present disclosure, the molding structure 230 is formed to surround the optical bridge 100A, the optical engine die 300, and the die 350. In some embodiments, the first photonic wiring structure R1 and the second photonic wiring structure 330 are separated by the molding structure 230. In some embodiments, the molding structure 230 may be formed of a suitable transparent material (e.g., silicon oxide) instead of an opaque material (e.g., a molding compound). Using a suitable transparent material for the molding structure 230 in this way allows optical signals to be transmitted through the molding structure 230. According to some embodiments of the present disclosure, after the molding structure 230 is formed to surround the optical bridge 100A, the optical engine die 300, and the die 350, a planarization process may be performed to expose the optical bridge 100A, the optical engine die 300, and the die 350.

[0125] like Figure 3D As shown in FIG. 1 , according to some embodiments of the present disclosure, the support substrate 240 is disposed on the optical bridge 100A, the optical engine die 300, and the die 350. In some embodiments, the dielectric structure 242 and the anti-reflection layer 244 are formed in the support substrate 240. In some embodiments, the dielectric structure 242 may have a curved surface, which may be used as a curved surface of a lens reflector. In some embodiments, the dielectric structure 242 and the protrusion 10C may be arranged in a direction perpendicular to the substrate 210 so that light can pass through this direction.

[0126] In some embodiments, the support substrate 240 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. In some embodiments, the dielectric structure 242 may include a suitable transparent material, such as silicon oxide. In some embodiments of the present disclosure, the anti-reflective layer 244 may include silicon oxide, silicon nitride, a polymer, benzocyclobutene (BCB), or any suitable material.

[0127] exist Figure 3EAccording to some embodiments of the present disclosure, a dielectric structure 250 is disposed on a support substrate 240. In some embodiments, a protrusion 252 is formed on a bottom surface of the dielectric structure 250, and a dielectric material 254 is disposed between the support substrate 240 and the dielectric structure 250 and around the protrusion 252. According to some embodiments of the present disclosure, an optical fiber 260 is connected to the dielectric structure 250.

[0128] In some embodiments, the dielectric structure 250 may be used as a fiber array unit (FAU) 250, which allows the optical fiber 260 to be connected to the semiconductor package 200A and allows light to pass through. In some embodiments, the dielectric structure 250 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the dielectric structure 250 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. In some embodiments, the protrusion 252 may have a curved bottom surface, which may be used as a curved surface of a lens reflector. According to some embodiments of the present disclosure, the dielectric material 254 may be formed of a suitable transparent material (e.g., silicon oxide).

[0129] In some embodiments, light 400 from the optical fiber 260 may penetrate the dielectric structure 250 and sequentially pass through the protrusion 252, the dielectric structure 242, and the protrusion 10C. After the light 400 reaches the reflective element 50, the direction of the light 400 may change to reach the first waveguide 40. In some embodiments, the protrusion 10C and the reflective element 50 are arranged in a direction different from the direction in which the reflective element 50 and the first waveguide 40 are arranged with respect to each other. In some embodiments, the protrusion 10C and the reflective element 50 are arranged in a direction substantially perpendicular to the substrate 10, and the reflective element 50 and the first waveguide 40 are arranged in a direction substantially parallel to the substrate 10. In some embodiments, in a direction perpendicular to the substrate 210, the first waveguide 40 partially overlaps with the third waveguide 228, and the third waveguide 228 partially overlaps with the second waveguide 332, so that the first waveguide 40 is optically coupled to the third waveguide 228, and the third waveguide 228 is optically coupled to the second waveguide 332. Then, the light 400 sequentially passes through the first waveguide 40, the third waveguide 228, and the second waveguide 332. The second waveguide 332 is optically coupled to the photonic die 320 so that the light 400 can reach the photonic die 320 to allow the external optical signal to be transmitted to the semiconductor package 200A. This interlayer transition improves the transition efficiency, thereby improving the performance.

[0130] By using the optical bridge 100A as the optical path of the semiconductor package 200A, the size of the optical engine die 300 can be reduced. In addition, no active components are formed in the optical bridge 100A, so the optical bridge 100A can be processed at a relatively high temperature to improve the performance and yield of the semiconductor package 200A, and the process can be simplified. On the other hand, the optical engine die 300 and the die 350 with active components will be prevented from being damaged by the high temperature process. For example, the protrusion 10C is used as a lens with a high radius of curvature (ROC) to enhance the focusing performance. In some embodiments, the pitch of the optical path can be reduced by providing the optical bridge 100A.

[0131] Figure 4 is a top view of a semiconductor package 200A according to some embodiments of the present disclosure. In some embodiments, FIG. 3A to FIG. 3E It is along Figure 4 In some embodiments, the semiconductor package 200A further has some dummy die 360 ​​disposed on the redistribution structure 220 and surrounded by the molding structure 230 to balance the stress in the semiconductor package 200A. In some embodiments, the reflective element 50 overlaps the protrusion 252 .

[0132] Figure 52 is a schematic diagram of a semiconductor package 200B according to some embodiments of the present disclosure. In some embodiments, the semiconductor package 200B may be similar to the semiconductor package 200A, and for the sake of brevity, the same elements are not described again. Figure 5 As shown in FIG. 1 , the optical bridge 100A and the optical bridge 100B are interchangeable. In some embodiments, the third waveguide 228 may be omitted, and the light 400 may be transmitted directly from the first waveguide 40 to the second waveguide 332 through the molded structure 230 via edge coupling. This configuration reduces the area requirements of the waveguides, thereby reducing costs.

[0133] Figure 6 FIG. 2 is a schematic diagram of a semiconductor package 200C according to some embodiments of the present disclosure. For the sake of brevity, the same elements are not described again. Figure 6 As shown in , according to some embodiments, a bonding layer 270 may be provided, which includes a conductive feature 272, a conductive feature 274, and a conductive feature 276 disposed in a dielectric layer 278. In some embodiments, the conductive features 272 and 274 may be conductive pads, and the conductive feature 276 may include a conductive bump (e.g., a tin-containing solder bump) and / or a conductive column (e.g., a copper column). The dielectric layer 278 may be made of one or more polymer materials or include one or more polymer materials. The polymer material may include polybenzoxazole (PBO), polyimide (PI), one or more other suitable polymer materials, or a combination thereof. In some embodiments, the polymer material is photosensitive. In some embodiments, some or all of the dielectric layer 108 are made of a dielectric material other than a polymer material, or include a dielectric material other than a polymer material. The dielectric material may include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or a combination thereof. The presence of the bonding layer 270 reduces the cost of the semiconductor package 200C.

[0134] In some embodiments, the molding structure 232 may be disposed to surround the optical bridge 100A, the optical engine die 300, and the die 350. In some embodiments, the molding structure 232 may include an optical clear adhesive (OCA) or other transparent materials to allow light to pass through.

[0135] Figure 7 FIG. 2 is a schematic diagram of a semiconductor package 200D according to some embodiments of the present disclosure. For the sake of brevity, the same elements are not described again. In some embodiments, Figure 7As shown in , the optical bridge 100C includes a dielectric layer 70 disposed between the substrate 10 and the oxide layer 60. In some embodiments, the dielectric layer 70 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the dielectric layer 70 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. The elemental semiconductor material may include, but is not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. The compound semiconductor material may include, but is not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The alloy semiconductor material may include, but is not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. In some embodiments, the thickness of the dielectric layer 70 may be less than about 20 microns.

[0136] In some embodiments, the dielectric structure 80 and the anti-reflection layer 82 are formed in the substrate 10. In some embodiments, the dielectric structure 80 may have a curved surface, which can be used as a curved surface of a lens reflector. In some embodiments, the dielectric structure 80 and the dielectric structure 242 may be arranged in a direction perpendicular to the substrate 210 so that light can pass through this direction. In some embodiments, the dielectric structure 80 may include a suitable transparent material, such as silicon oxide. In some embodiments of the present disclosure, the anti-reflection layer 82 may include silicon oxide, silicon nitride, a polymer, benzocyclobutene (BCB) or any suitable material.

[0137] Fig. 8A is a schematic diagram of a semiconductor package 200E according to some embodiments of the present disclosure, Figure 8B FIG. 2 is a top view of a semiconductor package 200E according to some embodiments of the present disclosure. For the sake of brevity, the same elements are not described again. Fig. 8A As shown in , according to some embodiments, an optical bridge 100D and an optical engine die 300A are provided. In some embodiments, the optical bridge 100D includes a substrate 11A, and the optical engine die 300A includes an electrical die 310A and a photonic die 320A. In some embodiments, the substrate 11A extends horizontally above the photonic die 320A and the molding structure 230. In some embodiments, the substrate 11A is in contact with the photonic die 320A. In alternative embodiments, the substrate 11A and the photonic die 320A are separated by the molding structure 230. In some embodiments, the width of the electrical die 310A is less than the width of the photonic die 320A. As shown in FIG. Figure 8B As shown in FIG. 1 , the substrate 11A partially overlaps the photon die 320A and is separated from the electrical die 310A. In this way, the size of the electrical die 310A can be reduced to achieve miniaturization. In addition, since the substrate 11A extends horizontally above the photon die 320A, the amount of the molding structure 230 can be reduced to reduce costs.

[0138] Fig. 9A is a schematic diagram of a semiconductor package 200F according to some embodiments of the present disclosure, Fig. 9B FIG. 2 is a top view of a semiconductor package 200F according to some embodiments of the present disclosure. For the sake of brevity, the same elements are not described again. Fig. 9A As shown in , according to some embodiments, an optical bridge 100E and an optical engine die 300B are provided. In some embodiments, the optical bridge 100E includes a substrate 11B, and the optical engine die 300B includes an electrical die 310B and a photonic die 320B. In some embodiments, the electrical die 310B extends horizontally above the dielectric layer 70 and the molding structure 230. In some embodiments, the electrical die 310B is in contact with the dielectric layer 70. In an alternative embodiment, the electrical die 310B and the dielectric layer 70 are separated by the molding structure 230. In some embodiments, the width of the electrical die 310A is greater than the width of the photonic die 320A. Fig. 9B As shown in FIG. 3 , the electrical die 310B partially overlaps the dielectric layer 70. As a result, the area of ​​the electrical die 310B can be increased to allow more electrical components to be disposed therein.

[0139] FIG. 10A to FIG. 10D FIG. 2 is a schematic diagram of a method for forming a semiconductor package 200G according to some embodiments of the present disclosure. Fig. 10A As shown in , a package component 500 is provided. According to some embodiments, the package component 500 includes a logic die, which may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a micro control unit (MCU) die, an input output (IO) die, a baseband (BB) die, an application processor (AP) die, etc. The package component 36 may also include a memory die, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc. The memory die may be a discrete memory die, or may be in the form of a die stack including a plurality of stacked memory die. The package component 500 may also include a system-on-chip (SOC) die. According to some embodiments, the package component 500 may be a discrete device die or a package.

[0140] In some embodiments, conductive feature 502 may be formed in package component 500. In some embodiments, conductive feature 502 may be a via, a conductive pad, or a conductive line, and may be made of or include copper, aluminum, cobalt, nickel, gold, silver, tungsten, one or more other suitable materials, or a combination thereof.

[0141] In some embodiments, Fig. 10A As shown in , the redistribution structure 510 is disposed on the package component 500. In some embodiments, the redistribution structure 510 includes a plurality of insulating layers 512 and conductive features 514. The conductive features 514 may include conductive lines, conductive vias, and / or conductive pads. In some embodiments, the insulating layer 512 may be made of a polymer material, a ceramic material, a metal material, a semiconductor material, one or more other suitable materials, or a combination thereof, or include a polymer material, a ceramic material, a metal material, a semiconductor material, one or more other suitable materials, or a combination thereof. In some embodiments, the conductive features 514 may be made of copper, aluminum, cobalt, nickel, gold, silver, tungsten, one or more other suitable materials, or a combination thereof, or include copper, aluminum, cobalt, nickel, gold, silver, tungsten, one or more other suitable materials, or a combination thereof.

[0142] like Fig. 10B As shown in FIG. 1 , according to some embodiments of the present disclosure, the first photonic wiring structure R1 is disposed adjacent to the package component 500 and the redistribution structure 510. In some embodiments, the first photonic wiring structure R1 has an oxide layer 20 and a dielectric layer 70, wherein the first waveguide 40 and the reflective element 50 are disposed in the oxide layer 20, and the dielectric layer 70 is disposed on the oxide layer 20. In some embodiments, a dielectric material 520 is dispensed (e.g., by a dispenser (not shown)) into the space between the oxide layer 20 and the package component 500 and the redistribution structure 510, and then cured (e.g., ultraviolet (UV) or thermal curing) to harden. The dielectric material 520 can be configured to provide a stronger mechanical connection and a thermal bridge between the components to reduce cracking in the semiconductor package 200G caused by thermal expansion mismatches, and protect the joints from contamination, thereby improving the reliability of the manufactured semiconductor package 200G. In some embodiments, dielectric material 520 includes liquid epoxy, deformable gel, silicone rubber, or the like.

[0143] exist Fig. 10C In the embodiment, the substrate 10 having the dielectric structure 80 and the anti-reflection layer 82, the optical engine die 300 and the die 350 are arranged on Fig. 10B Next, as Fig. 10D As shown in FIG. 1 , according to some embodiments of the present disclosure, a support substrate 240 is disposed on the substrate 10, the optical engine die 300, and the die 350. In some embodiments, a dielectric structure 242 and an anti-reflection layer 244 are formed in the support substrate 240. In some embodiments, the dielectric structure 242 may have a curved surface, which may be used as a curved surface of a lens reflector.

[0144] In some embodiments, according to some embodiments of the present disclosure, the dielectric structure 250 is disposed on the support substrate 240. In some embodiments, the protrusion 252 is formed on the bottom surface of the dielectric structure 250, and the dielectric material 254 is disposed between the support substrate 240 and the dielectric structure 250 and around the protrusion 252. According to some embodiments of the present disclosure, the optical fiber 260 is connected to the dielectric structure 250.

[0145] In some embodiments, the first photonic wiring structure R1, the substrate 10, the dielectric structure 80, and the anti-reflection layer 82 may be collectively referred to as an optical bridge 100F. According to some embodiments of the present disclosure, the molding structure 230 is formed to surround the optical bridge 100F, the optical engine die 300, and the die 350. In some embodiments, the dielectric layer 70 may be omitted, and the substrate 10 may be in direct contact with the oxide layer 20. In this configuration, the light 400 may pass through the optical bridge 100F to reach the photonic die 320.

[0146] In summary, some embodiments of the present invention provide a semiconductor package with an optical bridge and a method for forming the same. The optical bridge serves as an optical path for optical signal transmission, which alleviates the area limitation of the optical engine die, enhances the performance of the semiconductor package, simplifies the process, and improves the yield.

[0147] According to some embodiments, a method for forming a semiconductor package is provided, comprising forming a first photonic wiring structure on a substrate; disposing the first photonic wiring structure on a redistribution structure; disposing a second photonic wiring structure and an optical engine die on the redistribution structure; and forming a molding structure between the first photonic wiring structure and the second photonic wiring structure.

[0148] According to some embodiments, a molded structure is formed between a substrate and an optical engine die. According to some embodiments, the molded structure includes an optical glue. According to some embodiments, the method of forming a semiconductor package further includes forming a dielectric layer between the substrate and the first photonic wiring structure. According to some embodiments, the first photonic wiring structure includes a reflector formed of a high-refractive coating film, and the substrate has a curved surface, and the curved surface and the reflector are arranged in a first direction perpendicular to the substrate. According to some embodiments, the first photonic wiring structure includes a waveguide, and the reflector and the waveguide are arranged in a second direction different from the first direction.

[0149] According to some embodiments, a method of forming a semiconductor package is provided, including forming a redistribution structure on a substrate; disposing a first photonic wiring structure on the redistribution structure; disposing a second photonic wiring structure and an optical engine die on the redistribution structure, the second photonic wiring structure including a second dielectric structure and a second waveguide disposed in the second dielectric structure, the optical engine die being disposed on the second photonic wiring structure, and the second waveguide being optically coupled to the first waveguide and the optical engine die. Disposing the first photonic wiring structure on the redistribution structure includes forming a recess having a curved surface in an optical interposer die; forming a first dielectric structure covering the curved surface, the first waveguide being embedded in the first dielectric structure; and forming a reflective element on the first dielectric structure.

[0150] According to some embodiments, the method of forming a semiconductor package further includes forming an anti-reflection layer in the first dielectric structure. According to some embodiments, forming the anti-reflection layer further includes recessing the first dielectric structure to form an opening and forming the anti-reflection layer on the sidewalls of the opening. According to some embodiments, a curved surface of the optical interposer die is exposed from the opening, and the curved surface is spaced apart from the anti-reflection layer. According to some embodiments, the method of forming a semiconductor package further includes recessing a first surface of the optical interposer die to form a recess, the recess having a curved bottom surface, and the first surface facing the first photonic wiring structure. According to some embodiments, the method of forming a semiconductor package further includes forming an anti-reflection layer on the sidewalls of the recess. According to some embodiments, a third waveguide is formed in the redistribution structure, and the third waveguide is optically coupled to the first waveguide and the second waveguide. According to some embodiments, the direction in which the curved surface is arranged with the reflective element is different from the direction in which the reflective element is arranged with the second waveguide.

[0151] According to some embodiments, a semiconductor package is provided, including a substrate, a redistribution structure, a first photonic wiring structure, an optical interposer die, a second photonic wiring structure, an optical engine die, and a molding structure, wherein the redistribution structure is formed on the substrate, the first photonic wiring structure is arranged on the redistribution structure, the optical interposer die is arranged on the first photonic wiring structure, the second photonic wiring structure is arranged on the redistribution structure, the optical engine die is arranged on the second photonic wiring structure, and the molding structure is arranged between the first photonic wiring structure and the second photonic wiring structure.

[0152] According to some embodiments, the first photonic wiring structure includes a first dielectric structure, a first waveguide, and a reflective element, the first waveguide is arranged in the first dielectric structure, and the reflective element is arranged in the first dielectric structure. According to some embodiments, the second photonic wiring structure includes a second dielectric structure and a second waveguide, the second waveguide is arranged in the second dielectric structure and optically coupled to the first waveguide. According to some embodiments, the optical interposer die and the optical engine die are arranged in a direction parallel to the surface of the substrate. According to some embodiments, the optical engine die includes a photonic die and an electrical die, the photonic die is arranged on the second photonic wiring structure, the electrical die is arranged on the photonic die, and the photonic die and the electrical die have different widths. According to some embodiments, the optical interposer die covers the second photonic wiring structure and a portion of the molding structure.

[0153] The foregoing text summarizes the features of many embodiments so that those skilled in the art can better understand the present disclosure from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the novel spirit and scope of the present disclosure. Various changes, substitutions or modifications may be made to the present disclosure without departing from the novel spirit and scope of the present disclosure.

Claims

1. A semiconductor package, characterized in that: include: a substrate; a redistribution structure formed on the substrate; a first photonic wiring structure, disposed on the redistribution structure; An optical interposer die is disposed on the first photonic wiring structure; a second photonic wiring structure, disposed on the redistribution structure; An optical engine bare die, disposed on the second photonic wiring structure; as well as A molding structure is disposed between the first photon wiring structure and the second photon wiring structure.

2. The semiconductor package according to claim 1, wherein: The first photonic wiring structure comprises: a first dielectric structure; a first waveguide disposed in the first dielectric structure; and A reflective element is disposed in the first dielectric structure.

3. The semiconductor package according to claim 2, wherein: The second photonic wiring structure comprises: a second dielectric structure; and A second waveguide is disposed in the second dielectric structure and optically coupled to the first waveguide.

4. The semiconductor package according to claim 3, wherein: A third waveguide is formed in the redistribution structure, and the third waveguide is optically coupled to the first waveguide and the second waveguide.

5. The semiconductor package according to claim 1, wherein: The optical intermediate layer die and the optical engine die are arranged in a direction parallel to a surface of the substrate.

6. The semiconductor package according to claim 1, wherein: The optical engine die includes a photon die and an electric die, wherein the photon die is disposed on the second photon wiring structure, and the electric die is disposed on the photon die, wherein the photon die and the electric die have different widths.

7. The semiconductor package according to claim 6, wherein: The optical interposer die covers the second photonic wiring structure and a portion of the molding structure.

8. The semiconductor package according to claim 1, wherein: The molding structure is formed between the substrate and the optical engine die.

9. The semiconductor package according to claim 1, wherein: The molded structure includes an optical adhesive.

10. The semiconductor package according to claim 1, wherein: The first photonic wiring structure includes a reflector formed by a high-refractive coating film, and the substrate has a curved surface, wherein the curved surface and the reflector are arranged in a first direction perpendicular to the substrate.

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