Multi-wafer multi-isolation island chip structure, power supply chip and power supply management circuit

Abstract

The utility model relates to a multi-wafer multi-isolation island chip structure, a power supply chip and a power supply management circuit, comprising a substrate, the substrate is provided with a controller wafer and two field effect transistor wafers, and the two field effect transistor wafers are both electrically connected with the controller wafer and are respectively used as an upper bridge MOS and a lower bridge MOS of the chip; the controller wafer is packaged by a non-conductive adhesive, the field-effect tube wafers are packaged by a conductive adhesive and are electrically connected with the pins on the substrate through the conductive adhesive, and the controller wafer and the two field-effect tube wafers are subjected to field-effect tube grid isolation through the non-conductive adhesive and the conductive adhesive; according to the structure of the invention, the controller wafer is insulated and protected through the non-conductive adhesive, and the field effect transistor wafer is electrically connected with the pins on the substrate through the conductive adhesive, so that the number of wires is reduced, and the internal resistance is reduced. Different conductive adhesives are pasted on the controller wafer and the two field-effect tube wafers to serve as grid isolation of the field-effect tubes, and the risk that the upper bridge MOS and the lower bridge MOS are conducted at the same time can be reduced through grid isolation of the field-effect tubes.

Description

Technical Field

[0001] The utility model relates to the technical field of power chips, and more specifically to a multi-wafer multi-isolation island chip structure, a power chip and a power management circuit. Background Art

[0002] Existing low-power power ICs are all designed with a single wafer. As the current at the application end becomes larger and larger, the existing design is difficult to meet the application requirements for high power and high density. For this reason, European and American IC design companies have designed low-resistance power management chips from the wafer process to cope with ultra-high computing power SOC or memory chips; in multi-wafer design solutions, the wafer and the substrate are usually directly connected by wire bonding, which is difficult to process and will increase the overall internal resistance. A multi-wafer multi-isolation island chip solution is needed to improve this problem. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a multi-wafer multi-isolation island chip structure, a power chip and a power management circuit in view of the above-mentioned defects of the prior art.

[0004] The technical solution adopted by the utility model to solve its technical problems is:

[0005] A multi-wafer multi-isolation island chip structure is constructed, comprising a substrate, wherein a controller wafer and two field effect tube wafers are arranged on the substrate, the two field effect tube wafers are electrically connected to the controller wafer and respectively serve as an upper bridge MOS and a lower bridge MOS of the chip; the controller wafer is packaged by non-conductive glue, the field effect tube wafer is packaged by conductive glue and electrically connected to pins on the substrate by the conductive glue, and the controller wafer and the two field effect tube wafers are isolated from the field effect tube gates by the non-conductive glue and the conductive glue.

[0006] The multi-wafer multi-isolation island chip structure described in the utility model, wherein the two field effect tube wafers correspond to two different conductive glue blocks when packaged by conductive glue, the two conductive glue blocks are bonded, electrically connected or integrally formed, and the two conductive glue blocks are electrically connected to corresponding pins on basically different sides.

[0007] In the multi-wafer multi-isolation island chip structure described in the utility model, the controller wafer is electrically connected to corresponding pins on the substrate through wires.

[0008] In the multi-wafer multi-isolation island chip structure described in the utility model, the controller wafer is electrically connected to the field effect tube wafer via a wire.

[0009] A power chip, wherein the multi-wafer multi-isolation island chip structure as described above is arranged on the power chip.

[0010] A power management circuit, wherein the power chip as described above is arranged on the power management circuit.

[0011] The beneficial effects of the utility model are: by applying the structure of the present application, the controller wafer is insulated and protected by non-conductive glue, and conductive glue is used to electrically connect the field effect tube wafer to the pins on the substrate, thereby reducing the wires and lowering the internal resistance. In addition, the controller wafer and the two field effect tube wafers are affixed with different conductive glues for gate isolation. Field effect tube gate isolation can reduce the risk of simultaneous conduction of the upper and lower bridge MOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. The drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work:

[0013] Figure 1 This is a schematic structural diagram of a multi-wafer multi-isolation island chip structure according to a preferred embodiment of the utility model;

[0014] Figure 2 This is a circuit diagram of a multi-wafer multi-isolation island chip structure substrate of a preferred embodiment of the utility model;

[0015] Figure 3 This is a circuit diagram of a power chip of a preferred embodiment of the utility model. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the embodiments of the utility model clearer, the following will be combined with the technical solution in the embodiments of the utility model for a clear and complete description. Obviously, the described embodiments are partial embodiments of the utility model, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0017] The multi-wafer multi-isolation island chip structure of the preferred embodiment of the utility model is as follows Figure 1 See also Figure 2, including a substrate 100, on which a controller wafer 101 and two field effect tube wafers 102 are arranged, the two field effect tube wafers 102 are electrically connected to the controller wafer 101 and serve as an upper bridge MOS and a lower bridge MOS of the chip respectively; the controller wafer 101 is packaged by a non-conductive glue 103, the field effect tube wafer 102 is packaged by a conductive glue and electrically connected to the pins on the substrate 100 by the conductive glue, and the controller wafer 101 and the two field effect tube wafers 102 are isolated from the field effect tube gates by the non-conductive glue and the conductive glue;

[0018] By using the structure of the present application, the controller wafer 101 is insulated and protected by non-conductive glue, and the field effect tube wafer 102 is electrically connected to the pins on the substrate 100 by conductive glue, thereby reducing the wires and lowering the internal resistance. In addition, the controller wafer 101 and the two field effect tube wafers 102 are affixed with different conductive glues for gate isolation. Field effect tube gate isolation can reduce the risk of simultaneous conduction of the upper and lower bridge MOS.

[0019] Preferably, the two field effect transistor wafers 102 correspond to two different conductive adhesive blocks 104 when packaged with conductive adhesive, and the two conductive adhesive blocks 104 are bonded, electrically connected or integrally formed, and the two conductive adhesive blocks 104 are electrically connected to corresponding pins on substantially different sides.

[0020] It should be noted that the upper and lower bridge MOS can use MOSFETs with lower internal resistance according to the designed lower bridge time; the upper and lower bridge MOS cannot be turned on at the same time under PWM control, and the use of non-conductive glue to separately control the two GATE ends can shorten the wiring distance and thus reduce the overall internal resistance.

[0021] Preferably, the controller wafer 101 is electrically connected to corresponding pins on the substrate 100 through a wire; the controller wafer 101 is electrically connected to the field effect transistor wafer 102 through a wire.

[0022] A power chip, such as Figure 3 As shown, the power chip is provided with a multi-wafer multi-isolation island chip structure as described above; it should be noted that the present application Figure 3 The circuit shown in the figure is a conventional power supply circuit, which is only for auxiliary explanation and is not used to limit the circuit. It can also be other existing power supply circuits.

[0023] A power management circuit, wherein the power management circuit is provided with the power chip as above.

[0024] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to the utility model.

Claims

1. A multi-wafer multi-isolation island chip structure, comprising a substrate, characterized in that: A controller wafer and two field effect tube wafers are arranged on the substrate, and the two field effect tube wafers are electrically connected to the controller wafer and serve as the upper bridge MOS and lower bridge MOS of the chip respectively; the controller wafer is packaged by non-conductive glue, the field effect tube wafer is packaged by conductive glue and electrically connected to the pins on the substrate through the conductive glue, and the controller wafer and the two field effect tube wafers are isolated from the field effect tube gates by non-conductive glue and conductive glue.

2. The multi-wafer multi-isolation island chip structure according to claim 1, characterized in that: The two field effect tube wafers correspond to two different conductive adhesive blocks when packaged by conductive adhesive. The two conductive adhesive blocks are bonded, electrically connected or integrally formed. The two conductive adhesive blocks are electrically connected to corresponding pins on different sides.

3. The multi-wafer multi-isolation island chip structure according to claim 1, characterized in that: The controller wafer is electrically connected to corresponding pins on the substrate through wires.

4. The multi-wafer multi-isolation island chip structure according to claim 1, characterized in that: The controller wafer is electrically connected to the field effect transistor wafer via a wire.

5. A power chip, characterized in that: The power chip is provided with a multi-wafer multi-isolation island chip structure as described in any one of claims 1-4.

6. A power management circuit, characterized in that: The power management circuit is provided with the power chip as claimed in claim 5.

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