Semiconductor structure
By designing a curved and protruding test window on the metal pad of the semiconductor structure, the probe slide problem is solved, the chip density and production efficiency are improved, and the production cost is reduced.
Patent Information
- Application Number
- CN202420458710.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-09
- Publication Date
- 2025-01-28
- Estimated Expiration
- 2034-03-09
AI Technical Summary
In existing semiconductor structures, the smooth surface of the metal pad causes slip marks to appear on the probe during testing, limiting the size of the cutting channel design and affecting chip density and production costs.
A semiconductor structure is designed. The test window is set on the metal pad. The test window includes a curved first opening and a second opening that protrudes to the bottom of the first opening. Slim marks of needles.
By reducing the size of the metal pad and the sliding marks of the probe, the chip density is increased, the production cost is reduced, and the risk of testing problems and probe damage is reduced.
Smart Images
Figure CN222421976U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of semiconductors, and particularly relates to a semiconductor structure. Background Art
[0002] With the rapid development of integrated circuits, increasing chip density and reducing production costs have become the goals pursued by major companies. After the integrated circuit layout of each chip on the wafer is completed, a scribe line is defined in the adjacent areas between each chip, and then it is handed over to the packaging factory for wafer cutting. Among them, the scribe line size between chips is reduced, which can increase the density of the entire wafer. However, the scribe line size needs to meet the requirements of the wafer acceptance test (WAT), and the probe of the WAT test needs to be inserted into the metal pad for testing. The current metal pad is a rectangular structure with a smooth surface, which causes the probe needle to have large slip marks under stress. When the slip mark exceeds the size of the metal pad, it will cause test problems and even damage the probe. It also limits the size of the scribe line design and affects the chip density. Utility Model Content
[0003] The purpose of the utility model is to provide a semiconductor structure. Through the semiconductor structure provided by the utility model, the chip density can be improved, the testing problems can be reduced, and the production cost of the enterprise can be reduced.
[0004] In order to solve the above technical problems, the utility model provides a semiconductor structure, which at least includes:
[0005] A substrate, comprising a plurality of chips, wherein the area between adjacent chips is a dicing street;
[0006] At least one layer of metal pad, disposed on the cutting path;
[0007] A passivation layer, disposed on the substrate and covering the metal pad;
[0008] A test window is opened in the passivation layer and the metal pad, and the test window includes a first opening and a second opening that are interconnected. The bottom surface of the first opening is arranged in the metal pad, and the bottom of the first opening is arc-shaped. The second opening is arranged on one side of the first opening, and the bottom surface of the second opening protrudes from the bottom surface of the first opening. The area of the test window is less than or equal to the area of the metal pad.
[0009] In an embodiment of the present invention, the width of the first opening is 1.8 to 2.2 times the width of the second opening.
[0010] In one embodiment of the present invention, the width of the metal pad is 13 μm to 16 μm; and / or the thickness of the passivation layer is
[0011] In an embodiment of the present invention, two side edges of the test window are aligned with the edges of the metal pad.
[0012] In an embodiment of the present invention, at least one side edge of the test window is located on the metal pad.
[0013] In an embodiment of the present invention, the second opening exposes the surface of the metal pad, an edge of the first opening away from the second opening coincides with an edge of the metal pad, and a connection between the first opening and the second opening is arranged in an arc shape.
[0014] In an embodiment of the present invention, the metal pad includes a top metal pad, and the first opening is in the top metal pad.
[0015] In one embodiment of the present invention, the maximum depth of the first opening in the top metal pad is one quarter to one third of the thickness of the top metal pad; and / or the thickness of the top metal pad is
[0016] In an embodiment of the present invention, when the number of layers of the metal pads is greater than 1, the metal pads are connected via conductive plugs.
[0017] In an embodiment of the present invention, metal covering layers are provided on both sides of the metal pad in the thickness direction of the metal pad.
[0018] In summary, the utility model provides a semiconductor structure, which can reduce the size of the metal pad by improving the structure of the test window, thereby increasing the chip density and reducing the production cost; by setting the first opening, it can reduce the size of the slip mark caused by the probe, thereby reducing test problems, reducing probe damage problems, reducing test costs, and improving test efficiency; by setting the second opening, it can reduce test problems caused by the accumulation of metal pads, which can improve the production efficiency of the enterprise and reduce the production cost of the enterprise.
[0019] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for describing the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0021] Figure 1FIG. 4 is a schematic diagram of a metal pad in one embodiment.
[0022] Figure 2 FIG. 4 is a schematic diagram of a passivation layer in one embodiment.
[0023] Figure 3 FIG. 4 is a schematic diagram of a first recess in an embodiment.
[0024] Figure 4 FIG. 4 is a schematic diagram of a semiconductor structure in one embodiment.
[0025] Figure 5 FIG. 1 is a schematic diagram of the position of a probe in a semiconductor structure during testing in one embodiment.
[0026] Description of labels:
[0027] 10. Substrate; 101. Chip; 11. Interlayer dielectric layer; 12. Interconnection structure; 13. First dielectric; 14. First metal pad; 15. Metal covering layer; 16. Second dielectric layer; 17. Conductive plug; 18. Second metal pad; 19. Passivation layer; 201. First recess; 21. Test window; 211. First opening; 212. Second opening; 22. Probe. DETAILED DESCRIPTION
[0028] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0029] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0030] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.
[0031] The utility model provides a semiconductor structure, in which the shape of the detection window is set to a concave structure, which can reduce the size of the metal pad, increase the chip density, and reduce the production cost. At the same time, it can also reduce the size of the sliding mark caused by the probe, reduce the test problems, improve the test efficiency, and reduce the production cost of the enterprise. The semiconductor structure provided by the utility model can be widely used in different types of semiconductor integrated devices to improve the performance of semiconductor devices.
[0032] See also Figure 1 As shown, in one embodiment of the present invention, the semiconductor structure includes a substrate 10, and the substrate 10 is, for example, a semiconductor material such as single crystal silicon, polycrystalline silicon, amorphous silicon or silicon on insulator. A plurality of chips 101 are arranged on the substrate 10, and the present invention does not limit the type of the chips 101. The chip 101 is, for example, one or more of semiconductor devices such as a field effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), an insulated gate bipolar transistor (IGBT), a fast recovery diode (FRD), a high-speed and high-efficiency rectifier diode (HED), a constant voltage diode, a high-frequency diode, a light-emitting diode (LED), a gate light-closed thyristor (GTO), a light-triggered thyristor (LTT), a thyristor, a charge coupled device (CCD image sensor), a digital signal processor (DSP), a photorelay (PhotoRelay) or a microprocessor (Micro Processor), and the specific selection can be made according to the requirements of the integrated device. The area between adjacent chips 101 is defined as a dicing street for use in WAT testing and subsequent dicing of the chips 101 .
[0033] See also Figure 1As shown, in one embodiment of the utility model, an interlayer dielectric layer 11 is provided on the substrate 10, and a plurality of interconnection structures 12 are provided in the interlayer dielectric layer 11. The interconnection structure 12 is, for example, a metal connection or a conductive plug, and the interconnection structure 12 is provided on the chip 101 and in the cutting path between the chips 101. To make the picture simple, in this embodiment, only the interconnection structure 12 and the metal pad between the chips 101 are shown in the accompanying drawings, and the interconnection structure 12 and the metal wiring structure on the chip 101 are not shown. They can be designed according to actual production requirements and are not described in detail in this embodiment. Among them, the interlayer dielectric layer 11 is, for example, an insulating material such as silicon dioxide or silicon nitride, which can isolate the substrate 10 from the metal pad and prevent the diffusion of the metal from affecting the substrate 10. A barrier layer (not shown) is provided between the interconnect structure 12 and the interlayer dielectric layer 11. The barrier layer is, for example, a material with good adhesion such as tantalum (Ta), titanium (Ti), tantalum nitride (TaN) or titanium nitride (TiN), which enhances the adhesion between the interconnect structure 12 and the interlayer dielectric layer 11 and reduces the electromigration phenomenon. The thickness of the barrier layer is, for example, 2nm to 8nm. In this embodiment, the interconnect structure 12 is, for example, a low-resistance material such as tungsten, copper, silver or gold, to ensure that the resistance of the interconnect structure 12 is small, thereby improving the performance of the integrated device.
[0034] See also Figure 1 As shown, in one embodiment of the utility model, at least one layer of metal pads is arranged on the interlayer dielectric layer 11, and the metal pads are arranged on the cutting path. In this embodiment, two layers of metal pads are used as an example for explanation. The metal pads include a first metal pad 14 and a second metal pad 18, and the second metal pad 18 is arranged on the first metal pad 14. When the number of layers of the metal pads is greater than 1, adjacent metal pads are connected by conductive plugs 17. The conductive plugs 17 are, for example, low-resistance materials such as tungsten, copper, silver or gold, and the first metal pads 14 and the second metal pads 18 are, for example, metal materials such as aluminum or copper. The first metal pad 14 is arranged in the first dielectric 13, and the first dielectric 13 is arranged on the interlayer dielectric layer 11. The first dielectric 13 is, for example, a low dielectric constant (Low-K) material such as silicon oxide (SiO2) or silicon fluoride (SiF), silicon oxycarbide (SiOC) or silicon oxyfluoride (SiOF) to improve the reliability of the first metal pad 14. The second metal pad 18 is disposed in the second dielectric layer 16 , and the second dielectric layer 16 is disposed on the first dielectric 13 , wherein the second dielectric layer 16 is, for example, a low dielectric constant material such as silicon oxide or silicon fluoride, silicon oxycarbide or silicon oxyfluoride to improve the reliability of the second metal pad 18 .
[0035] See also Figure 1As shown, in one embodiment of the utility model, the conductive plug 17 is arranged in the second dielectric layer 16, and a barrier layer (not shown in the figure) is arranged between the conductive plug 17 and the second dielectric layer 16. The barrier layer is, for example, a material with good adhesion such as tantalum, titanium, tantalum nitride or titanium nitride, which enhances the adhesion between the conductive plug 17 and the second dielectric layer 16 and prevents the occurrence of electromigration. The thickness of the barrier layer is, for example, 2nm to 8nm. In the present application, a dielectric cover layer (not shown in the figure) can also be arranged between the interlayer dielectric layer 11, the first dielectric 13 and the second dielectric layer 16. The dielectric cover layer is, for example, silicon carbide nitride (SiCN) or silicon carbide (SiC), etc., to prevent the diffusion of metal ions in the metal pad to the interlayer dielectric layer 11. At the same time, the dielectric cover layer has high strength to increase the stress bearing capacity of the first dielectric layer 13 and the second dielectric layer 16 during the manufacturing process and reduce the cracking of the dielectric layer.
[0036] See also Figure 1 As shown, in one embodiment of the present invention, the metal pad located at the top is defined as the top metal pad. In this embodiment, the second metal pad 18 is the top metal pad. The thickness of the top metal pad is, for example, This is to meet the testing requirements of different products and prevent the probe card from piercing the metal pad on the top layer. In this embodiment, the thickness of the first metal pad 14 is, for example, The thickness of the first metal pad 14 may be equal to or unequal to the thickness of the second metal pad 18, depending on the requirements of the semiconductor structure. The width of the first metal pad 14 is equal to the width of the second metal pad 18, for example, 13μm to 16μm, and for example, 15μm. Compared with the commonly used metal pad size, for example, 30μm, the present application can reduce the size of the second metal pad 18, and the chip density on a wafer is increased by about 0.1%, which can increase the chip density and reduce production costs. In this embodiment, in order to make the picture clear, the width and thickness of the metal pad shown in the accompanying drawings are only for the purpose of clearly showing the semiconductor structure, and are different from the actual width and thickness.
[0037] See also Figure 1 As shown, in one embodiment of the utility model, in the thickness direction, a metal covering layer 15 is provided on both sides of the metal pad, that is, a metal covering layer 15 is provided between the first metal pad 14 and the interconnection structure 12 and the conductive plug 17, and a metal covering layer 15 is provided between the second metal pad 18 and the conductive plug 17 and on the top of the second metal pad 18. The metal covering layer 15 is, for example, at least one of titanium or titanium nitride, so as to reduce the electromigration of metal ions in the metal pad and improve the performance of the semiconductor structure. In one embodiment of the utility model, in the width direction, barrier layers can also be provided on both sides of the metal pad to reduce the diffusion of metal ions in the metal pad to the dielectric layer.
[0038] See also Figure 1 to Figure 2 As shown, in one embodiment of the present invention, the semiconductor structure further includes a passivation layer 19, which covers, for example, the second dielectric layer 16 and the metal cover layer 15 on the second metal pad 18. The passivation layer 19 is, for example, an insulating material such as silicon oxide, and the thickness of the passivation layer 19 is, for example, To meet the needs of different products.
[0039] See also Figures 2 to 5 As shown, in an embodiment of the utility model, the semiconductor structure further includes a test window 21, the test window 21 is opened in the passivation layer 19 and the metal pad, and the test window 21 includes a first opening 211 and a second opening 212 that are interconnected, the bottom surface of the first opening 211 is arranged in the metal pad, the bottom of the first opening 211 is arc-shaped, the second opening 212 is arranged on one side of the first opening 211, and the bottom surface of the second opening 212 protrudes from the bottom surface of the first opening 211. In this embodiment, the second opening 212 is, for example, located on the outer surface of the top metal pad to expose the surface of the top metal pad. The first opening 211 and the second opening 212 are obtained by two etchings, and the first opening 211 is obtained by wet etching, and the second opening 212 is obtained by dry etching. The area of the test window 21 is less than or equal to the area of the metal pad. When the area of the test window 21 is equal to the area of the metal pad, the two side edges of the test window 21 are aligned with the edges of the metal pad. When the area of the test window 21 is smaller than the area of the metal pad, at least one side edge of the test window 21 is located on the metal pad, that is, one side edge of the test window 21 is aligned with one side edge of the metal pad, or both side edges of the test window 21 are disposed on the metal pad. In this embodiment, for example, the area of the test window 21 is equal to the area of the metal pad.
[0040] See also Figures 2 to 5As shown, in one embodiment of the utility model, when obtaining the first opening 211, a first patterned photoresist layer (not shown in the figure) is formed on the passivation layer 19, and the first patterned photoresist layer starts from one side of the second metal pad 18, exposing a portion of the passivation layer 19 on the second metal pad 18. For example, the passivation layer 19 is dry-etched to expose a portion of the metal cover layer 15 on the second metal pad 18, and then the metal cover layer 15 and a portion of the second metal pad 18 are removed by wet etching to form the first recess 201. The etching gas for dry etching the passivation layer 19 is, for example, one or a combination of several gases selected from trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or nitrogen (N2), or a combination of these and oxygen (O2). The etching solution for etching the metal cover layer 15 and the second metal pad 18 is, for example, concentrated phosphoric acid, the mass fraction of which is, for example, 80% to 85%, and the concentrated phosphoric acid is etched at, for example, 40° C. to 65° C., and the etching time is controlled. The maximum depth of the etched second metal pad 18 is, for example, one quarter to one third of the thickness of the second metal pad 18. In the wet etching process, the isotropy of wet etching is utilized to form a groove with an arc at the edge, and one side of the formed first concave portion 201 is arc-shaped.
[0041] See also Figures 2 to 5 As shown, in one embodiment of the utility model, when the second opening 212 is obtained, a second patterned photoresist layer (not shown in the figure) is re-formed on the passivation layer 19, and the second patterned photoresist layer exposes the passivation layer 19 on the second metal pad 18 outside the first recess 201. For example, the exposed passivation layer 19 and the metal cover layer 15 are removed by dry etching until the second metal pad 18 is exposed and the etching is stopped to form a test window 21. Among them, the etching gas for dry etching the passivation layer 19 is, for example, a combination of one or several gases such as trifluoromethane, difluoromethane, sulfur hexafluoride or nitrogen, or a combination of them and oxygen. The etching gas for etching the metal cover layer 15 is, for example, a combination of one or several gases such as boron trichloride (BCl3), chlorine (Cl2) or carbon tetrafluoride (CF4), or a combination of them and oxygen. By controlling the etching time, the etching is stopped when the second metal pad 18 is etched. During the dry etching process, the gas generated by the reaction is pumped out of the reaction chamber through the exhaust system to reduce the residual reaction products and ensure that the dry etching forms the morphology of the test window 21 to form a second opening 212 with a regular structure.
[0042] See also Figures 4 to 5As shown, in one embodiment of the utility model, the width of the first opening 211 is, for example, 1.8 to 2.2 times the width of the second opening 212, and the maximum depth of the first opening 211 is, for example, one quarter to one third of the thickness of the top metal pad. On the side of the first opening 211 away from the second opening 212, the edge of the first opening 211 coincides with the edge of the second metal pad 18, and on the side of the first opening 211 close to the second opening 212, the first opening 211 transitions to the second opening 212 through an arc, that is, the connection between the first opening 211 and the second opening 212 is an arc, and a concave structure is formed between the first opening 211 and the second opening 212. When performing the WAT test, the optical detection system of the control platform is used to scan the substrate and record the coordinates of the first opening 211. During the test, the probe 22 is controlled to move to the coordinates of the first opening 211, and then the needle test is performed to test the electrical parameters of the semiconductor structure to detect the process of each wafer product, evaluate the quality and stability of the semiconductor manufacturing process, and warn of possible situations.
[0043] See also Figures 4 to 5 As shown, in one embodiment of the utility model, during the test process, according to the coordinates of the first opening 211, the probe 22 is moved to the first opening 211, and the probe 22 acts on the second metal pad 18 in the first opening 211. The second metal pad 18 is subjected to lateral and longitudinal forces. Since there is a concave structure between the first opening 211 and the second opening 212, the lateral force on the second metal pad 18 will be partially offset or even eliminated under the reaction of the concave structure, and the lateral sliding distance of the probe 22 is significantly reduced, which reduces the size of the sliding marks caused by the needle piercing stress of the probe 22, thereby reducing test problems, reducing the damage problem of the probe 22, reducing test costs, and improving test efficiency. At the same time, during the test process, under the force of the probe 22, the metal generated by the second metal pad 18 of the first opening 211 accumulates on the second opening 212, avoiding test problems caused by accumulation on the passivation layer 19, and further improving test efficiency. During the WAT test process, if the probe pierces the metal pad and causes a test problem, it takes about 1 hour to handle it. The semiconductor structure provided in the present application can greatly reduce the problem of abnormal needle insertion. Compared with regular rectangular metal pads, each test machine can save at least 0.5h to 1h per week, which can improve the production efficiency of the enterprise and reduce the production cost of the enterprise.
[0044] To sum up, the utility model provides a semiconductor structure. By improving the semiconductor structure, the size of the metal pad can be reduced, thereby increasing the chip density and reducing the production cost; the size of the slip mark caused by the probe can be reduced, thereby reducing test problems, reducing probe damage problems, reducing test costs, and improving test efficiency; the test problems caused by the accumulation of metal pads can be reduced, and the production efficiency of the enterprise can be improved and the production cost of the enterprise can be reduced.
[0045] The embodiments of the utility model disclosed above are only used to help illustrate the utility model. The embodiments do not describe all the details in detail, nor do they limit the utility model to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the utility model, so that technicians in the relevant technical field can well understand and use the utility model. The utility model is limited only by the claims and their full scope and equivalents.
Claims
1. A semiconductor structure, characterized in that: At least: A substrate, comprising a plurality of chips, wherein the area between adjacent chips is a dicing street; At least one layer of metal pad, disposed on the cutting path; A passivation layer, disposed on the substrate and covering the metal pad; A test window is opened in the passivation layer and the metal pad, and the test window includes a first opening and a second opening that are interconnected. The bottom surface of the first opening is arranged in the metal pad, and the bottom of the first opening is arc-shaped. The second opening is arranged on one side of the first opening, and the bottom surface of the second opening protrudes from the bottom surface of the first opening. The area of the test window is less than or equal to the area of the metal pad.
2. The semiconductor structure according to claim 1, characterized in that: The width of the first opening is 1.8 to 2.2 times the width of the second opening.
3. The semiconductor structure according to claim 2, characterized in that: The width of the metal pad is 13 μm to 16 μm; and / or the thickness of the passivation layer is 4. The semiconductor structure according to claim 1, characterized in that: The two side edges of the test window are aligned with the edges of the metal pad.
5. The semiconductor structure according to claim 1, characterized in that: At least one side edge of the test window is located on the metal pad.
6. The semiconductor structure according to claim 1, characterized in that The second opening exposes the surface of the metal pad, an edge of the first opening away from the second opening coincides with an edge of the metal pad, and a connection between the first opening and the second opening is arranged in an arc shape.
7. The semiconductor structure according to claim 1, characterized in that: The metal pad includes a top metal pad, and the first opening is within the top metal pad.
8. The semiconductor structure according to claim 7, characterized in that: The maximum depth of the first opening in the top metal pad is one quarter to one third of the thickness of the top metal pad; and / or the thickness of the top metal pad is 9. The semiconductor structure according to claim 1, characterized in that: When the number of layers of the metal pads is greater than 1, the metal pads are connected via conductive plugs.
10. The semiconductor structure according to claim 1, characterized in that Metal covering layers are arranged on both sides of the metal pad in the thickness direction of the metal pad.