Low-noise amplification circuit and radio frequency chip

Abstract

The utility model provides a low-noise amplification circuit and a radio frequency chip. The low-noise amplification circuit comprises a substrate, a plurality of first transistors, at least two first inductors and a second transistor, wherein the first transistors, the at least two first inductors and the second transistor are arranged on the substrate. The plurality of first transistors are divided into at least two groups, and each group of first transistors respectively correspond to one first inductor; the first transistors and the second transistors are located in the first area of the substrate, and the first inductors are arranged on the sides, close to the corresponding set of first transistors, outside the first area in a wiring mode. The low-noise amplification circuit can improve the consistency of the gain of each transistor.

Description

Technical Field

[0001] The present application relates to the field of radio frequency technology, and in particular to a low-noise amplifier circuit and a radio frequency chip. Background Art

[0002] In the field of radio frequency, a low-noise amplifier circuit is usually provided to perform low-noise amplification on radio frequency signals. For a low-noise amplifier circuit with multiple input terminals, multiple transistors are usually provided as the input terminals of the low-noise amplifier circuit. However, due to the influence of some parasitic parameters in the low-noise amplifier circuit, the gain of each transistor is inconsistent. Therefore, how to improve the consistency of the gain of each transistor in the low-noise amplifier circuit has become an urgent problem to be solved. Utility Model Content

[0003] The main purpose of the present application is to provide a low-noise amplifier circuit and a radio frequency chip, aiming to improve the consistency of the gain of each transistor in the low-noise amplifier circuit.

[0004] In a first aspect, the present application provides a low-noise amplifier circuit, comprising a substrate and a plurality of first transistors, at least two first inductors and a second transistor disposed on the substrate; the plurality of first transistors are divided into at least two groups, and each group of the first transistors corresponds to one first inductor;

[0005] The first end of each of the first transistors is used to receive a radio frequency signal, the second end of each of the first transistors is connected to the third end of the second transistor, the third end of each of the first transistors is connected to the first end of the corresponding first inductor, and the second end of each of the first inductors is grounded; the first end of the second transistor is used to receive a bias signal, and the second end of the second transistor is connected to the output port of the low-noise amplifier circuit;

[0006] The first transistor and the second transistor are located in a first region of the substrate, and each of the first inductors is arranged in a routing manner on a side outside the first region and adjacent to a corresponding group of the first transistors.

[0007] In one embodiment, the plurality of first transistors are divided into a first transistor group and a second transistor group, and the first inductor includes a first sub-inductor and a second sub-inductor; wherein the first transistor group corresponds to the first sub-inductor, and the second transistor group corresponds to the second sub-inductor;

[0008] The first transistor group is arranged on a first side of the first region, and the second transistor group is arranged on a second side of the first region; the first sub-inductor is arranged outside the first side of the first region, and the second sub-inductor is arranged outside the second side of the first region.

[0009] In one embodiment, the second transistor is arranged at a first position in the first region; at least two groups of the first transistors are respectively arranged on both sides of the first position in a first direction, and / or at least two groups of the first transistors are arranged on the same side of the first position in a second direction, wherein the first direction intersects with the second direction.

[0010] In one embodiment, the low-noise amplifier circuit also includes at least one bypass module, each of the bypass modules corresponds to one of the first transistors, and different bypass modules correspond to different first transistors; the first end of the bypass module is connected to the first end of the corresponding first transistor, and the second end of the bypass module is connected to the second end of the second transistor.

[0011] In one embodiment, the bypass module includes a first switch and a first capacitor; the first end of the first switch serves as the first end of the bypass module, the second end of the first switch is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the second end of the second transistor; each of the first switches is arranged on one side of the corresponding first transistor, and each of the first capacitors is arranged on a side of the second transistor away from each of the first transistors.

[0012] In one embodiment, the low-noise amplifier circuit further includes at least two groups of second switches, and the at least two groups of second switches correspond one-to-one to at least two of the first inductors;

[0013] Each switch in each group of the second switches is respectively connected to a different node in the corresponding first inductor; each group of the second switches is respectively arranged on one side of the corresponding first inductor, and is used to control the inductance of the corresponding first inductor.

[0014] In one embodiment, the low-noise amplifier circuit also includes a matching capacitor module; the first end of the matching capacitor module is connected to the second end of the second transistor, and the second end of the matching capacitor module is connected to the output port of the low-noise amplifier circuit; the matching capacitor module is arranged on a side of the second transistor away from each of the first transistors.

[0015] In one embodiment, the matching capacitor module includes multiple second capacitors; the low-noise amplifier circuit also includes at least one third switch; each of the third switches corresponds to one of the second capacitors and is connected in series or in parallel with the corresponding second capacitor; the third switch is arranged on one side of the matching capacitor module to control the capacitance value of the matching capacitor module.

[0016] In one embodiment, the low-noise amplifier circuit also includes a second inductor; a first end of the second inductor is connected to a power supply port of the substrate, and a second end of the second inductor is connected to a second end of the second transistor; the second inductor is arranged outside the first region and opposite to the second transistor.

[0017] In one embodiment, the low-noise amplifier circuit further includes a third capacitor; a first end of the third capacitor is connected to the first end of the second transistor, and a second end of the third capacitor is grounded; and the third capacitor is arranged outside the first region.

[0018] In one embodiment, the low-noise amplifier circuit further includes a feedback module; the feedback module is connected between the first end and the second end of the second transistor; the feedback module is arranged in the first region and is located on a side of the second transistor away from each of the first transistors.

[0019] In one embodiment, the low-noise amplifier circuit further includes a bias module; the bias module is respectively connected to the first end of each first transistor and the first end of the second transistor, and is used to provide a first bias signal for each first transistor and a second bias signal for the second transistor.

[0020] In a second aspect, an embodiment of the present application further provides a radio frequency chip, comprising a low-noise amplifier circuit as described in any one of the embodiments of the present application.

[0021] The low-noise amplifier circuit provided in the embodiment of the present application divides a plurality of first transistors into at least two groups, and each group of first transistors corresponds to a first inductor. In addition, the first transistor and the second transistor are located in the first region of the substrate, and each first inductor is arranged in a wiring manner on a side adjacent to a corresponding group of first transistors outside the first region. Through the circuit design and layout design of the low-noise amplifier circuit, a plurality of first transistors are grouped and connected to different first inductors to ensure that the difference in the wiring length between any two first transistors and the corresponding first inductor is controlled within a reasonable range, thereby avoiding the different gains of different first transistors due to excessive differences in parasitic inductance, thereby improving the consistency of the gains of each first transistor in the low-noise amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1A circuit diagram of an implementation of a low-noise amplifier circuit provided in an embodiment of the present application;

[0024] Figures 2 to 4 A top view of an implementation of a low-noise amplifier circuit provided in an embodiment of the present application;

[0025] Figure 5 A top view of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0026] Figure 6 A circuit diagram of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0027] Figure 7 A top view of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0028] Figure 8 A top view of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0029] Fig. 9 A circuit diagram of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0030] Fig.10 A top view of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0031] Fig.11 A top view of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0032] Fig.12 A circuit diagram of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0033] Fig.13 A top view of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0034] Fig.14 A top view of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0035] Fig.15 A circuit diagram of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0036] Fig.16 A top view of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0037] Fig.17 A circuit diagram of another implementation of the low-noise amplifier circuit provided in an embodiment of the present application;

[0038] Fig.18 A schematic block diagram of a radio frequency chip provided in an embodiment of the present application.

[0039] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0041] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0042] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0043] With the rapid development of wireless communication systems, the industry has higher and higher requirements on the performance of wireless communication systems. In wireless communication systems, a low-noise amplifier circuit is usually provided to perform low-noise amplification on radio frequency signals.

[0044] For a multi-input low-noise amplifier circuit, multiple transistors are usually arranged side by side, and the first end of each transistor can be used as an input end of the low-noise amplifier circuit to receive a radio frequency signal. In some application scenarios, each transistor is required to have the same gain, but due to the influence of some parasitic parameters in the circuit, it is difficult to keep the gain of each transistor consistent. How to reduce the difference in the gain of each transistor in the low-noise amplifier circuit is an urgent problem to be solved.

[0045] Based on the above problems, the present application proposes a low-noise amplifier circuit and a radio frequency chip, which improve the consistency of the gains of different transistors by controlling the wiring lengths between different transistors and the ground inductor.

[0046] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0047] like Figure 1 As shown, Figure 1 A circuit diagram of an implementation of a low noise amplifier circuit provided in an embodiment of the present application. Figures 2 to 4 As shown, Figures 2 to 4 A top view of an implementation of a low-noise amplifier circuit provided in an embodiment of the present application.

[0048] The low noise amplifier circuit 100 includes a substrate 110 and a plurality of first transistors 111, at least two first inductors 112 and a second transistor 113 disposed on the substrate 110. The plurality of first transistors 111 are divided into at least two groups, and each group of first transistors 111 corresponds to one first inductor 112.

[0049] Specifically, the first end of each first transistor 111 is connected to the input port RFin of the low-noise amplifier circuit 100, and is used to receive a radio frequency signal. The second end of each first transistor 111 is connected to the third end of the second transistor 113, and the third end of each first transistor 111 is connected to the first end of the corresponding first inductor 112. The second end of each first inductor 112 is grounded. The first end of the second transistor 113 is used to receive a bias signal Vp, and the second end of the second transistor 113 is connected to the output port RFout of the low-noise amplifier circuit 100.

[0050] It should be noted that the substrate 110 can be a chip substrate or a base substrate. The number of first transistors 111 in each group can be an odd number or an even number. The number of first transistors 111 in any two groups can be the same or different. The first ends of different first transistors 111 can receive radio frequency signals of the same frequency band or different frequency bands. The bias signal Vp can be provided by a bias module, for example, to ensure the accuracy of the amplified signal. The first transistor 111 and the second transistor 113 can be MOS tubes (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) or triodes, and of course can also be other types of transistors. When the first transistor 111 and the second transistor 113 are triodes, they can specifically be heterojunction bipolar transistors.

[0051] Specifically, the first transistor 111 and the second transistor 113 are located in the first region 10 of the substrate 110, and each first inductor 112 is arranged in a routing manner on a side adjacent to the corresponding group of first transistors 111 outside the first region 10. Among them, the first inductor 112 is arranged on a side adjacent to the corresponding group of first transistors 111, which may mean that the first inductor 112 and the corresponding group of first transistors 111 are not separated by other components. The first region 10 can be set on the substrate 110 according to actual conditions, for example, the first region 10 can be set in the middle area of ​​the substrate 110. The adjacent side can be determined according to the position of the first region 10. For example, when the position of the first region 10 is taken as the origin, the adjacent side can be the left side, right side, upper side or lower side relative to the first region 10, and of course, it can also be the left oblique side, right oblique side, upper oblique side or lower oblique side relative to the first region 10, and this application does not make specific limitations on this.

[0052] It should be noted that when the RF signal is transmitted between the first transistor 111 and the first inductor 112 through a wire, a parasitic inductance will be formed in the wiring between the first transistor 111 and the first inductor 112. When the wiring material and width are fixed, the longer the wiring length, the greater the parasitic inductance generated; the shorter the wiring, the smaller the parasitic inductance generated. If the parasitic inductance is too large, the gain of the first transistor 111 may be degraded. Therefore, the parasitic inductance formed between each first transistor 111 and the first inductor 112 can be minimized, that is, the wiring length between the third end of each first transistor 111 and the first end of the first inductor 112 can be minimized.

[0053] For a multi-input low-noise amplifier circuit having multiple first transistors 111, it is also necessary to keep the gains of different first transistors 111 consistent. When the number of first transistors 111 is large, if the third ends of all first transistors 111 are connected to the first end of the same first inductor 112, the wiring lengths from the third ends of different first transistors 111 to the first end of the first inductor 112 may differ greatly, and the parasitic inductances generated by different wirings vary greatly, resulting in inconsistent effects on the gains of the first transistors 111, resulting in the inability to meet the gain consistency requirements of the multiple first transistors 111.

[0054] In the embodiment of the present application, a plurality of first transistors 111 are connected to different first inductors 112 in groups, and each first inductor 112 is arranged in a routing manner on a side outside the first region 10 adjacent to a corresponding group of first transistors 111, so that the difference in routing length between any two first transistors 111 and the first end of the corresponding first inductor 112 is controlled within a reasonable range, thereby avoiding different gains of different first transistors 111 due to excessive differences in parasitic inductance, and effectively improving the gain consistency of the plurality of first transistors 111 in the low-noise amplifier circuit 100.

[0055] It is understandable that the inductive reactance of the first inductor 112 will affect the gain of the first transistor 111. Specifically, the larger the inductive reactance of the first inductor 112, the smaller the corresponding gain of the first transistor 111; the smaller the inductive reactance of the first inductor 112, the larger the corresponding gain of the second transistor 113. However, the stability of the first transistor 111 will also be affected by the first inductor 112. Specifically, the larger the inductive reactance of the first inductor 112, the better the stability of the first transistor 111; the smaller the inductive reactance of the first inductor 112, the worse the stability of the first transistor 111. As an implementation method, under the premise that the inductive reactance of the first inductor 112 is greater than a certain threshold to ensure the stability of the second transistor 113, the inductive reactance 120 of the first inductor 112 can be made as small as possible.

[0056] In one embodiment, each of the first transistors 111 and the second transistor 113 is located in the first region 10 of the substrate 110, and the layout position of each of the first transistors 111 can be determined according to the first position where the second transistor 113 is located. Figure 2 As shown, at least two groups of first transistors can be arranged on opposite sides of the second transistor 113 in the first direction, i.e., the X direction, and at least two groups of first transistors 111 can be arranged on the same side of the second transistor 113 in the second direction, i.e., the Y direction, wherein the first direction intersects the second direction. Optionally, the first direction is substantially perpendicular to the second direction.

[0057] It should be noted that by grouping the multiple first transistors 111 and determining the layout position of each group of first transistors 111 according to the first position of the second transistor 113, the circuit layout in the first area 10 is more reasonable, thereby reducing the wiring length between each first transistor 111 and the second transistor 113, and reducing the circuit area of ​​the noise amplifier circuit 100.

[0058] In some examples, the second transistor 113 is arranged at a first position in the first region 10, and at least two groups of first transistors 111 are arranged on both sides of the first position in the X direction. It can be understood that the two sides in the X direction of the first position refer to the projections of at least two groups of first transistors 111 in the X direction distributed on both sides of the projection of the first position in the X direction, without limiting whether the projections of at least two groups of first transistors 111 and the first position in the direction perpendicular to the X direction overlap. For example, when at least two groups of first transistors 111 are arranged along the X direction, the second transistor 113 can be sandwiched between at least two groups of first transistors 111 and overlap with the projections of each first transistor 111 in the Y direction. Alternatively, that is, the second transistor 113 can also be staggered with each first transistor 111 in the Y direction, as long as the projection of the second transistor 111 in the X direction is located between the projections of any two groups of first transistors 111 in the X direction.

[0059] As an implementation manner, the projections of at least two groups of first transistors 111 in the second direction Y direction may be staggered with each other, for example, distributed on both sides of the projection of the first position in the Y direction.

[0060] It can be understood that the two sides of the first position in the Y direction refer to the projections of at least two groups of first transistors 111 in the Y direction being distributed on both sides of the projection of the first position in the Y direction, without limiting whether the projections of at least two groups of first transistors 111 overlap with the projection of the first position in the Y direction perpendicular to the Y direction.

[0061] like Figure 3 As shown, the second transistor 113 is arranged at the first position in the first region 10, at least one group of first transistors 111 is arranged on the first side of the first position in the X direction, and on the first side (upper side) in the Y direction of the first position; in addition, at least one group of first transistors 111 is arranged on the second side of the first position in the X direction, and is located on the second side (lower side) of the first position in the Y direction.

[0062] As an implementation, the projections of at least two groups of first transistors 111 in the second direction Y direction may be located on the same side of the projection of the first position in the Y direction, for example, the projections of at least two groups of first transistors 111 in the second direction Y direction may overlap.

[0063] like Figure 2 As shown, the second transistor 113 is arranged at a first position in the first region 10 , and at least two groups of first transistors 111 are arranged at both sides of the first position in the X direction and at a first side in the Y direction, respectively.

[0064] like Figure 4As shown, the second transistor 113 is arranged at a first position in the first region 10 , and at least two groups of first transistors 111 are arranged at two sides of the first position in the X direction and at a second side in the Y direction, respectively.

[0065] In some examples, the second transistor 113 is arranged at a first position in the first region 10, and at least two groups of first transistors 111 are arranged on the same side of the first position in the Y direction. Figure 2 As shown, the second transistor 113 is arranged at the first position in the first region 10, and at least two groups of first transistors 111 are arranged at the first position on the first side (upper side) in the Y direction. Specifically, at least one group of first transistors 111 is arranged at the first side (left side) in the X direction, and at least one group of first transistors 111 is arranged at the first position on the second side (right side) in the X direction.

[0066] like Figure 4 As shown, the second transistor 113 is arranged in the first region 10, and at least two groups of first transistors 111 are arranged on the second side (lower side) of the first position in the Y direction. Specifically, at least one group of first transistors 111 is arranged on the left side of the first position in the X direction, and at least one group of first transistors 111 is arranged on the right side of the first position in the X direction.

[0067] In one embodiment, the plurality of first transistors 111 are divided into a first transistor group and a second transistor group, and the first inductor 112 includes a first sub-inductor and a second sub-inductor; wherein the first transistor group corresponds to the first sub-inductor, and the second transistor group corresponds to the second sub-inductor. The first transistor group is arranged on the first side of the first region 10, and the second transistor group is arranged on the second side of the first region 10; the first sub-inductor is arranged outside the first side of the first region 10, and the second sub-inductor is arranged outside the second side of the first region 10.

[0068] It should be noted that the first side and the second side of the first area 10 may be opposite sides. For example, when the position of the first area 10 is used as a reference, the first side and the second side of the first area 10 may be the left side and the right side of the first area 10, respectively, and of course, they may also be the left oblique side and the right oblique side relative to the first area 10. Alternatively, the first side and the second side of the first area 10 may be the upper side or the lower side of the first area 10, respectively, and of course, they may also be the upper oblique side or the lower oblique side relative to the first area 10. When the first side and the second side are the left side, the right side, the upper side or the lower side of the first area 10, the outer side of the first side and the second side may be the left side of the left side, the right side of the right side, the upper side of the upper side or the lower side of the lower side of the first area 10, and the outer side may of course also be the oblique outer side, and this application does not make specific limitations on this.

[0069] When the plurality of first transistors 111 are divided into a first transistor group and a second transistor group, and the first inductor 112 includes a first sub-inductor and a second sub-inductor, the first sub-inductor and the second sub-inductor can be respectively arranged outside the position of a corresponding group of first transistors 111, such as the first sub-inductor is arranged outside the first side of the first region 10, and the second sub-inductor is arranged outside the second side of the first region 10, so that the difference in the wiring length between any two first transistors 111 and the corresponding first inductor 112 is controlled within a reasonable range, thereby avoiding different gains of different first transistors 111 due to excessive differences in parasitic inductance, and effectively improving the gain consistency of the plurality of first transistors 111 in the low-noise amplifier circuit 100.

[0070] For example, Figure 5 As shown, the plurality of first transistors 111 in the low noise amplifier circuit 100 are divided into a first transistor group D1 and a second transistor group D2, and the first inductor 112 may specifically include a first sub-inductor L1 and a second sub-inductor L2. Thus, the first transistor group D1 may correspond to the first sub-inductor L1, and the second transistor group D2 may correspond to the second sub-inductor L2.

[0071] The third end of each first transistor 111 in the first transistor group D1 is connected to the first end of the first sub-inductor L1, and the third end of each first transistor 111 in the second transistor group D2 can be connected to the first end of the second sub-inductor L2. The second end of the first sub-inductor L1 and the second end of the second sub-inductor L2 are both grounded. The first transistor group D1 is arranged on the first side of the first region 10, and the second transistor group D2 is arranged on the second side of the first region 10; the first sub-inductor L1 is arranged outside the first side of the first region 10, and the second sub-inductor L2 is arranged outside the second side of the first region 10. Therefore, the difference in the routing length from the third end of each first transistor 111 to the first end of the corresponding first inductor 112 will not be too large, which can ensure the stability and gain consistency of multiple first transistors 111.

[0072] It is easy to understand that the magnitude of the parasitic inductance from the third terminals of every two or three first transistors 111 to the first terminals of the corresponding first inductor 112 is positively correlated with the wiring length from the third terminals of every two or three first transistors 111 to the first terminals of the corresponding first inductor 112.

[0073] Regardless of whether the plurality of first transistors 111 are in the same group, for any two first transistors 111, the difference in the wiring length between them and the corresponding first inductor 112 is less than or equal to the second value. The wiring length between the third terminals of every two first transistors 111 and the first terminals of the corresponding first inductor 112 can be the same, and the parasitic inductances generated thereby can be equal or approximately equal.

[0074] In one embodiment, if Figure 6 As shown, the low noise amplifier circuit 100 further includes at least one bypass module 120, each bypass module 120 corresponds to a first transistor 111, and different bypass modules 120 correspond to different first transistors 111. A first end of the bypass module 120 is connected to a first end of the corresponding first transistor 111, and a second end of the bypass module 120 is connected to a second end of the second transistor 113.

[0075] It should be noted that the bypass module 120 is used to provide a bypass channel for the corresponding first transistor 111. When the first transistor 111 is not required to provide gain amplification, the first transistor 111 can be controlled to be turned off, and the bypass module 120 corresponding to the first transistor 111 can be controlled to be turned on. In practical applications, one or more bypass modules 120 can be set as needed, and a bypass module 120 can be set for each of the first transistors 111, or the bypass module 120 can be not set for some of the first transistors 111.

[0076] For example, Figure 6 As shown, the bypass module 120 includes a first switch S1 and a first capacitor C1. The first end of the first switch S1 serves as the first end of the bypass module 120 and is connected to the first end of the corresponding first transistor 111. The second end of the first switch S1 is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected to the second end of the second transistor 113.

[0077] In one embodiment, if Figure 7 As shown, the bypass module 120 includes a first switch S1 and a first capacitor C1. The first end of the first switch S1 serves as the first end of the bypass module 120 and is connected to the first end of the corresponding first transistor 111. The second end of the first switch S1 is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected to the second end of the second transistor 113. Each first switch S1 is arranged on one side of the corresponding first transistor 111, and each first capacitor C1 is arranged on a side of the second transistor 113 away from each first transistor 111.

[0078] It should be noted that by placing the first switch S1 on one side of the corresponding first transistor 111 and arranging the first capacitor C1 on the side of the second transistor 113 away from each first transistor 111, the circuit layout of the bypass module 120 can be made more reasonable, thereby reducing the wiring length required for the bypass module 120 and reducing the circuit area occupied by the noise amplifier circuit 100.

[0079] In one embodiment, the low noise amplifier circuit 100 further includes at least two groups of second switches, and the at least two groups of second switches correspond to at least two first inductors 112 one by one. Each switch in each group of second switches is respectively connected to a different node in the corresponding first inductor 112; each group of second switches is respectively arranged on one side of the corresponding first inductor 112, and is used to control the inductance of the corresponding first inductor 112.

[0080] Each group of second switches includes at least two switches. At least two switches in each group of second switches can be connected to different nodes in the corresponding first inductor 112, respectively, and the different nodes include the second end of the first inductor 112 and at least one routing node. The circuit structure of the at least two groups of second switches can be determined according to actual conditions. By controlling the switches in each group of second switches to be turned on or off, the inductance of the corresponding first inductor 112 can be adjusted.

[0081] Exemplarily, the number of second switches in each group is at least two, the first end of a second switch in each group is connected to the second end of the corresponding first inductor, the first end of at least one second switch is connected to a node in the corresponding first inductor, and the second end of each second switch is grounded. By controlling one switch in each group of second switches to be turned on and the other switches to be turned off, the inductance of the first inductor 112 is adjusted.

[0082] For example, Figure 8 As shown, the low noise amplifier circuit 100 also includes at least two groups of second switches 130, and the at least two groups of second switches 130 correspond to at least two first inductors 112 one by one. Each switch in each group of second switches 130 is respectively connected to a different node in the corresponding first inductor 112; each group of second switches 130 is respectively arranged on one side of the corresponding first inductor 112, and each group of second switches 130 is used to control the inductance of the corresponding first inductor 112. By arranging each group of second switches 130 on one side of the corresponding first inductor 112, the wiring length between each group of second switches 130 and the corresponding first inductor 112 can be reduced, so that the layout design of the noise amplifier circuit 100 is more reasonable.

[0083] In one embodiment, if Fig. 9 and Fig.10 As shown, the low noise amplifier circuit 100 further includes a matching capacitor module 140. A first end of the matching capacitor module 140 is connected to a second end of the second transistor 113, and a second end of the matching capacitor module 140 is connected to an output port RFout of the low noise amplifier circuit 100; the matching capacitor module 140 is arranged on a side of the second transistor 113 away from each first transistor 111.

[0084] Among them, the matching capacitor module may include multiple second capacitors, and the size and selection of the second capacitors can be determined according to the characteristics and requirements of different components in the circuit. By arranging the matching capacitor module 140 on the side of the second transistor 113 away from each first transistor 111, the wiring length between the second transistor 113 and the matching capacitor module 140 can be reduced, and the layout space of the substrate 110 can be reasonably utilized, thereby making the layout design more reasonable.

[0085] For example, Fig.11 As shown, the low noise amplifier circuit 100 further includes at least one third switch S3, and the matching capacitor module 140 includes a plurality of second capacitors. Each third switch S3 corresponds to a second capacitor and is connected in series or in parallel with the corresponding second capacitor; the third switch S3 is arranged on one side of the matching capacitor module 140, and is used to control the capacitance value of the matching capacitor module 140.

[0086] It should be noted that when the matching capacitor module 140 includes multiple second capacitors, at least one third switch S3 can be set to control the capacitance value of the matching capacitor module 140. The connection mode of the third switch S3 and the corresponding second capacitor can be set according to the actual situation. For example, the third switch S3 can be connected in series or in parallel with the corresponding second capacitor. By placing the third switch S3 on one side of the matching capacitor module 140, the wiring length between the third switch S3 and the matching capacitor module 140 can be reduced, and the layout space of the substrate 110 can be reasonably utilized, so that the layout design is more reasonable.

[0087] In one embodiment, if Fig.12 and Fig.13 As shown, the low noise amplifier circuit 100 further includes a second inductor 114. A first end of the second inductor 114 is used to connect to the power supply port VCC, and a second end of the second inductor 114 is connected to a second end of the second transistor 113. The second inductor 114 is arranged outside the first region 10 and opposite to the second transistor 113.

[0088] It should be noted that the power supply port VCC can be connected to an internal power supply or an external power supply to provide a power supply signal for the low-noise amplifier circuit 100. It is easy to understand that the power supply signal received by the power supply port VCC is a DC signal, and the power supply signal may carry an AC interference component. Therefore, the second inductor 114 plays a choking role to prevent the AC interference component carried in the power supply signal from entering the low-noise amplifier circuit 100. By arranging the second inductor 114 outside the first area 10 and at the relative position of the second transistor 113, for example, arranging the second inductor 114 at a second position on the side of the second transistor 113 away from each first transistor 111, the layout space of the low-noise amplifier circuit 100 can be reasonably utilized, so that the layout design of the low-noise amplifier circuit 100 is more reasonable. It should be noted that the second inductor 114 can also form an output matching unit with the matching capacitor module 140, which is used to adjust the output impedance of the noise amplifier circuit 100 to achieve impedance matching, thereby improving the quality and stability of the amplified signal transmission.

[0089] In one embodiment, if Fig.14 As shown, the low noise amplifier circuit 100 also includes a third capacitor C3. The first end of the third capacitor C3 is connected to the first end of the second transistor 113, and the second end of the third capacitor C3 is grounded; the third capacitor C3 is arranged outside the first area 10. It should be noted that the third capacitor C3 is connected between the second transistor 113 and the ground terminal, which can improve the circuit stability. The third capacitor C3 is arranged outside the first area 10, and the specific position can be determined according to the actual situation, so as to ensure the rationality of the layout of the noise amplifier circuit 100.

[0090] In one embodiment, if Fig.15 and Fig.16 As shown, the low noise amplifier circuit 100 further includes a feedback module 150. The feedback module 150 is connected between the first end and the second end of the second transistor 113; the feedback module 150 is arranged in the first region 10 and is located on a side of the second transistor 113 away from each first transistor 111. The feedback module 150 may be an RC feedback circuit. By adding the feedback module 150 between the first end and the second end of the second transistor 113, a feedback path can be formed to improve the stability of the low noise amplifier circuit 100.

[0091] It should be noted that by disposing the feedback module 150 in the first region 10 and on the side of the second transistor 113 away from the first transistors 111, the layout space of the low-noise amplifier circuit 100 can be reasonably utilized, making the layout design of the low-noise amplifier circuit 100 more reasonable.

[0092] In one embodiment, if Fig.17As shown, the low noise amplifier circuit also includes a bias module 160. The bias module is connected to the first end of each first transistor 111 and the first end of the second transistor 113, respectively, and is used to provide a first bias signal Vp1 for each first transistor 111 and a second bias signal Vp2 for the second transistor 113. The first bias signal Vp1 and the second bias signal Vp2 can be a bias current or a bias voltage. The bias module 160 can include a number of components, such as a bias resistor, etc. The bias module 160 can be arranged in a second area adjacent to the first area in the substrate 110, thereby reducing the wiring between the bias module 160 and the first transistor 111 and the second transistor 113, thereby saving the circuit area of ​​the low noise amplifier circuit 100.

[0093] It should be noted that the bias module 160 can be set according to the grouping of the first transistors 111, for example, a corresponding bias module 160 is configured for each group of the first transistors 111. The bias module 160 can be set according to the number of the first transistors 111, for example, the bias module 160 can also be M, where M can specifically be the number of the first transistors 111, and each bias module can correspond to the first transistor 111.

[0094] The bias module 160 may also be set according to the sum of the number of the first transistors 111 and the number of the second transistors 113. The bias module 160 may also include N bias modules, where N may be the sum of the number of the first transistors 111 and the number of the second transistors 113. Different bias modules are used to provide bias signals for each transistor, and the bias signals do not affect each other, thereby improving the working stability of the low-noise amplifier circuit 100.

[0095] The low-noise amplifier circuit 100 described in the above embodiment divides the plurality of first transistors 111 into at least two groups, and each group of first transistors 111 corresponds to a first inductor 112. In addition, the first transistors 111 and the second transistors 113 are located in the first region 10 of the substrate 110, and each first inductor 112 is arranged in a wiring manner on a side outside the first region 10 and adjacent to the corresponding group of first transistors 111. Through the circuit design and layout design of the low-noise amplifier circuit 100, the plurality of first transistors 111 are grouped and connected to different first inductors 112, ensuring that the difference in the wiring length between any two first transistors 111 and the corresponding first inductor 112 is controlled within a reasonable range, thereby avoiding different gains of different first transistors 111 due to excessive differences in parasitic inductance, thereby improving the consistency of the gains of each first transistor 111 in the low-noise amplifier circuit 100.

[0096] Please refer to Fig.18 , Fig.18A schematic block diagram of a radio frequency chip provided in an embodiment of the present application.

[0097] like Fig.18 As shown, the radio frequency chip 200 includes the low noise amplifier circuit 210 described in the above embodiment.

[0098] The low noise amplifier circuit 210 may be the low noise amplifier circuit 100 described in the above embodiment. The substrate in the low noise amplifier circuit 210 may include the base plate in the radio frequency chip 200 .

[0099] It should be noted that the RF chip 200 can be a component that integrates two or more discrete devices such as a RF switch, a low noise amplifier, a filter, a duplexer, a power amplifier, etc. into an independent module, thereby improving the integration and miniaturizing the volume. Specifically, the RF chip 200 can be applied to devices with communication functions such as smart phones, tablet computers, and smart watches.

[0100] It can be understood that the beneficial effects that can be achieved by the radio frequency chip provided in the embodiment of the present application can refer to the beneficial effects of the low-noise amplifier circuit in the corresponding embodiment provided above, and will not be repeated here.

[0101] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A low noise amplifier circuit, characterized in that: The device comprises a substrate and a plurality of first transistors, at least two first inductors and a second transistor arranged on the substrate; the plurality of first transistors are divided into at least two groups, and each group of the first transistors corresponds to one first inductor; The first end of each of the first transistors is used to receive a radio frequency signal, the second end of each of the first transistors is connected to the third end of the second transistor, the third end of each of the first transistors is connected to the first end of the corresponding first inductor, and the second end of each of the first inductors is grounded; the first end of the second transistor is used to receive a bias signal, and the second end of the second transistor is connected to the output port of the low-noise amplifier circuit; The first transistor and the second transistor are located in a first region of the substrate, and each of the first inductors is arranged in a routing manner on a side outside the first region and adjacent to a corresponding group of the first transistors.

2. The low noise amplifier circuit according to claim 1, characterized in that: The first transistors are divided into a first transistor group and a second transistor group, and the first inductor includes a first sub-inductor and a second sub-inductor; wherein the first transistor group corresponds to the first sub-inductor, and the second transistor group corresponds to the second sub-inductor; The first transistor group is arranged on a first side of the first region, and the second transistor group is arranged on a second side of the first region; the first sub-inductor is arranged outside the first side of the first region, and the second sub-inductor is arranged outside the second side of the first region.

3. The low noise amplifier circuit according to claim 1, characterized in that: The second transistor is arranged at a first position in the first region; At least two groups of the first transistors are respectively arranged on both sides of the first position in a first direction, and / or at least two groups of the first transistors are arranged on the same side of the first position in a second direction, wherein the first direction and the second direction intersect.

4. The low noise amplifier circuit according to claim 1, characterized in that: The low-noise amplifier circuit further includes at least one bypass module, each of the bypass modules corresponds to one of the first transistors, and different bypass modules correspond to different first transistors; The first end of the bypass module is connected to the first end of the corresponding first transistor, and the second end of the bypass module is connected to the second end of the second transistor.

5. The low noise amplifier circuit according to claim 4, characterized in that: The bypass module includes a first switch and a first capacitor; The first end of the first switch serves as the first end of the bypass module, the second end of the first switch is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the second end of the second transistor; each of the first switches is arranged on one side of the corresponding first transistor, and each of the first capacitors is arranged on a side of the second transistor away from each of the first transistors.

6. The low noise amplifier circuit according to claim 1, characterized in that: The low-noise amplifier circuit further includes at least two groups of second switches, and the at least two groups of second switches correspond one-to-one to at least two of the first inductors; Each switch in each group of the second switches is respectively connected to a different node in the corresponding first inductor; each group of the second switches is respectively arranged on one side of the corresponding first inductor, and is used to control the inductance of the corresponding first inductor.

7. The low noise amplifier circuit according to claim 1, characterized in that: The low-noise amplifier circuit also includes a matching capacitor module; The first end of the matching capacitor module is connected to the second end of the second transistor, and the second end of the matching capacitor module is connected to the output port of the low-noise amplifier circuit; the matching capacitor module is arranged on a side of the second transistor away from each of the first transistors.

8. The low noise amplifier circuit according to claim 7, characterized in that: The matching capacitor module includes a plurality of second capacitors; the low-noise amplifier circuit also includes at least one third switch; Each of the third switches corresponds to one of the second capacitors and is connected in series or in parallel with the corresponding second capacitor; the third switch is arranged on one side of the matching capacitor module and is used to control the capacitance value of the matching capacitor module.

9. The low noise amplifier circuit according to claim 1, characterized in that: The low-noise amplifier circuit also includes a second inductor; The first end of the second inductor is used to connect to the power supply port, and the second end of the second inductor is connected to the second end of the second transistor; the second inductor is arranged outside the first area and opposite to the second transistor.

10. The low noise amplifier circuit according to claim 1, characterized in that: The low noise amplifier circuit further includes a third capacitor; A first end of the third capacitor is connected to a first end of the second transistor, and a second end of the third capacitor is grounded; the third capacitor is arranged outside the first region.

11. The low-noise amplifier circuit according to any one of claims 1 to 10, characterized in that: The low noise amplifier circuit also includes a feedback module; The feedback module is connected between the first end and the second end of the second transistor; the feedback module is arranged in the first region and is located at a side of the second transistor away from each of the first transistors.

12. The low-noise amplifier circuit according to any one of claims 1 to 10, characterized in that: The low noise amplifier circuit also includes a bias module; The bias module is connected to the first end of each of the first transistors and the first end of the second transistor respectively, and is used to provide a first bias signal for each of the first transistors and a second bias signal for the second transistors.

13. A radio frequency chip, characterized in that: Comprising the low-noise amplifier circuit as described in any one of claims 1-12.

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