Clock synchronization system of edge server
By designing the edge server clock synchronization system that is compatible with a variety of clock sources, the existing system needs to be designed according to the specific design line of the clock source, and the cost of the system is reduced and the high -precision clock synchronization is achieved.
Patent Information
- Application Number
- CN202323436864.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-15
- Publication Date
- 2025-01-28
- Estimated Expiration
- 2033-12-15
AI Technical Summary
The existing edge server clock synchronization system needs to design the clock synchronization line according to the clock source selected by the user, resulting in incompatibility between the boards and cards, long development time and high cost, and increasing design costs.
Design a clock synchronization system for the edge server, including server motherboard, PCIE standard card and external card. It forms a variety of clock synchronization paths through the first and second clock chips and the plate clock clock source or serial clock source to achieve multiple types of various types Compatibility of clock source.
This system can be compatible with a variety of clock sources, reduce the development cost of the clock synchronization system, meet the high -precision clock synchronization requirements of the small base station, and have a wide range of application prospects.
Smart Images
Figure CN222423693U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of server clock synchronization, and in particular relates to a clock synchronization system of an edge server. Background Art
[0002] GNNS is the abbreviation of Global Navigation Satellite System.
[0003] PTP, short for Precision Time Protocol, is a protocol for synchronizing time and frequency for standard Ethernet terminal devices, also known as the IEEE1588 protocol.
[0004] In order to meet the high-precision clock synchronization requirements of wireless base stations, edge servers need to support GNSS and PTP protocols to adapt to different environments and meet the clock synchronization requirements of small base station scenarios. There are many existing clock sources, including optical module PTP, PCIe clock card, OCP card or self-developed clock card, but the clock source selected by the user is uncertain, and the synchronization methods of different clock sources are different. The current clock synchronization requires the design of clock synchronization circuit boards according to the clock source selected by the user. The boards are not compatible, the development time is long, and the cost is high, resulting in high design costs for the existing clock synchronization system.
[0005] In summary, edge servers need to support multiple clock sources, and the synchronization of each clock source requires specific circuit design on the board. The board development cost of the clock synchronization system is high.
[0006] Therefore, in view of the above defects, it is very necessary to provide a clock synchronization system for an edge server. Summary of the invention
[0007] In view of the defects that the above-mentioned edge server needs to support multiple clock sources, the synchronization of each clock source requires specific circuits to be designed on the board, and the board development cost of the clock synchronization system is high, the utility model provides a clock synchronization system for an edge server to solve the above-mentioned technical problems.
[0008] The utility model provides a clock synchronization system for an edge server, including a server mainboard, a PCIe standard card and an external card;
[0009] The server motherboard is equipped with CPU, PCH, BMC, serial port and optical port. The serial port is connected to the serial port clock source, and the optical port is connected to the onboard network card clock source.
[0010] The PCIe standard card is provided with a first clock chip, and the external card is provided with a second clock chip;
[0011] The first clock chip forms a clock synchronization path through the server mainboard and the onboard network card clock source or the serial port clock source;
[0012] The second clock chip forms a clock synchronization path through the server mainboard and the onboard network card clock source or the serial port clock source.
[0013] Furthermore, the clock synchronization path formed by the first clock chip through the server mainboard and the onboard network card clock source includes a timing path from the optical port to the PCIe standard card and a timing path from the PCIe standard card to the optical port;
[0014] The optical port to PCIe standard card timing path includes a first timing path and a second timing path;
[0015] The first timekeeping path includes an onboard network card clock source, an optical port, and a first clock chip connected in sequence;
[0016] The second punctuality path includes the onboard network card clock source, the optical port, the PCH, the CPU, the BMC and the first clock chip connected in sequence;
[0017] The timing path from the PCIe card to the optical port includes a first timing path and a second timing path;
[0018] The first timing path includes a first clock chip, an optical port and an onboard network card clock source connected in sequence;
[0019] The second timing path includes a first clock chip and a BMC connected in sequence.
[0020] Furthermore, the clock path formed by the first clock chip through the server mainboard and the serial port clock source includes a serial port to PCIe standard card timing path and a PCIe standard card to serial port timing path;
[0021] The serial port to PCIe standard card timing path includes the third timing path and the fourth timing path;
[0022] The third timekeeping path includes a serial port clock source, a serial port, and a first clock chip connected in sequence;
[0023] The fourth timekeeping path includes a serial port clock source, a serial port, a BMC and a first clock chip connected in sequence;
[0024] The timing path from the PCIe card to the serial port includes the third timing path and the fourth timing path;
[0025] The third timing path includes a first clock chip, a serial port, and a serial port clock source connected in sequence;
[0026] The fourth timing path includes a first clock chip, a BMC, a serial port and a serial port clock source which are connected in sequence.
[0027] Furthermore, the external card adopts an OCP card.
[0028] Further, the clock synchronization path formed by the second clock chip through the server mainboard and the onboard network card clock source includes an optical port to OCP card timing path and an OCP card to optical port timing path;
[0029] The optical port to OCP card timing path includes the fifth timing path and the sixth timing path;
[0030] The fifth timekeeping path includes an onboard network card clock source, an optical port, and a second clock chip connected in sequence;
[0031] The sixth punctual path includes an onboard network card clock source, an optical port, a PCH, a CPU, a BMC and a second clock chip connected in sequence;
[0032] The timing path from the OCP card to the optical port includes the fifth timing path and the sixth timing path;
[0033] The fifth timing path includes a second clock chip, an optical port and an onboard network card clock source connected in sequence;
[0034] The sixth timing path includes a second clock chip and a BMC which are connected in sequence.
[0035] Further, the clock path formed by the second clock chip through the server mainboard and the serial port clock source includes a serial port to OCP card timing path and an OCP card to serial port timing path;
[0036] The serial port to OCP card timing path includes the seventh timing path and the eighth timing path;
[0037] The seventh timekeeping path includes a serial port clock source, a serial port and a second clock chip connected in sequence;
[0038] The eighth timekeeping path includes a serial port clock source, a serial port, a BMC and a second clock chip connected in sequence;
[0039] The timing path from the OCP card to the serial port includes the seventh timing path and the eighth timing path;
[0040] The seventh timing path includes a second clock chip, a serial port and a serial port clock source connected in sequence;
[0041] The eighth timing path includes a second clock chip, a BMC, a serial port and a serial port clock source which are connected in sequence.
[0042] Furthermore, the external card adopts a self-developed card.
[0043] Furthermore, the clock synchronization path formed by the second clock chip through the server mainboard and the onboard network card clock source includes a timing path from the optical port to the self-developed card and a timing path from the external card to the optical port;
[0044] The timing path from the optical port to the self-developed card includes the ninth timing path and the tenth timing path;
[0045] The ninth timekeeping path includes an onboard network card clock source, an optical port, and a second clock chip connected in sequence;
[0046] The tenth timekeeping path includes the onboard network card clock source, the optical port, the PCH, the CPU, the BMC and the second clock chip connected in sequence;
[0047] The timing paths from the self-developed card to the optical port include the seventh timing path and the eighth timing path;
[0048] The ninth timing path includes a second clock chip, an optical port and an onboard network card clock source connected in sequence;
[0049] The tenth timing path includes a second clock chip and a BMC which are connected in sequence.
[0050] Furthermore, the clock path formed by the second clock chip through the server mainboard and the serial port clock source includes a serial port to self-developed card timing path and a self-developed card to serial port timing path;
[0051] The serial port to self-developed card timing path includes the eleventh timing path and the twelfth timing path;
[0052] The eleventh timekeeping path includes a serial port clock source, a serial port, and a second clock chip connected in sequence;
[0053] The twelfth timekeeping path includes a serial port clock source, a serial port, a BMC and a second clock chip connected in sequence;
[0054] The timing path from the self-developed card to the serial port includes the eleventh timing path and the twelfth timing path;
[0055] The eleventh timing path includes a second clock chip, a serial port and a serial port clock source connected in sequence;
[0056] The twelfth timing path includes a second clock chip, a BMC, a serial port and a serial port clock source which are connected in sequence.
[0057] Furthermore, the serial port clock source adopts an RS422 serial port clock source.
[0058] The beneficial effects of the utility model are:
[0059] The clock synchronization system of the edge server provided by the utility model is compatible with the synchronization of multiple clocks such as PCIe standard cards, OCP cards, self-developed cards, onboard network card clock sources and serial port clock sources, and can be flexibly connected according to needs, reducing the development cost of the clock synchronization system and meeting the high-precision clock synchronization needs of small base stations.
[0060] In addition, the utility model has a reliable design principle, a simple structure and a very broad application prospect.
[0061] It can be seen that compared with the prior art, the utility model has substantial characteristics and progress, and the beneficial effects of its implementation are also obvious. BRIEF DESCRIPTION OF THE DRAWINGS
[0062] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0063] Figure 1 It is a schematic diagram of the clock synchronization path of the onboard network card clock source for connecting the PCIe clock label card with the optical port in the clock synchronization system of the edge server of the utility model.
[0064] Figure 2 It is a schematic diagram of the clock synchronization path of the serial port clock source for connecting the PCIe clock card with the serial port in the clock synchronization system of the edge server of the utility model.
[0065] Figure 3 The utility model is a schematic diagram of the clock synchronization path of the onboard network card clock source for connecting the external card to the optical port of the clock synchronization system of the edge server.
[0066] Figure 4 It is a schematic diagram of the clock synchronization path of the serial port clock source for connecting an external card to the serial port in the clock synchronization system of the edge server of the utility model.
[0067] In the figure, 1-server motherboard; 2-PCIe standard card; 3-external card; 4-CPU; 5-PCH; 6-BMC; 7-serial port; 8-optical port; 9-serial port clock source; 10-onboard network card clock source; 11-first clock chip; 12-second clock chip. DETAILED DESCRIPTION
[0068] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0069] PPS, short for Pulse Per Second, means one pulse per second and is a time synchronization term.
[0070] TOD is the abbreviation of Time of Day, time information, time information sent within the PPS second pulse period.
[0071] Embodiment 1:
[0072] like Figure 1 As shown, the utility model provides a clock synchronization system for an edge server, including a server mainboard 1, a PCIe standard card 2 and an external card 3;
[0073] The server mainboard 1 is provided with a CPU 4, a PCH 5, a BMC 6, a serial port 7 and an optical port 8. The serial port 7 is connected to a serial port clock source 9, and the optical port 8 is connected to an onboard network card clock source 10.
[0074] The PCIe standard card 2 is provided with a first clock chip 11, and the external card 3 is provided with a second clock chip 12;
[0075] The first clock chip 11 forms a clock synchronization path through the server mainboard 1 and the onboard network card clock source 10 or the serial port clock source 9;
[0076] The second clock chip 12 forms a clock synchronization path through the server mainboard 1 and the onboard network card clock source 10 or the serial port clock source 9;
[0077] The clock synchronization path formed by the first clock chip 11 through the server mainboard 1 and the onboard network card clock source 10 includes a timing path from the optical port to the PCIe standard card and a timing path from the PCIe standard card to the optical port;
[0078] The optical port to PCIe standard card timing path includes a first timing path and a second timing path;
[0079] The first timekeeping path includes an onboard network card clock source 10, an optical port 8 and a first clock chip 11 connected in sequence;
[0080] The second timing path includes an onboard network card clock source 10, an optical port 8, a PCH 5, a CPU 4, a BMC 6 and a first clock chip 11 connected in sequence;
[0081] The timing path from the PCIe card to the optical port includes a first timing path and a second timing path;
[0082] The first timing path includes a first clock chip 11, an optical port 8 and an onboard network card clock source 10 connected in sequence;
[0083] The second timing path includes the first clock chip 11 and the BMC 6 connected in sequence;
[0084] It should be noted that in the first punctual path, the onboard network card clock source 10 recovers the second pulse PPS from the PTP protocol clock to the PCIe standard card 2 for clock calibration;
[0085] In the second timekeeping path, the onboard network card clock source 10 receives the TOD message from the PTP protocol clock and transmits it to the CPU 4 through the PCH 5. The application layer software of the CPU 4 interprets the message and sends it to the BMC 6. The BMC 6 transmits the message to the PCIe standard card 3 for calibration.
[0086] In the first timing path, the PCIe card 3 outputs the second pulse PPS to the onboard network card clock source 10;
[0087] In the second timing path, the PCIe card 3 outputs a TOD message to the BMC 6 .
[0088] Embodiment 2:
[0089] like Figure 2 As shown, the utility model provides a clock synchronization system for an edge server, including a server mainboard 1, a PCIe standard card 2 and an external card 3;
[0090] The server mainboard 1 is provided with a CPU 4, a PCH 5, a BMC 6, a serial port 7 and an optical port 8. The serial port 7 is connected to a serial port clock source 9, and the optical port 8 is connected to an onboard network card clock source 10. The serial port clock source 9 adopts an RS422 serial port clock source.
[0091] The PCIe standard card 2 is provided with a first clock chip 11, and the external card 3 is provided with a second clock chip 12;
[0092] The first clock chip 11 forms a clock synchronization path through the server mainboard 1 and the onboard network card clock source 10 or the serial port clock source 9;
[0093] The second clock chip 12 forms a clock synchronization path through the server mainboard 1 and the onboard network card clock source 10 or the serial port clock source 9;
[0094] The clock path formed by the first clock chip 11 through the server mainboard 1 and the serial port clock source 9 includes a serial port to PCIe standard card timing path and a PCIe standard card to serial port timing path;
[0095] The serial port to PCIe standard card timing path includes the third timing path and the fourth timing path;
[0096] The third timekeeping path includes the serial port clock source 9, the serial port 7 and the first clock chip 11 connected in sequence;
[0097] The fourth timekeeping path includes the serial port clock source 9, the serial port 7, the BMC 6 and the first clock chip 11 connected in sequence;
[0098] The timing path from the PCIe card to the serial port includes the third timing path and the fourth timing path;
[0099] The third timing path includes a first clock chip 11, a serial port 7 and a serial port clock source 9 connected in sequence;
[0100] The fourth timing path includes the first clock chip 11, the BMC 6, the serial port 7 and the serial port clock source 9 connected in sequence;
[0101] It should be noted that in the third timing path, the serial port clock source 9 inputs the second pulse PPS via the serial port 7 to the PCIe card 3 for clock calibration;
[0102] In the fourth timekeeping path, the serial port clock source 9 inputs the TOD message through the serial port 7 and sends it to the BMC 6, and the BMC 6 transmits the message to the PCIe standard card 3 for calibration;
[0103] In the third timing path, the PCIe card 3 outputs the second pulse PPS to the serial port clock source 9;
[0104] In the fourth timing path, the PCIe card 3 outputs the TOD message to the BMC 6 and then transmits it back to the serial port clock source 9.
[0105] Embodiment 3:
[0106] like Figure 3 As shown, the utility model provides a clock synchronization system for an edge server, including a server mainboard 1, a PCIe standard card 2 and an external card 3;
[0107] The server mainboard 1 is provided with a CPU 4, a PCH 5, a BMC 6, a serial port 7 and an optical port 8. The serial port 7 is connected to a serial port clock source 9, and the optical port 8 is connected to an onboard network card clock source 10. The serial port clock source 9 adopts an RS422 serial port clock source.
[0108] The PCI e standard card 2 is provided with a first clock chip 11, and the external card 3 is provided with a second clock chip 12;
[0109] The first clock chip 11 forms a clock synchronization path through the server mainboard 1 and the onboard network card clock source 10 or the serial port clock source 9;
[0110] The second clock chip 12 forms a clock synchronization path through the server mainboard 1 and the onboard network card clock source 10 or the serial port clock source 9;
[0111] External card 3 uses OCP card;
[0112] The clock synchronization path formed by the second clock chip 12 through the server mainboard 1 and the onboard network card clock source 10 includes a timing path from the optical port to the OCP card and a timing path from the OCP card to the optical port;
[0113] The optical port to OCP card timing path includes the fifth timing path and the sixth timing path;
[0114] The fifth timekeeping path includes the onboard network card clock source 10, the optical port 8 and the second clock chip 12 connected in sequence;
[0115] The sixth punctual path includes the onboard network card clock source 10, the optical port 8, the PCH 5, the CPU 4, the BMC 6 and the second clock chip 12 connected in sequence;
[0116] The timing path from the OCP card to the optical port includes the fifth timing path and the sixth timing path;
[0117] The fifth timing path includes a second clock chip 12, an optical port 8 and an onboard network card clock source 10 connected in sequence;
[0118] The sixth timing path includes a second clock chip 12 and a BMC 6 connected in sequence;
[0119] It should be noted that in the fifth timekeeping path, the onboard network card clock source 10 recovers the second pulse PPS from the PTP protocol clock to the OCP card for clock calibration;
[0120] In the sixth timekeeping path, the onboard network card clock source 10 receives the TOD message from the PTP protocol clock and transmits it to the CPU 4 through the PCH 5. The application layer software of the CPU 4 interprets the message and sends it to the BMC 6. The BMC 6 transmits the message to the OCP card for calibration.
[0121] In the fifth timing path, the OCP card outputs the second pulse PPS to the onboard network card clock source 10;
[0122] In the sixth timing path, the OCP card outputs the TOD message to BMC 6.
[0123] Embodiment 4:
[0124] like Figure 4 As shown, the utility model provides a clock synchronization system for an edge server, including a server mainboard 1, a PCIe standard card 2 and an external card 3;
[0125] The server mainboard 1 is provided with a CPU 4, a PCH 5, a BMC 6, a serial port 7 and an optical port 8. The serial port 7 is connected to a serial port clock source 9, and the optical port 8 is connected to an onboard network card clock source 10. The serial port clock source 9 adopts an RS422 serial port clock source.
[0126] The PCIe standard card 2 is provided with a first clock chip 11, and the external card 3 is provided with a second clock chip 12;
[0127] The first clock chip 11 forms a clock synchronization path through the server mainboard 1 and the onboard network card clock source 10 or the serial port clock source 9;
[0128] The second clock chip 12 forms a clock synchronization path through the server mainboard 1 and the onboard network card clock source 10 or the serial port clock source 9;
[0129] External card 3 uses OCP card;
[0130] The clock path formed by the second clock chip 12 through the server mainboard 1 and the serial port clock source 9 includes a serial port to OCP card timing path and an OCP card to serial port timing path;
[0131] The serial port to OCP card timing path includes the seventh timing path and the eighth timing path;
[0132] The seventh timekeeping path includes the serial port clock source 9, the serial port 7 and the second clock chip 12 connected in sequence;
[0133] The eighth timekeeping path includes the serial port clock source 9, the serial port 7, the BMC 6 and the second clock chip 12 connected in sequence;
[0134] The timing path from the OCP card to the serial port includes the seventh timing path and the eighth timing path;
[0135] The seventh timing path includes a second clock chip 12, a serial port 7 and a serial port clock source 9 connected in sequence;
[0136] The eighth timing path includes a second clock chip 12, a BMC 6, a serial port 7 and a serial port clock source 9 connected in sequence;
[0137] It should be noted that in the seventh timekeeping path, the serial port clock source 9 inputs the second pulse PPS via the serial port 7 to the OCP card for clock calibration;
[0138] In the eighth timekeeping path, the serial port clock source 9 inputs the TOD message to the BMC 6 via the serial port 7, and the BMC 6 transmits the message to the OCP card for calibration;
[0139] In the seventh timing path, the OCP card outputs the second pulse PPS to the serial port clock source 9;
[0140] In the eighth timing path, the OCP card outputs the TOD message to the BMC 6 and then transmits it back to the serial port clock source 9.
[0141] Embodiment 5:
[0142] like Figure 3 As shown, the utility model provides a clock synchronization system for an edge server, including a server mainboard 1, a PCIe standard card 2 and an external card 3;
[0143] The server mainboard 1 is provided with a CPU 4, a PCH 5, a BMC 6, a serial port 7 and an optical port 8. The serial port 7 is connected to a serial port clock source 9, and the optical port 8 is connected to an onboard network card clock source 10. The serial port clock source 9 adopts an RS422 serial port clock source.
[0144] The PCIe standard card 2 is provided with a first clock chip 11, and the external card 3 is provided with a second clock chip 12;
[0145] The first clock chip 11 forms a clock synchronization path through the server mainboard 1 and the onboard network card clock source 10 or the serial port clock source 9;
[0146] The second clock chip 12 forms a clock synchronization path through the server mainboard 1 and the onboard network card clock source 10 or the serial port clock source 9;
[0147] External card 3 uses a self-developed card;
[0148] The clock synchronization path formed by the second clock chip 12 through the server mainboard 1 and the onboard network card clock source 10 includes a timing path from the optical port to the self-developed card and a timing path from the external card to the optical port;
[0149] The timing path from the optical port to the self-developed card includes the ninth timing path and the tenth timing path;
[0150] The ninth timekeeping path includes the onboard network card clock source 10, the optical port 8 and the second clock chip 12 connected in sequence;
[0151] The tenth timekeeping path includes the onboard network card clock source 10, the optical port 8, the PCH 5, the CPU 4, the BMC 6 and the second clock chip 12 connected in sequence;
[0152] The timing paths from the self-developed card to the optical port include the seventh timing path and the eighth timing path;
[0153] The ninth timing path includes a second clock chip 12, an optical port 8 and an onboard network card clock source 10 connected in sequence;
[0154] The tenth timing path includes a second clock chip 12 and a BMC 6 connected in sequence;
[0155] It should be noted that in the ninth timekeeping path, the onboard network card clock source 10 recovers the second pulse PPS from the PTP protocol clock to the self-developed card for clock calibration;
[0156] In the tenth timekeeping path, the onboard network card clock source 10 receives the TOD message from the PTP protocol clock and transmits it to the CPU 4 through the PCH5. The application layer software of the CPU 4 interprets the message and sends it to the BMC 6. The BMC 6 transmits the message to the self-developed card for calibration.
[0157] In the ninth timing path, the self-developed card outputs the second pulse PPS to the onboard network card clock source 10;
[0158] In the tenth timing path, the self-developed card outputs the TOD message to BMC 6.
[0159] Embodiment 6:
[0160] like Figure 4 As shown, the utility model provides a clock synchronization system for an edge server, including a server mainboard 1, a PCIe standard card 2 and an external card 3;
[0161] The server mainboard 1 is provided with a CPU 4, a PCH 5, a BMC 6, a serial port 7 and an optical port 8. The serial port 7 is connected to a serial port clock source 9, and the optical port 8 is connected to an onboard network card clock source 10. The serial port clock source 9 adopts an RS422 serial port clock source.
[0162] The PCI e standard card 2 is provided with a first clock chip 11, and the external card 3 is provided with a second clock chip 12;
[0163] The first clock chip 11 forms a clock synchronization path through the server mainboard 1 and the onboard network card clock source 10 or the serial port clock source 9;
[0164] The second clock chip 12 forms a clock synchronization path through the server mainboard 1 and the onboard network card clock source 10 or the serial port clock source 9;
[0165] External card 3 uses a self-developed card;
[0166] The clock path formed by the second clock chip 12 through the server mainboard 1 and the serial port clock source 9 includes a serial port to self-developed card timing path and a self-developed card to serial port timing path;
[0167] The serial port to self-developed card timing path includes the eleventh timing path and the twelfth timing path;
[0168] The eleventh timekeeping path includes the serial port clock source 9, the serial port 7 and the second clock chip 12 connected in sequence;
[0169] The twelfth timekeeping path includes the serial port clock source 9, the serial port 7, the BMC 6 and the second clock chip 12 connected in sequence;
[0170] The timing path from the self-developed card to the serial port includes the eleventh timing path and the twelfth timing path;
[0171] The eleventh timing path includes a second clock chip 12, a serial port 7 and a serial port clock source 9 connected in sequence;
[0172] The twelfth timing path includes a second clock chip 12, a BMC 6, a serial port 7 and a serial port clock source 9 connected in sequence;
[0173] It should be noted that in the eleventh timekeeping path, the serial port clock source 9 inputs the second pulse PPS through the serial port 7 to the self-developed clock card for clock calibration;
[0174] In the twelfth timekeeping path, the serial port clock source 9 inputs the TOD message to the BMC 6 via the serial port 7, and the BMC 6 transmits the message to the self-developed clock card for calibration;
[0175] In the eleventh timing path, the self-developed clock card outputs the second pulse PPS to the serial port clock source 9;
[0176] In the twelfth timing path, the self-developed clock card outputs the TOD message to the BMC 6 and then transmits it back to the serial port clock source 9.
[0177] Although the utility model is described in detail by referring to the accompanying drawings and in combination with the preferred embodiments, the utility model is not limited thereto. Without departing from the spirit and essence of the utility model, a person of ordinary skill in the art may make various equivalent modifications or substitutions to the embodiments of the utility model, and these modifications or substitutions shall be within the scope of the utility model / any person of ordinary skill in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the utility model, and they shall be within the scope of protection of the utility model. Therefore, the scope of protection of the utility model shall be based on the scope of protection of the claims.
Claims
1. A clock synchronization system for an edge server, characterized in that: Including server motherboard, PCIe standard card and external card; The server motherboard is equipped with CPU, PCH, BMC, serial port and optical port. The serial port is connected to the serial port clock source, and the optical port is connected to the onboard network card clock source. The PCIe standard card is provided with a first clock chip, and the external card is provided with a second clock chip; The first clock chip forms a clock synchronization path through the server mainboard and the onboard network card clock source or the serial port clock source; The second clock chip forms a clock synchronization path through the server mainboard and the onboard network card clock source or the serial port clock source.
2. The clock synchronization system of the edge server as claimed in claim 1, characterized in that: The clock synchronization path formed by the first clock chip through the server mainboard and the onboard network card clock source includes a timing path from the optical port to the PCIe standard card and a timing path from the PCIe standard card to the optical port; The optical port to PCIe standard card timing path includes a first timing path and a second timing path; The first timekeeping path includes an onboard network card clock source, an optical port, and a first clock chip connected in sequence; The second punctuality path includes the onboard network card clock source, the optical port, the PCH, the CPU, the BMC and the first clock chip connected in sequence; The timing path from the PCIe card to the optical port includes a first timing path and a second timing path; The first timing path includes a first clock chip, an optical port and an onboard network card clock source connected in sequence; The second timing path includes a first clock chip and a BMC connected in sequence.
3. The clock synchronization system of the edge server as claimed in claim 1, characterized in that: The clock path formed by the first clock chip through the server mainboard and the serial port clock source includes a serial port to PCIe standard card timing path and a PCIe standard card to serial port timing path; The serial port to PCIe standard card timing path includes the third timing path and the fourth timing path; The third timekeeping path includes a serial port clock source, a serial port, and a first clock chip connected in sequence; The fourth timekeeping path includes a serial port clock source, a serial port, a BMC and a first clock chip connected in sequence; The timing path from the PCIe card to the serial port includes the third timing path and the fourth timing path; The third timing path includes a first clock chip, a serial port, and a serial port clock source connected in sequence; The fourth timing path includes a first clock chip, a BMC, a serial port and a serial port clock source which are connected in sequence.
4. The clock synchronization system of the edge server as claimed in claim 1, characterized in that: The external card uses an OCP card.
5. The clock synchronization system of the edge server as claimed in claim 4, characterized in that: The clock synchronization path formed by the second clock chip through the server mainboard and the onboard network card clock source includes the optical port to OCP card timing path and the OCP card to optical port timing path; The optical port to OCP card timing path includes the fifth timing path and the sixth timing path; The fifth timekeeping path includes an onboard network card clock source, an optical port, and a second clock chip connected in sequence; The sixth punctual path includes an onboard network card clock source, an optical port, a PCH, a CPU, a BMC and a second clock chip connected in sequence; The timing path from the OCP card to the optical port includes the fifth timing path and the sixth timing path; The fifth timing path includes a second clock chip, an optical port and an onboard network card clock source connected in sequence; The sixth timing path includes a second clock chip and a BMC which are connected in sequence.
6. The clock synchronization system of the edge server as claimed in claim 4, characterized in that: The clock path formed by the second clock chip through the server mainboard and the serial port clock source includes a serial port to OCP card timing path and an OCP card to serial port timing path; The serial port to OCP card timing path includes the seventh timing path and the eighth timing path; The seventh timekeeping path includes a serial port clock source, a serial port and a second clock chip connected in sequence; The eighth timekeeping path includes a serial port clock source, a serial port, a BMC and a second clock chip connected in sequence; The timing path from the OCP card to the serial port includes the seventh timing path and the eighth timing path; The seventh timing path includes a second clock chip, a serial port and a serial port clock source connected in sequence; The eighth timing path includes a second clock chip, a BMC, a serial port and a serial port clock source which are connected in sequence.
7. The clock synchronization system of the edge server as claimed in claim 1, characterized in that: The external card is a self-developed card.
8. The clock synchronization system of the edge server as claimed in claim 7, characterized in that: The clock synchronization path formed by the second clock chip through the server motherboard and the onboard network card clock source includes the optical port to the self-developed card timing path and the external card to the optical port timing path; The timing path from the optical port to the self-developed card includes the ninth timing path and the tenth timing path; The ninth timekeeping path includes an onboard network card clock source, an optical port, and a second clock chip connected in sequence; The tenth timekeeping path includes the onboard network card clock source, the optical port, the PCH, the CPU, the BMC and the second clock chip connected in sequence; The timing paths from the self-developed card to the optical port include the seventh timing path and the eighth timing path; The ninth timing path includes a second clock chip, an optical port and an onboard network card clock source connected in sequence; The tenth timing path includes a second clock chip and a BMC which are connected in sequence.
9. The clock synchronization system of the edge server as claimed in claim 7, characterized in that: The clock path formed by the second clock chip through the server mainboard and the serial port clock source includes a serial port to self-developed card timing path and a self-developed card to serial port timing path; The serial port to self-developed card timing path includes the eleventh timing path and the twelfth timing path; The eleventh timekeeping path includes a serial port clock source, a serial port, and a second clock chip connected in sequence; The twelfth timekeeping path includes a serial port clock source, a serial port, a BMC and a second clock chip connected in sequence; The timing path from the self-developed card to the serial port includes the eleventh timing path and the twelfth timing path; The eleventh timing path includes a second clock chip, a serial port and a serial port clock source connected in sequence; The twelfth timing path includes a second clock chip, a BMC, a serial port and a serial port clock source which are connected in sequence.
10. The clock synchronization system of the edge server according to claim 1, characterized in that: The serial port clock source uses the RS422 serial port clock source.