Bias current source circuit and circuit board
By designing a bias current source circuit containing multiple current mirrors and electronic switches, the problem of leakage current of the current source at high power supply voltage is solved, and a wider operating voltage range and stable bias current are achieved.
Patent Information
- Application Number
- CN202420286552.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-06
- Publication Date
- 2025-02-07
- Estimated Expiration
- 2034-02-06
AI Technical Summary
When the current source is started, if the power supply voltage is too large, leakage current will occur, limiting the operating range of VDD.
A bias current source circuit is designed, through a combination of a first current mirror, a second current mirror, a third current mirror, a current copy unit, a voltage pull-up unit, a voltage pull-down unit, a first electronic switch and a second electronic switch , control the gate voltage of the PMOS tube and NMOS tube to ensure that no leakage current is generated under high power supply voltage.
It effectively avoids the problem of leakage current at high power supply voltage, expands the working range of the power supply voltage VDD, and maintains the stability of the bias current in the range of 1.6V to 3.5V.
Smart Images
Figure CN222439879U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of current sources, in particular to a bias current source circuit and a circuit board. Background Art
[0002] As a key circuit unit of analog integrated circuits, current sources are widely used in operational amplifiers, A / D converters and D / A converters to provide high-precision, low-temperature drift reference currents for these circuits.
[0003] When designing a bias circuit that is independent of the power supply, the circuit designer needs to consider the existence of "degenerate points". When the electrical relationship equations of the circuit are established according to KCL / KVL, there may be at least two solutions that satisfy the equations, that is, there are at least two operating points. For some operating points, when disturbances occur, such as various noises in the actual circuit, the various components in the circuit may deviate slightly from the original operating point, but as time goes by, the circuit will automatically return to stability. The operating points that meet these conditions are called stable solutions; and for some operating points, when any disturbance occurs, the circuit will deviate from this operating point and transition to another operating point. Such operating points are called unstable solutions. If a circuit has more than two stable solutions, but usually only one of them is the target operating point, and the other solutions are not what we need, then a startup circuit should be added to make the new set of equations have only one stable solution.
[0004] Existing bias circuits such as Figure 1 As shown in the figure, the circuit has two degenerate points, one is normal operation, and the other is that the current of all MOS tubes is zero, and the gate potential of MOS tube M3 is high. Therefore, a startup circuit is needed to pull down the gate potential of MOS tube M3 so that the circuit can work normally. Figure 2 In the embodiment, a diode-connected MOS tube M5 is provided, so that when VDD is powered on, a current path from VDD to MOS tube M3 to MOS tube M5 to MOS tube M1 and then to ground is provided, so MOS tube M3 and MOS tube M1 will not be turned off, and thus MOS tube M2 and MOS tube M4 will not be turned off.
[0005] However, in actual use, there are prerequisite conditions for this startup method. VDD must meet the following two conditions: Condition 1: VTH1 + VTH5 + |VTH3| < VDD, where VTH1, VTH3, and VTH5 are the threshold voltages of MOS transistors M1, M3, and M5 respectively. Condition 2: VDD - VGS1 - |VGS3| < VTH5, where VGS1 and VGS3 are the gate-source voltages of MOS transistors M1 and M3 after the circuit starts up, that is, the VDD voltage should be less than the sum of the gate-source voltages of MOS transistors M1 and M3 and the threshold voltage of MOS transistor M5. Among them, Condition 1 is to ensure that MOS transistor M5 can conduct after VDD is powered on, and Condition 2 is to ensure that MOS transistor M5 can remain off after the circuit starts up and reaches a stable state. From the above two conditions, it can be obtained that when VDD is relatively large in the existing startup circuit, MOS transistor M5 is very likely to be unable to turn off, resulting in leakage current in MOS transistor M5. Additionally, from Figure 2 the shown simulation diagram, it can be obtained that when VDD = 1.6V, there is a leakage current of 131nA in MOS transistor M5. Therefore, the operating range of VDD of the traditional current source startup circuit is very limited. Summary of the Invention
[0006] In view of the deficiencies of the background technology, the present invention provides a bias current source circuit and a circuit board. The technical problem to be solved is that when the power supply voltage is too large during the startup of the current source, there will be a situation of generating leakage current.
[0007] To solve the above technical problems, in the first aspect, the present invention provides the following technical solution: A bias current source circuit includes a first current mirror based on PMOS transistors, a second current mirror based on NMOS transistors, a third current mirror based on NMOS transistors, a current replication unit, a voltage pull-up unit, a voltage pull-down unit, a first electronic switch, and a second electronic switch;
[0008] Two current output terminals of the first current mirror are electrically connected to two current input terminals of the second current mirror. Two current output terminals of the second current mirror are electrically connected to two current input terminals of the third current mirror. Two current output terminals of the third current mirror are grounded. The current replication unit is electrically connected to the first current mirror, replicates the current generated by the first current mirror, and outputs a bias current;
[0009] The gate of the PMOS transistor of the first current mirror is electrically connected to the gate of the NMOS transistor of the second current mirror through the first electronic switch, and the gate of the PMOS transistor of the first current mirror is also electrically connected to the gate of the NMOS transistor of the third current mirror through the second electronic switch;
[0010] The voltage pull-up unit is electrically connected to the control end of the first electronic switch and the control end of the second electronic switch, respectively, and is used to output a pull-up voltage for driving the first electronic switch and the second electronic switch to conduct when powered on;
[0011] The voltage pull-down unit is electrically connected to the gate of the NMOS tube of the third current mirror, and pulls down the voltage of the voltage output end of the voltage pull-up unit based on the gate voltage of the NMOS tube of the third current mirror, so that the first electronic switch and the second electronic switch are turned off.
[0012] In a certain implementation manner of the first aspect, the first current mirror includes a PMOS tube P1 and a PMOS tube P2, the source of the PMOS tube P1 is electrically connected to the source of the PMOS tube P2, and is used to access the working voltage VDD; the gate of the PMOS tube P1 is electrically connected to the gate of the PMOS tube P2 and the drain of the PMOS tube P2, respectively, and the drain of the PMOS tube P1 and the drain of the PMOS tube P2 are two current output terminals of the first current mirror;
[0013] The current copy unit is used to copy the current flowing through the PMOS tube P2.
[0014] In a certain embodiment of the first aspect, the current replication unit includes a PMOS tube P4, a source of the PMOS tube P4 is electrically connected to a source of the PMOS tube P2, a gate of the PMOS tube P4 is electrically connected to a gate of the PMOS tube P2, and a drain of the PMOS tube P4 is used to output a bias current.
[0015] In a certain embodiment of the first aspect, the second current mirror includes an NMOS tube N6 and an NMOS tube N7, the drain of the NMOS tube N6 is electrically connected to the drain of the PMOS tube P1, the gate of the NMOS tube N6 and the gate of the NMOS tube N7 respectively, the drain of the NMOS tube N7 is electrically connected to the drain of the PMOS tube P2, and the source of the NMOS tube N6 and the source of the NMOS tube N7 are two current output ends of the second current mirror.
[0016] In a certain embodiment of the first aspect, the first electronic switch is an NMOS tube N2, the gate of the PMOS tube P2 is electrically connected to the drain of the NMOS tube N2, the source of the NMOS tube N2 is electrically connected to the gate of the NMOS tube N6, and the gate of the NMOS tube N2 is the control end of the first electronic switch.
[0017] In a certain embodiment of the first aspect, the third current mirror includes an NMOS tube N8 and an NMOS tube N9, the drain of the NMOS tube N8 is electrically connected to the source of the NMOS tube N6, the gate of the NMOS tube N8 and the gate of the NMOS tube N9 respectively, the drain of the NMOS tube N9 is electrically connected to the source of the NMOS tube N7, the source of the NMOS tube N8 and the source of the NMOS tube N9 are two current output ends of the third current mirror; wherein the source of the NMOS tube N9 is grounded through the resistor R2.
[0018] In a certain embodiment of the first aspect, the second electronic switch is an NMOS tube N3, the drain of the NMOS tube N3 is electrically connected to the gate of the PMOS tube P2, the source of the NMOS tube N3 is electrically connected to the gate of the NMOS tube N9, and the gate of the NMOS tube N3 is the control end of the second electronic switch.
[0019] In a certain embodiment of the first aspect, the voltage pull-up unit includes a resistor R1, a PMOS tube P3 and an NMOS tube N1, one end of the resistor R1 is used to input the working voltage VDD, the other end of the resistor R1 is electrically connected to the source of the PMOS tube P3, the gate of the PMOS tube P3 is electrically connected to the drain of the PMOS tube P3, the drain of the NMOS tube N1, the gate of the NMOS tube N1, the control end of the first electronic switch and the control end of the second electronic switch, and the source of the NMOS tube N1 is electrically connected to the voltage pull-down unit.
[0020] In a certain embodiment of the first aspect, the voltage pull-down unit includes an NMOS tube N4 and an NMOS tube N5; the gate of the NMOS tube N5 is electrically connected to the gate of the NMOS tube of the third current mirror, the source of the NMOS tube N5 is electrically connected to the source of the NMOS tube N4, and the drain of the NMOS tube N5 is electrically connected to the gate of the NMOS tube N4, the drain of the NMOS tube N4 and the source of the NMOS tube N1 respectively.
[0021] The second utility model provides a circuit board, on which the above-mentioned bias current source circuit is arranged.
[0022] Compared with the prior art, the utility model has the following beneficial effects: the bias current source circuit of the utility model electrically connects the gate of the PMOS tube of the first current mirror with the gate of the NMOS tube of the second current mirror and the gate of the PMOS tube of the first current mirror with the gate of the NMOS tube of the third current mirror through the first electronic switch and the second electronic switch respectively, so that when powered on, the voltage pull-up unit drives the first electronic switch and the second electronic switch to be turned on, so that the first to third current mirrors generate current, and as the generated current becomes larger and larger, the gate voltage of the NMOS tube of the third current mirror becomes larger, and the voltage pull-down unit pulls down the output voltage of the voltage pull-up unit based on the increasing gate voltage of the NMOS tube of the third current mirror, so that the first electronic switch and the second electronic switch are turned off, so that there is no need to worry about leakage current caused by excessive power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 is a circuit diagram of an existing current source;
[0024] Figure 2 for Figure 1 Simulation schematic diagram of the circuit;
[0025] Figure 3 is a circuit diagram of a bias current source circuit of Embodiment 1;
[0026] Figure 4 for Figure 3 Simulation diagram of the circuit. DETAILED DESCRIPTION
[0027] Now the utility model is further described in detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the utility model in a schematic manner, and therefore only show the components related to the utility model.
[0028] Embodiment 1
[0029] like Figure 3 As shown, a bias current source circuit includes a first current mirror 1 based on a PMOS tube, a second current mirror 2 based on an NMOS tube, a third current mirror 3 based on an NMOS tube, a current copy unit 8, a voltage pull-up unit 6, a voltage pull-down unit 7, a first electronic switch 4 and a second electronic switch 5;
[0030] Two input terminals of the first current mirror 1 are used to access the working voltage VDD, two current output terminals of the first current mirror 1 are electrically connected to two current input terminals of the second current mirror 2, two current output terminals of the second current mirror 2 are electrically connected to two current input terminals of the third current mirror 3, and two current output terminals of the third current mirror 3 are grounded; the current copy unit 8 is electrically connected to the first current mirror 1, copies the current generated by the first current mirror 1 and outputs the bias current Ibias;
[0031] In actual use, the current used for copying by the current copying unit 8 is generated by the first current mirror 1, the second current mirror 2 and the third current mirror 3;
[0032] The gate of the PMOS tube of the first current mirror 1 is electrically connected to the gate of the NMOS tube of the second current mirror 2 through the first electronic switch 4, and the gate of the PMOS tube of the first current mirror 1 is also electrically connected to the gate of the NMOS tube of the third current mirror 3 through the second electronic switch 5; in actual use, the gate voltage of the PMOS tube of the first current mirror 1 can be pulled down through the first electronic switch 4 and the second electronic switch 5, so that the PMOS tube is turned on to generate current;
[0033] The voltage pull-up unit 6 is electrically connected to the control end of the first electronic switch 4 and the control end of the second electronic switch 5, respectively, and is used to output a pull-up voltage to drive the first electronic switch 4 and the second electronic switch 5 to conduct when powered on;
[0034] The voltage pull-down unit 7 is electrically connected to the gate of the NMOS tube of the third current mirror 3 , and pulls down the voltage of the voltage output end of the voltage pull-up unit 6 based on the gate voltage of the NMOS tube of the third current mirror 3 , so that the first electronic switch 4 and the second electronic switch 5 are turned off.
[0035] Specifically, in Figure 3 In the embodiment, the first current mirror 1 includes a PMOS tube P1 and a PMOS tube P2, the source of the PMOS tube P1 is electrically connected to the source of the PMOS tube P2, and is used to access the working voltage VDD; the gate of the PMOS tube P1 is electrically connected to the gate of the PMOS tube P2 and the drain of the PMOS tube P2, respectively, and the drain of the PMOS tube P1 and the drain of the PMOS tube P2 are two current output terminals of the first current mirror 1.
[0036] Specifically, the current copy unit 8 is used to copy the current flowing through the PMOS tube P2, wherein the current copy unit 8 includes a PMOS tube P4, the source of the PMOS tube P4 is electrically connected to the source of the PMOS tube P2, the gate of the PMOS tube P4 is electrically connected to the gate of the PMOS tube P2, and the drain of the PMOS tube P4 is used to output the bias current Ibias;
[0037] The PMOS transistor P2 and the PMOS transistor P4 form a current mirror structure. In actual use, the current replication ratio of the current replication unit 8 is adjusted by adjusting the ratio of the width-to-length ratio of the PMOS transistor P4 to the width-to-length ratio of the PMOS transistor P2.
[0038] exist Figure 3In the embodiment, the second current mirror 2 includes an NMOS tube N6 and an NMOS tube N7, the drain of the NMOS tube N6 is electrically connected to the drain of the PMOS tube P1, the gate of the NMOS tube N6 and the gate of the NMOS tube N7 respectively, the drain of the NMOS tube N7 is electrically connected to the drain of the PMOS tube P2, and the source of the NMOS tube N6 and the source of the NMOS tube N7 are two current output terminals of the second current mirror.
[0039] exist Figure 3 In the embodiment, the first electronic switch 4 is an NMOS tube N2, the gate of the PMOS tube P2 is electrically connected to the drain of the NMOS tube N2, the source of the NMOS tube N2 is electrically connected to the gate of the NMOS tube N6, and the gate of the NMOS tube N2 is the control end of the first electronic switch.
[0040] exist Figure 3 In the embodiment, the third current mirror 3 includes an NMOS tube N8 and an NMOS tube N9, the drain of the NMOS tube N8 is electrically connected to the source of the NMOS tube N6, the gate of the NMOS tube N8 and the gate of the NMOS tube N9 respectively, the drain of the NMOS tube N9 is electrically connected to the source of the NMOS tube N7, the source of the NMOS tube N8 and the source of the NMOS tube N9 are two current output terminals of the third current mirror 3; wherein the source of the NMOS tube N9 is grounded through the resistor R2.
[0041] exist Figure 3 In the embodiment, the second electronic switch 5 is an NMOS tube N3, the drain of the NMOS tube N3 is electrically connected to the gate of the PMOS tube P2, the source of the NMOS tube N3 is electrically connected to the gate of the NMOS tube N9, and the gate of the NMOS tube N3 is the control end of the second electronic switch 5.
[0042] exist Figure 3 In the figure, the voltage pull-up unit 6 includes a resistor R1, a PMOS tube P3 and an NMOS tube N1. One end of the resistor R1 is used to input the working voltage VDD, and the other end of the resistor R1 is electrically connected to the source of the PMOS tube P3. The gate of the PMOS tube P3 is respectively electrically connected to the drain of the PMOS tube P3, the drain of the NMOS tube N1, the gate of the NMOS tube N1, the control end of the first electronic switch 4 and the control end of the second electronic switch 5, and the source of the NMOS tube N1 is electrically connected to the voltage pull-down unit 7.
[0043] exist Figure 3 In the embodiment, the voltage pull-down unit 7 includes an NMOS tube N4 and an NMOS tube N5; the gate of the NMOS tube N5 is electrically connected to the gate of the NMOS tube of the third current mirror 3, the source of the NMOS tube N5 is electrically connected to the source of the NMOS tube N4, and the drain of the NMOS tube N5 is electrically connected to the gate of the NMOS tube N4, the drain of the NMOS tube N4 and the source of the NMOS tube N1 respectively.
[0044] right Figure 3 The circuit is analyzed as follows: When the working VDD is powered on, if the current source circuit is in a zero-current state, the gate voltage of PMOS transistor P1 is at a high potential, turning off PMOS transistor P1 and PMOS transistor P2. At this time, the working voltage VDD pulls up the gate of NMOS transistor N1 in the voltage boosting unit 6 to generate a bias voltage, which acts on the gates of NMOS transistor N2 and NMOS transistor N3 simultaneously, turning on NMOS transistor N2 and NMOS transistor N3. At this time, NMOS transistor N2 and NMOS transistor N3 will generate current, pulling down the gate voltage of PMOS transistor P1, and then gradually generating current in PMOS transistor P1 and PMOS transistor P2;
[0045] Then, through the positive feedback effect of the current source circuit itself, a larger start-up current is generated. At this time, the gate voltages of NMOS transistor N6 and NMOS transistor N8 also gradually increase. When the current source circuit is fully established and working in a stable state, the gate voltage of NMOS transistor N8 turns on NMOS transistor N5, and then pulls down the gate voltage of NMOS transistor N4. Also, because NMOS transistor N1 is connected in diode configuration, the gate voltage of NMOS transistor N1 is also pulled down, that is, the gate voltages of NMOS transistor N2 and NMOS transistor N3 become lower, making VGS2 < VTH2 and VGS3 < VTH3, and finally turning off NMOS transistor N2 and NMOS transistor N3. Therefore, NMOS transistor N2 and NMOS transistor N3 in the present invention serve as both current-conducting control devices and sensing devices for sensing and judging shutdown.
[0046] For Figure 3 the circuit, a simulation is carried out. The simulation schematic diagram is as Figure 4 shown. It can be obtained from Figure 4 that when the working voltage VDD ranges from 1.6 to 3.5V, there is basically no leakage current in NMOS transistor N2 and NMOS transistor N3, and the bias current is stable at about 300 nA. From this simulation result, it can be known that the current source circuit of the present invention can be normally started when the working voltage is between 1.6V and 3.5V, and NMOS transistor N2 and NMOS transistor N3 can be normally turned off after the circuit reaches a stable state, increasing the range of the working voltage VDD.
[0047] Embodiment 2
[0048] This embodiment provides a circuit board, on which a bias current source circuit in Embodiment 1 is provided.
[0049] The above is based on the disclosure of the utility model. Through the above description, relevant staff can make various changes and modifications without deviating from the technical concept of the utility model. The technical scope of the utility model is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.
Claims
1. A bias current source circuit, characterized in that: It includes a first current mirror based on a PMOS tube, a second current mirror based on an NMOS tube, a third current mirror based on an NMOS tube, a current copy unit, a voltage pull-up unit, a voltage pull-down unit, a first electronic switch, and a second electronic switch; The two current output terminals of the first current mirror are electrically connected to the two current input terminals of the second current mirror, the two current output terminals of the second current mirror are electrically connected to the two current input terminals of the third current mirror, and the two current output terminals of the third current mirror are grounded; the current copying unit is electrically connected to the first current mirror, copies the current generated by the first current mirror and outputs a bias current; The gate of the PMOS tube of the first current mirror is electrically connected to the gate of the NMOS tube of the second current mirror through the first electronic switch, and the gate of the PMOS tube of the first current mirror is also electrically connected to the gate of the NMOS tube of the third current mirror through the second electronic switch; The voltage pull-up unit is electrically connected to the control end of the first electronic switch and the control end of the second electronic switch, respectively, and is used to output a pull-up voltage for driving the first electronic switch and the second electronic switch to conduct when powered on; The voltage pull-down unit is electrically connected to the gate of the NMOS tube of the third current mirror, and pulls down the voltage of the voltage output end of the voltage pull-up unit based on the gate voltage of the NMOS tube of the third current mirror, so that the first electronic switch and the second electronic switch are turned off.
2. A bias current source circuit according to claim 1, characterized in that: The first current mirror includes a PMOS tube P1 and a PMOS tube P2, wherein the source of the PMOS tube P1 is electrically connected to the source of the PMOS tube P2 for accessing the working voltage VDD; the gate of the PMOS tube P1 is electrically connected to the gate of the PMOS tube P2 and the drain of the PMOS tube P2 respectively, and the drain of the PMOS tube P1 and the drain of the PMOS tube P2 are two current output terminals of the first current mirror; The current copy unit is used to copy the current flowing through the PMOS tube P2.
3. A bias current source circuit according to claim 2, characterized in that: The current copy unit includes a PMOS tube P4, a source of the PMOS tube P4 is electrically connected to a source of the PMOS tube P2, a gate of the PMOS tube P4 is electrically connected to a gate of the PMOS tube P2, and a drain of the PMOS tube P4 is used to output a bias current.
4. The bias current source circuit according to claim 2, characterized in that: The second current mirror includes an NMOS tube N6 and an NMOS tube N7. The drain of the NMOS tube N6 is electrically connected to the drain of the PMOS tube P1, the gate of the NMOS tube N6 and the gate of the NMOS tube N7 respectively. The drain of the NMOS tube N7 is electrically connected to the drain of the PMOS tube P2. The source of the NMOS tube N6 and the source of the NMOS tube N7 are two current output terminals of the second current mirror.
5. A bias current source circuit according to claim 4, characterized in that: The first electronic switch is an NMOS tube N2, the gate of the PMOS tube P2 is electrically connected to the drain of the NMOS tube N2, the source of the NMOS tube N2 is electrically connected to the gate of the NMOS tube N6, and the gate of the NMOS tube N2 is the control end of the first electronic switch.
6. The bias current source circuit according to claim 4, characterized in that: The third current mirror includes an NMOS tube N8 and an NMOS tube N9, wherein the drain of the NMOS tube N8 is electrically connected to the source of the NMOS tube N6, the gate of the NMOS tube N8 and the gate of the NMOS tube N9 respectively, the drain of the NMOS tube N9 is electrically connected to the source of the NMOS tube N7, and the source of the NMOS tube N8 and the source of the NMOS tube N9 are two current output terminals of the third current mirror; wherein the source of the NMOS tube N9 is grounded through the resistor R2.
7. The bias current source circuit according to claim 6, characterized in that: The second electronic switch is an NMOS tube N3, the drain of the NMOS tube N3 is electrically connected to the gate of the PMOS tube P2, the source of the NMOS tube N3 is electrically connected to the gate of the NMOS tube N9, and the gate of the NMOS tube N3 is the control end of the second electronic switch.
8. A bias current source circuit according to any one of claims 1 to 7, characterized in that: The voltage pull-up unit includes a resistor R1, a PMOS tube P3 and an NMOS tube N1. One end of the resistor R1 is used to input the working voltage VDD, and the other end of the resistor R1 is electrically connected to the source of the PMOS tube P3. The gate of the PMOS tube P3 is electrically connected to the drain of the PMOS tube P3, the drain of the NMOS tube N1, the gate of the NMOS tube N1, the control end of the first electronic switch and the control end of the second electronic switch respectively. The source of the NMOS tube N1 is electrically connected to the voltage pull-down unit.
9. The bias current source circuit according to claim 8, characterized in that: The voltage pull-down unit includes an NMOS tube N4 and an NMOS tube N5; the gate of the NMOS tube N5 is electrically connected to the gate of the NMOS tube of the third current mirror, the source of the NMOS tube N5 is electrically connected to the source of the NMOS tube N4, and the drain of the NMOS tube N5 is electrically connected to the gate of the NMOS tube N4, the drain of the NMOS tube N4 and the source of the NMOS tube N1 respectively.
10. A circuit board, characterized in that: The circuit board is provided with a bias current source circuit as described in any one of claims 1-9.