Synchronous rectification circuit capable of being applied to positive end and negative end

Abstract

A first chip ground GND, a second chip ground GND and a third chip ground GND of the synchronous rectification circuit are connected in parallel and then are connected with an inductor, the inductor is connected with an output voltage cathode VO-, and a chip power supply VDD is connected with the third chip GND through a first capacitor C1. A first chip high-voltage power supply and signal detection pin D, a second chip high-voltage power supply and signal detection pin D, a third chip high-voltage power supply and signal detection pin D and a fourth chip high-voltage power supply and signal detection pin D are connected in parallel and then connected to an output voltage positive electrode VO +, and a second capacitor C2 and a resistor R are connected between the output voltage positive electrode VO + and an output voltage negative electrode VO-in parallel. The phenomenon that the driving chip is switched on by mistake due to excitation oscillation can be avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of lithium battery charging, in particular to a synchronous rectification circuit applicable to both positive and negative ends. Background Art

[0002] In traditional secondary rectification circuits, output rectification devices mostly use Schottky diodes. However, as the power continues to increase, the loss of Schottky diodes also continues to increase, seriously restricting the improvement of system efficiency. Since power MOSFET has the characteristics of low on-resistance and mature technology, using MOSFET synchronous rectification instead of Schottky diodes in secondary rectification circuits has become an effective means to improve system efficiency.

[0003] However, in the synchronous rectification circuit that drives the power MOSFET, since the synchronous circuit is a passive working mode, it is necessary to accurately control the opening and closing of the power MOSFET. However, in actual system applications, the passive working mode of the synchronous circuit causes the shutdown of the synchronous MOSFET to always lag behind the conduction of the primary switch, so it is inevitable that the secondary synchronous MOSFET will be short-term collapsed, resulting in a very high voltage overshoot in the drain-source voltage Vds of the synchronous MOSFET, which leads to the phenomenon of incorrect opening of the driver chip due to excitation oscillation, and is not compatible with a variety of switching power supply control systems. Utility Model Content

[0004] The technical problem to be solved by the utility model is to provide a synchronous rectification circuit which can be applied to both positive and negative ends, in view of the shortcomings of the existing synchronous rectification chip, such as the driver chip being mistakenly turned on due to the excitation oscillation and being incompatible with a variety of switch power supply control systems.

[0005] The technical solution adopted by the utility model to solve the above technical problems is as follows:

[0006] Provided is a synchronous rectification circuit applicable to both positive and negative ends, comprising a synchronous rectification chip, wherein the synchronous rectification chip comprises a first chip ground GND, a second chip ground GND, a third chip ground GND, a first chip high-voltage power supply and signal detection pin D, a second chip high-voltage power supply and signal detection pin D, a third chip high-voltage power supply and signal detection pin D, a fourth chip high-voltage power supply and signal detection pin D and a chip power supply VDD, wherein the first chip ground GND, the second chip ground GND and the third chip ground GND are connected in parallel to an inductor, and the inductor is connected to an output voltage negative electrode VO-, the fourth chip VDD is connected to the third chip GND through a first capacitor C1, the first chip high-voltage power supply and signal detection pin D, the second chip high-voltage power supply and signal detection pin D, the third chip high-voltage power supply and signal detection pin D and the fourth chip high-voltage power supply and signal detection pin D are connected in parallel to an output voltage positive electrode VO+, and a second capacitor C2 and a resistor R are connected in parallel between the output voltage positive electrode VO+ and the output voltage negative electrode VO-.

[0007] Furthermore, the first chip ground GND, the second chip ground GND and the third chip ground GND are respectively connected to the source of the synchronous rectifier tube built in the synchronous rectifier chip.

[0008] Furthermore, the high-voltage power supply and signal detection pin D of the first chip, the high-voltage power supply and signal detection pin D of the second chip, the high-voltage power supply and signal detection pin D of the third chip, and the high-voltage power supply and signal detection pin D of the fourth chip are respectively connected to the drain of the synchronous rectifier tube built into the synchronous rectifier chip.

[0009] Furthermore, the chip power supply VCC voltage is between -0.3V and 7V.

[0010] Furthermore, the voltages of the first chip high voltage power supply and signal detection pin D, the second chip high voltage power supply and signal detection pin D, the third chip high voltage power supply and signal detection pin D and the fourth chip high voltage power supply and signal detection pin D are respectively between -0.3V and 45V.

[0011] Compared with the prior art, the synchronous rectification circuit provided by the utility model can be applied to both the positive and negative ends, which includes a synchronous rectification chip, the synchronous rectification chip includes a first chip ground GND, a second chip ground GND, a third chip ground GND, a first chip high-voltage power supply and signal detection pin D, a second chip high-voltage power supply and signal detection pin D, a third chip high-voltage power supply and signal detection pin D, a fourth chip high-voltage power supply and signal detection pin D and a chip power supply VDD, the first chip ground GND, the second chip ground GND and the third chip ground GND are connected in parallel and then connected to an inductor, and the inductor is connected to the output voltage negative electrode VO-, the fourth chip VDD is connected to the third chip GND through a first capacitor C1, the first chip high-voltage power supply and signal detection pin D, the second chip high-voltage power supply and signal detection pin D, the third chip high-voltage power supply and signal detection pin D and the fourth chip high-voltage power supply and signal detection pin D are connected in parallel and then connected to the output voltage positive electrode VO+, the output voltage positive electrode VO+ and the output voltage negative electrode VO- A second capacitor C2 and a resistor R are connected in parallel between them. In this way, when the DCM is working, due to the excitation effect of the inductor, oscillation will be generated when the primary chip is turned off. In order to prevent the oscillation signal from being detected incorrectly and causing abnormal opening of the synchronous rectifier, when the primary chip is turned off, the voltage between the first chip high-voltage power supply and signal detection pin D, the second chip high-voltage power supply and signal detection pin D, the third chip high-voltage power supply and signal detection pin D and the fourth chip high-voltage power supply and signal detection pin D and the first chip ground GND, the second chip ground GND and the third chip ground GND drops rapidly. By detecting the falling voltage threshold and falling rate between the first chip high-voltage power supply and signal detection pin D, the second chip high-voltage power supply and signal detection pin D, the third chip high-voltage power supply and signal detection pin D and the first chip ground GND, the second chip ground GND and the third chip ground GND, the opening of the synchronous rectifier can be accurately judged to avoid the phenomenon of incorrect opening of the drive chip caused by excitation oscillation. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solution of the present utility model, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0013] Figure 1 Schematic diagram of a synchronous rectification circuit applicable to both positive and negative ends provided in this embodiment.

[0014] Figure 2 This is a packaging structure diagram of a synchronous rectification circuit and a synchronous rectification chip applicable to both positive and negative ends provided by this embodiment. DETAILED DESCRIPTION

[0015] In order to make the technical problems, technical solutions and beneficial effects solved by the utility model more clear, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.

[0016] Please refer to Figure 1 to Figure 2 As shown, in an embodiment of the utility model, a synchronous rectification circuit applicable to both positive and negative ends is provided, including a synchronous rectification chip, the synchronous rectification chip including a first chip ground GND1, a second chip ground GND2, a third chip ground GND3, a first chip high-voltage power supply and signal detection pin D1, a second chip high-voltage power supply and signal detection pin D2, a third chip high-voltage power supply and signal detection pin D3, a fourth chip high-voltage power supply and signal detection pin D4 and a chip power supply VDD, the first chip ground GND1, the second chip ground GND2 and the third chip ground GND3 are connected in parallel to an inductor L and the inductor L is connected to the output voltage negative electrode VO-, the chip power supply VDD is connected to the third chip GND3 through a first capacitor C1, the first chip high-voltage power supply and signal detection pin D1, the second chip high-voltage power supply and signal detection pin D2, the third chip high-voltage power supply and signal detection pin D3, the fourth chip high-voltage power supply and signal detection pin D4 and a chip power supply VDD, the first chip ground GND1, the second chip ground GND2 and the third chip ground GND3 are connected in parallel to an inductor L and the inductor L is connected to the output voltage negative electrode VO-, the chip power supply VDD is connected to the third chip GND3 through a first capacitor C1, the first chip high-voltage power supply and signal detection pin D1, the second chip high-voltage The power supply and signal detection pin D2, the third chip high-voltage power supply and signal detection pin D3 and the fourth chip high-voltage power supply and signal detection pin D4 are connected in parallel to the output voltage positive electrode VO+, and a second capacitor C2 and a resistor R are connected in parallel between the output voltage positive electrode VO+ and the output voltage negative electrode VO-. In this way, both the output voltage positive electrode VO+ and the output voltage negative electrode VO- can be used. When DCM is working, due to the excitation effect of the inductor, when the primary chip is turned off, oscillation will occur. In order to prevent the oscillation signal from being misdetected and causing abnormal opening of the synchronous rectifier tube, when the primary chip is turned off, the voltage between its drain D and GND drops rapidly. By detecting the falling voltage threshold and the falling rate between D and GND, the opening of the synchronous rectifier tube can be accurately judged to avoid the phenomenon of mis-opening of the drive chip caused by excitation oscillation.

[0017] In this embodiment, after the system is powered on, the output capacitor is charged through the body diode of the built-in MOS, and the output voltage rises. The first chip high-voltage power supply and signal detection pin D1, the second chip high-voltage power supply and signal detection pin D2, the third chip high-voltage power supply and signal detection pin D3, and the fourth chip high-voltage power supply and signal detection pin D4 are connected to the output voltage. When the output voltage rises, the VCC capacitor is charged through the internal power supply circuit of the chip. When the voltage of VCC is charged to the turn-on threshold voltage, the internal control circuit of the chip starts to work, and the MOS is turned on and off normally. When the MOS is turned on normally, the current no longer flows through the body diode, but flows through the channel of the MOS. When the chip works normally, the required working current still supplies power to VCC through the first chip high-voltage power supply and signal detection pin D1, the second chip high-voltage power supply and signal detection pin D2, the third chip high-voltage power supply and signal detection pin D3, and the fourth chip high-voltage power supply and signal detection pin D4, thereby being compatible with a variety of switching power supply control systems to ensure that the chip will not work under voltage in both constant current and constant voltage working states of the primary control system.

[0018] In this embodiment, the bypass capacitor of the chip power supply VDD needs to be close to the chip VCC pin and the first chip GND1 pin, the second chip GND2 pin and the third chip GND3 pin.

[0019] In this embodiment, the copper area of ​​the D pin is increased to improve the heat dissipation of the chip.

[0020] In this embodiment, the first chip ground GND1, the second chip GND2 and the third chip GND3 are respectively connected to the source of the synchronous rectifier tube built in the synchronous rectifier chip.

[0021] In this embodiment, the first chip high-voltage power supply and signal detection pin D1, the second chip high-voltage power supply and signal detection pin D2, the third chip high-voltage power supply and signal detection pin D3, and the fourth chip high-voltage power supply and signal detection pin D4 are respectively connected to the drain of the synchronous rectifier tube built into the synchronous rectifier chip.

[0022] In this embodiment, the chip power supply VCC voltage is between -0.3V and 7V.

[0023] In this embodiment, the voltages of the first chip high voltage power supply and signal detection pin D1, the second chip high voltage power supply and signal detection pin D2, the third chip high voltage power supply and signal detection pin D3 and the fourth chip high voltage power supply and signal detection pin D4 are respectively between -0.3V and 45V.

[0024] Compared with the prior art, the synchronous rectification circuit provided by the utility model can be applied to both the positive and negative ends, which includes a synchronous rectification chip, the synchronous rectification chip includes a first chip ground GND, a second chip ground GND, a third chip ground GND, a first chip high-voltage power supply and signal detection pin D, a second chip high-voltage power supply and signal detection pin D, a third chip high-voltage power supply and signal detection pin D, a fourth chip high-voltage power supply and signal detection pin D and a chip power supply VDD, the first chip ground GND, the second chip ground GND and the third chip ground GND are connected in parallel and then connected to an inductor, and the inductor is connected to the output voltage negative electrode VO-, the fourth chip VDD is connected to the third chip GND through a first capacitor C1, the first chip high-voltage power supply and signal detection pin D, the second chip high-voltage power supply and signal detection pin D, the third chip high-voltage power supply and signal detection pin D and the fourth chip high-voltage power supply and signal detection pin D are connected in parallel and then connected to the output voltage positive electrode VO+, the output voltage positive electrode VO+ and the output voltage negative electrode VO- A second capacitor C2 and a resistor R are connected in parallel between them. In this way, when the DCM is working, due to the excitation effect of the inductor, oscillation will be generated when the primary chip is turned off. In order to prevent the oscillation signal from being detected incorrectly and causing abnormal opening of the synchronous rectifier, when the primary chip is turned off, the voltage between the first chip high-voltage power supply and signal detection pin D, the second chip high-voltage power supply and signal detection pin D, the third chip high-voltage power supply and signal detection pin D and the fourth chip high-voltage power supply and signal detection pin D and the first chip ground GND, the second chip ground GND and the third chip ground GND drops rapidly. By detecting the falling voltage threshold and falling rate between the first chip high-voltage power supply and signal detection pin D, the second chip high-voltage power supply and signal detection pin D, the third chip high-voltage power supply and signal detection pin D and the first chip ground GND, the second chip ground GND and the third chip ground GND, the opening of the synchronous rectifier can be accurately judged to avoid the phenomenon of incorrect opening of the drive chip caused by excitation oscillation.

[0025] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A synchronous rectification circuit applicable to both positive and negative terminals, characterized in that: It comprises a synchronous rectification chip, which comprises a first chip ground GND, a second chip ground GND, a third chip ground GND, a first chip high-voltage power supply and signal detection pin D, a second chip high-voltage power supply and signal detection pin D, a third chip high-voltage power supply and signal detection pin D, a fourth chip high-voltage power supply and signal detection pin D and a chip power supply VDD. The first chip ground GND, the second chip ground GND and the third chip ground GND are connected in parallel to an inductor, and the inductor is connected to the output voltage negative electrode VO-. The fourth chip VDD is connected to the third chip GND through a first capacitor C1. The first chip high-voltage power supply and signal detection pin D, the second chip high-voltage power supply and signal detection pin D, the third chip high-voltage power supply and signal detection pin D and the fourth chip high-voltage power supply and signal detection pin D are connected in parallel to the output voltage positive electrode VO+. A second capacitor C2 and a resistor R are connected in parallel between the output voltage positive electrode VO+ and the output voltage negative electrode VO-.

2. The synchronous rectification circuit applicable to both positive and negative ends as claimed in claim 1, characterized in that: The first chip ground GND, the second chip ground GND and the third chip ground GND are respectively connected to the source of the synchronous rectifier tube built in the synchronous rectifier chip.

3. The synchronous rectification circuit applicable to both positive and negative ends as claimed in claim 1, characterized in that: The first chip high voltage power supply and signal detection pin D, the second chip high voltage power supply and signal detection pin D, the third chip high voltage power supply and signal detection pin D, and the fourth chip high voltage power supply and signal detection pin D are respectively connected to the drain of the synchronous rectifier tube built into the synchronous rectifier chip.

4. The synchronous rectification circuit applicable to both positive and negative ends as claimed in claim 1, characterized in that: The chip power supply VCC voltage is between -0.3V and 7V.

5. The synchronous rectification circuit applicable to both positive and negative terminals as claimed in claim 1, characterized in that: The voltages of the first chip high voltage power supply and signal detection pin D, the second chip high voltage power supply and signal detection pin D, the third chip high voltage power supply and signal detection pin D and the fourth chip high voltage power supply and signal detection pin D are respectively between -0.3V and 45V.

Images