Package structure

Abstract

A package structure includes a first chip structure including a first electronic device and a first interconnect structure electrically connected to a front side of the first electronic device. The first chip structure also includes a first backside via electrically connected to a backside of the first electronic device, and a first waveguide layer overlapping the first electronic device. In addition, the first waveguide layer is closer to the back side of the first electronic device than the front side of the first electronic device. The first chip structure also includes a plurality of first waveguide features formed over the first waveguide layer, and a first via formed through the first waveguide layer and electrically connected to the first backside via.

Description

Technical Field

[0001] The embodiments of the utility model relate to semiconductor technology, and in particular to a packaging structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuous advances in semiconductor manufacturing processes have resulted in semiconductor devices with more sophisticated functionality and / or higher levels of integration. Functional density (i.e., the number of devices interconnected per chip area) has increased while geometry size (i.e., the smallest component produced during the manufacturing process) has decreased. This process of device size miniaturization generally provides the benefits of increased production efficiency and reduced associated costs.

[0003] The chip package not only provides protection for the semiconductor device from environmental pollution, but also provides a connection interface for the semiconductor device packaged therein. Smaller package structures that occupy less space or have a lower height have been developed to package semiconductor devices.

[0004] New packaging technologies have been developed to further improve the density and functionality of semiconductor dies. These relatively new semiconductor die packaging technologies face manufacturing challenges. Utility Model Content

[0005] The purpose of the present invention is to provide a packaging structure to solve at least one of the above problems.

[0006] In some embodiments, a packaging structure is provided, the packaging structure including a first chip structure, wherein the first chip structure includes a first electronic device; a first interconnect structure electrically connected to a front side of the first electronic device; a first back side via electrically connected to a back side of the first electronic device; a first waveguide layer overlapping the first electronic device, wherein the first waveguide layer is closer to the back side of the first electronic device than to the front side of the first electronic device; a plurality of first waveguide components formed above the first waveguide layer; and a first via formed through the first waveguide layer and electrically connected to the first back side via.

[0007] According to one embodiment of the present invention, it also includes: an interposer structure, including: an interposer substrate; an optical structure formed above the interposer substrate; and an interposer via formed through the interposer substrate, wherein the first chip structure is bonded to the interposer structure.

[0008] According to one embodiment of the present invention, it also includes: an input / output chip structure connected to the intermediate layer structure; and an optical fiber attached to the intermediate layer structure, wherein the first chip structure is a processor chip structure.

[0009] According to one embodiment of the present invention, the present invention further includes: a second chip structure attached to the interposer structure, wherein the second chip structure includes: a second electronic device; a second interconnect structure electrically connected to the front side of the second electronic device;

[0010] a second backside via electrically connected to the back side of the second electronic device; a second waveguide layer overlapping the second electronic device; a plurality of second waveguide components formed above the second waveguide layer; and a second via formed through the second waveguide layer and electrically connected to the second backside via, wherein the plurality of first waveguide components, the first waveguide layer and the second waveguide layer are made of LiNbO3, and the plurality of second waveguide components are made of SiN.

[0011] According to one embodiment of the present invention, the first chip structure also includes: a second electronic device, wherein the first interconnect structure is electrically connected to the front side of the second electronic device; and an isolation layer formed above the first waveguide layer and vertically overlapping with the first electronic device and the second electronic device.

[0012] According to one embodiment of the present invention, the first chip structure also includes: a second electronic device, wherein the first interconnect structure is electrically connected to the front side of the second electronic device; and an amorphous silicon layer formed above the first waveguide layer, wherein in a cross-sectional schematic diagram, the width of the amorphous silicon layer is greater than the width of one of the plurality of first waveguide components and less than the width of the first waveguide layer.

[0013] According to one embodiment of the present invention, the width of the first waveguide layer is smaller than the width of the first interconnection structure.

[0014] According to one embodiment of the present invention, it also includes: a dielectric layer adjacent to the first waveguide layer.

[0015] According to one embodiment of the present invention, the first electronic device includes: a gate structure; and a source / drain structure formed adjacent to the gate structure, wherein the first back side via is connected to the back side of the source / drain structure.

[0016] According to one embodiment of the present invention, the first interconnect structure is electrically connected to the gate structure and the source / drain structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The embodiments of the present invention can be better understood according to the following detailed description and the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features shown in the figures are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make the description clear.

[0018] Figure 1 A diagrammatic perspective view showing an intermediate stage in the fabrication of an electronic device according to some embodiments.

[0019] Figure 2A-1 , Figure 2B-1 , Figure 2C-1 , Figure 2D-1 , Figure 2A-2 , Figure 2B-2 , Figure 2C-2 , Figure 2D-2 , Figure 2A-3 , Figure 2B-3 , Figure 2C-3 , Figure 2D-3 According to some embodiments, along Figure 1 Lines YSD-YSD', YMG-YMG', and XX' show schematic cross-sectional views of intermediate stages of manufacturing an electronic device.

[0020] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Fig. 3I , Figure 3J A schematic cross-sectional view showing an intermediate stage of manufacturing a package structure according to some embodiments.

[0021] Figure 3E-1 , Figure 3E-2 , Figure 3E-3 According to some embodiments, along Figure 1 A schematic cross-sectional view of the electronic device shown by lines YSD-YSD', YMG-YMG', and XX'.

[0022] Figure 4 A schematic cross-sectional view of a package structure according to some embodiments is shown.

[0023] Figure 5A , Figure 5B , Figure 5C , Figure 5D A schematic cross-sectional view showing an intermediate stage of manufacturing a package structure according to some embodiments.

[0024] Figure 6 A cross-sectional schematic diagram of a package structure according to some embodiments is shown.

[0025] Fig. 7A and Figure 7B FIG. 4 is a cross-sectional view showing an intermediate stage of manufacturing a package structure according to some embodiments.

[0026] Figure 8A cross-sectional schematic diagram of a package structure according to some embodiments is shown.

[0027] Fig.9A and Fig. 9B FIG. 4 is a cross-sectional view showing an intermediate stage of manufacturing a package structure according to some embodiments.

[0028] Fig.10 A cross-sectional schematic diagram of a package structure according to some embodiments is shown.

[0029] Fig.11A , Fig. 11B , Fig. 11C A schematic cross-sectional view showing an intermediate stage of manufacturing a package structure according to some embodiments.

[0030] Fig.12 A cross-sectional schematic diagram of a package structure according to some embodiments is shown.

[0031] Fig.13 A cross-sectional schematic diagram of a package structure according to some embodiments is shown.

[0032] Fig.14 A cross-sectional schematic diagram of a package structure according to some embodiments is shown.

[0033] Fig.15 A schematic top view of a package structure according to some embodiments is shown.

[0034] Fig.16A and Fig. 16B Representative cross-sectional views of various stages of forming a package structure according to some embodiments are shown.

[0035] Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 A cross-sectional schematic diagram of a package structure according to some embodiments is shown.

[0036] The reference numerals are as follows:

[0037] 40-1,40-2,40-3,40-4,40-5,40-1A,40-2A,40-5A,40-1B,40-2B,40-5C: Chip structure

[0038] 100: Electronic devices

[0039] 100-5A: Electronics area

[0040] 102: Base

[0041] 102_FS:Front side

[0042] 102_BS: Back side

[0043] 104: Fin structure

[0044] 104B: Base fin structure

[0045] 106: first semiconductor material layer

[0046] 108: second semiconductor material layer

[0047] 108': Channel structure

[0048] 110: Mask structure

[0049] 116: Isolation Structure

[0050] 130: dummy gate structure

[0051] 132: dummy gate dielectric layer

[0052] 134: dummy gate electrode layer

[0053] 136: Hard mask layer

[0054] 140: Gate spacer

[0055] 142: Fin spacer

[0056] 144: Source / drain notch

[0057] 148:Internal spacer

[0058] 150: Source / drain structure

[0059] 160: contact etching stop layer

[0060] 162: Interlayer dielectric layer

[0061] 168: Gate structure

[0062] 170: Interface layer

[0063] 172: Gate dielectric layer

[0064] 174: Gate stack

[0065] 180: Silicide layer

[0066] 182: Source / drain contact

[0067] 190,190-5A,230,230-5A: Interconnection structure

[0068] 192,192-5A,212,228,228b,228c,228d,228-5A,532: Conductive structure

[0069] 192',234: Contact plug

[0070] 194,202,210,210a,226,226d,232,514: Dielectric layer

[0071] 196,196-5A: Carrying base

[0072] 200,200',200a,200a',200b,200b',200c,200c',200d,200d',200e,200f,400,400A,400B,400C,400D,400E,400F:Package structure

[0073] 204: Back silicide layer

[0074] 206,208: Back side vias

[0075] 220, 220a, 220b, 220d: waveguide layer

[0076] 222,222b,222d: vias

[0077] 224,224b,224c,224d,240,240-5A,520: Waveguide components

[0078] 236,236-5A:Metal layer

[0079] 238: Conductive bump

[0080] 242,242-5A,522: Grating Coupler

[0081] 244,244-5A,516: Bonding layer

[0082] 246,246-5A,534,602,604: Conductive bonding pads

[0083] 250: Fiber Optic

[0084] 301: Isolation layer

[0085] 303: amorphous silicon layer

[0086] 500: Intermediary layer structure

[0087] 512: Intermediate layer substrate

[0088] 513: Optical structure

[0089] 515:Joint structure

[0090] 530:Intermediary layer via

[0091] 536: Under-bump metallization layer

[0092] 538:Conductive connector

[0093] 606: Sealant

[0094] R1: Mach-Zehnder modulation phase transition region

[0095] R2: Light detection area DETAILED DESCRIPTION

[0096] It should be understood that the following disclosure provides many different embodiments or examples to implement different parts of the subject provided. The following describes specific examples of each component and its arrangement in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the embodiments of the utility model. For example, the size of the component is not limited to the scope or value of an embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the component. In addition, in the subsequent description, the first component formed above or on the second component includes an embodiment in which the first and second components are formed in direct contact, and may also include an additional component that can be formed between the first and second components so that the first and second components may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity, and are not intended to limit the relationship between the various embodiments and / or the appearance structure.

[0097] Some variations of the embodiments are described herein. In the various views and display embodiments, similar reference symbols are used to mark similar elements. It should be understood that additional operations may be performed before, during, and after the method, and that some of the operations described may be replaced or eliminated for other embodiments of the method.

[0098] Furthermore, spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, may be used to conveniently describe the relationship of one element or component to another (plural) element or component in the drawings. Spatially relative terms also encompass different orientations of the device in use or operation in addition to the orientations shown in the drawings. The device may also be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the description of the spatially relative terms used would be interpreted accordingly.

[0099] The nanostructure transistors described below (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon field effect transistors, and gate all around (GAA) transistors) may be patterned by any suitable method. For example, these structures may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-aligned processes to create patterns with smaller pitches, for example, patterns with smaller pitches than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the nanostructures.

[0100] The present invention may be related to packaging structures, such as three-dimensional (3D) packaging, three-dimensional integrated circuit devices, and 2.5D packaging. The present invention forms a packaging structure, which includes a substrate that carries one or more dies or packages and a protective element (such as a protective cover) located next to the dies or packages. The protective element may also serve as a warpage control element and / or a heat dissipation element.

[0101] Other components and processes may also be included. For example, test structures may be included to assist in verification testing of 3D packages, three-dimensional integrated circuit devices, and / or 2.5D packages. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate to allow testing using probes or probe cards and the like. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods that may be used herein may be used in conjunction with test methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0102] The package structure may include an electronic device and an optical device. The electronic device may be formed in a first chip / wafer, and the optical device may be formed in a second chip / wafer, and the first chip / wafer and the second chip / wafer may be bonded together to form a photonic electronic integrated circuit. However, the size of the integrated circuit may be relatively large, and the wiring in the device may be relatively complex.

[0103] Therefore, in some embodiments of the present invention, a packaging structure having an electronic device and an optical device formed in a single structure and a method for manufacturing the same are provided. More specifically, an electronic device (e.g., a transistor) can be formed, and an interconnect structure can be formed on the front side of the electronic device, while the optical device can be formed on the back side of the electronic device. In addition, the conductive structure can be electrically connected to the back side of the transistor, so that the conductive structure formed on the front side of the electronic device can be electrically connected to the conductive structure formed on the back side of the electronic device. Therefore, the electronic wiring in the packaging structure can be relatively short, and the size of the packaging structure can be reduced.

[0104] Figure 1 A diagrammatic perspective view is shown of an intermediate stage in the fabrication of an electronic device 100 in accordance with some embodiments. Figure 2A-1 , Figure 2B-1 , Figure 2C-1 , Figure 2D-1 , Figure 2A-2 , Figure 2B-2 , Figure 2C-2 , Figure 2D-2 , Figure 2A-3 , Figure 2B-3 , Figure 2C-3 , Figure 2D-3 According to some embodiments, along Figure 1 Line Y SD -Y SD’ (i.e. Y direction), Y MG -Y MG’ (ie, Y direction) and XX' (ie, X direction) are cross-sectional views showing the intermediate stages of manufacturing the electronic device 100. More specifically, Figure 2A-1 , Figure 2A-2 , Figure 2A-3 Display Manufacturing Figure 1 is a cross-sectional schematic diagram of an electronic device 100 at an intermediate stage, Figure 2B-1 , Figure 2C-1 , Figure 2D-1 , Figure 2B-2 , Figure 2C-2 , Figure 2D-2 , Figure 2B-3 , Figure 2C-3 , Figure 2D-3 A schematic cross-sectional view of an intermediate stage of electronic device 100 after fabrication is shown. Electronic device 100 may be a transistor, such as a nanostructure transistor (eg, a nanosheet transistor, a nanowire transistor, a multi-bridge channel transistor, a nanoribbon field effect transistor, or a gate-all-around (GAA) transistor).

[0105] First, according to some embodiments, such as Figure 1As shown, a substrate 102 is formed, and a semiconductor stack including a first semiconductor material layer 106 and a second semiconductor material layer 108 is formed above the substrate 102. The substrate 102 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 102 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. The elemental semiconductor material may include, but is not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. The compound semiconductor material may include, but is not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. The alloy semiconductor material may include, but is not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0106] In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are alternately stacked on the substrate 102 to form a semiconductor stack. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layer 106 is made of SiGe, and the second semiconductor material layer 108 is made of silicon. It should be understood that although Figure 1 Four first semiconductor material layers 106 and three second semiconductor material layers 108 are shown, but the semiconductor stack may include fewer or more alternating first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor stack may include two to five first semiconductor material layers 106 and two to five second semiconductor material layers 108.

[0107] The first semiconductor material layer 106 and the second semiconductor material layer 108 may be formed by using low-pressure chemical vapor deposition (LPCVD), epitaxial growth process, other suitable methods or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD) or vapor phase epitaxy (VPE).

[0108] According to some embodiments, Figure 1As shown, after the first semiconductor material layer 106 and the second semiconductor material layer 108 are formed as a semiconductor stack above the substrate 102, the semiconductor stack is patterned to form a fin structure 104. The fin structure 104 may extend longitudinally in the X direction. In some embodiments, the patterning process includes forming a mask structure 110 above the semiconductor material stack, and etching the semiconductor material stack and the substrate 102 below through the mask structure 110. In some embodiments, the mask structure 110 is a multilayer structure including a pad oxide layer and a nitride layer formed above the pad oxide layer. The pad oxide layer may be made of silicon oxide, which is formed by thermal oxidation or chemical vapor deposition, and the nitride layer may be made of silicon nitride, which is formed by chemical vapor deposition, such as low pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the fin structure 104 includes a base fin structure 104B and a semiconductor stack formed over the base fin structure 104B, the semiconductor stack including a first semiconductor material layer 106 and a second semiconductor material layer 108 .

[0109] According to some embodiments, Figure 1 , Figure 2A-1 , Figure 2A-2 , Figure 2A-3 As shown, after forming the fin structure 104, an isolation structure 116 is formed to surround the fin structure 104. According to some embodiments, the isolation structure 116 is configured to electrically isolate an active region of a semiconductor structure (eg, the fin structure 104), and is also referred to as a shallow trench isolation (STI) feature.

[0110] More specifically, an insulating layer may be formed around and cover the fin structure 104, and the insulating layer may be recessed to form an isolation structure 116, wherein the fin structure 104 protrudes from the top surface of the isolation structure 116. In some embodiments, the insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), other suitable insulating materials, or a combination thereof. In addition, before forming the insulating layer, a liner layer (not shown) may be formed, and the liner layer may also be recessed together with the insulating layer to form the isolation structure 116. In some embodiments, the liner layer includes a plurality of dielectric material layers.

[0111] Then, according to some embodiments, such as Figure 2B-1 , Figure 2B-2 , Figure 2B-3 As shown, a dummy gate structure 130 is formed across the fin structure 104, and gate spacers 140 and fin spacers 142 are formed on the sidewalls of the dummy gate structure 130. The dummy gate structure 130 may be used to define a channel region of a final transistor structure.

[0112] In some embodiments, the dummy gate structure 130 includes a dummy gate dielectric layer 132 and a dummy gate electrode layer 134. In some embodiments, the dummy gate dielectric layer 132 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or a combination thereof. In some embodiments, the dummy gate dielectric layer 132 is formed by using thermal oxidation, chemical vapor deposition, atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable methods, or a combination thereof.

[0113] In some embodiments, the dummy gate electrode layer 134 is made of a conductive material, and the conductive material includes polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), or a combination thereof. In some embodiments, the dummy gate electrode layer 134 is formed by using chemical vapor deposition, physical vapor deposition, or a combination thereof.

[0114] In some embodiments, the hard mask layer 136 is formed on the dummy gate electrode layer 134. In some embodiments, the hard mask layer 136 includes multiple layers, such as an oxide layer and a nitride layer. In some embodiments, the oxide layer is silicon oxide, and the nitride layer is silicon nitride.

[0115] The formation of the dummy gate structure 130 may include conformally forming a dielectric material as a dummy gate dielectric layer 132. Thereafter, a conductive material may be formed on the dielectric material as a dummy gate electrode layer 134, and a hard mask layer 136 may be formed on the conductive material. Next, the dielectric material and the conductive material may be patterned through the hard mask layer 136 to form the dummy gate structure 130.

[0116] According to some embodiments, Figure 2B-1 , Figure 2B-2 , Figure 2B-3 As shown, after forming the dummy gate structure 130, a spacer is formed to cover the top surface and sidewalls of the dummy gate structure 130 and the fin structure 104, and an etching process may be performed to form a gate spacer 140, a fin spacer 142, and a source / drain recess 144 in the fin structure 104. The gate spacer 140 may be configured to separate a source / drain structure (formed later) from the dummy gate structure 130, and the fin spacer 142 may be configured to limit the growth of the source / drain structure formed therein.

[0117] In some embodiments, the spacer layer is made of one or more dielectric materials. The dielectric material may include silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or combinations thereof. According to some embodiments, after forming the spacer layer, the spacer layer is etched to form gate spacers 140 on both sidewalls of the dummy gate structure 130, and to form fin spacers 142 to cover the sidewalls of the fin structure 104. In addition, according to some embodiments, portions of the fin structure 104 not covered by the dummy gate structure 130 and the gate spacers 140 are etched to form source / drain recesses 144 during the etching process. The etching process may be an anisotropic etching process, such as dry plasma etching, and the dummy gate structure 130 and the gate spacers 140 may be used as etching masks during the etching process. In some embodiments, the isolation structure 116 is also slightly etched during the etching process.

[0118] According to some embodiments, Figure 2C-1 , Figure 2C-2 , Figure 2C-3 As shown, after forming the source / drain recesses 144, the first semiconductor material layer 106 exposed by the source / drain recesses 144 is laterally recessed to form a notch, and an internal spacer 148 is formed in the notch. In some embodiments, an etching process is performed to laterally recess the first semiconductor material layer 106 of the fin structure 104 from the source / drain recesses 144. In some embodiments, during the etching process, the first semiconductor material layer 106 has a greater etching rate (or etching amount) than the second semiconductor material layer 108, thereby forming a notch between adjacent second semiconductor material layers 108. In some embodiments, during the etching process, the second semiconductor material layer 108 is also slightly etched, so that according to some embodiments, the portion of the second semiconductor material layer 108 exposed by the notch is thinner than other portions. In some embodiments, the etching process is an isotropic etching, such as dry etching, remote plasma etching, wet chemical etching, other suitable techniques and / or combinations thereof.

[0119] Next, according to some embodiments, an internal spacer 148 is formed in the gap between the second semiconductor material layer 108. The internal spacer 148 can be configured to separate the source / drain structure and the gate structure formed in the subsequent manufacturing process. As described above, according to some embodiments, since the second semiconductor material layer 108 is also partially etched when the gap is formed, the internal spacer 148 formed in the gap is thicker than the thickness of the first semiconductor material layer 106. In addition, according to some embodiments, the internal spacer 148 has a curved sidewall. In some embodiments, the internal spacer 148 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon oxycarbon nitride (SiOCN), or a combination of the foregoing.

[0120] According to some embodiments, Figure 2C-1 , Figure 2C-2 , Figure 2C-3 As shown, after forming the inner spacer 148, a source / drain structure 150 is formed in the source / drain recess 144, and a contact etch stop layer 160 and an interlayer dielectric layer 162 are formed over the source / drain structure 150. The source / drain structures described herein may represent a source or a drain individually or collectively depending on the context.

[0121] In some embodiments, the source / drain structure 150 is formed using an epitaxial growth process, such as molecular beam epitaxy, metal organic chemical vapor deposition, vapor phase epitaxy, other applicable epitaxial growth processes, or combinations thereof. In some embodiments, the source / drain structure 150 is made of any applicable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or combinations thereof. In some embodiments, the source / drain structure 150 is in-situ doped during the epitaxial growth process. In some embodiments, the source / drain structure 150 is doped in one or more implantation processes after the epitaxial growth process.

[0122] According to some embodiments, after forming the source / drain structure 150, a contact etch stop layer (CESL) 160 is conformally formed to cover the source / drain structure 150, and an interlayer dielectric (ILD) layer 162 is formed on the contact etch stop layer 160. In some embodiments, the contact etch stop layer 160 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, other suitable dielectric materials, or a combination thereof. The dielectric material of the contact etch stop layer 160 can be conformally deposited on the semiconductor structure by performing chemical vapor deposition, atomic layer deposition, other application methods, or a combination thereof.

[0123] The interlayer dielectric layer 162 may include multiple layers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or other applicable low-k dielectric materials. The interlayer dielectric layer 162 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other applicable processes.

[0124] According to some embodiments, after depositing the contact etch stop layer 160 and the interlayer dielectric layer 162, a planarization process (such as chemical mechanical polishing or an etch back process) is performed until the dummy gate electrode layer 134 is exposed. Figure 2D-1 , Figure 2D-2 , Figure 2D-3 As shown, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form a gate trench, and the gate structure 168 is formed in the gate trench. More specifically, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form the second semiconductor material layer 108 of the fin structure 104 into a channel structure 108' (e.g., a nanostructure). According to some embodiments, Figure 2D-3 As shown, the channel structures 108' are vertically suspended above the substrate 102 and are spaced apart from each other in the Z direction. In addition, according to some embodiments, the channel structures 108' extend laterally in the X direction and are located between the source / drain structures 150. Although not explicitly shown in FIG. Figure 2D-2 , but the channel structure 108 ′ and the base fin structure 104B may have rounded corners.

[0125] The removal process may include one or more etching processes. For example, when the dummy gate electrode layer 134 may be made of polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layer 134. Thereafter, the dummy gate dielectric layer 132 may be removed by using plasma dry etching, dry chemical etching, and / or wet etching. The first semiconductor material layer 106 may be removed by performing a selective wet etching process, such as an ammonia hydroxide-hydrogen peroxide-water mixture (APM) etching process. For example, the wet etching process uses an etchant such as ammonium hydroxide (NH4OH), ethylenediamine pyrocatechol (EDP), and / or potassium hydroxide (KOH) solution.

[0126] According to some embodiments, Figure 2D-1 , Figure 2D-2 , Figure 2D-3 As shown, after forming the channel structure 108 ′, an interface layer 170 , a gate dielectric layer 172 , and a gate stack 174 are formed to surround the channel structure 108 ′ as a gate structure 168 .

[0127] The interface layer 170 may be used to improve the interface between the channel structure 108' and the dielectric layer formed later. In addition, the interface layer 170 may be able to help suppress the decrease in the mobility of carriers in the channel structure 108' used as the transistor channel region. In some embodiments, the interface layer 170 is an oxide layer formed by performing a thermal process. In some embodiments, the interface layer 170 has a thickness in the range of about 0.5 nm to about 1.5 nm.

[0128] According to some embodiments, after forming the interface layer 170, a gate dielectric layer 172 is conformally formed in the gate trench. In some embodiments, the gate dielectric layer 172 covers the interface layer 170 and surrounds the channel structure 108'. In some embodiments, the gate dielectric layer 172 is made of one or more layers of dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other applicable high dielectric constant dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 172 is formed by using chemical vapor deposition, atomic layer deposition, other applicable methods, or combinations thereof.

[0129] Next, according to some embodiments, a gate stack 174 is formed over the gate dielectric layer 172. In some embodiments, the gate stack 174 is made of one or more layers of conductive materials, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, or combinations thereof. In some embodiments, the gate stack 174 is formed by using chemical vapor deposition, atomic layer deposition, electroplating, other applicable methods, or combinations thereof.

[0130] According to some embodiments, Figure 2D-1 , Figure 2D-2 , Figure 2D-3As shown, after forming the gate structure 168, a silicide layer 180 and a source / drain contact 182 are formed over the source / drain structure 150. More specifically, a contact trench may be formed through the contact etch stop layer 160 and the interlayer dielectric layer 162 to expose the source / drain structure 150. Thereafter, according to some embodiments, a silicide layer 180 is formed over the exposed portion of the source / drain structure 150, and a source / drain contact 182 is formed in the contact trench over the silicide layer 180.

[0131] The silicide layer 180 may be formed by forming a metal layer over the top surface of the source / drain structure 150 and annealing the metal layer so that the metal layer reacts with the source / drain structure 150. After forming the silicide layer 180, the unreacted metal layer may be removed.

[0132] In some embodiments, the source / drain contacts 182 are made of a conductive material, and the conductive material includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other applicable conductive materials or combinations of the foregoing.

[0133] The source / drain contacts 182 may further include a liner and / or a barrier layer. For example, a liner (not shown) may be formed on the sidewalls and bottom of the contact trench. The liner may be made of silicon nitride, but any other applicable dielectric may be used as an alternative. The liner may be formed using a plasma-assisted chemical vapor deposition (PECVD) process, but other applicable processes may be used as an alternative, such as physical vapor deposition or thermal processes. A barrier layer (not shown) may be formed over the liner (if any) and may cover the sidewalls and top of the opening. The barrier layer may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted chemical vapor deposition (PECVD), plasma-assisted physical vapor deposition (plasmaenhanced PVD, PEPVD), atomic layer deposition (ALD), or any other applicable deposition process. The barrier layer may be made of tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, or the like may also be used.

[0134] According to some embodiments, Figure 2D-1 , Figure 2D-2 , Figure 2D-3As shown, the electronic device 100 includes a channel structure 108' suspended above the substrate 102 in the Z direction, a source / drain structure 150 attached to both sides of the channel structure 108' in the X direction, and a gate structure 168 surrounding the channel structure 108' and extending in the Y direction. In addition, the source / drain contact 182 is connected to the front side of the source / drain structure 150 of the electronic device 100.

[0135] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Fig. 3I , Figure 3J The cross-sectional view of the intermediate stage of manufacturing the package structure 200 according to some embodiments is shown. More specifically, according to some embodiments, as Figure 3A As shown, Figure 2D-1 , Figure 2D-2 , Figure 2D-3 The plurality of electronic devices 100 shown are formed on a front side 102_FS of a substrate 102. The front side 102_FS of the substrate 102 is opposite to the back side 102_BS of the substrate 102. According to some embodiments, the diagrams are simplified for clarity. Figures 3A to 3J The structure of the electronic device 100 is shown in FIG. Figure 1 , Figure 2A-1 to Figure 2D-1 , Figure 2A-2 to Figure 2D-2 , Figure 2A-3 to Figure 2D-3 In addition, the number and arrangement of the electronic devices 100 in the package structure 200 may be changed depending on the application.

[0136] According to some embodiments, Figure 3B As shown, interconnect structure 190 is formed over interlayer dielectric layer 162. That is, according to some embodiments, interconnect structure 190 is formed over the front side of electronic device 100, while substrate 102 is located at the back side of electronic device 100.

[0137] In some embodiments, the interconnect structure 190 is a front-side interconnect structure. In some embodiments, the interconnect structure 190 includes a conductive structure 192 (e.g., vias and metal lines) formed in a plurality of dielectric layers 194. In some embodiments, the source / drain contacts 182 are electrically connected to the conductive structure 192 in the interconnect structure 190. In some embodiments, the interconnect structure 190 further includes a contact plug 192' located on the gate structure 168 and electrically connected to the gate structure 168.

[0138] The dielectric layer 194 may include multiple layers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) and / or other applicable low-k dielectric materials. The dielectric layer 194 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other applicable processes.

[0139] In some embodiments, the conductive structure 192 and the contact plug 192' are made of a conductive material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, a combination of the foregoing, or other applicable materials. In some embodiments, the conductive structure 192 and the contact plug 192' are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other applicable deposition processes.

[0140] After forming the interconnect structure 190, a carrier substrate 196 is attached to the interconnect structure 190 to provide temporary mechanical and structural support for the semiconductor structure during subsequent manufacturing processes. The carrier substrate 196 may include glass, silicon oxide, aluminum oxide, metal, combinations of the foregoing, and / or the like. In some embodiments, the interconnect structure 190 is attached to the carrier substrate 196 by an adhesive layer (not shown). The adhesive layer serves as a temporary adhesive layer. The adhesive layer may be glue or tape.

[0141] Next, the structure may be turned upside down to form a device on the back side 102_BS of the substrate 102. More specifically, according to some embodiments, Figure 3C As shown, after the carrier substrate 196 is attached to the interconnect structure 190, the substrate 102 is turned upside down and a planarization process is performed on the back side 102_BS of the substrate 102. In some embodiments, the substrate 102 is planarized until the isolation structure 116 (not shown) is exposed. Figure 3C In some embodiments, after the planarization process, the remaining substrate 102 has a thickness in a range of about 5 nm to about 100 nm.

[0142] Next, according to some embodiments, such as Figure 3D As shown, dielectric layer 202 is formed over back side 102_BS of substrate 102. In some embodiments, dielectric layer 202 is made of a low dielectric constant dielectric material having a dielectric constant value less than 7. In some embodiments, dielectric layer 202 is made of SiO2, SiN, SiCN, SiOC, SiOCN, or the like. Dielectric layer 202 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0143] According to some embodiments, Figure 3E , Figure 3E-1 , Figure 3E-2 , Figure 3E-3 As shown, after forming the dielectric layer 202, a backside silicide layer 204 and a backside via 206 are formed. More specifically, Figure 3E-1 , Figure 3E-2 , Figure 3E-3 According to some embodiments, along Figure 1 Line Y SD -Y SD’ (i.e. in the Y direction), Y MG -Y MG’ (ie, in the Y direction) and XX′ (ie, in the X direction) are cross-sectional schematic diagrams of the electronic device 100 in the package structure 200 .

[0144] In some embodiments, a backside via trench is formed through the dielectric layer 202 and the substrate 102 to expose the bottom of the source / drain structure 150. In some embodiments, the bottom of the source / drain structure 150 is also slightly removed. Then, according to some embodiments, as shown in FIGS. 3E, 3E-1, 3E-2, and 3E-3, a backside silicide layer 204 is formed on the exposed source / drain structure 150, and a backside via 206 is formed on the backside silicide layer 204. In some embodiments, the backside silicide layer 204 is formed by forming a metal layer on the exposed surface of the source / drain structure 150 and annealing the metal layer so that the metal layer reacts with the source / drain structure 150. Then, according to some embodiments, after the backside silicide layer 204 is formed, the unreacted metal layer is removed. In some embodiments, the back silicide layer 204 is an N-type epitaxial silicide, such as TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSI, GdSi, LuSi, DySi, ErSi, YbSi, or the like. In some embodiments, the side silicide layer 204 is a P-type epitaxial silicide, such as NiSi, CoSi, MnSi, Wsi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, or the like.

[0145] According to some embodiments, Figure 3E , Figure 3E-1 , Figure 3E-2 , Figure 3E-3As shown, after forming the backside silicide layer 204, a conductive filling layer is formed to fill the backside via trench, and a grinding process is performed to form the backside via 206. In some embodiments, a backside via 208 is further formed through the dielectric layer 202, the substrate 102 and the interlayer dielectric layer 162, and is electrically connected to the conductive structure 192 in the interconnect structure 190. Therefore, the electronic signal on the back side of the substrate 102 can be transmitted to the device formed on the front side of the substrate 102. According to some embodiments, as Figure 3E , Figure 3E-1 , Figure 3E-2 , Figure 3E-3 As shown, the source / drain contacts 182 are located on the front side of the source / drain structure 150 of the electronic device 100 , and the backside vias 206 are located on the back side of the source / drain structure 150 of the electronic device 100 .

[0146] In some embodiments, the backside vias 206 and 208 are made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or combinations thereof. The backside vias 206 and 208 may be formed by using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other applicable deposition processes.

[0147] A liner layer (not shown) and / or a barrier layer (not shown) may be formed on the sidewalls of the backside vias 206 and 208. For example, the liner layer may include silicon nitride, but any other applicable dielectric may be used as an alternative. For example, the barrier layer may include tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, or the like may also be used. The liner layer and the barrier layer may be formed by using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other applicable deposition processes. In some embodiments, each of the backside vias 206 and 208 has a width in the range of about 15 nm to about 300 nm in the X direction and / or the Y direction. In some other embodiments, after forming the backside vias 206 and 208, the substrate 102 is completely removed.

[0148] Then, according to some embodiments, such as Figure 3FAs shown, a dielectric layer 210 is formed over the back side of the electronic device 100, and a conductive structure 212 is formed in the dielectric layer 210. In some embodiments, the conductive structure 212 is a metal line buried in the dielectric layer 210. In some embodiments, the dielectric layer 210 includes multiple layers made of a low dielectric constant dielectric material having a dielectric constant value less than 7. In some embodiments, the dielectric layer 210 is made of SiO2, SiN, SiCN, SiOC, SiOCN, or the like. The dielectric layer 210 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0149] In some embodiments, the conductive structure 212 is made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or combinations thereof. The conductive structure 212 may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition process.

[0150] Then, according to some embodiments, such as Figure 3G As shown, the waveguide layer 220 is disposed above the dielectric layer 210, and a via 222 is formed through the waveguide layer 220. The waveguide layer 220 is configured to transmit an optical signal in an optical device. More specifically, the waveguide layer 220 provides an optical medium for light transmission. For example, the optical signal can be captured and guided by the waveguide layer 220.

[0151] In some embodiments, the waveguide layer 220 is a LiNbO3 (lithium niobate) layer. In some embodiments, the waveguide layer 220 has a thickness in the range of about 300 nm to about 800 nm in the Z direction. The thickness of the waveguide layer 220 is controlled so that the light transmission is confined to the waveguide layer 220. In some embodiments, the waveguide layer 220 is a wafer and is directly bonded to the dielectric layer 210. In some embodiments, the width of the waveguide layer 220 in the X and Y directions is as large as the width of the substrate. The waveguide layer 220 can be attached to the dielectric layer 210 by an adhesive layer (e.g., an oxide layer).

[0152] According to some embodiments, Figure 3GAs shown, after the waveguide layer 220 is provided, the waveguide layer 220 and the dielectric layer 210 are patterned to form a groove, and the via 222 is formed in the groove. In some embodiments, the conductive structure 212 is exposed through the groove, so the via 222 directly contacts the conductive structure 212. In some embodiments, the via 222 is made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or a combination of the foregoing. The via 222 can be formed by using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition process.

[0153] Next, according to some embodiments, such as Figure 3H As shown, the waveguide component 224 is formed above the waveguide layer 220. In some embodiments, the waveguide component 224 includes an optical waveguide (e.g., a ridge waveguide, a rib waveguide, a buried channel waveguide, and a diffuse waveguide) or a coupler (e.g., a grating coupler and an edge coupler). The waveguide component 224 is configured to guide an optical signal in an optical device. More specifically, when a voltage is applied to the optical device, the refractive index of the waveguide layer 220 can be changed, and light will be transmitted at an interface between the waveguide component 224 and the waveguide layer 220. In some embodiments, the waveguide component 224 and the waveguide layer 220 are made of different materials. In some embodiments, the waveguide component 224 is made of SiN. In some embodiments, the waveguide component 224 has a thickness in the range of about 100 nm to about 800 nm in the Z direction.

[0154] In some embodiments, the waveguide component 224 is formed by performing a deposition process to form a material layer and patterning the material layer. The deposition process may include chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted chemical vapor deposition (PECVD), plasma-assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or other applicable deposition processes. The patterning process may include a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

[0155] Then, according to some embodiments, such as Fig. 3IAs shown, a dielectric layer 226 is formed, and a conductive structure 228 is formed in the dielectric layer 226. In some embodiments, the conductive structure 228 is a contact metal formed in the dielectric layer 226. In some embodiments, the dielectric layer 226 is a multilayer made of a low dielectric constant dielectric material having a dielectric constant value less than 7. In some embodiments, the dielectric layer 226 is made of SiO2, SiN, SiCN, SiOC, SiOCN, or the like. The dielectric layer 226 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0156] In some embodiments, the conductive structure 228 is made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or combinations thereof. The conductive structure 228 may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition process.

[0157] Next, according to some embodiments, such as Figure 3J As shown, interconnect structure 230 is formed over dielectric layer 226. Interconnect structure 230 may be a backside interconnect structure. Interconnect structure 230 may be used as a redistribution (RDL) structure for wiring.

[0158] In some embodiments, the interconnect structure 230 includes a dielectric layer 232, a contact plug 234 and a metal layer 236 buried in the dielectric layer 232, and a conductive bump 238. In some embodiments, the interconnect structure 230 further includes a waveguide component 240 buried in the dielectric layer 232.

[0159] In some embodiments, dielectric layer 232 includes multiple layers made of a low dielectric constant dielectric material having a dielectric constant value less than 7. In some embodiments, dielectric layer 232 is made of SiO2, SiN, SiCN, SiOC, SiOCN, or the like. Dielectric layer 232 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0160] In some embodiments, the contact plug 234 and the metal layer 236 are made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or combinations thereof. The contact plug 234 and the metal layer 236 may be formed by using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition process.

[0161] In some embodiments, the conductive bump 238 includes a solder material. The solder material may be a tin-containing material. The tin-containing material may also include copper, silver, gold, aluminum, lead, one or more other suitable materials, or a combination of the foregoing. In some embodiments, the solder material does not contain lead.

[0162] In some embodiments, the waveguide component 240 includes an optical waveguide (e.g., a ridge waveguide, a rib waveguide, a buried channel waveguide, and a diffused waveguide) or a coupler (e.g., a grating coupler and an edge coupler). The waveguide component 240 is configured to guide an optical signal in an optical device. In some embodiments, the waveguide component 240 and the waveguide component 224 are made of the same material. In some embodiments, the waveguide component 240 and the waveguide layer 220 are made of different materials. In some embodiments, the waveguide component 240 is made of SiN. In some embodiments, each waveguide component 240 has a thickness in the range of about 100 nm to about 800 nm in the Z direction.

[0163] As described above, according to some embodiments, the electronic device 100 and the optical device (eg, the waveguide layer 220 and the waveguide components 224 and 240) are formed on the same wafer. Figure 3J As shown, the package structure 200 includes a Mach-Zehnder modulator phase shifter region R1. Since the Mach-Zehnder modulator phase shifter region R1 has an electrical device and an optical device therein, light can be transmitted in the optical device, and the signal can be adjusted by the electronic device. For example, the electronic device 100 can receive and process an electrical signal, and the optical device (such as the waveguide layer 220 and the waveguide components 224 and 240) can receive and process an optical signal. Since the electronic device 100 and the optical device are formed on a single wafer, rather than formed on different chips and then bonded together, the channels of the electrical and optical signals can be reduced. In other words, the wiring of the optical or electrical signals in the package structure 200 can be reduced, and the transmission rate of the electrical and optical signals can be improved.

[0164] In addition, according to some embodiments, the backside power supply network (e.g., backside via 206) is formed on the backside of the electronic device 100, so that the interconnection structures 190 and 230 can be formed on both sides of the electronic device 100 and can be electrically connected to each other. Therefore, the electrical wiring in the package structure 100 can be simplified and reduced. In addition, the backside conductive structure (e.g., contact plug 234 and metal layer 236) and the optical element (e.g., waveguide component 240) are integrated into the interconnection structure 230, so that the wiring area can also be reduced.

[0165] After the electronic device and the optical device are formed in the package structure 200 (eg, a wafer), the package structure 200 may be cut into a plurality of chip structures, each of which also includes the electronic device and the optical device formed therein.

[0166] Figure 4 A cross-sectional schematic diagram of a package structure 200' is shown according to some embodiments. According to some embodiments, the package structure 200' may be similar to the package structure 200 described above, except that an optical fiber is attached to the package structure 200'. The process and materials used to form the package structure 200' may be similar to or the same as the process and materials used to form the package structure 200 described above, and are not described in detail herein.

[0167] More specifically, according to some embodiments, Figure 4 As shown, optical fiber 250 is attached to the sidewall of waveguide layer 220. In some embodiments, optical fiber 250 overlaps with waveguide layer 220 laterally (e.g., in the X direction). In some embodiments, optical fiber 250 also overlaps with waveguide component 224 laterally (e.g., in the X direction). Optical fiber 250 can be an edge-coupled device configured as an input / output port for optical signals of an optical device in packaging structure 200'. Optical fiber 250 can be fixed in place using an optical glue (not shown separately). In some embodiments, the optical glue includes a polymer material (e.g., an epoxyacrylate oligomer) and can have a refractive index between about 1 and about 3.

[0168] Similar to the package structure 200, the package structure 200' includes the electronic device 100 and the optical device (eg, the waveguide layer 220 and the waveguide components 224 and 240) formed on a single chip, so that electrical and optical communication and operation can be improved. Figure 4 The arrangement of the electronic devices 100 in the package structure 200 ′ is different from that in FIG. Figure 3J The arrangement of the electronic devices 100 in the package structure 200 is shown as another example for arranging the electronic devices 100 .

[0169] Figure 5A , Figure 5B , Figure 5C , Figure 5D A cross-sectional view of an intermediate stage of manufacturing a package structure 200a according to some embodiments is shown. According to some embodiments, the package structure 200a may be similar to the package structure 200 described above, except that the waveguide layer of the package structure 200a is smaller than the substrate 102. The process and materials used to form the package structure 200a may be similar to or the same as the process and materials used to form the package structure 200 described above, and are not described in detail herein.

[0170] More specifically, according to some embodiments, Figure 5A As shown, proceed as Figure 2A-1 to Figure 2D-1 , Figure 2A-2 to Figure 2D-2 , Figure 2A-3 to Figure 2D-3 , FIG. 3A to FIG. 3F The process shown in FIG. 1 is a process for fabricating a waveguide layer 220a, and the waveguide layer 220a is disposed on or die-to-wafer bonded to the dielectric layer 210. In some embodiments, the waveguide layer 220a is a LiNbO3 layer. The waveguide layer 220a can be the same as the waveguide layer 220 described above, except that the waveguide layer 220a has a smaller size. In some embodiments, the width of the waveguide layer 220a is less than the width of the substrate 102 in the X-direction and the Y-direction. According to some embodiments, similar to the waveguide layer 220, the electronic device 100 is completely within the projected area of ​​the waveguide layer 220a in a top view. That is, according to some embodiments, the electronic device 100 vertically overlaps with the waveguide layer 220a (e.g., in the Z-direction).

[0171] According to some embodiments, Figure 5B As shown, after the waveguide layer 220a is provided, an additional dielectric layer 210a is formed around the waveguide layer 220a, and a via 222 is formed through the waveguide layer 220a and is located on the conductive structure 212. More specifically, according to some embodiments, the dielectric layer 210a surrounds the sidewalls of the waveguide layer 220a and covers the portion of the dielectric layer 210 not covered by the waveguide layer 220a. In some embodiments, the dielectric layer 210a directly contacts the top surface of the dielectric layer 210 and the sidewalls of the waveguide layer 220a. In some embodiments, the top surface of the dielectric layer 210a is substantially flush with the top surface of the waveguide layer 220a.

[0172] In some embodiments, the dielectric layer 210a is made of a low dielectric constant dielectric material having a dielectric constant value less than 7. In some embodiments, the dielectric layer 210a is made of SiO2, SiN, SiCN, SiOC, SiOCN, or the like. The dielectric layer 210a can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes. After forming the dielectric layer 210a, the via 222 is formed through the waveguide layer 220a and electrically connected to the conductive structure 212.

[0173] Next, according to some embodiments, such as Figure 5CAs shown, the processes shown in FIGS. 3H and 3I are performed to form a waveguide component 224 and a conductive structure 228 in the dielectric layer 226 above the waveguide layer 220a. Then, according to some embodiments, Figure 5D As shown, the above Figure 3J The process shown is to form a package structure 200a. According to some embodiments, similar to the package structure 200, the package structure 200a includes the electronic device 100 and the optical device (eg, the waveguide layer 220a and the waveguide components 224 and 240) formed on the same wafer.

[0174] Figure 6 A schematic cross-sectional view of a package structure 200a' is shown according to some embodiments. According to some embodiments, the package structure 200a' may be similar to the package structure 200a described above, except that the optical fiber 250 is attached to the package structure 200a'. The process and materials used to form the package structure 200a' may be similar to or the same as the process and materials used to form the package structure 200a described above, and are not described in detail herein.

[0175] More specifically, according to some embodiments, Figure 6 As shown, the optical fiber 250 is attached to the sidewall of the waveguide layer 220a. In some embodiments, the optical fiber 250 overlaps the waveguide layer 220a laterally. In some embodiments, the optical fiber 250 also overlaps the waveguide component 224 laterally. According to some embodiments, similar to the package structure 200a, the package structure 200a' includes an electronic device 100 and an optical device (such as the waveguide layer 220a and the waveguide components 224 and 240) formed on a single chip, so that electrical and optical communications and operations can be improved. In addition, Figure 6 The arrangement of the electronic devices 100 in the package structure 200a' is different from that in FIG. Figure 5D The arrangement of the electronic devices 100 in the package structure 200 a is shown as another example for arranging the electronic devices 100 .

[0176] Fig. 7A and Figure 7B A cross-sectional schematic diagram showing an intermediate stage of manufacturing a package structure 200b according to some embodiments. According to some embodiments, the package structure 200b may be similar to the package structure 200 described above, except that the isolation layer 301 is formed above the waveguide layer and the waveguide component. The process and materials used to form the package structure 200b may be similar to or the same as the process and materials used to form the package structure 200 described above, and are not described in detail herein.

[0177] More specifically, according to some embodiments, Fig. 7AAs shown, the processes shown in FIGS. 2A-1 to 2D-1, 2A-2 to 2D-2, 2A-3 to 2D-3, and 3A to 3F are performed, and the waveguide layer 220b and the waveguide component 224b are formed on the dielectric layer 210, and the isolation layer 301 is formed to cover the waveguide layer 220b and the waveguide component 224b. Then, according to some embodiments, Fig. 7A As shown, the via 222 b is formed through the isolation layer 301 and the waveguide layer 220 b and is electrically connected to the conductive structure 212 .

[0178] The isolation layer 301 is configured to separate the waveguide layer 220b from the conductive structure 228b to reduce or avoid light absorption by the metal of the conductive structure 228b. Therefore, the energy efficiency of the final packaging structure can be improved.

[0179] In some embodiments, the isolation layer 301 has a thickness in the range of about 10 nm to about 200 nm. In some embodiments, the isolation layer 301 is an oxide layer, such as SiO2. In some embodiments, the isolation layer 301 is made of a dielectric material having a dielectric constant value less than 7. In some embodiments, the isolation layer 301 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes.

[0180] According to some embodiments, Figure 7B As shown, after forming the isolation layer 301, the above-mentioned Figure 3I to Figure 3J The process shown in FIG. 1 is used to form a package structure 200 b. According to some embodiments, as shown in FIG. Figure 7B As shown, the isolation layer 301 is vertically located between the bottom surface of the conductive structure 228b and the top surface of the waveguide layer 220b, so that the conductive structure 228b is vertically spaced apart (e.g., separated) from the waveguide layer 220b. Therefore, the light loss caused by the absorption of the conductive structure 228b can be reduced. In addition, since the isolation layer 301 covers the waveguide component 224b, the waveguide component 224b is separated from the dielectric layer 226 formed later. In some embodiments, the isolation layer 301 vertically overlaps the electronic device 100.

[0181] The processes and materials used to form the waveguide layer 220b, the waveguide component 224b, the via 222b, and the conductive structure 228b may be similar to or the same as the processes and materials used to form the waveguide layer 220, the waveguide component 224, the via 222, and the conductive structure 228, and are not described in detail herein. According to some embodiments, similar to the package structure 200, the package structure 200b includes the electronic device 100 and the optical device (e.g., the waveguide layer 220b and the waveguide components 224b and 240) formed on the same wafer.

[0182] Figure 8A cross-sectional schematic diagram of a package structure 200b' is shown according to some embodiments. According to some embodiments, the package structure 200b' may be similar to the package structure 200b described above, except that the optical fiber 250 is attached to the package structure 200b'. The process and materials used to form the package structure 200b' may be similar to or the same as the process and materials used to form the package structure 200b described above, and are not described in detail herein.

[0183] More specifically, according to some embodiments, Figure 8 As shown, the optical fiber 250 is attached to the sidewall of the waveguide layer 220b. In some embodiments, the optical fiber 250 overlaps the waveguide layer 220b laterally. In some embodiments, the optical fiber 250 also overlaps the waveguide component 224b laterally. According to some embodiments, similar to the package structure 200b, the package structure 200b' includes an electronic device 100 and an optical device (such as the waveguide layer 220b and the waveguide components 224 and 240) formed on a single chip, so that electrical and optical communications and operations can be improved. In addition, Figure 8 The arrangement of the electronic devices 100 in the package structure 200b' is different from Figure 7B The arrangement of the electronic devices 100 in the package structure 200 b is shown as another example for arranging the electronic devices 100 .

[0184] Fig.9A and Fig. 9B A cross-sectional view of an intermediate stage of manufacturing a package structure 200c according to some embodiments is shown. According to some embodiments, the package structure 200c may be similar to the package structure 200 described above, except that an amorphous silicon layer is formed over at least one waveguide component. The processes and materials used to form the package structure 200c may be similar to or the same as the processes and materials used to form the package structure 200 described above, and are not described in detail herein.

[0185] More specifically, according to some embodiments, Fig.9A As shown, proceed as Figure 2A-1 to Figure 2D-1 , Figure 2A-2 to Figure 2D-2 , Figure 2A-3 to Figure 2D-3 , FIG. 3A to FIG. 3H The process shown in FIG. 1 is repeated, and an amorphous silicon layer 303 is formed to cover the waveguide component 224c of at least one waveguide component 224. Since light will be absorbed by the amorphous silicon layer 303, the current in the region will be changed. That is, the change in current can be detected when light passes through. Therefore, the final structure can be used as a light detector for the package structure 200c. In some embodiments, the amorphous silicon layer 303 has a thickness in the range of about 50nm to about 300nm.

[0186] According to some embodiments, Fig. 9B As shown, after forming the amorphous silicon layer 303, the above-mentioned Figure 3I to Figure 3JThe process shown in FIG. 1 is used to form a package structure 200c. According to some embodiments, as shown in FIG. Fig. 9B As shown, the conductive structure 228c is partially formed above the amorphous silicon layer 303. That is, some portions of the amorphous silicon layer 303 are vertically located between the bottom surface of the conductive structure 228c and the top surface of the waveguide layer 220. In addition, since the waveguide component 224c is covered by the amorphous silicon layer 303, the waveguide component 224c is separated from the dielectric layer 226 formed later. In some embodiments, in the cross-sectional schematic diagram, the width of the amorphous silicon layer 303 in the X direction is greater than the width of the waveguide component 224c, but less than the width of the waveguide layer 220 in the X direction.

[0187] The process and materials used to form the waveguide component 224c and the conductive structure 228c are similar to or the same as the process and materials used to form the waveguide component 224 and the conductive structure 228, and are not described in detail herein. According to some embodiments, similar to the package structure 200, the package structure 200c includes the electronic device 100 and the optical device (e.g., the waveguide layer 220 and the waveguide components 224, 224c, and 240) formed on the same wafer. In addition, according to some embodiments, the package structure 200c includes a Mach-Zehnder modulation phase conversion region R1 and a light detection region R2.

[0188] Fig.10 A cross-sectional schematic diagram of a package structure 200c' is shown according to some embodiments. According to some embodiments, the package structure 200c' may be similar to the package structure 200c described above, except that the optical fiber 250 is attached to the package structure 200c'. The process and materials used to form the package structure 200c' may be similar to or the same as the process and materials used to form the package structure 200c described above, and are not described in detail herein. More specifically, according to some embodiments, as Fig.10 As shown, the optical fiber 250 is attached to the sidewall of the waveguide layer 220. Similar to the package structure 200c, the package structure 200c' includes the electronic device 100 and the optical device (such as the waveguide layer 220 and the waveguide components 224, 224c and 240) formed on a single chip, so that electrical and optical communication and operation can be improved. In addition, Fig.10 The arrangement of the electronic devices 100 in the package structure 200c' is different from Fig. 9B The arrangement of the electronic devices 100 in the package structure 200 c is shown as another example for arranging the electronic devices 100 .

[0189] FIG. 11A to FIG. 11CA cross-sectional schematic diagram of an intermediate stage of manufacturing a package structure 200d according to some embodiments is shown. The package structure 200d may be similar to the package structure 200 described above, except that the waveguide component of the package structure 200d is formed by a waveguide layer. The process and materials used to form the package structure 200d may be similar to or the same as the process and materials used to form the package structure 200 described above, and are not described in detail herein.

[0190] More specifically, according to some embodiments, Fig.11A As shown, proceed as Figure 2A-1 to Figure 2D-1 , Figure 2A-2 to Figure 2D-2 , Figure 2A-3 to Figure 2D-3 , FIG. 3A to FIG. 3F The process shown in FIG. 2 is a process for preparing a waveguide layer 220d, and the waveguide layer 220d is disposed on the dielectric layer 210. In some embodiments, the waveguide layer 220d is a LiNbO3 layer. In some embodiments, the thickness of the waveguide layer 220d is in the range of about 300 nm to about 800 nm.

[0191] According to some embodiments, Fig. 11B As shown, after the waveguide layer 220d is provided, the upper portion of the waveguide layer 220d is patterned to form a waveguide member 224d. According to some embodiments, since the waveguide member 224d is formed by patterning the waveguide layer 220d, the waveguide layer 220d and the waveguide member 224d are made of the same material, such as LiNbO3. Since the waveguide layer 220d and the waveguide member 224d are made of the same material, light loss during light transmission can be reduced. In addition, according to some embodiments, there is no interface between the waveguide layer 220d and the waveguide member 224d. In some embodiments, the waveguide member 224d has a thickness in the range of about 100 nm to about 800 nm in the Z direction.

[0192] Next, according to some embodiments, such as Fig. 11C As shown, a via hole 222d, a conductive structure 228d and a dielectric layer 226d are formed, and the above-mentioned Figure 3J The process shown in FIG. 1 is used to form the package structure 200d. More specifically, according to some embodiments, a via 222d is formed through the waveguide layer 220d, and a dielectric layer 226d is formed above the waveguide layer 220d and around the waveguide component 224d. In addition, according to some embodiments, a conductive structure 228d is formed through the dielectric layer 226d.

[0193] According to some embodiments, similar to the package structure 200, the package structure 200d includes the electronic device 100 and the optical device (e.g., the waveguide layer 220d and the waveguide components 224d and 240) formed on the same wafer. The processes and materials used to form the waveguide layer 220d, the dielectric layer 226d, the via 222d, and the conductive structure 228d may be similar to or the same as the processes and materials used to form the waveguide layer 220, the dielectric layer 226, the via 222, and the conductive structure 228, and are not described in detail herein.

[0194] Fig.12 A schematic cross-sectional view of a package structure 200d' is shown according to some embodiments. According to some embodiments, the package structure 200d' may be similar to the package structure 200d described above, except that the optical fiber 250 is attached to the package structure 200d'. The process and materials used to form the package structure 200d' may be similar to or the same as the process and materials used to form the package structure 200d described above, and are not described in detail herein.

[0195] More specifically, according to some embodiments, Fig.12 As shown, the optical fiber 250 is attached to the sidewall of the waveguide layer 220d. In some embodiments, the optical fiber 250 overlaps the waveguide layer 220d laterally. In some embodiments, the optical fiber 250 also overlaps the waveguide component 224d laterally. According to some embodiments, similar to the package structure 200d, the package structure 200d' includes an electronic device 100 and an optical device (such as the waveguide layer 220d and the waveguide components 224d and 240) formed on a single chip, so that electrical and optical communications and operations can be improved. In addition, Fig.12 The arrangement of the electronic devices 100 in the package structure 200d' is different from Fig. 11C The arrangement of the electronic devices 100 in the package structure 200 d is shown as another example for arranging the electronic devices 100 .

[0196] Fig.13 A cross-sectional view of a package structure 200e is shown according to some embodiments. According to some embodiments, the package structure 200e may be similar to the package structure 200d' described above, except that an isolation layer 301 is formed. More specifically, according to some embodiments, Fig. 7A , Figure 7B , Figure 8 The isolation layer 301 shown is applied to Fig.12 The package structure 200d' is shown.

[0197] Fig.14 A cross-sectional view of a package structure 200f is shown according to some embodiments. According to some embodiments, the package structure 200f may be similar to the package structure 200d' described above, except that an amorphous silicon layer 303 is formed. More specifically, according to some embodiments, Fig.9A , Fig. 9B , Fig.10 The amorphous silicon layer 303 shown is applied to Fig.12 The package structure 200d' is shown.

[0198] The package structure can be cut (ie, divided) into a plurality of chip structures, and each chip structure includes the electronic device 100 and the optical device. The chip structure can be further connected to other components. For example, the chip structure can be connected to an interposer structure. Fig.15 A schematic top view of a package structure 400 is shown according to some embodiments. In some embodiments, the package structure 400 includes chip structures 40-1, 40-2, 40-3, 40-4, and 40-5. In some embodiments, the chip structures 40-1, 40-2, 40-3, 40-4 are formed by cutting the package structure 200, 200', 200a, 200a', 200b, 200b', 200c, 200c', 200d, 200d', 200e, or 200f. In some embodiments, the chip structures 40-1, 40-2, 40-3, 40-4 are processor chip structures, and the chip structure 40-5 is an input / output chip structure. In some embodiments, the chip structures 40-1, 40-2, 40-3, 40-4 have the same structure. In some embodiments, the chip structures 40 - 1 , 40 - 2 , 40 - 3 , 40 - 4 include at least two chip structures formed by cutting the package structure 200 , 200 ′, 200 a , 200 a ′, 200 b , 200 b ′, 200 c , 200 c ′, 200 d , 200 d ′ 200 e , or 200 f .

[0199] Fig.16A and Fig. 16B Representative cross-sectional views of various stages of forming a package structure 400A according to some embodiments are shown. The package structure 400A may have Fig.15 Top view shown.

[0200] First, according to some embodiments, such as Fig.16A As shown, an interposer structure 500 is formed. The interposer structure 500 may be an optical interposer structure including a conductive structure and an optical element formed therein. That is, the interposer structure 500 may receive various signals, including electrical signals or optical signals, convert the signals into optical signals, route optical signals, convert optical signals into electrical signals, and send the electrical signals to designated components. In some embodiments, the interposer structure 500 includes an interposer substrate 512, an optical structure 513, and a bonding structure 515. In some embodiments, the interposer substrate 512 is a silicon substrate, such as a silicon wafer.

[0201] In some embodiments, the optical structure 513 includes a dielectric layer 514 formed on the interposer substrate 512 and an optical element formed in the dielectric layer 514. In some embodiments, the dielectric layer 514 includes a low-k dielectric material and / or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, polyparaxylene, bis-benzocyclobutenes (BCB), or polyimide.

[0202] In some embodiments, the optical element (including the waveguide component 520 and the grating coupler 522) is formed in the dielectric layer 514. The waveguide component 520 and the grating coupler 522 are configured to receive the optical fiber 250 (eg, Fig. 16B The waveguide component 520 and the grating coupler 522 may be formed of the materials used to form the waveguide components 224 and 240 as described above.

[0203] In addition, according to some embodiments, interposer vias 530 are formed through the interposer substrate 512. The interposer vias 530 penetrate the interposer substrate 512 to provide a fast path for power, data, and ground through the interposer substrate 512. In some embodiments, the interposer vias 530 are spaced apart from the waveguide components 520 and the grating couplers 522. A liner and / or barrier layer (not shown) may be formed around the interposer vias 530. For example, the liner layer may be made of an insulating material, such as an oxide, a nitride, or other applicable materials, and the diffusion barrier layer may be made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), or other applicable materials.

[0204] In addition, according to some embodiments, a conductive structure 532 is formed above the interposer via 530 and is electrically connected to the interposer via 530. In some embodiments, the interposer via 530 and the conductive structure 532 are made of a conductive material, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, combinations thereof, or other applicable materials.

[0205] In some embodiments, Fig.16AAs shown, the bonding structure 515 includes a bonding layer 516, and a conductive bonding pad 534 is formed in the bonding layer 516. In some embodiments, the bonding layer 516 is made of silicon oxide. In some embodiments, the bonding layer 516 is made of a polymer, such as a benzocyclobutene (BCB) polymer, a polyimide (PI) or a polybenzoxazole (PBO) or other applicable materials. In some embodiments, the conductive bonding pad 534 is made of a conductive material, such as copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy or other applicable materials.

[0206] In some embodiments, Fig.16A As shown, an UBM layer 536 is formed below the interposer via 530, and a conductive connector 538 is formed and attached to the UBM layer 536. According to some embodiments, the conductive connector 538 is electrically connected to the conductive structure 532 through the interposer via 530.

[0207] In some embodiments, the UBM layer 536 is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), titanium tungsten (TiW), nickel (Ni), gold (Au), chromium (Cr), copper (Cu), copper alloy, other applicable materials or combinations thereof. In some embodiments, the UBM layer 536 and the conductive connector 538 are formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma assisted chemical vapor deposition (PECVD), plasma assisted physical vapor deposition (PEPVD), atomic layer deposition (ALD) or other applicable deposition processes.

[0208] Then, according to some embodiments, such as Fig. 16B As shown, the chip structures 40-1A, 40-2A, 40-5A and the optical fiber 250 are disposed above the interposer structure 500. The chip structures 40-1A, 40-2A, 40-5A may have Fig.15 The chip structures 40-1, 40-2, and 40-5 shown in the figure have the same layout. In addition, the other two chip structures have the same or similar structures, and the chip structures 40-1A and 40-2A may have the same or similar structures. Fig.15 The chip structures 40-3 and 40-4 shown have the same layout, but are not shown in FIG. Fig. 16B middle.

[0209] The chip structures 40-1A and 40-2A can be Figures 1 to 3I In addition, according to some embodiments, the grating coupler 242 is formed in the dielectric layer 232. Furthermore, according to some embodiments, as Fig. 16BAs shown, a bonding layer 244 is formed to cover the interconnect structure 230 instead of the conductive bump 238, and a conductive bonding pad 246 is formed in the bonding layer 244. The process and materials used to form the bonding layer 244 and the conductive bonding pad 246 may be similar to or the same as the process and materials used to form the bonding layer 516 and the conductive bonding pad 534 described above, and will not be described in detail herein.

[0210] According to some embodiments, Fig. 16B As shown, after forming the bonding layer 244 and the conductive bonding pad 246, the package structure is cut to form chip structures 40-1A and 40-2A, and the chip structures 40-1A and 40-2A are bonded to the interposer structure 500 by a hybrid bonding process. More specifically, the hybrid bonding involves at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding. In some embodiments, the bonding layer 516 is bonded to the bonding layer 244 and the conductive bonding pad 534 is bonded to the conductive bonding pad 246 by applying pressure and heat. In addition, according to some embodiments, the grating coupler 242 is substantially aligned with the grating coupler 522 in the Z direction in the cross-sectional schematic diagram. As described above, the chip structures 40-1A and 40-2A each include an electronic device 100 and an optical device (e.g., a waveguide layer 220 and waveguide components 224, 240, and 242).

[0211] Chip structure 40 - 5A may be an input / output (I / O) chip designed to operate with chip structures 40 - 1A and 40 - 2A. For example, chip structure 40 - 5A may control signals entering and exiting chip structures 40 - 1A and 40 - 2A and coordinate signals entering and exiting interposer structure 500 through optical fiber 250 .

[0212] In some embodiments, chip structure 40-5A also includes electronic devices and optical devices, but rather than forming the electronic devices and optical devices in the same wafer as described above, the electronic devices and optical devices are formed on separate wafers and then bonded together. Chip structure 40-5A can be formed by forming a first wafer having an electronic device region 100-5A and an interconnect structure 190-5A formed over a front side of electronic device region 100-5A. In some embodiments, electronic device region 100-5A includes Figure 2D-1 , Figure 2D-2 and Figure 2D-3 The electronic device 100 is shown. The interconnect structure 190-5A includes a conductive structure 192-5A connected to the front side of the electronic device in the electronic device region 100-5A. In addition, a conductive bonding pad 602 is formed over the top of the interconnect structure 190-5A (the chip structure 40-5A also includes the conductive structure 228-5A).

[0213] A second wafer with an optical device may be formed separately. For example, the second wafer may include an interconnect structure 230-5A with a metal layer 236-5A, a waveguide component 240-5A, and a grating coupler 242-5A formed therein. In addition, a conductive bonding pad 604 is formed above the top of the interconnect structure 230-5A. Thereafter, the first wafer and the second wafer are bonded via the conductive bonding pads 602 and 604, using the carrier substrate 196-5A as a support to form a package structure, and the package structure is cut to form a chip structure 40-5A.

[0214] The chip structure 40 - 5A may be bonded to the interposer structure 500 in a manner similar to the chip structures 40 - 1A and 40 - 2A. More specifically, according to some embodiments, Fig. 16B As shown, the chip structure 40-5A can be bonded to the interposer structure 500 through the bonding layer 244-5A and the conductive bonding pad 246-5A. The processes and materials used to form the interconnect structure 190-5A, the conductive structure 192-5A, the interconnect structure 230-5A, the metal layer 236-5A, the waveguide component 240-5A, the grating coupler 242-5A, the carrier substrate 196-5A, the bonding layer 244-5A and the conductive bonding pad 246-5A, 602, 604 can be similar to or the same as the processes and materials used to form the interconnect structure 190, the conductive structure 192, the interconnect structure 230, the metal layer 236, the waveguide component 240, the grating coupler 242, the carrier substrate 196, the bonding layer 244 and the conductive bonding pad 246, and are not described in detail herein.

[0215] According to some embodiments, after the chip structures 40-1A, 40-2A, 40-5A are bonded to the interposer structure 500, the sealant 606 may be formed on and around the chip structures 40-1A, 40-2A, 40-5A and the optical fiber 250. In some embodiments, the sealant 606 is a molding compound such as an epoxy resin or the like. The sealant 606 may be applied by compression molding, transfer molding, or the like.

[0216] According to some embodiments, Fig. 16BAs shown, after applying the sealant 606, the sealant 606 may be subjected to a planarization process until the top surfaces of the chip structures 40-1A, 40-2A, 40-5A are exposed. In some embodiments, after the planarization process, the top surfaces of the sealant 606 and the chip structures 40-1A, 40-2A, 40-5A are substantially flush with each other. The planarization process may be, for example, chemical-mechanical polishing (CMP), a grinding process, or the like. In some embodiments, the planarization may be omitted.

[0217] As described above, the electronic device 100 and the optical device in the chip structures 40-1A and 40-2A are formed in the same wafer without using additional bonding structures (e.g., bonding pads or bumps). In addition, according to some embodiments, a backside conductive structure is formed to electrically connect to the back side of the electronic device 100, so that the interconnect structure 190 and the optical device (e.g., the waveguide layer 220) can be formed on the opposite side of the electronic device 100. Therefore, the electrical wiring of the chip structures 40-1A and 40-2A can be improved.

[0218] On the other hand, according to some embodiments, the interconnection structure 190-5A and the optical device (eg, the waveguide component 240-5A) are formed in the electronic device 100 (not shown) in the electronic device region 100-5A of the chip structure 40-5A. Fig. 16B According to some embodiments, the chip structure 40 - 5A may thus have a higher voltage tolerance and may thus be used as an input / output chip of the package structure 400A.

[0219] Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 According to some embodiments, package structures 400B, 400C, 400D, 400E, and 400F are shown in cross-sectional view. According to some embodiments, similar to package structure 400A, package structures 400B, 400C, 400D, 400E, and 400F also have the following features: Fig.15 Same layout as shown.

[0220] Fig.17 A cross-sectional view of a package structure 400B is shown according to some embodiments. According to some embodiments, the package structure 400B may be similar to the package structure 400A described above, except that the waveguide component is formed by patterning the waveguide layer. More specifically, the chip structures 40-1B and 40-2B are cut into Fig. 11C The package structure 200 d is shown formed except that the conductive bumps 238 are replaced with bonding layers 244 and conductive bonding pads 246 .

[0221] Fig.18 A cross-sectional view of a package structure 400C is shown according to some embodiments. According to some embodiments, the package structure 400C may be similar to the package structure 400A described above, except that the chip structure 40-5C replaces the chip structure 40-5A. More specifically, the chip structure 40-5C may also be used as an input / output chip structure, but the chip structure 40-5C has a structure similar to the chip structures 40-1A and 40-2A. That is, according to some embodiments, Fig.18 As shown, a backside conductive structure is formed, and interconnect structure 190 and optical devices (such as waveguide layer 220) are formed on the opposite side of electronic device 100. Waveguide layer 220 in chip structure 40-5C can be controlled by relatively low voltage, so the structure can be used in devices whose input / output devices require lower voltages.

[0222] Fig.19 A cross-sectional view of a package structure 400D according to some embodiments is shown. According to some embodiments, the package structure 400D may be similar to the package structure 400B described above, except that the chip structure 40 - 5A is replaced by a chip structure 40 - 5C.

[0223] Fig. 20 A cross-sectional view of a package structure 400E is shown according to some embodiments. According to some embodiments, the package structure 400E may be similar to the package structure 400A described above, except that the chip structure 40-2A is replaced by the chip structure 40-2B. That is, according to some embodiments, the chip structures 40-1A and 40-2B have different structures.

[0224] Fig.21 A cross-sectional view of a package structure 400F according to some embodiments is shown. According to some embodiments, the package structure 400F may be similar to the package structure 400E described above, except that the chip structure 40 - 5A is replaced by a chip structure 40 - 5C.

[0225] As described above, if the electronic device and the optical device are formed on separate chips and then bonded together, the paths of the optical and electrical signals may be relatively long, and power consumption may be less efficient. Therefore, in some embodiments of the present invention, the electronic device 100 and the optical device (e.g., the waveguide layers 220, 220a, 220b, 220d) are integrated into the same wafer / chip structure. More specifically, a backside power supply network is applied to the electronic device 100 so that signals can be transmitted from the front side of the electronic device 100 to the back side of the electronic device 100. Therefore, the wiring of the final chip structure can be shortened, and the speed and energy efficiency can be improved.

[0226] In addition, according to some embodiments, the waveguide layer (eg, waveguide layers 220, 220a, 220b, 220d) may be a LiNbO3 layer. Compared to other waveguide materials (eg, SiN), the LiNbO3 layer may have lower optical loss and may provide improved optical communication and computing for package structures.

[0227] It should be understood that the components shown in the package structures 200, 200', 200a, 200a', 200b, 200b', 200c, 200c', 200d, 200d', 200e, 200f, 400, 400A, 400B, 400C, 400D, 400E, and 400F may be combined and / or interchanged. For example, the package structure may have Fig.15 The layout shown, and has Figures 1 to 14 Various chip structures are shown.

[0228] In addition, it should be noted that Figures 1 to 21 The same elements in the present invention may be labeled with the same symbols, may include the same or similar materials, and may be formed by the same or similar processes, so for the sake of brevity, these redundant details are omitted. Figures 1 to 21 For the description related to the method, it should be understood that Figures 1 to 21 The disclosed structures are not limited to the methods, but can exist independently as structures independent of the methods. Figures 1 to 21 The method shown is not limited to the disclosed structure and may be independent of the structure. Furthermore, according to some embodiments, the channel structure (eg, nanostructure) may include nanowires, nanosheets, or other applicable nanostructures.

[0229] Furthermore, although the above disclosed method is shown and described as a series of actions or events, it should be understood that in some other embodiments, the order of the drawings of these actions or events can be changed. For example, some actions can occur in different orders and / or occur simultaneously with other actions or events other than those shown and / or described above. In addition, all illustrated actions may not be required to implement one or more aspects or embodiments described above. Furthermore, the above one or more actions can be performed as one or more separate actions and / or stages.

[0230] Furthermore, the terms "approximately", "substantially", "about" used above take into account small variations and may vary in different technologies and are within the range of deviations understood by those skilled in the art. For example, when used in conjunction with an event or situation, these terms can represent both the situation where the event or situation occurs exactly and the situation where the event or situation occurs in a very close manner.

[0231] Embodiments of forming a package structure may be provided. The package structure may include an electronic device formed on a substrate and an interconnect structure formed on a front side of the electronic device. Afterwards, a backside via may be formed and connected to the back side of the electronic device, and an optical device may be formed on the backside via. That is, by forming the backside via, the wiring between the electronic device and the optical device may be shortened, and the speed and power consumption of the final package structure may be improved.

[0232] In some embodiments, a method for manufacturing a package structure is provided, the method comprising forming an electronic device on a substrate, and forming an interconnect structure on a front side of the electronic device. The method also comprises thinning the substrate, and forming a backside via connected to a back side of the electronic device. The method also comprises attaching a waveguide layer on the back side of the electronic device, and forming a via through the waveguide layer and electrically connected to the backside via.

[0233] In some other embodiments, the method further includes forming a plurality of waveguide components above the waveguide layer; and forming a dielectric layer to cover the plurality of waveguide components and the vias.

[0234] In some other embodiments, the method further includes forming an isolation layer above the plurality of waveguide components and the waveguide layer, wherein the via is formed through the isolation layer.

[0235] In some other embodiments, the method further includes forming an amorphous silicon layer to cover at least one of the plurality of waveguide components; and forming a conductive structure to partially cover the amorphous silicon layer and contact the via, the waveguide layer and the amorphous silicon layer.

[0236] In some other embodiments, the method further includes forming a bonding structure above the dielectric layer; and bonding the bonding structure to the interposer structure, wherein the interposer structure includes: an interposer via electrically connected to the via.

[0237] In some other embodiments, the interposer structure further includes: an interposer substrate; and an optical structure formed above the interposer substrate, wherein the interposer via penetrates the interposer substrate.

[0238] In some embodiments, a method for manufacturing a package structure is provided, the method comprising forming a transistor above a first side of a semiconductor substrate, and forming a first interconnect structure above the first side of the transistor. The method also comprises at least partially removing the semiconductor substrate from a second side of the semiconductor substrate, and forming a backside via on the second side of the transistor. The method also comprises disposing a waveguide layer above the backside via, and forming a first waveguide component above the waveguide layer. The method also comprises forming a second interconnect structure covering the first waveguide component and the waveguide layer. In addition, the first interconnect structure and the second interconnect structure are on opposite sides of the transistor.

[0239] In some other embodiments, the second waveguide component is embedded in the second interconnect structure.

[0240] In some other embodiments, the method further includes forming a via hole through the waveguide layer, wherein the via hole is electrically connected to the backside via hole.

[0241] In some other embodiments, the method further comprises patterning a first portion of the waveguide layer to form a first waveguide component before forming the via hole, wherein the via hole is formed through the second portion of the waveguide layer.

[0242] In some other embodiments, the transistor includes a gate structure; and a source / drain structure formed adjacent to the gate structure, wherein the backside via is connected to a back side of the source / drain structure.

[0243] In some other embodiments, the transistor further includes a plurality of channel layers vertically spaced apart from the first side of the semiconductor substrate and each other, wherein the gate structure surrounds the plurality of channel layers.

[0244] In some other embodiments, the waveguide layer is a LiNbO 3 layer.

[0245] In some other embodiments, the width of the waveguide layer is smaller than the width of the semiconductor substrate.

[0246] In some embodiments, a packaging structure is provided, the packaging structure comprising a first chip structure, the first chip structure comprising a first electronic device and a first interconnect structure electrically connected to a front side of the first electronic device. The first chip structure further comprises a first backside via electrically connected to a back side of the first electronic device, and a first waveguide layer overlapping the first electronic device. In addition, the first waveguide layer is closer to the back side of the first electronic device than the front side of the first electronic device. The first chip structure further comprises a plurality of first waveguide components formed above the first waveguide layer, and a first via formed through the first waveguide layer and electrically connected to the first backside via.

[0247] In some other embodiments, the above-mentioned packaging structure also includes an interposer structure, including an interposer substrate; an optical structure formed above the interposer substrate; and an interposer via formed through the interposer substrate, wherein the first chip structure is bonded to the interposer structure.

[0248] In some other embodiments, the packaging structure further includes an input / output chip structure bonded to the interposer structure; and an optical fiber attached to the interposer structure, wherein the first chip structure is a processor chip structure.

[0249] In some other embodiments, the above-mentioned packaging structure also includes a second chip structure attached to the interposer structure, wherein the second chip structure includes a second electronic device; a second interconnect structure electrically connected to the front side of the second electronic device; a second back side via electrically connected to the back side of the second electronic device; a second waveguide layer overlapping the second electronic device; a plurality of second waveguide components formed above the second waveguide layer; and a second via formed through the second waveguide layer and electrically connected to the second back side via, wherein the plurality of first waveguide components, the first waveguide layer and the second waveguide layer are made of LiNbO3, and the plurality of second waveguide components are made of SiN.

[0250] In some other embodiments, the first chip structure further includes a second electronic device, wherein the first interconnect structure is electrically connected to the front side of the second electronic device; and an isolation layer is formed above the first waveguide layer and vertically overlaps the first electronic device and the second electronic device.

[0251] In some other embodiments, the first chip structure further includes a second electronic device, wherein the first interconnect structure is electrically connected to the front side of the second electronic device; and an amorphous silicon layer formed above the first waveguide layer, wherein in the cross-sectional schematic diagram, the width of the amorphous silicon layer is greater than the width of one of the plurality of first waveguide components and less than the width of the first waveguide layer.

[0252] The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the utility model from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the utility model, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the embodiments of the utility model. Various changes, substitutions or modifications can be made to the embodiments of the utility model without departing from the spirit and scope of the embodiments of the utility model.

Claims

1. A packaging structure, characterized in that: include: A first chip structure, wherein the first chip structure comprises: a first electronic device; a first interconnect structure electrically connected to the front side of the first electronic device; a first back-side conductive via electrically connected to the back side of the first electronic device; a first waveguide layer overlapping the first electronic device, wherein the first waveguide layer is closer to the back side of the first electronic device than the front side of the first electronic device; a plurality of first waveguide components formed above the first waveguide layer; as well as A first via is formed through the first waveguide layer and electrically connected to the first backside via.

2. The packaging structure according to claim 1, further comprising: An interposer structure, comprising: an interposer substrate; an optical structure formed above the interposer substrate; and An interposer via is formed through the interposer substrate, wherein the first chip structure is bonded to the interposer structure.

3. The packaging structure according to claim 2, further comprising: an input / output chip structure bonded to the interposer structure; and An optical fiber is attached to the intermediate layer structure, wherein the first chip structure is a processor chip structure.

4. The packaging structure according to claim 2, further comprising: a second chip structure attached to the interposer structure, wherein the second chip structure comprises: a second electronic device; a second interconnect structure electrically connected to the front side of the second electronic device; a second back-side conductive via electrically connected to the back side of the second electronic device; a second waveguide layer overlapping the second electronic device; a plurality of second waveguide components formed above the second waveguide layer; as well as A second via is formed through the second waveguide layer and electrically connected to the second backside via, wherein the plurality of first waveguide components, the first waveguide layer and the second waveguide layer are made of LiNbO3, and the plurality of second waveguide components are made of SiN.

5. The package structure as claimed in claim 1, wherein the first chip structure further comprises: a second electronic device, wherein the first interconnect structure is electrically connected to a front side of the second electronic device; and An isolation layer is formed above the first waveguide layer and vertically overlaps the first electronic device and the second electronic device.

6. The package structure as claimed in claim 1, wherein the first chip structure further comprises: a second electronic device, wherein the first interconnect structure is electrically connected to a front side of the second electronic device; and An amorphous silicon layer is formed on the first waveguide layer, wherein in a cross-sectional view, the width of the amorphous silicon layer is greater than the width of one of the plurality of first waveguide components and smaller than the width of the first waveguide layer. 7 . The packaging structure as claimed in claim 1 , wherein a width of the first waveguide layer is smaller than a width of the first interconnect structure.

8. The package structure according to claim 7, further comprising: A dielectric layer is adjacent to the first waveguide layer.

9. The package structure as claimed in claim 1, wherein the first electronic device comprises: a gate structure; and A source / drain structure is formed adjacent to the gate structure, wherein the first backside via is connected to the backside of the source / drain structure. 10 . The package structure of claim 9 , wherein the first interconnect structure is electrically connected to the gate structure and the source / drain structure.

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