Control circuit of four-switch BUCK-BOOST + LLC converter

Abstract

The embodiment of the utility model discloses a control circuit of a four-switch BUCK-BOOST + LLC converter, in the control circuit, a pulse width modulation controller generates a pulse width modulation control signal to realize closed-loop voltage stabilization control; the pulse width modulation logic control circuit is used for generating an input signal of the BUCK drive circuit and an input signal of the BOOST drive circuit; the peak current sampling circuit is used for collecting a peak current value; the frequency synchronization circuit is used for synchronizing a pulse width modulation signal output by the pulse width modulation controller; the digital control circuit is used for controlling the working mode of the converter, outputting a frequency synchronization signal, outputting a current compensation signal and outputting an LLC driving signal, so that the control of the four-switch BUCK-BOOST + LLC converter is realized, and the working mode is smoothly switched; and a peak current control mode is adopted, so that the circuit has the characteristics of fast transient closed-loop response, fast transient response to the change of input voltage and the change of output load and easy design of a control loop, and also has an instantaneous peak current limiting function.

Description

Technical Field

[0001] The present application relates to the field of electronic circuits, and in particular to a control circuit of a four-switch BUCK-BOOST+LLC converter. Background Art

[0002] The four-switch BUCK-BOOST+LLC converter has attracted much attention due to its wide input range, high efficiency, and input-output isolation. However, there is no proprietary analog controller in the prior art to achieve complete control of the four-switch BUCK-BOOST+LLC converter. Most of the prior art uses digital control, but traditional digital control has an inherent response delay problem. The digital controller usually samples only once per cycle, and the sampling of the previous cycle must respond in the next switching cycle, so short-circuit protection or overcurrent protection cannot be achieved within one cycle. Utility Model Content

[0003] The embodiment of the present application provides a control circuit of a four-switch BUCK-BOOST+LLC converter, which can realize control of the four-switch BUCK-BOOST+LLC converter and improve the response speed.

[0004] The present application provides a control circuit of a four-switch BUCK-BOOST+LLC converter, the control circuit comprising: a pulse width modulation controller, a digital control circuit, a pulse width modulation logic control circuit, a peak current sampling circuit and a frequency synchronization circuit;

[0005] The output end of the pulse width modulation controller is connected to the first input end of the pulse width modulation logic control circuit, the first input end of the pulse width modulation controller is connected to the optical coupler, the second input end of the pulse width modulation controller is connected to the output end of the peak current sampling circuit, and the third input end of the pulse width modulation controller is connected to the output end of the frequency synchronization circuit;

[0006] The first output end of the digital control circuit is connected to the input end of the frequency synchronization circuit, the second output end of the digital control circuit is connected to the second input end of the pulse width modulation logic control circuit, the third output end of the digital control circuit is connected to the third input end of the pulse width modulation logic control circuit, the fourth output end of the digital control circuit is respectively connected to the LLC drive circuit and the synchronous rectification isolation drive circuit, the fifth output end of the digital control circuit is respectively connected to the LLC drive circuit and the synchronous rectification isolation drive circuit, the first input end of the digital control circuit is used to collect the input voltage value, and the second input end of the digital control circuit is used to collect the bus voltage value;

[0007] The first output end of the pulse width modulation logic control circuit is connected to the first input end of the BUCK driving circuit, the second output end of the pulse width modulation logic control circuit is connected to the second input end of the BUCK driving circuit, the third output end of the pulse width modulation logic control circuit is connected to the first input end of the BOOST driving circuit, and the fourth output end of the pulse width modulation logic control circuit is connected to the second input end of the BOOST driving circuit;

[0008] The first input end of the peak current sampling circuit is connected to the sampling resistor, the second input end of the peak current sampling circuit is connected to the sixth output end of the digital control circuit, and the third input end of the peak current sampling circuit is connected to the output end of the pulse width modulation controller.

[0009] Optionally, the pulse width modulation logic control circuit includes an OR gate, an AND gate, a first NOT gate and a second NOT gate;

[0010] The output end of the OR gate is connected to the input end of the first NOT gate, the output end of the AND gate is connected to the input end of the second NOT gate; the first input end of the OR gate is connected to the first input end of the AND gate.

[0011] Optionally, the first input terminal of the AND gate and the first input terminal of the OR gate are connected to the output terminal of the pulse width modulation controller;

[0012] The second input end of the OR gate is connected to the second output end of the digital control circuit, and the second input end of the AND gate is connected to the third output end of the digital control circuit; the output end of the OR gate is connected to the first input end of the BUCK drive circuit; the output end of the AND gate is connected to the first input end of the BOOST drive circuit;

[0013] The output end of the first NOT gate is connected to the second input end of the BUCK driving circuit; the output end of the second NOT gate is connected to the second input end of the BOOST driving circuit.

[0014] Optionally, the frequency synchronization circuit includes a first resistor, a second resistor, a third resistor, a first capacitor and a second capacitor;

[0015] The first end of the first resistor is connected to the reference voltage output end of the pulse width modulation controller, and the second end of the first resistor is connected to the first end of the second resistor and the first end of the first capacitor respectively;

[0016] The second end of the second resistor is connected to the first end of the third resistor, the second end of the first capacitor and the first end of the second capacitor;

[0017] A second end of the third resistor is grounded.

[0018] Optionally, the first end of the first resistor is connected to the third input end of the pulse width modulation controller as the output end of the frequency synchronization circuit;

[0019] The second end of the second capacitor is connected to the first output end of the digital control circuit as an input end of the frequency synchronization circuit.

[0020] Optionally, the peak current sampling circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a third capacitor, a diode, a triode and a third NOT gate;

[0021] The first end of the fourth resistor is connected to the reference voltage output end of the pulse width modulation controller; the second end of the fourth resistor is connected to the first end of the seventh resistor and the collector of the transistor respectively;

[0022] The second end of the seventh resistor is respectively connected to the first end of the third capacitor, the second end of the fifth resistor and the second end of the sixth resistor;

[0023] The cathode of the diode is connected to the first end of the fifth resistor; the output end of the third NOT gate is connected to the base of the transistor; the emitter of the transistor and the second end of the third capacitor are grounded.

[0024] Optionally, the second end of the seventh resistor is connected to the second input end of the pulse width modulation controller as the output end of the peak current sampling circuit;

[0025] The anode of the diode is connected to the sixth output terminal of the digital control circuit as the second input terminal of the peak current sampling circuit; the first end of the sixth resistor is connected to the first end of the sampling resistor as the first input terminal of the peak current sampling circuit;

[0026] The input end of the third NOT gate is connected to the output end of the pulse width modulation controller as the third input end of the peak current sampling circuit.

[0027] Optionally, the digital control circuit includes an input voltage sampling circuit and a bus voltage sampling circuit;

[0028] The input voltage sampling circuit is used to collect the input voltage value;

[0029] The bus voltage sampling circuit is used to collect the bus voltage value.

[0030] Optionally, when the input voltage value is greater than the bus voltage value, the output duty cycle of the second output terminal of the digital control circuit is a pulse width modulation signal of 10%, and the output duty cycle of the third output terminal of the digital control circuit is a pulse width modulation signal of 10%; the pulse width modulation signal at the first input terminal of the BUCK drive circuit is the same as the pulse width modulation signal at the output terminal of the pulse width modulation controller, and the duty cycle of the pulse width modulation signal at the first input terminal of the BOOST drive circuit is 10%; the output of the fifth output terminal of the digital control circuit is a low level.

[0031] Optionally, when the input voltage value is less than the bus voltage value, the output duty cycle of the second output terminal of the digital control circuit is a pulse width modulation signal of 90%, and the output duty cycle of the third output terminal of the digital control circuit is a pulse width modulation signal of 90%; the pulse width modulation signal at the first input terminal of the BOOST drive circuit is the same as the pulse width modulation signal at the output terminal of the pulse width modulation controller, and the duty cycle of the pulse width modulation signal at the first input terminal of the BUCK drive circuit is 90%; the output of the fifth output terminal of the digital control circuit is a high level.

[0032] The embodiment of the present application discloses a control circuit of a four-switch BUCK-BOOST+LLC converter, in which a pulse width modulation controller generates a pulse width modulation control signal to realize closed-loop voltage stabilization control; a pulse width modulation logic control circuit is used to generate an input signal of a BUCK drive circuit and an input signal of a BOOST drive circuit; a peak current sampling circuit is used to collect a peak current value; a frequency synchronization circuit is used to synchronize the pulse width modulation signal output by the pulse width modulation controller; a digital control circuit is used to control the working mode of the converter, output a frequency synchronization signal, an output current compensation signal, and an output LLC drive signal, thereby realizing control of the four-switch BUCK-BOOST+LLC converter and smoothly switching the working mode; and a peak current control mode is adopted, which has the characteristics of fast transient closed-loop response, fast transient response to changes in input voltage and changes in output load, easy control loop design, and instantaneous peak current limiting function. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1A circuit diagram of a control circuit of a four-switch BUCK-BOOST+LLC converter provided in an embodiment of the present application;

[0035] Figure 2 A circuit diagram of a pulse width modulation logic control provided in an embodiment of the present application;

[0036] Figure 3 A circuit diagram of a frequency synchronization circuit provided in an embodiment of the present application;

[0037] Figure 4 A circuit diagram of a peak current sampling circuit provided in an embodiment of the present application;

[0038] Figure 5 A waveform diagram of a four-switch BUCK-BOOST+LLC converter in BUCK mode provided in an embodiment of the present application;

[0039] Figure 6 A waveform diagram of a four-switch BUCK-BOOST+LLC converter in BOOST mode provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The embodiment of the present application provides a control circuit of a four-switch BUCK-BOOST+LLC converter, which can realize the control of the four-switch BUCK-BOOST converter and the LLC converter and improve the response speed.

[0041] For ease of understanding, the application scenarios of the embodiments of the present application are first introduced.

[0042] As energy crisis and environmental problems become increasingly serious, fuel cells have become one of the most promising energy technologies in distributed power systems and electric vehicles due to their energy security, environmental affinity, fuel diversity and other advantages. Lithium-ion overcharge or undercharge requires a DC-DC converter with a wide input range to improve output characteristics. Electric vehicle power battery packs also require on-board DC-DC converters with a wide input voltage range. In these applications, the isolation, efficiency and parameter optimization of wide voltage range DC-DC converters must be considered. Therefore, it is of great significance to study DC-DC converters with a wide input voltage range and high efficiency.

[0043] The four-switch BUCK-BOOST+LLC converter has attracted much attention due to its wide input range, high efficiency, and input-output isolation. However, there is no proprietary analog controller in the prior art to achieve complete control of the four-switch BUCK-BOOST+LLC converter. At present, digital control is mostly used, but traditional digital control has an inherent response delay problem. Digital controllers usually only sample once per cycle, and the sampling of the previous cycle must respond in the next switching cycle. Therefore, there is a delay problem compared to analog control, and short-circuit protection or overcurrent protection cannot be achieved within one cycle.

[0044] Analog control methods are mainly divided into voltage mode and current mode. The voltage mode mainly includes an error amplifier and a logic circuit. The two input ends of the error amplifier receive the output voltage sampling signal and the reference signal respectively. The output signal is compared with the sawtooth wave signal, and then a switch control signal is generated through the logic circuit. This circuit requires the addition of a more complex compensation circuit, and the dynamic response is very slow.

[0045] Therefore, the embodiment of the present application proposes a control circuit of a four-switch BUCK-BOOST+LLC converter. The control circuit can not only well realize the control of the four-switch BUCK-BOOST+LLC converter, but also the working mode of the BUCK-BOOST converter can be smoothly switched. Moreover, the peak current control mode is adopted, and the circuit has the characteristics of fast transient closed-loop response, fast transient response to changes in input voltage and output load, easy control loop design, etc., and has the function of instantaneous peak current limiting.

[0046] See also Figure 1 , which is a circuit diagram of a control circuit of a four-switch BUCK-BOOST+LLC converter provided in an embodiment of the present application. The control circuit includes: a pulse width modulation (PWM) controller (hereinafter referred to as: PWM controller), a digital (Micro Control Unit, MCU) control circuit (hereinafter referred to as: MCU control circuit), a pulse width modulation (PWM) logic control circuit (hereinafter referred to as: PWM logic control circuit), a peak current sampling circuit and a frequency synchronization circuit. Among them, the four-switch BUCK-BOOST+LLC converter is a four-switch BUCK-BOOST+LLC converter.

[0047] The PWM controller is provided with a first input terminal COMP, a second input terminal CS, a third input terminal RTCT and an output terminal OUT. The PWM logic control circuit is provided with a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, a third output terminal and a fourth output terminal. The MCU control circuit is provided with a first input terminal, a second input terminal, a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal and a sixth output terminal. The peak current sampling circuit is provided with a first input terminal, a second input terminal, a third output terminal and an output terminal. The frequency synchronization circuit is provided with an input terminal and an output terminal.

[0048] The output end of the PWM controller is connected to the first input end of the PWM logic control circuit; the first input end of the PWM controller is connected to the output end of the optocoupler; the second input end of the PWM controller is connected to the output end of the peak current sampling circuit; the third input end of the PWM controller is connected to the output end of the frequency synchronization circuit, wherein the optocoupler is used to achieve optocoupler isolation.

[0049] Specifically, the COMP signal at the first input terminal of the PWM controller and the CS signal at the second input terminal of the PWM controller are sent to the PWM comparator inside the PWM controller to generate a PWM control signal. The on-time of the PWM control signal is determined by the third input terminal RTCT of the PWM controller, that is, when each frequency synchronization signal arrives, the PWM signal will change from a low level to a high level, which is the on-time of each cycle PWM, and the off-time is compared by the COMP signal and the CS signal. When the CS signal is equal to the COMP signal, the PWM signal is turned off, thereby realizing the closed-loop voltage regulation control of the converter.

[0050] The MCU control circuit specifically includes an MCU controller, an input voltage sampling circuit and a bus voltage sampling circuit. The first output end of the MCU control circuit is connected to the input end of the frequency synchronization circuit; the second output end of the MCU control circuit is connected to the second input end of the PWM logic control circuit; the third output end of the MCU control circuit is connected to the third input end of the PWM logic control circuit; the fourth output end of the MCU control circuit is respectively connected to the LLC drive circuit and the synchronous rectification isolation drive circuit, and the fifth output end of the MCU control circuit is respectively connected to the LLC drive circuit and the synchronous rectification isolation drive circuit; the first input end of the MCU controller is connected to the input voltage sampling circuit; the second input end of the MCU controller is connected to the bus voltage sampling circuit.

[0051] A first output end of the PWM logic control circuit is connected to a first input end of the BUCK driving circuit, a second output end of the PWM logic control circuit is connected to a second input end of the BUCK driving circuit, a third output end of the PWM logic control circuit is connected to a first input end of the BOOST driving circuit, and a fourth output end of the PWM logic control circuit is connected to a second input end of the BOOST driving circuit; the PWM logic control circuit is used to perform a logic operation on an output of the PWM controller and an output of the MCU control circuit to generate a BUCK driving circuit input signal and a BOOST driving circuit input signal.

[0052] Specifically, the first input terminal of the MCU control circuit collects the input voltage value V through the input voltage sampling circuit. in The second input terminal of the MCU control circuit collects the bus voltage value V through the bus voltage sampling circuit bus When the input voltage V in Greater than bus voltage V bus When the PWM signal is turned on, the second output terminal of the MCU control circuit outputs a PWM signal with a duty cycle of 10%, and the third output terminal of the MCU control circuit outputs a PWM signal with a duty cycle of 10%. After passing through the PWM logic control circuit, the PWM signal output to the first input terminal of the BUCK drive circuit is the same as the PWM signal output by the PWM controller, and the PWM signal output to the first input terminal of the BOOST drive circuit has a duty cycle of 10%. At the same time, the fifth output terminal of the MCU control circuit outputs a low level signal.

[0053] When the input voltage V in Less than bus voltage V bus When the PWM signal is turned on, the second output terminal of the MCU control circuit outputs a PWM signal with a duty cycle of 90%, and the third output terminal of the MCU control circuit outputs a PWM signal with a duty cycle of 90%. After passing through the PWM logic control circuit, the PWM signal output to the first input terminal of the BOOST drive circuit is the same as the PWM signal output by the PWM controller, and the PWM signal output to the first input terminal of the BUCK drive circuit has a duty cycle of 90%. At the same time, the fifth output terminal of the MCU control circuit outputs a high level signal.

[0054] The first input terminal of the peak current sampling circuit is connected to the sampling resistor Rs, the second input terminal of the peak current sampling circuit is connected to the sixth output terminal of the MCU control circuit, and the third input terminal of the peak current sampling circuit is connected to the output terminal of the PWM controller.

[0055] In one implementation of the embodiment of the present application, Figure 2 As shown, this figure is a circuit diagram of a pulse width modulation logic control provided for an embodiment of the present application. The PWM logic control circuit includes an OR gate U1, an AND gate U2, a first NOT gate U3 and a second NOT gate U4.

[0056] The output of U1 is connected to the input of U3, and the output of U2 is connected to the input of U4; the first input of U1 is connected to the first input of U2. The first input of U2 and the first input of U1 are connected to the output of the PWM controller as the first input of the PWM logic control circuit; the second input of U1 is connected to the second output of the MCU control circuit, and the second input of U2 is connected to the third output of the MCU control circuit; the output of U1 is connected to the first input of the BUCK drive circuit; the output of U2 is connected to the first input of the BOOST drive circuit; the output of U3 is connected to the second input of the BUCK drive circuit; the output of U4 is connected to the second input of the BOOST drive circuit. Among them, the output of U1 is complementary to the output of U3, and the output of U2 is complementary to the output of U4. The complementary relationship is that the levels are symmetrically opposite, for example, U1 is high level and U3 is low level.

[0057] Specifically, when the input voltage value V in Greater than bus voltage V bus When the PWM signal is on, the second output terminal of the MCU control circuit outputs a PWM signal with a duty cycle of 10%, the third output terminal of the MCU control circuit outputs a PWM signal with a duty cycle of 10%, the duty cycle of the PWM signal output by the PWM controller is greater than 10% and less than 90%, after the PWM signal output by the second output terminal of the MCU control circuit and the PWM signal output by the PWM controller are compared by U1, the PWM signal output by U1 is the same as the PWM signal output by the PWM controller, that is, the PWM signal output to the first input terminal of the BUCK drive circuit is the same as the PWM signal output by the PWM controller, and after the PWM signal output by U1 passes through U3, the PWM signal output by U3 is complementary to the PWM signal output by U1. After the PWM signal output from the third output terminal of the MCU control circuit is compared with the PWM signal output from the PWM controller by U2, the PWM signal output from U2 is the same as the PWM signal output from the third output terminal of the MCU control circuit, and the duty cycle is 10%, that is, the duty cycle of the PWM signal output to the first input terminal of the BOOST drive circuit is 10%. After the PWM signal output from U2 passes through U4, the PWM signal output from U4 is complementary to the PWM signal output from U2, that is, the duty cycle of the PWM signal output to the second input terminal of the BOOST drive circuit is 90%. At this time, the converter works in BUCK mode, the duty cycle of the BUCK drive circuit is determined by the output of the PWM controller, the duty cycle of the BOOST drive circuit is fixed at 10%, and the gain of the BUCK-BOOST converter is:

[0058]

[0059] Among them, Dbuck is the duty cycle of the BUCK drive circuit, D boost is the duty cycle of the BOOST drive circuit, D PWM It is the duty cycle of the PWM signal output by the PWM controller.

[0060] When the input voltage V in Less than bus voltage V bus When the PWM signal is on, the second output terminal of the MCU control circuit outputs a PWM signal with a duty cycle of 90%, the third output terminal of the MCU control circuit outputs a PWM signal with a duty cycle of 90%, the duty cycle of the PWM signal output by the PWM controller is greater than 10% and less than 90%, and after the PWM signal output by the third output terminal of the MCU control circuit and the PWM signal output by the PWM controller are compared by U2, the PWM signal output by U2 is the same as the PWM signal output by the PWM controller, that is, the PWM signal output to the first input terminal of the BOOST drive circuit is the same as the PWM signal output by the PWM controller, and after the PWM signal output by U2 passes through U4, the PWM signal output by U4 is complementary to the PWM signal output by U2. After the PWM signal output from the second output terminal of the MCU control circuit is compared with the PWM signal output from the PWM controller by U1, the PWM signal output from U1 is the same as the PWM signal output from the second output terminal of the MCU control circuit, and the duty cycle is 90%, that is, the duty cycle of the PWM signal output to the first input terminal of the BUCK drive circuit is 90%. After the PWM signal output from U1 passes through U3, the PWM signal output from U3 is complementary to the PWM signal output from U1, that is, the duty cycle of the PWM signal output to the second input terminal of the BUCK drive circuit is 10%. At this moment, the converter works in BOOST mode, the duty cycle of the BOOST drive circuit is determined by the output of the PWM controller, the duty cycle of the BUCK circuit is fixed at 90%, and the gain of the BUCK-BOOST converter is:

[0061]

[0062] Among them, D buck is the duty cycle of the BUCK drive circuit, D boost is the duty cycle of the BOOST drive circuit, D PWM It is the duty cycle of the PWM signal output by the PWM controller.

[0063] In the embodiment of the present application, the PWM controller may adopt a single-ended current mode PWM controller, which is more commonly used, inexpensive, and can be domestically designed.

[0064] In one implementation of the embodiment of the present application, Figure 3As shown, this figure is a circuit diagram of a frequency synchronization circuit provided in an embodiment of the present application. The frequency synchronization circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1 and a second capacitor C2.

[0065] The first end of R1 is connected to the reference voltage output terminal VREF of the PWM controller, the second end of R1 is connected to the first end of R2 and the first end of C1 respectively; the second end of R2 is connected to the first end of R3, the second end of C1 and the first end of C2; the second end of R3 is grounded. The first end of R1 is connected to the third input terminal of the PWM controller as the output terminal of the frequency synchronization circuit; the second end of C2 is connected to the first output terminal of the MCU control circuit as the input terminal of the frequency synchronization circuit.

[0066] In one implementation of the embodiment of the present application, Figure 4 As shown, this figure is a circuit diagram of a peak current sampling circuit provided in an embodiment of the present application. The peak current sampling circuit includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a third capacitor C3, a diode D1, a transistor Q1 and a third NOT gate U5.

[0067] The first end of R4 is connected to VREF; the second end of R4 is respectively connected to the first end of R7 and the collector of Q1; the second end of R7 is respectively connected to the first end of C3, the second end of R5 and the second end of R6; the negative end of D1 is connected to the first end of R5; the output end of U5 is connected to the base of Q1; the emitter of Q1 and the second end of C3 are grounded. The second end of R7 is connected to the second input end of the PWM controller as the output end of the peak current sampling circuit; the positive end of D1 is connected to the sixth output end of the MCU control circuit as the second input end of the peak current sampling circuit; the first end of T6 is connected to the first end of the sampling resistor as the first input end of the peak current sampling circuit; the input end of U5 is connected to the output end of the PWM controller as the third input end of the peak current sampling circuit.

[0068] Specifically, the first input terminal of the peak current sampling circuit collects the current value and sends it to the output terminal of the peak current sampling circuit through R6. The output terminal of the peak current sampling circuit is connected to the second input terminal of the PWM controller. The COMP signal of the first input terminal of the PWM controller and the CS signal of the second input terminal are sent to the PWM comparator inside the PWM controller to generate a PWM control signal. When the PWM signal output by the PWM controller is high, it changes to a low level through U5, Q1 is in the off state, and the current waveform at the output terminal of the peak current sampling circuit gradually rises; when the PWM signal output by the PWM controller changes to a low level, it changes to a high level through U5, Q1 changes from off to on, C3 discharges through R7, and the current waveform at the output terminal of the peak current sampling circuit gradually decreases.

[0069] When the input voltage V in Greater than bus voltage V bus When the converter works in BUCK mode, the second input terminal of the peak current sampling circuit is at a low level, D1 is in a cut-off state, and the output waveform of the peak current sampling circuit is only determined by the sampling signal of the first input terminal of the peak current sampling circuit.

[0070] When the input voltage V in Less than bus voltage V bus When the converter works in BOOST mode, the second input terminal of the peak current sampling circuit is high level, D1 is in the on state, and the high level signal output by the sixth output terminal of the MCU control circuit is compensated by R5 for the output waveform of the peak current sampling circuit. C3 is used to filter the high-frequency noise of the current waveform.

[0071] like Figure 5 As shown, this figure is a waveform diagram of a four-switch BUCK-BOOST+LLC converter in BUCK mode provided in an embodiment of the present application, including a peak current waveform, a BUCK drive waveform, and a BOOST drive waveform of the four-switch BUCK-BOOST+LLC converter in BUCK mode.

[0072] When the input voltage V in Greater than bus voltage V bus When , the converter works in BUCK mode. Figure 5 As shown, in BUCK mode, the duty cycle of the BOOST drive circuit is fixed at 10%. The duty cycle of the BUCK drive circuit is determined by the output of the PWM controller. The output of the PWM controller is generated by the PWM comparator inside the PWM controller, which is sent by the first input terminal COMP signal of the PWM controller and the second input terminal CS signal. When the CS signal is equal to the COMP signal, the PWM signal is turned off.

[0073] like Figure 6 As shown, the figure is a waveform schematic diagram of a four-switch BUCK-BOOST+LLC converter in BOOST mode provided in an embodiment of the present application, including a peak current waveform, a BUCK drive waveform, and a BOOST drive waveform of the four-switch BUCK-BOOST+LLC converter in BOOST mode.

[0074] like Figure 6 As shown, when the input voltage value V in Less than bus voltage V bus, the converter works in BOOST mode. In BOOST mode, the duty cycle of the BUCK drive circuit is fixed at 90%, and the duty cycle of the BOOST drive circuit is determined by the output of the PWM controller. The output of the PWM controller is generated by the PWM comparator inside the PWM controller, which is sent by the first input terminal COMP signal of the PWM controller and the second input terminal CS signal. When the CS signal is equal to the COMP signal, the PWM signal is turned off.

[0075] When the input voltage V in and bus voltage value V bus In order to avoid frequent mode, a hysteresis voltage is usually set. If the converter switches from BOOST mode to BUCK mode, only when V in >V bus +ΔV, the switching operation will be performed; similarly, if the converter switches from BUCK mode to BOOST mode, it will only be switched when V in <V bus -ΔV, the switching operation will be performed, where ΔV is the hysteresis voltage.

[0076] The embodiment of the present application discloses a control circuit of a four-switch BUCK-BOOST+LLC converter, in which a pulse width modulation controller generates a pulse width modulation control signal to realize closed-loop voltage stabilization control; a pulse width modulation logic control circuit is used to generate an input signal of a BUCK drive circuit and an input signal of a BOOST drive circuit; a peak current sampling circuit is used to collect a peak current value; a frequency synchronization circuit is used to synchronize the pulse width modulation signal output by the pulse width modulation controller; a digital control circuit is used to control the working mode of the converter, output a frequency synchronization signal, an output current compensation signal, and an output LLC drive signal, thereby realizing control of the four-switch BUCK-BOOST+LLC converter and smoothly switching the working mode; and a peak current control mode is adopted, which has the characteristics of fast transient closed-loop response, fast transient response to changes in input voltage and changes in output load, easy control loop design, and instantaneous peak current limiting function.

[0077] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0078] The above specific implementation methods further describe in detail the purpose, technical solutions and beneficial effects of the present utility model. It should be understood that the above are only specific implementation methods of the present utility model.

[0079] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A control circuit for a four-switch BUCK-BOOST+LLC converter, characterized in that: The control circuit includes: a pulse width modulation controller, a digital control circuit, a pulse width modulation logic control circuit, a peak current sampling circuit and a frequency synchronization circuit; The output end of the pulse width modulation controller is connected to the first input end of the pulse width modulation logic control circuit, the first input end of the pulse width modulation controller is connected to the optical coupler, the second input end of the pulse width modulation controller is connected to the output end of the peak current sampling circuit, the third input end of the pulse width modulation controller is connected to the output end of the frequency synchronization circuit, and the pulse width modulation controller is used to generate a pulse width modulation control signal; The first output end of the digital control circuit is connected to the input end of the frequency synchronization circuit, the second output end of the digital control circuit is connected to the second input end of the pulse width modulation logic control circuit, the third output end of the digital control circuit is connected to the third input end of the pulse width modulation logic control circuit, the fourth output end of the digital control circuit is respectively connected to the LLC drive circuit and the synchronous rectification isolation drive circuit, the fifth output end of the digital control circuit is respectively connected to the LLC drive circuit and the synchronous rectification isolation drive circuit, the first input end of the digital control circuit is used to collect the input voltage value, the second input end of the digital control circuit is used to collect the bus voltage value, the digital control circuit is used to control the working mode of the BUCK-BOOST converter, the digital control circuit is also used to output a frequency synchronization signal, a current compensation signal and an LLC drive signal, and the frequency synchronization circuit is used to synchronize the pulse width modulation control signal output by the pulse width modulation controller; The first output end of the pulse width modulation logic control circuit is connected to the first input end of the BUCK driving circuit, the second output end of the pulse width modulation logic control circuit is connected to the second input end of the BUCK driving circuit, the third output end of the pulse width modulation logic control circuit is connected to the first input end of the BOOST driving circuit, and the fourth output end of the pulse width modulation logic control circuit is connected to the second input end of the BOOST driving circuit; the pulse width modulation logic control circuit is used to perform a logic operation on the output of the pulse width modulation controller and the output of the digital control circuit to generate the BUCK driving circuit input signal and the BOOST driving circuit input signal; The first input end of the peak current sampling circuit is connected to the sampling resistor, the second input end of the peak current sampling circuit is connected to the sixth output end of the digital control circuit, and the third input end of the peak current sampling circuit is connected to the output end of the pulse width modulation controller; the peak current sampling circuit is used to collect the peak current value of the BUCK-BOOST converter.

2. The control circuit according to claim 1, characterized in that: The pulse width modulation logic control circuit includes an OR gate, an AND gate, a first NOT gate and a second NOT gate; The output end of the OR gate is connected to the input end of the first NOT gate, the output end of the AND gate is connected to the input end of the second NOT gate; the first input end of the OR gate is connected to the first input end of the AND gate.

3. The control circuit according to claim 2, characterized in that: The first input terminal of the AND gate and the first input terminal of the OR gate are connected to the output terminal of the pulse width modulation controller; The second input end of the OR gate is connected to the second output end of the digital control circuit, and the second input end of the AND gate is connected to the third output end of the digital control circuit; the output end of the OR gate is connected to the first input end of the BUCK drive circuit; the output end of the AND gate is connected to the first input end of the BOOST drive circuit; The output end of the first NOT gate is connected to the second input end of the BUCK driving circuit; the output end of the second NOT gate is connected to the second input end of the BOOST driving circuit.

4. The control circuit according to claim 1, characterized in that: The frequency synchronization circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor and a second capacitor; The first end of the first resistor is connected to the reference voltage output end of the pulse width modulation controller, and the second end of the first resistor is connected to the first end of the second resistor and the first end of the first capacitor respectively; The second end of the second resistor is connected to the first end of the third resistor, the second end of the first capacitor and the first end of the second capacitor; A second end of the third resistor is grounded.

5. The control circuit according to claim 4, characterized in that: The first end of the first resistor is connected to the third input end of the pulse width modulation controller as the output end of the frequency synchronization circuit; The second end of the second capacitor is connected to the first output end of the digital control circuit as an input end of the frequency synchronization circuit.

6. The control circuit according to claim 1, characterized in that: The peak current sampling circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a third capacitor, a diode, a triode and a third NOT gate; The first end of the fourth resistor is connected to the reference voltage output end of the pulse width modulation controller; the second end of the fourth resistor is connected to the first end of the seventh resistor and the collector of the transistor respectively; The second end of the seventh resistor is respectively connected to the first end of the third capacitor, the second end of the fifth resistor and the second end of the sixth resistor; The cathode of the diode is connected to the first end of the fifth resistor; the output end of the third NOT gate is connected to the base of the transistor; the emitter of the transistor and the second end of the third capacitor are grounded.

7. The control circuit according to claim 6, characterized in that: The second end of the seventh resistor is connected to the second input end of the pulse width modulation controller as the output end of the peak current sampling circuit; The anode of the diode is connected to the sixth output terminal of the digital control circuit as the second input terminal of the peak current sampling circuit; the first end of the sixth resistor is connected to the first end of the sampling resistor as the first input terminal of the peak current sampling circuit; The input end of the third NOT gate is connected to the output end of the pulse width modulation controller as the third input end of the peak current sampling circuit.

8. The control circuit according to claim 1, characterized in that: The digital control circuit includes an input voltage sampling circuit and a bus voltage sampling circuit; The input voltage sampling circuit is used to collect the input voltage value; The bus voltage sampling circuit is used to collect the bus voltage value.

9. The control circuit according to claim 8, characterized in that: When the input voltage value is greater than the bus voltage value, the second output terminal of the digital control circuit outputs a pulse width modulation signal with a duty cycle of 10%, and the third output terminal of the digital control circuit outputs a pulse width modulation signal with a duty cycle of 10%; the pulse width modulation signal at the first input terminal of the BUCK drive circuit is the same as the pulse width modulation signal at the output terminal of the pulse width modulation controller, and the duty cycle of the pulse width modulation signal at the first input terminal of the BOOST drive circuit is 10%; The output of the fifth output terminal of the digital control circuit is a low level.

10. The control circuit according to claim 9, characterized in that: When the input voltage value is less than the bus voltage value, the output duty cycle of the second output terminal of the digital control circuit is a pulse width modulation signal of 90%, and the output duty cycle of the third output terminal of the digital control circuit is a pulse width modulation signal of 90%; the pulse width modulation signal of the first input terminal of the BOOST drive circuit is the same as the pulse width modulation signal of the output terminal of the pulse width modulation controller, and the duty cycle of the pulse width modulation signal of the first input terminal of the BUCK drive circuit is 90%; the output of the fifth output terminal of the digital control circuit is a high level.

Images