Dynamic bias circuit and discrete time circuit using same

Abstract

The utility model provides a dynamic bias circuit and a discrete time circuit using the dynamic bias circuit. The dynamic bias circuit comprises a first switch S11, a second switch S12, a third switch S21, a fourth switch S22, a fifth switch S23, a pre-charging current source I1, a bias current source I2, a first pre-charging capacitor Cs1, a second pre-charging capacitor Cs2, a first MOS tube MN1 and a second MOS tube MN2. Compared with the prior art, the problem that a traditional dynamic bias technology is slow in starting is solved, by improving the bias circuit, the power consumption of the operational amplifier can be increased in a short time, the starting speed of the operational amplifier is greatly increased, and therefore a discrete time circuit formed by the operational amplifier can work at a higher frequency.

Description

[Technical field]

[0001] The utility model relates to the technical field of circuit design, in particular to a dynamic bias circuit and a discrete time circuit using the dynamic bias circuit. [Background technology]

[0002] Dynamic bias technology is widely used in discrete time circuits. Take the discrete time integrator as an example: the working cycle of the integrator is mainly divided into the sampling cycle and the integration cycle. During the sampling cycle, the output of the op amp inside the integrator does not change. Only during the integration cycle does the output of the op amp need to have a slew rate to drive the load capacitor to change the output voltage. This means that the power consumption of the op amp during the sampling cycle can be much lower than that during the integration cycle. Therefore, the traditional way is to control the switch during the sampling cycle to make the power consumption of the op amp lower during this cycle, and then make the power consumption of the op amp higher during the integration cycle.

[0003] The problem is that it is easy to reduce the power consumption of an op amp (operational amplifier) ​​at a general switching moment, but it is difficult to increase the power consumption of an op amp instantly. This is because the bias circuit of the op amp has a lot of parasitic capacitance, and if the current of the op amp increases, it means that the bias voltage on the bias circuit will increase, which means that the bias circuit has a current to charge the capacitor, so that the bias voltage can eventually increase. This limits the operating frequency of the discrete time integrator, because the operating frequency must be low enough to wait for the power consumption of the op amp to increase, so that the op amp can have enough slew rate during the integration period.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above problems. [Contents of the utility model]

[0005] One of the purposes of the utility model is to provide a dynamic bias circuit and a discrete time circuit using the dynamic bias circuit, which can provide a bias current that increases instantaneously.

[0006] According to one aspect of the utility model, the utility model provides a dynamic bias circuit, which includes a first switch S11, a second switch S12, a third switch S21, a fourth switch S22, a fifth switch S23, a pre-charge current source I1, a bias current source I2, a first pre-charge capacitor Cs1, a second pre-charge capacitor Cs2, a first MOS transistor MN1 and a second MOS transistor MN2, wherein the input end of the pre-charge current source I1 is connected to the power supply end, and the output end thereof is connected to the first connection end of the first switch S11, the second connection end of the first switch S11 is connected to the first connection end of the second pre-charge capacitor Cs2, and the second connection end of the second pre-charge capacitor Cs2 is grounded; the first connection end of the second switch S12 is connected to the output end of the pre-charge current source I1, and the second connection end thereof is connected to the first connection end of the first pre-charge capacitor Cs1, and the first pre-charge current source I1 is connected to the first connection end of the first pre-charge capacitor Cs1. The second connection end of the charging capacitor Cs1 is grounded; the first connection end of the third switch S21 is connected to the first connection end of the second pre-charging capacitor Cs2, and the second connection end thereof is connected to the connection node A; the input end of the bias current source I2 is connected to the power supply end, and the output end thereof is connected to the first connection end of the fourth switch S22, and the second connection end of the fourth switch S22 is connected to the connection node B; the first connection end of the fifth switch S23 is connected to the first connection end of the first pre-charging capacitor Cs1, and the second connection end thereof is connected to the connection node B; the first connection end of the first MOS transistor MN1 is connected to the connection node B, the second connection end thereof is grounded, and the control end thereof is connected to the first connection end thereof; the first connection end of the second MOS transistor MN2 is connected to the connection node A, the second connection end thereof is grounded, and the control end thereof is connected to the control end of the first MOS transistor MN1.

[0007] Further, when the first switch S11 and the second switch S12 are controlled to be turned on, the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned off; when the first switch S11 and the second switch S12 are controlled to be turned off, the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned on.

[0008] Furthermore, the first MOS transistor MN1 is an NMOS transistor, and the first connection end, the second connection end and the control end of the first MOS transistor MN1 are respectively the drain, the source and the gate of the NMOS transistor; the second MOS transistor MN2 is an NMOS transistor, and the first connection end, the second connection end and the control end of the second MOS transistor MN2 are respectively the drain, the source and the gate of the NMOS transistor.

[0009] Further, the third switch S21 is an NMOS transistor, and the first connection end, the second connection end and the control end of the third switch S21 are respectively the drain, the source and the gate of the NMOS transistor; the fourth switch S22 is an NMOS transistor, and the first connection end, the second connection end and the control end of the fourth switch S22 are respectively the drain, the source and the gate of the NMOS transistor; the fifth switch S23 is an NMOS transistor, and the first connection end, the second connection end and the control end of the fifth switch S23 are respectively the drain, the source and the gate of the NMOS transistor.

[0010] Further, a first parasitic capacitor Cp1 is formed between the control end and the ground end of the first MOS transistor MN1, and a second parasitic capacitor Cp2 is formed between the first connection end and the ground end of the second MOS transistor MN2. When the first switch S11 and the second switch S12 are controlled to be turned on, and the third switch S21, the fourth switch S22, and the fifth switch S23 are controlled to be turned off, the pre-charging current source I1 pre-charges the first pre-charging capacitor Cs1 and the second pre-charging capacitor Cs2; when the first switch S11 and the second switch S12 are controlled to be turned off, and the third switch S21, the fourth switch S22, and the fifth switch S23 are controlled to be turned on, the charge of the first pre-charging capacitor Cs1 will be shared with the first parasitic capacitor Cp1, and the charge of the second pre-charging capacitor Cs2 will be shared with the second parasitic capacitor Cp2.

[0011] Furthermore, the connection node A is connected to a current mirror, and the connection node A provides a bias current to the current mirror.

[0012] According to another aspect of the utility model, the utility model provides a discrete time circuit, which includes the dynamic bias circuit as described in the utility model.

[0013] Further, the discrete time circuit is a discrete time integrator; a working cycle of the discrete time integrator includes a sampling cycle and an integration cycle; in a working cycle, during the sampling cycle, the first switch S11 and the second switch S12 are controlled to be turned on, and the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned off, and during the integration cycle, the first switch S11 and the second switch S12 are controlled to be turned off, and the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned on.

[0014] Compared with the prior art, the utility model solves the problem of slow start-up of the traditional dynamic bias technology, and can provide an instantaneously increased bias current by improving the bias circuit.

Brief Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0016] Figure 1 FIG. 4 is a circuit diagram of a dynamic bias circuit in one embodiment of the present invention. [Specific implementation method]

[0017] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0018] The "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the utility model. The "in one embodiment" that appears in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words "coupled", "connected", "connected", "connected", "connected" and the like that indicate electrical connection in this document all indicate direct or indirect connection. For example, A is connected to B, which includes both direct electrical connection between A and B and connection between A and B through electrical components or circuits.

[0019] In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0020] Please refer to Figure 1 As shown, it is a circuit diagram of a dynamic bias circuit in one embodiment of the utility model. Figure 1 The dynamic bias circuit shown includes a first switch S11, a second switch S12, a third switch S21, a fourth switch S22, a fifth switch S23, a pre-charge current source I1, a bias current source I2, a first pre-charge capacitor Cs1, a second pre-charge capacitor Cs2, a first MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) MN1 and a second MOS transistor MN2.

[0021] Among them, the input end of the pre-charging current source I1 is connected to the power supply end Vdd, and the output end thereof is connected to the first connection end of the first switch S11, the second connection end of the first switch S11 is connected to the first connection end of the second pre-charging capacitor Cs2, and the second connection end of the second pre-charging capacitor Cs2 is grounded; the first connection end of the second switch S12 is connected to the output end of the pre-charging current source I1, and the second connection end thereof is connected to the first connection end of the first pre-charging capacitor Cs1, and the second connection end of the first pre-charging capacitor Cs1 is grounded; the first connection end of the third switch S21 is connected to the first connection end of the second pre-charging capacitor Cs2, and the second connection end thereof is connected to the connection node A is connected to the bias current source I2; the input end of the bias current source I2 is connected to the power supply end Vdd, and the output end thereof is connected to the first connection end of the fourth switch S22, and the second connection end of the fourth switch S22 is connected to the connection node B; the first connection end of the fifth switch S23 is connected to the first connection end of the first pre-charge capacitor Cs1, and the second connection end thereof is connected to the connection node B; the first connection end of the first MOS transistor MN1 is connected to the connection node B, the second connection end thereof is grounded, and the control end thereof is connected to the first connection end thereof; the first connection end of the second MOS transistor MN2 is connected to the connection node A, the second connection end thereof is grounded, and the control end thereof is connected to the control end of the first MOS transistor MN1.

[0022] exist Figure 1 In the specific embodiment shown, the first MOS transistor MN1 is an NMOS (N-Metal-Oxide-Semiconductor) transistor, and the first connection terminal, the second connection terminal and the control terminal of the first MOS transistor MN1 are respectively the drain, the source and the gate of the NMOS transistor; the second MOS transistor MN2 is an NMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the second MOS transistor MN2 are respectively the drain, the source and the gate of the NMOS transistor.

[0023] exist Figure 1 In the specific embodiment shown, a first parasitic capacitor Cp1 is formed between the control terminal and the ground terminal of the first MOS transistor MN1, and a second parasitic capacitor Cp2 is formed between the first connection terminal and the ground terminal of the second MOS transistor MN2.

[0024] exist Figure 1 In the specific embodiment shown, Figure 1 The connection node A of the dynamic bias circuit shown is connected to the current mirror 110 , and the connection node A of the dynamic bias circuit provides a bias current to the current mirror 110 .

[0025] The following is a detailed introduction Figure 1 The working process of the dynamic bias circuit is shown.

[0026] First, the first switch S11 and the second switch S12 are controlled to be turned on, and the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned off. At this time, the pre-charging current source I1 pre-charges the first pre-charging capacitor Cs1 and the second pre-charging capacitor Cs2. After charging, the charge Q1 on the first pre-charging capacitor Cs1 = Cs1*Vdd, and the charge Q2 on the second pre-charging capacitor Cs2 = Cs2*Vdd. That is, when the first switch S11 and the second switch S12 are controlled to be turned on, and the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned off, the pre-charging current source I1 pre-charges the first pre-charging capacitor Cs1 and the second pre-charging capacitor Cs2.

[0027] Then, the first switch S11 and the second switch S12 are controlled to be turned off, and the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned on. At this time, the bias current source I2 charges the first parasitic capacitor Cp1 and the second parasitic capacitor Cp2 of the bias circuit. The charging process at this time will be limited by the time constant. However, due to the existence of the first pre-charge capacitor Cs1 and the second pre-charge capacitor Cs2, the charges of the first pre-charge capacitor Cs1 and the second pre-charge capacitor Cs2 will be quickly shared with the first parasitic capacitor Cp1 and the second parasitic capacitor Cp2, respectively, so as to quickly start the bias circuit. That is, when the first switch S11 and the second switch S12 are turned off, and the third switch S21, the fourth switch S22 and the fifth switch S23 are turned on, the bias current source I2 charges the first parasitic capacitor Cp1 and the second parasitic capacitor Cp2, and at the same time, the charge of the first pre-charge capacitor Cs1 will be shared with the first parasitic capacitor Cp1, and the charge of the second pre-charge capacitor Cs2 will be shared with the second parasitic capacitor Cp2, so as to quickly start Figure 1 The dynamic bias circuit is shown.

[0028] Since there will be burrs at the moment of capacitor discharge, excessive burrs will make the instantaneous current of the bias circuit too large, thereby increasing unnecessary power consumption. Therefore, the third switch S21, the fourth switch S22 and the fifth switch S23 will use NMOS transistors as switches, rather than NMOS transistors and PMOS (positive channel Metal Oxide Semiconductor) transistors together to form CMOS switches as switches, because NMOS transistors as switches can limit the voltage at both ends of the switch to the level range of Vdd-Vthn (Vthn is the threshold voltage or the turn-on voltage). That is to say, in a specific embodiment, the third switch S21 is an NMOS transistor, and the first connection end, the second connection end and the control end of the third switch S21 are respectively the drain, source and gate of the NMOS transistor; the fourth switch S22 is an NMOS transistor, and the first connection end, the second connection end and the control end of the fourth switch S22 are respectively the drain, source and gate of the NMOS transistor; the fifth switch S23 is an NMOS transistor, and the first connection end, the second connection end and the control end of the fifth switch S23 are respectively the drain, source and gate of the NMOS transistor.

[0029] According to another aspect of the present invention, the present invention provides a discrete time circuit, which includes: Figure 1 Dynamic bias circuit.

[0030] In a specific embodiment, Figure 1 The discrete time circuit shown is a discrete time integrator; one working cycle of the discrete time integrator includes a sampling cycle and an integration cycle; in one working cycle, during the sampling cycle, the first switch S11 and the second switch S12 are controlled to be turned on, and the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned off, and during the integration cycle, the first switch S11 and the second switch S12 are controlled to be turned off, and the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned on.

[0031] In summary, the utility model solves the problem of slow start-up of traditional dynamic bias technology. By improving the bias circuit, it can provide an instantaneously increased bias current, so that the power consumption of the operational amplifier can be increased in a very short time, which greatly speeds up the "turn-on" speed of the operational amplifier, so that the switched capacitor discrete time integrator composed of such an operational amplifier can operate at a higher frequency.

[0032] In the present utility model, words such as “connect”, “connected”, “connected”, “connected”, etc. indicating electrical connection, if not otherwise specified, indicate direct or indirect electrical connection.

[0033] The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment. Any equivalent modifications or changes made by ordinary technicians in this field based on the disclosure of the present invention should be included in the protection scope recorded in the claims.

Claims

1. A dynamic bias circuit, characterized in that: It includes a first switch S11, a second switch S12, a third switch S21, a fourth switch S22, a fifth switch S23, a pre-charge current source I1, a bias current source I2, a first pre-charge capacitor Cs1, a second pre-charge capacitor Cs2, a first MOS transistor MN1 and a second MOS transistor MN2. The input end of the pre-charging current source I1 is connected to the power supply end, and the output end thereof is connected to the first connection end of the first switch S11, the second connection end of the first switch S11 is connected to the first connection end of the second pre-charging capacitor Cs2, and the second connection end of the second pre-charging capacitor Cs2 is grounded; A first connection end of the second switch S12 is connected to the output end of the pre-charging current source I1, a second connection end thereof is connected to a first connection end of the first pre-charging capacitor Cs1, and a second connection end of the first pre-charging capacitor Cs1 is grounded; A first connection end of the third switch S21 is connected to a first connection end of the second pre-charge capacitor Cs2, and a second connection end thereof is connected to a connection node A; The input end of the bias current source I2 is connected to the power supply end, the output end thereof is connected to the first connection end of the fourth switch S22, and the second connection end of the fourth switch S22 is connected to the connection node B; A first connection end of the fifth switch S23 is connected to a first connection end of the first pre-charge capacitor Cs1, and a second connection end thereof is connected to the connection node B; The first connection end of the first MOS transistor MN1 is connected to the connection node B, the second connection end thereof is grounded, and the control end thereof is connected to the first connection end thereof; A first connection end of the second MOS transistor MN2 is connected to the connection node A, a second connection end thereof is grounded, and a control end thereof is connected to the control end of the first MOS transistor MN1.

2. The dynamic bias circuit according to claim 1, characterized in that: When the first switch S11 and the second switch S12 are controlled to be turned on, the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned off; When the first switch S11 and the second switch S12 are controlled to be turned off, the third switch S21 , the fourth switch S22 and the fifth switch S23 are controlled to be turned on.

3. The dynamic bias circuit according to claim 2, characterized in that: The first MOS transistor MN1 is an NMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the first MOS transistor MN1 are respectively the drain, the source and the gate of the NMOS transistor; The second MOS transistor MN2 is an NMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the second MOS transistor MN2 are respectively the drain, the source and the gate of the NMOS transistor.

4. The dynamic bias circuit according to claim 3, characterized in that: The third switch S21 is an NMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the third switch S21 are respectively the drain, the source and the gate of the NMOS transistor; The fourth switch S22 is an NMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the fourth switch S22 are respectively the drain, the source and the gate of the NMOS transistor; The fifth switch S23 is an NMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the fifth switch S23 are respectively the drain, the source and the gate of the NMOS transistor.

5. The dynamic bias circuit according to claim 2, characterized in that: A first parasitic capacitor Cp1 is formed between the control terminal and the ground terminal of the first MOS transistor MN1, and a second parasitic capacitor Cp2 is formed between the first connection terminal and the ground terminal of the second MOS transistor MN2. When the first switch S11 and the second switch S12 are controlled to be turned on, and the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned off, the pre-charging current source I1 pre-charges the first pre-charging capacitor Cs1 and the second pre-charging capacitor Cs2; When the first switch S11 and the second switch S12 are controlled to be turned off, and the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned on, the charge of the first pre-charge capacitor Cs1 will be shared with the first parasitic capacitor Cp1, and the charge of the second pre-charge capacitor Cs2 will be shared with the second parasitic capacitor Cp2.

6. The dynamic bias circuit according to claim 2, characterized in that: The connection node A is connected to a current mirror, The connection node A provides a bias current to the current mirror.

7. A discrete time circuit, characterized in that: It comprises a dynamic bias circuit as described in any one of claims 1-6.

8. The discrete-time circuit according to claim 7, characterized in that The discrete time circuit is a discrete time integrator; A working cycle of the discrete time integrator includes a sampling cycle and an integration cycle; In a working cycle, during the sampling period, the first switch S11 and the second switch S12 are controlled to be turned on, and the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned off; during the integration period, the first switch S11 and the second switch S12 are controlled to be turned off, and the third switch S21, the fourth switch S22 and the fifth switch S23 are controlled to be turned on.

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