CMOS power supply

Abstract

The utility model relates to the technical field of servers, in particular to a CMOS (complementary metal oxide semiconductor) power supply, which comprises a computer power supply connected with a first input end of a multiplexer through a first voltage converter; the super capacitor is connected with the second input end of the multiplexer through a second voltage converter; the computer power supply is electrically connected with the charging circuit of the super capacitor; the battery is connected with the third input end of the multiplexer; the output end of the multiplexer is connected with the CMOS; and a control pin of the multiplexer is connected with the BMC chip. The method can stably supply power to the CMOS of the server all the time, and a coin battery does not need to be replaced for the CMOS.

Description

Technical Field

[0001] The utility model belongs to the technical field of servers, and in particular relates to a CMOS power supply. Background Art

[0002] In server applications, CR2032 coin batteries are often used to store RTC (Real-Time Clock) information in CMOS (Complementary Metal-Oxide Semiconductor). CMOS technology is a technology widely used to manufacture integrated circuits, and in computer hardware, CMOS memory is used to store BIOS setup information. RTC is responsible for maintaining the time information in the system.

[0003] CMOS memory requires a steady source of power to maintain its data, even when the system is turned off or loses power. This is where the CR2032 battery comes in. The CR2032 is a 3-volt button cell that is widely used in such applications due to its high energy density, long life, and stability.

[0004] However, first-tier data centers have at least 50,000 to 100,000 servers. The general lifespan of CR2032 is about 5 years, and the service life of servers usually exceeds 5 years. If the CR2032 battery needs to be replaced at that time, it will be a huge workload. Utility Model Content

[0005] In view of the above-mentioned deficiencies in the prior art, the utility model provides a CMOS power supply to solve the above-mentioned technical problems.

[0006] The utility model provides a CMOS power supply, comprising:

[0007] A computer power supply, the computer power supply being connected to a first input terminal of the multiplexer via a first voltage converter;

[0008] A supercapacitor, wherein the supercapacitor is connected to the second input terminal of the multiplexer via a second voltage converter; the computer power supply is electrically connected to a charging circuit of the supercapacitor;

[0009] a battery, wherein the battery is connected to the third input terminal of the multiplexer;

[0010] The output end of the multiplexer is connected to CMOS;

[0011] The control pins of the multiplexer are connected to the BMC chip.

[0012] In an optional embodiment, it includes:

[0013] The output end of the computer power supply is provided with a first voltage sensor, the output end of the super capacitor is provided with a second voltage sensor, and the output end of the battery is provided with a third voltage sensor;

[0014] The first voltage sensor, the second voltage sensor and the third voltage sensor are all connected to the BMC chip through an I2C bus.

[0015] In an optional embodiment, the supercapacitor includes a first supercapacitor and a second supercapacitor, the first supercapacitor and the second supercapacitor are connected in series; and the output voltages of the first supercapacitor and the second supercapacitor are both 2.7V.

[0016] In an optional embodiment, the charging circuit of the supercapacitor includes a voltage divider circuit and a dynamic voltage equalization circuit.

[0017] In an optional embodiment, the voltage divider circuit includes a first resistor and a second resistor, the first end of the first resistor is connected to the positive electrode of the computer power supply, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the negative electrode of the computer power supply; the resistance value of the first resistor is 8K, and the resistance value of the second resistor is 25K.

[0018] In an optional embodiment, the dynamic voltage balancing circuit includes an operational amplifier, a third resistor, a fourth resistor, an NPN transistor, a PNP transistor, a fifth resistor and a sixth resistor; the same-direction signal input terminal of the operational amplifier is connected to the second end of the first resistor; the first end of the third resistor is connected to the positive electrode of the computer power supply, and the second end of the third resistor is respectively connected to the first end of the fourth resistor, the collector of the NPN transistor and the first end of the first super capacitor; the second end of the fourth resistor is connected to the reverse signal input terminal of the operational amplifier; the emitter of the NPN transistor is connected to the collector of the PNP transistor, and the collector of the PNP transistor is connected to the reverse signal input terminal of the operational amplifier; the output terminal of the operational amplifier is respectively connected to the base of the NPN transistor and the base of the PNP transistor; the emitter of the NPN transistor is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the second end of the first super capacitor; the second end of the first super capacitor is connected to the first end of the second super capacitor, the second end of the second super capacitor is grounded, the first end of the second super capacitor is connected to the first end of the sixth resistor, and the second end of the sixth resistor is connected to the reverse signal input terminal of the operational amplifier.

[0019] In an optional implementation, both the first voltage converter and the second voltage converter use BUCK-Boost chips.

[0020] In an optional implementation, a first filter capacitor is provided between the supercapacitor and the second voltage converter; and a second filter capacitor is provided at the output end of the second voltage converter.

[0021] In an optional implementation, a heat sink is attached to the supercapacitor, a temperature sensor is provided on the heat sink, and the temperature sensor is connected to the BMC chip via an I2C line.

[0022] In an optional embodiment, a plurality of heat dissipation bubbles are attached to the heat dissipation surface of the heat sink, and the heat dissipation bubbles are filled with liquid.

[0023] The beneficial effect of the utility model is that the power supply of the CMOS provided by the utility model can stably supply power to the CMOS of the server for life, without replacing the coin battery for the CMOS.

[0024] In addition, the utility model has a reliable design principle, a simple structure and a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 It is a schematic diagram of a power supply of a CMOS according to an embodiment of the utility model.

[0027] Figure 2 It is a schematic diagram of charging and discharging of a supercapacitor of a CMOS power supply according to an embodiment of the utility model.

[0028] Figure 3 The figure is a schematic diagram of a dynamic voltage equalization circuit of a supercapacitor of a CMOS power supply according to an embodiment of the utility model.

[0029] Figure 4 The figure is a schematic diagram of power switching logic of a CMOS power supply according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0032] For details, please refer to Figure 1 , the power supply of CMOS includes:

[0033] A computer power supply PSU, the computer power supply PSU is connected to the first input end of the multiplexer via a first voltage converter; a supercapacitor, the supercapacitor is connected to the second input end of the multiplexer via a second voltage converter; the computer power supply PSU is electrically connected to a charging circuit of the supercapacitor; a battery, the battery is connected to the third input end of the multiplexer; the output end of the multiplexer is connected to the CMOS; and the control pin of the multiplexer is connected to the BMC chip.

[0034] The original single power supply was changed to a multi-combination power supply, and a computer power supply PSU (PSU) and supercapacitor were introduced. The battery still uses a CR2032 coin battery. This power supply can power the CMOS when the server is powered on or off. In this way, the life of the entire power supply is greatly improved, and the life is much longer than the server life. The BMC chip is an independent power supply, and the BMC chip can still operate after the motherboard is powered off. Therefore, the switching control of the power supply can be realized through the BMC chip to improve the stability of the power supply.

[0035] Among them, the supercapacitor includes a first supercapacitor SuperCap1 and a second supercapacitor SuperCap2, and the first supercapacitor SuperCap1 and the second supercapacitor SuperCap2 are connected in series; the output voltages of the first supercapacitor SuperCap1 and the second supercapacitor SuperCap2 are both 2.7V, and the output voltage of the supercapacitor connected in series is 5.4V, so a second voltage converter is required to convert the 5.4V voltage into the 3.3V voltage required by COMS.

[0036] like Figure 2As shown, the charging circuit of the supercapacitor includes a voltage divider circuit and a dynamic voltage equalization circuit. The voltage divider circuit includes a first resistor R1 and a second resistor R2, wherein the first end of the first resistor R1 is connected to the positive electrode of the computer power supply PSU, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the negative electrode of the computer power supply PSU; the resistance value of the first resistor R1 is 8K, and the resistance value of the second resistor R2 is 25K. The dynamic voltage balancing circuit includes an operational amplifier, a third resistor R3, a fourth resistor R4, an NPN transistor Q1, a PNP transistor Q2, a fifth resistor R5 and a sixth resistor R6; the same-direction signal input end of the operational amplifier is connected to the second end of the first resistor R1; the first end of the third resistor R3 is connected to the positive electrode of the computer power supply PSU, and the second end of the third resistor R3 is respectively connected to the first end of the fourth resistor R4, the collector of the NPN transistor Q1 and the first end of the first supercapacitor SuperCap1; the second end of the fourth resistor R4 is connected to the reverse signal input end of the operational amplifier; the emitter of the NPN transistor Q1 is connected to the collector of the PNP transistor Q2, and the collector of the PNP transistor Q2 is connected to the collector of the PNP transistor Q2. The electrode is connected to the reverse signal input terminal of the operational amplifier; the output terminal of the operational amplifier is respectively connected to the base of the NPN transistor Q1 and the base of the PNP transistor Q2; the emitter of the NPN transistor Q1 is connected to the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is connected to the second end of the first super capacitor SuperCap1; the second end of the first super capacitor SuperCap1 is connected to the first end of the second super capacitor SuperCap2, the second end of the second super capacitor SuperCap2 is grounded, the first end of the second super capacitor SuperCap2 is connected to the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is connected to the reverse signal input terminal of the operational amplifier. A first filter capacitor C1 is provided between the super capacitor and the second voltage converter; a second filter capacitor C2 is provided at the output end of the second voltage converter.

[0037] Dynamic voltage equalization circuit such as Figure 3 As shown, this voltage balancing design can start when the terminal voltage of the single supercapacitor is 1.2V, so that effective voltage balancing can be achieved during the charging process from 1.2V to 2.5V or 2.7V.

[0038] The first voltage converter and the second voltage converter both use BUCK-Boost chips. The first voltage converter converts 12V voltage into 3.3V, and the second voltage converter converts 5.4V voltage into 3.3V.

[0039] The supercapacitor is charged by the charging circuit and discharged through the second voltage converter when needed. When the computer power is turned on, the Buck / Boost controller of the first voltage converter enters Buck on mode, which turns on the bypass field effect transistor (FET) and supplies a constant current of 500 mA to the supercapacitor and stops charging when the voltage of the supercapacitor reaches 2.5 V. The computer power supply directly supplies power to VOUT.

[0040] High temperature will have an adverse effect on the supercapacitor, so the following heat dissipation design is adopted: a heat sink is attached to the supercapacitor, and a temperature sensor is attached to the heat sink. The temperature sensor is connected to the BMC chip through the I2C line. Multiple heat dissipation bubbles are attached to the heat dissipation surface of the heat sink, and the heat dissipation bubbles are filled with liquid. The liquid is water with a large specific heat capacity. This design not only increases the heat dissipation surface area of ​​the heat sink, but also can absorb a large amount of heat.

[0041] In order to further improve the power supply stability and ensure the normal level of the power supply voltage, the output end of the computer power supply is provided with a first voltage sensor, the output end of the supercapacitor is provided with a second voltage sensor, and the output end of the battery is provided with a third voltage sensor; the first voltage sensor, the second voltage sensor and the third voltage sensor are all connected to the BMC chip through the I2C bus.

[0042] The BMC chip sets the priority of three power sources: computer power > battery > supercapacitor. When the motherboard is powered on, the computer power is enabled. When the computer power is unavailable, it switches to battery power. When the battery voltage does not reach the voltage threshold of 2.6V, the supercapacitor is enabled.

[0043] For details, please refer to Figure 4 In one embodiment, the power switching logic includes:

[0044] Power Input: The system is designed to accept multiple power inputs, including 12V DC, alternating current (AC), CR2032 button battery, and a 5.4V supercapacitor dynamic balancing circuit. Each power supply is regulated to the required 3.3V voltage through a Buck / Boost converter.

[0045] Source switching: The switching logic includes a switch and switching signals designed to automatically or manually select the best source based on the availability and suitability of the sources.

[0046] Voltage monitoring and control: The system includes voltage monitoring components to ensure that the output voltage is stable at 3.3 V. If a voltage deviation is detected, the system will adjust the power supply by switching to maintain voltage stability.

[0047] Controller interface: The system interfaces with the Intel Platform Controller Hub or AMD central processing unit (CPU), which may be used to receive power switching instructions or provide power status feedback.

[0048] Output to RTC CMOS: The final 3.3V output is supplied to the RTC CMOS module, along with a 32.768KHz crystal, ensuring that time is kept accurate.

[0049] Power switching logic: Proper power switching logic should ensure that at any given moment, the system selects the best available power supply and switches seamlessly when the power state changes to prevent power interruption to the RTC CMOS module.

[0050] Voltage stability: Regulating each supply to 3.3V output via a Buck / Boost converter is a valid design decision that ensures output voltage stability suitable for sensitive RTC CMOS modules.

[0051] In general, the switching logic can conceptually ensure that the RTC CMOS continues to operate stably under different power supply conditions. However, in actual implementation, the priority order between power supplies and how to seamlessly switch when a power supply fails must be considered to maximize the reliability and stability of the system.

[0052] Although the present invention is described in detail by referring to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person skilled in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions shall be within the scope of the present invention. Any person skilled in the art who is familiar with the present technical field may easily think of changes or substitutions within the technical scope disclosed in the present invention, and these shall be within the scope of protection of the present invention.

Claims

1. A CMOS power supply, characterized in that: include: A computer power supply, the computer power supply being connected to a first input terminal of the multiplexer via a first voltage converter; A supercapacitor, wherein the supercapacitor is connected to the second input terminal of the multiplexer via a second voltage converter; the computer power supply is electrically connected to a charging circuit of the supercapacitor; a battery, wherein the battery is connected to the third input terminal of the multiplexer; The output end of the multiplexer is connected to CMOS; The control pins of the multiplexer are connected to the BMC chip.

2. The CMOS power supply according to claim 1, characterized in that: include: The output end of the computer power supply is provided with a first voltage sensor, the output end of the super capacitor is provided with a second voltage sensor, and the output end of the battery is provided with a third voltage sensor; The first voltage sensor, the second voltage sensor and the third voltage sensor are all connected to the BMC chip through an I2C bus.

3. The CMOS power supply according to claim 1, characterized in that: The supercapacitor includes a first supercapacitor and a second supercapacitor, the first supercapacitor and the second supercapacitor are connected in series; the output voltages of the first supercapacitor and the second supercapacitor are both 2.7V.

4. The CMOS power supply according to claim 3, characterized in that: The charging circuit of the supercapacitor includes a voltage dividing circuit and a dynamic voltage equalizing circuit.

5. The CMOS power supply according to claim 4, characterized in that: The voltage divider circuit includes a first resistor and a second resistor, the first end of the first resistor is connected to the positive electrode of the computer power supply, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the negative electrode of the computer power supply; the resistance value of the first resistor is 8K, and the resistance value of the second resistor is 25K.

6. The CMOS power supply according to claim 5, characterized in that: The dynamic voltage equalization circuit includes an operational amplifier, a third resistor, a fourth resistor, an NPN transistor, a PNP transistor, a fifth resistor and a sixth resistor; the same-direction signal input end of the operational amplifier is connected to the second end of the first resistor; the first end of the third resistor is connected to the positive electrode of the computer power supply, and the second end of the third resistor is respectively connected to the first end of the fourth resistor, the collector of the NPN transistor and the first end of the first super capacitor; the second end of the fourth resistor is connected to the reverse signal input end of the operational amplifier; the emitter of the NPN transistor is connected to the collector of the PNP transistor, and the collector of the PNP transistor is connected to the reverse signal input end of the operational amplifier; the output end of the operational amplifier is respectively connected to the base of the NPN transistor and the base of the PNP transistor; the emitter of the NPN transistor is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the second end of the first super capacitor; the second end of the first super capacitor is connected to the first end of the second super capacitor, the second end of the second super capacitor is grounded, the first end of the second super capacitor is connected to the first end of the sixth resistor, and the second end of the sixth resistor is connected to the reverse signal input end of the operational amplifier.

7. The CMOS power supply according to claim 1, characterized in that: The first voltage converter and the second voltage converter both use BUCK-Boost chips.

8. The CMOS power supply according to claim 1, characterized in that: A first filter capacitor is provided between the supercapacitor and the second voltage converter; and a second filter capacitor is provided at the output end of the second voltage converter.

9. The CMOS power supply according to claim 1, characterized in that: A heat sink is attached to the super capacitor, a temperature sensor is provided on the heat sink, and the temperature sensor is connected to the BMC chip via an I2C line.

10. The CMOS power supply according to claim 9, characterized in that: A plurality of heat dissipation bubbles are attached to the heat dissipation surface of the heat dissipation fin, and liquid is filled in the heat dissipation bubbles.

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