Semiconductor device
By designing the end of the conductive clip with engraved in the semiconductor device and combining the opening structure of the conductive substrate, the problem of difficult clip manufacturing and processing in small-sized power semiconductor devices is solved, and efficient electrical coupling and structural flatness are achieved.
Patent Information
- Application Number
- CN202323252507.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-29
- Filing Date
- 2023-11-30
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2033-11-30
AI Technical Summary
In small-sized power semiconductor devices, the clips are difficult to manufacture and handle, and the pads are undesirably asymmetric and uneven, resulting in difficulty in electrical coupling.
Design a semiconductor device, using a combination of a conductive substrate and a conductive clip, the end of the clip includes a planar proximal portion and a distal protrusion, the distal portion is provided with an opening engraved to engage the conductive lead array, and the clip is fixed to the semiconductor The bridge position between the chip and the conductive lead.
Through this design, the clamping is centered using the peripheral features of the lead frame to avoid additional depressions on the pads, simplifying the manufacturing and installation process of the clamping, and improving the electrical coupling efficiency of the device and the flatness of the structure.
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Figure CN222483369U_ABST
Abstract
Description
Technical Field
[0001] This specification relates to semiconductor integrated circuit devices.
[0002] The solutions described herein may be applied to power semiconductor devices, such as power quad flat no-lead (QFN) packages, for example, in automotive products. Background Art
[0003] In power semiconductor integrated circuit devices, the current transferred from the high power section to the output pads of the device can be significant. For this purpose, clips are used instead of wires.
[0004] Clips are currently stamped from flat material. In order to center the clip on the lead frame, the material is also pressed by stamping to form the pins. Recesses are formed at the corresponding lead frame locations to accommodate the clip pins for centering purposes.
[0005] In small packages (eg, power quad flat no-lead (QFN)) and / or if several channels are required in the final package, more pads are needed and the size of the recess and clip on the lead frame may become relatively small.
[0006] The relatively small size may make the clip difficult to manufacture and handle.
[0007] Furthermore, providing several depressions on a pad may cause the pad to be undesirably uneven and not flat.
[0008] There is a need in the art for solutions to the above problems. Utility Model Content
[0009] An object of the present disclosure is to provide a semiconductor device to at least partially solve the above-mentioned problems existing in the prior art.
[0010] One aspect of the present disclosure provides a semiconductor device, comprising: a conductive substrate, comprising a conductive lead array having a plurality of recesses at the periphery of the conductive substrate; at least one semiconductor die, arranged at a die mounting position of the conductive substrate; at least one conductive clip, arranged in a bridge-like position between the at least one semiconductor die and at least one conductive lead in the conductive lead array to provide electrical coupling between the at least one semiconductor die and the at least one conductive lead; wherein the at least one conductive clip has an end coupled to the at least one conductive lead in the conductive lead array; wherein the end comprises: a planar proximal portion, contacting the at least one conductive lead at the proximal end of the recess; and a distal portion, the distal end protruding beyond the proximal portion, the distal portion being provided with an engraving, the engraving engaging the recess and fixing the at least one conductive clip in the bridge-like position between the at least one semiconductor chip and the at least one conductive lead in the conductive lead array, wherein the distal portion of the at least one conductive clip is exposed at the periphery of the device.
[0011] According to one or more embodiments, wherein the distal portion has a fork-like shape comprising a plurality of prongs protruding distally beyond the proximal portion, and wherein the engraving is provided in the plurality of prongs.
[0012] According to one or more embodiments, the end of the at least one conductive clip is a lower portion of the conductive clip.
[0013] In accordance with one or more embodiments, the engraving includes at least one protrusion from a distal portion of the tip of the at least one conductive clip.
[0014] In accordance with one or more embodiments, wherein the electrically conductive substrate is a pre-molded lead frame having a pre-molding compound, and wherein the pre-molding compound is not present in the recess.
[0015] According to one or more embodiments, further comprising solder bumps between the at least one conductive clip and the at least one semiconductor chip and between the at least one conductive clip and the at least one conductive lead.
[0016] According to one or more embodiments, a material packaging body is further included, and wherein a distal end portion of the conductive clip is exposed at a periphery of the material packaging body.
[0017] Utilizing embodiments of the present disclosure advantageously utilizes peripheral features of the lead frame for centering purposes without having additional recesses on the pads. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:
[0019] Figure 1 and Figure 2 is a plan view showing the structure of a power semiconductor device;
[0020] Figure 3 is a schematic diagram of a method for manufacturing a clip;
[0021] Figure 4 is along Figure 2 A cross-sectional view of line IV-IV;
[0022] Figure 5 is a plan view showing the structure of a power semiconductor device;
[0023] Figure 6 and Figure 7 are respectively a plan view and a cross-sectional view showing an embodiment of a clip of the present specification;
[0024] Figure 8 is a plan view showing a clip as described herein mounted on a semiconductor device;
[0025] Fig. 9 and 10 They are Figure 8 A plan view and a cross-sectional view of the portion indicated by arrow IX; and
[0026] Fig.11 and Fig.12 shows that after further processing steps Figure 8 the same part. DETAILED DESCRIPTION
[0027] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The accompanying drawings are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the drawings do not necessarily represent the end of the feature range.
[0028] In the following description, one or more specific details are shown for the purpose of providing a deeper understanding of the examples of the embodiments of the present description. The embodiments may be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.
[0029] References to "one embodiment" or "an embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment.
[0030] Furthermore, in one or more embodiments, the particular conformations, structures or characteristics may be combined in any suitable manner.
[0031] The headings / references used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.
[0032] For simplicity and ease of explanation, throughout the specification, unless the context otherwise indicates, the same parts or elements are denoted by the same reference numerals in the various drawings, and the corresponding description is not repeated for each drawing.
[0033] Figure 1 and Figure 2 shows the low power part (in Figure 1 and 2 The left hand side shows the high power part (in Figure 1 and 2 The structure of the power semiconductor device 10 is shown on the right hand side of FIG. The low power portion includes, for example, a controller integrated circuit die or chip attached to a first die pad 12A in the lead frame 12. The high power portion includes, for example, one or more power integrated circuit dies or chips attached to one or more second die pads 12A in the lead frame 12.
[0034] As used herein, the terms chip and die are considered synonymous.
[0035] An array of leads 12B is arranged around the die pad 12A on which the low-power and high-power dies are mounted.
[0036] As described herein by way of example, in addition to a substrate (lead frame) 12 having one or more semiconductor chips or dies 14 disposed thereon, an integrated circuit semiconductor device such as device 10 includes: conductive structures 16, 18 coupling the semiconductor chip(s) 14 to leads (external pads) 12B in the substrate; and an insulating encapsulation (e.g., a resin, only in contact with the substrate). Fig.10 1 and indicated here with reference numeral 20 ), which is molded over the assembly thus formed to complete the plastic body of the device 10 .
[0037] The name "lead frame" (or "leadframe") (see, e.g., the USPC Incorporated Glossary of the U.S. Patent and Trademark Office) refers to the metal frame that provides support for an integrated circuit chip or die, and the electrical leads that interconnect the integrated circuits in the die or chip to other components or contacts.
[0038] Essentially, the leadframe 12 includes an array of conductive structures (or leads, e.g., 12B) extending inwardly from a contoured position in the direction of the semiconductor chip or die (e.g., 14) such that the die pads (e.g., Figure 4 12A) forms an array of conductive structures, the die pad being configured to have at least one (integrated circuit) semiconductor chip or die attached thereto. This can be achieved by conventional means such as a die attach adhesive (e.g., a die attach film (DAF)).
[0039] In some cases, the leadframe may be of the pre-molded type, i.e., a leadframe type comprising an engraved metal (e.g., copper) structure formed by etching a metal sheet and comprising empty spaces filled with an insulating compound (e.g., resin) "pre-molded" over the engraved metal structure.
[0040] In current manufacturing processes of (integrated circuit) semiconductor devices, multiple devices / lead frames are processed simultaneously.
[0041] Several lead frames are arranged in a lead frame strip and held together via tie bars extending around each individual lead frame. The lead frames are connected to the tie bars via so-called tie bars, which are bridge-like structures that connect the pads (e.g., 12A) or leads (e.g., 12B) of the lead frames to the tie bars.
[0042] Connecting rods and tie rods Figures 8 to 10 , and are represented here by the reference numerals CB and TB, respectively.
[0043] The connecting bars CB are removed (eg, by sawing) in a final "sigulation" step to obtain individual devices.
[0044] As described above, conductive structures 16, 18 are provided to couple the semiconductor chip(s) 14 to leads (external pads) 12B in the substrate. The conductive structures 16 are often referred to as wire bonds or bond wires.
[0045] In power semiconductor devices (e.g. Figure 1 and Figure 2 In the device 10 shown in FIG. 1 , the current delivered from the high power portion to the output pad 12B of the device may be significant. Figure 2 As shown on the right-hand side of the drawing, the clip 18 is therefore used instead of the wire.
[0046] Wire 16 can still be used, such as Figure 2 , to provide electrical coupling to the low power portions of the device (e.g., a controller).
[0047] That is, Figure 1 and Figure 2 As shown, a conductive structure including a wire bonding pattern 16 is provided, and the wire bonding pattern 16 connects the low power part (for example, Figure 1 and 2 The left-hand side of the chip is coupled to the selected lead 12B. These wire bonding patterns are coupled to a die pad (not visible in the figure) provided at the front or top surface of the chip.
[0048] Instead, use clips to separate the high power section ( Figure 2 The right hand side of the device 10 is coupled to selected ones of leads 12B which serve as (power) output pads of device 10. The use of clips instead of wires accounts for the fact that the current transferred from the high power section to the output pads in the power semiconductor device can be quite large.
[0049] According to one method, for example Figure 3 The clip 18 shown is formed by stamping a flat metal (e.g., copper) material. Pins 181 are also formed (by stamping, P) at the terminal portion of the clip that will be coupled to the lead 12 (at Figure 3 on the right hand side of the ).
[0050] The pin 181 of the lead 12B in the lead frame 12 and the corresponding recessed portion 182 (eg Figure 1 ) facilitates centering of the clip when mounting the clip on the lead frame-chip assembly.
[0051] Figure 4 Cross-sectional view of Figure 3 How the clip 18 shown in FIG. 1 is included in Figure 2 , such that clip 18 may provide electrical coupling between the (integrated circuit) chip or die 14 and one of the leads 12B.
[0052] The distal end of the clip 18 (at Figure 4 The lead 12B (right side in FIG. 1 ) is positioned so that the pin 181 is inserted into the recessed portion 182 of the lead 12B. The solder SM is used to form an electrical connection therebetween.
[0053] The proximal end of the clip 18 (at Figure 4 , left side in FIG. 1 ) can be soldered (via solder bumps SM) to pads 22 located on the front / top surface of chip 14 .
[0054] The device structures discussed thus far are conventional in the art, such that a more detailed description need not be provided herein.
[0055] As mentioned above, the method just described for providing electrical coupling to the power portion of the device via the clip may face various difficulties when manufacturing power devices of small size or when several electrical paths are involved.
[0056] For example, when several channels are required, it may become difficult to provide the (power) output lead 12B with a recess 182 while keeping the lead 12B flat.
[0057] Furthermore, producing a relatively small clip 18 with pins 181 by stamping may be difficult due to the small space available.
[0058] In the case of small package devices, these problems may already arise when more than two channels (and therefore more than two clips) are required.
[0059] Solutions to this problem may include improving clip stamping techniques and machining or selecting a different clip material.
[0060] These approaches have the disadvantage of increasing production costs, and in addition, the different materials used for the clip may result in reduced electrical performance of the device.
[0061] Another possible approach to addressing this problem may include increasing the package size, thereby imposing constraints on the device design.
[0062] The solution described herein does not involve forming additional recesses on the pads of the lead frame.
[0063] Figure 5 A lead frame 12 is shown with a chip 14 mounted thereon, similar to Figure 1 The lead frame is shown without the recess 182 .
[0064] The solution described therein is applicable to standard (non-pre-molded) lead frames as well as to pre-molded type lead frames (adding additional processing steps).
[0065] Hereinafter, for simplicity, the case of a standard lead frame 12 which is not a pre-molded type will be discussed.
[0066] As discussed, the manufacturing process of semiconductor devices currently involves Figure 8 The simultaneous manufacture of multiple devices is enabled by holding multiple leadframes (or leadframe portions) 12 in a leadframe strip by tie bars indicated with CB in the figure. Each leadframe (portion) 12 is connected to a tie bar CB by a bridge-like "tie bar" TB.
[0067] That is, in the solution as discussed herein, a plurality of lead frames (portions) may be included in a set (e.g., strip) of conductive substrates 12 having corresponding die mounting locations 12A. The conductive substrates (lead frames) in the set are coupled via sacrificial tie bars CB between conductive leads 12B in adjacent conductive substrates 12 in the set.
[0068] As discussed below, these conductive substrates 12 in a set or strip coupled via sacrificial tie bars CB that extend transversely to the length of the lead frame group or strip are processed simultaneously.
[0069] Such processing involves: arranging the semiconductor die 14 at the corresponding die mounting position (die pad 12A); and arranging the conductive clip in a bridge-like position between the semiconductor die 14 and the conductive leads 12B, wherein the semiconductor die 14 is arranged at the corresponding die mounting position 12A in the array of conductive leads 12B of the lead frame 12 in the set or strip to provide electrical coupling therebetween.
[0070] After this process, the leadframe collection or strip (with semiconductor die 14 and clips attached thereto) is cut at the sacrificial tie bars. In this way, "singulated" semiconductor devices are provided with conductive leads 12B having notches at the periphery of each leadframe / device resulting from singulation.
[0071] like Figure 5 As can be seen on the middle right, the connecting bars CB between the various lead frames (lead frame parts) in the set or strip have openings (e.g., gaps or holes) 282 on both sides thereof located at the (mutually facing) peripheral areas of two lead frames 12 in the set or strip.
[0072] Once the leadframe collection or strip (with semiconductor die 14 and clips attached thereto) is cut at the sacrificial tie bars CB, openings (holes) 282 create notches at the periphery of each "singulated" leadframe / device by removing the tie bars.
[0073] It should be appreciated that providing the openings 282 (eg, as vias) during the manufacturing process of the leadframe 12 (eg, via etching of metal strips) does not involve any additional processing steps.
[0074] The actual design of the lead frame 12 may vary from Figure 5 ; however, openings such as 282 may be provided at any suitable location during the lead frame formation steps (eg, via photolithography).
[0075] Openings such as 282 may be advantageously used for clip centering purposes at the expense of (simple) modification of the clip.
[0076] Figure 6 and Figure 7 Clip 28 is shown configured to utilize opening 282 as a centering feature.
[0077] To better understand the shape and design of this clip, here is a plan view ( Figure 6 ) and side view ( Figure 7 ).
[0078] and Figure 3 Compared to the clip 18 shown in FIG, the clip 28 shown in the figure has a longer “tail” 200 , ie, a distal portion 200 that protrudes beyond the proximal portion 202 so as to reach the opening 282 at the periphery of the lead frame 12 .
[0079] Notice, Figure 6 and Figure 7 The particular shape of clip 28 shown in any other details is merely an example of possible designs for clip 28; clips having different shapes and adapted to match a particular design of lead frame may be provided.
[0080] As shown, the distal portion (or "tail") 200 of the clip 28 may have a forked (rake) shape including a plurality of prongs that protrude beyond (and away from) the planar proximal portion 202.
[0081] As discussed below, the plurality of prongs may be provided with engravings (eg, pins) 281 configured to engage corresponding openings 282 at the periphery of the lead frame 12 .
[0082] The ends 200 , 202 may also be configured as downset portions of the clip 28 .
[0083] The clips 28 described herein may be provided by other conventional methods known to those skilled in the art, such as stamping or embossing.
[0084] Pins 281 on the rear (bottom) surface of the tail portion 200 of the clip 28 are configured to fit within (ie, engage or cooperate with) the openings or holes 282 to facilitate centering of the clip 28 in subsequent processing steps.
[0085] The pin 281 may be formed by any known technique suitable for the purpose (e.g., stamping, such as Figure 3 shown) provided.
[0086] Additive manufacturing techniques such as laser induced forward transfer (LIFT) may be advantageously used.
[0087] The LIFT process is a deposition process in which the transfer of material from a donor tape or sheet to a receptor substrate (here the back / bottom side of the clip 28) is facilitated by laser pulses.
[0088] General information about the LIFT process can be found, for example, in P. Serra et al.: “Laser-Induced Forward Transfer: Fundamentals and Applications”, published in Advanced Materials Technologies / Vol. 4, 1st Edition (incorporated herein by reference).
[0089] The use of additional techniques such as LIFT may be advantageous because such techniques may facilitate the formation of engravings 282 (eg, pins) in smaller clips, which may be difficult to achieve through traditional techniques such as stamping.
[0090] Figure 8 and Fig. 9 (The latter is Figure 8 The portion indicated by the arrow IX presented in an enlarged scale) illustrates the just described installation on the lead frame 12 (eg, Figure 5 Clips 28 (three clips in this example) are provided on the lead frame of the power chip 14 to provide electrical coupling between the power chip 14 (via the die pad 22 on the front / top surface of the chip 14) and the leads 12B of the lead frame 12.
[0091] It should be noted that Figure 8 Also shown are portions of adjacent lead frames 12 separated by tie bars CB.
[0092] In practice, as mentioned previously, in current manufacturing processes, a plurality of lead frames 12 are processed simultaneously. The plurality of lead frames are arranged in a lead frame strip 12, wherein the individual lead frames are separated by connecting formations (eg, tie bars) CB.
[0093] Each individual lead frame is connected to a respective tie bar via a respective tie bar TB.
[0094] Portions 201 and 202 of clip 28 contact die pad 22 and lead 12B, respectively, thereby providing electrical coupling between chip 14 and lead 12B.
[0095] Similar to conventional clip mounting, solder bumps may be used to form connections between portion 202 of clip 28 and leads 12B and between portion 201 and die pad 22 .
[0096] The tail portion 200 extends toward (and may partially overlap) the connecting rod CB so that a pin 281 on the back / bottom surface of the tail portion can be received in a hole 282 defined by the tie rod TB.
[0097] To summarize the above discussion, one or more conductive clips 28 are arranged in a bridge-like position between semiconductor die 14 and one or more conductive leads 12B to provide electrical coupling therebetween.
[0098] As shown, the conductive clip 28 has ends 200 , 202 that are configured to be coupled to the conductive lead 12B.
[0099] As shown, such a clip end includes a planar proximal portion 202 configured to contact the conductive lead 12B at a proximal end of the opening 282 , and a distal portion 200 that protrudes beyond the proximal portion 202 at a distal end thereof.
[0100] As shown, the distal portion is provided with an engraving 281 (e.g., Figure 7 The engraving 281 is configured to engage the opening 282 to facilitate securing the conductive clip 28 in a bridge-like position between the semiconductor chip 14 and the conductive lead 12B.
[0101] This contrasts with the arrangement disclosed in U.S. Patent Application Publication No. 2023 / 0245955 (incorporated herein by reference and corresponding to Italian Patent Application No. 102022000001649), in which the clip is shown having a dedicated fixing area configured for providing welding or gluing at the opposite lateral ends of the clip.
[0102] The previously described method involves additional steps when processing lead frames of the pre-molded type.
[0103] In this case, openings 281 are filled with pre-molding compound during the pre-molding step and cannot be used as centering features for pins 282 as they are.
[0104] The pre-mold compound filling openings 281 may be removed in an additional step, leaving these spaces clean of pre-mold resin before mounting clip 28 onto leadframe 12. This may be accomplished, for example, by etching after leadframe pre-molding or by other methods such as laser removal.
[0105] After clip 28 is mounted to the leadframe and chip assembly, an electrically insulating mold compound (eg, epoxy) is molded over the assembly to provide a protective plastic package for device 10 .
[0106] Fig.10 It is along Fig. 9 , which illustrates the device 10 after molding a mold compound 20 onto the device.
[0107] The parts removed in the segmentation step are indicated by two dashed lines SW. The segmentation step may be performed, for example, by means of a saw or any other suitable technique known per se to a person skilled in the art.
[0108] In the singulation step, the tie bars CB are completely removed, thereby dividing the device strip into individual devices 10 .
[0109] It should be noted that in the case where the tail 200 partially overlaps the tie bar CB, a portion of the tail 200 of the clip 28 is also removed during the singulation step. As shown in the following figures, this allows the tail 200 to be located on the side of the device ( Fig.10 ) is visible on the right side of the
[0110] Fig.11 and Fig.12 shows the difference between Fig. 9 and Fig.10 The same parts of the devices are shown respectively.
[0111] One aspect of the present disclosure provides a method, comprising: providing at least one conductive clip, the conductive clip having an end, the end comprising: a planar proximal portion and a distal portion protruding beyond the planar proximal portion, wherein the distal portion comprises an engraving; arranging at least one semiconductor die at a die mounting position of a conductive substrate, the conductive substrate comprising an array of conductive leads having an opening at the periphery of the conductive substrate; and arranging the at least one conductive clip in a bridge-like position between the at least one semiconductor die and at least one conductive lead in the conductive lead array to provide electrical coupling between the at least one semiconductor die and the at least one conductive lead; wherein arranging the at least one conductive clip comprises: contacting the planar proximal portion with the at least one conductive lead at the proximal end of the opening; and engaging the engraving in the opening so as to fix the at least one conductive clip in the bridge-like position between the at least one semiconductor chip and the at least one conductive lead in the conductive lead array.
[0112] According to one or more embodiments, providing the at least one conductive clip further comprises providing the distal portion with a fork-like shape comprising a plurality of prongs protruding distally beyond the proximal portion, wherein the engraving is provided in the plurality of prongs.
[0113] According to one or more embodiments, providing the at least one conductive clip further includes providing the end as a lower portion of the conductive clip.
[0114] According to one or more embodiments, the method further comprises providing the engraving as at least one protrusion from the distal portion of the tip of the at least one conductive clip.
[0115] According to one or more embodiments, the method further comprises providing the engraving via additive manufacturing.
[0116] According to one or more embodiments, the method further comprises providing the engraving via a Laser Induced Forward Transfer (LIFT) process.
[0117] According to one or more embodiments, wherein the conductive substrate is a pre-molded lead frame having a pre-molded compound in the opening, the method further includes removing the pre-molded compound from the opening before arranging the at least one conductive clip in a bridge-like position between the at least one semiconductor die and at least one conductive lead in the conductive lead array.
[0118] According to one or more embodiments, the method also includes welding the at least one conductive clip to the at least one semiconductor chip and the at least one conductive lead to provide electrical coupling between the at least one semiconductor chip and the at least one conductive lead, wherein the at least one conductive clip is fixed in the bridge-like position due to the carving in the distal portion engaging the opening.
[0119] According to one or more embodiments, the method further includes: including the conductive substrate in a conductive substrate set having corresponding die mounting positions, wherein the conductive substrates in the set are coupled via sacrificial connecting bars between conductive leads in adjacent conductive substrates in the set; processing the conductive substrates in the set coupled via the sacrificial connecting bars by: arranging semiconductor die at corresponding die mounting positions, and arranging a conductive clip at a bridge-like position between the semiconductor die arranged at the corresponding die mounting position and the conductive leads in the conductive lead array of the conductive substrate in the set to provide electrical coupling between the semiconductor die at the corresponding die mounting position and the conductive leads in the conductive lead array of the conductive substrate in the set; and after the processing, cutting the conductive substrate set on which the semiconductor die and the conductive clip are arranged at the sacrificial connecting bars, producing a singulated semiconductor device as a result of the cutting, wherein the distal end portion of the conductive clip is exposed at the periphery of the singulated semiconductor device.
[0120] One or more embodiments are directed to a method.
[0121] One or more embodiments are directed to corresponding integrated circuit semiconductor devices.
[0122] In the solution described here, a clip having a defined shape is formed starting from a metallic material, for example copper.
[0123] In a solution as described herein, such a clip may be provided with pins formed via additive manufacturing techniques, optionally via Laser Induced Forward Transfer (LIFT).
[0124] The solution described herein advantageously utilizes peripheral features of the lead frame for centering purposes without having additional recesses on the pads.
[0125] The solution described herein can also be applied to lead frames of the pre-molded type.
[0126] The solution described herein contemplates providing a lead frame on which a die is mounted, with electrical connections being made between the die and leads in the lead frame by clip bonding.
[0127] In one embodiment, a method includes: arranging at least one semiconductor die at a die mounting location of a conductive substrate, the conductive substrate including an array of conductive leads having an opening at a periphery of the conductive substrate; arranging at least one conductive clip in a bridge-like position between the at least one semiconductor die and at least one conductive lead in the array of conductive leads to provide electrical coupling therebetween. The at least one conductive clip is provided with an end configured to couple to the at least one conductive lead in the array of conductive leads. The end includes: a planar proximal portion configured to contact the at least one conductive lead at a proximal end of the opening; and a distal portion protruding from its distal end beyond the proximal portion, the distal portion having an engraving configured to engage the opening to facilitate fixing the at least one conductive clip in the bridge-like position between the at least one semiconductor die and the at least one conductive lead in the array of conductive leads.
[0128] In one embodiment, a device includes: at least one semiconductor die arranged at a die mounting position of a conductive substrate, the conductive substrate including an array of conductive leads, the array of conductive leads having a notch at the periphery of the conductive substrate; at least one conductive clip arranged in a bridge-like position between the at least one semiconductor die and at least one conductive lead in the array of conductive leads to provide electrical coupling therebetween, wherein the at least one conductive clip has an end coupled to the at least one conductive lead in the array of conductive leads. The end includes: a planar proximal portion that contacts the at least one conductive lead at a proximal end of the notch, and a distal portion that protrudes beyond the proximal portion at a distal end, the distal portion being provided with an engraving that engages the notch and fixes the at least one conductive clip in the bridge-like position, wherein the distal portion of the at least one conductive clip is exposed at the periphery of the device, the bridge-like position being arranged between the at least one semiconductor die and the at least one conductive lead in the array of conductive leads.
[0129] The steps discussed so far are merely exemplary, as in actual processes, other steps may be added or performed in different ways.
[0130] The claims are an integral part of the technical teaching provided with respect to the embodiments.
[0131] Without prejudice to the essential principles, the details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without departing from the scope of protection, which is determined by the appended claims.
Claims
1. A semiconductor device, characterized in that: include: a conductive substrate including an array of conductive leads having a plurality of notches at a periphery of the conductive substrate; at least one semiconductor die disposed at a die mounting location of the conductive substrate; at least one conductive clip disposed in a bridge-like position between the at least one semiconductor die and at least one conductive lead in the array of conductive leads to provide electrical coupling between the at least one semiconductor die and the at least one conductive lead; wherein the at least one conductive clip has a terminal end coupled to the at least one conductive lead in the array of conductive leads; Wherein the end comprises: a planar proximal portion contacting the at least one conductive lead at a proximal end of the recess; as well as A distal portion protrudes beyond the proximal portion, the distal portion being provided with an engraving that engages the recess and secures the at least one conductive clip in the bridge-like position between the at least one semiconductor chip and the at least one conductive lead in the conductive lead array, wherein the distal portion of the at least one conductive clip is exposed at the periphery of the device.
2. The semiconductor device according to claim 1, wherein: The distal portion has a fork-like shape comprising a plurality of prongs protruding distally beyond the proximal portion, and wherein the engraving is provided in the plurality of prongs.
3. The semiconductor device according to claim 1, wherein: The end of the at least one conductive clip is a lower portion of the conductive clip.
4. The semiconductor device according to claim 1, wherein: The engraving includes at least one protrusion from a distal portion of the tip of the at least one conductive clip.
5. The semiconductor device according to claim 1, wherein: The conductive substrate is a pre-molded lead frame having a pre-molding compound, and wherein the pre-molding compound is absent in the recess.
6. The semiconductor device according to claim 1, wherein: Also included are solder bumps between the at least one conductive clip and the at least one semiconductor chip and between the at least one conductive clip and the at least one conductive lead.
7. The semiconductor device according to claim 1, wherein: A package body is also included, and wherein a distal end portion of the conductive clip is exposed at a periphery of the package body.
Citation Information
Patent Citations
Method of manufacturing semiconductor devices and corresponding semiconductor device
US20230245955A1