Controllable under-voltage and overvoltage protection circuit

Abstract

The utility model provides a controllable under-voltage and over-voltage protection circuit, which comprises a power supply access end connected with an external power supply and an output connection end used for output connection, the anti-reverse-connection circuit is connected with the power supply access end and used for preventing equipment damage caused by reverse connection of positive and negative power supplies; the low-voltage power supply generation circuit is connected with the output end of the anti-reverse-connection circuit and used for providing stable working voltage; the voltage comparison circuit is connected with the output end of the anti-reverse-connection circuit and used for determining whether the voltage of the output end of the anti-reverse-connection circuit is overvoltage or undervoltage or not through comparison, and the output end of the switching circuit is connected with the output connection end. The voltage comparison circuit is connected with the switching circuit through the logic circuit to form an under-voltage and over-voltage comparison protection circuit, and the low-voltage power supply generation circuit is connected with the logic circuit. According to the utility model, the logic structure can be simplified, the cost is reduced and the reliability is strong.

Description

Technical Field

[0001] The utility model relates to the technical field of power protection, in particular to a controllable undervoltage and overvoltage protection circuit. Background Art

[0002] In order to improve the flexibility of equipment, many devices have adopted a wide input voltage design, that is, the working power supply voltage of the equipment can be within a range, such as 9V-36V, 9-60V, etc., and the devices used in the equipment are also selected according to these ranges. When the power supply voltage exceeds the range specified by the equipment, the internal devices of the equipment are at risk of not working properly or even being damaged. Therefore, it is necessary to perform undervoltage protection on the lowest input voltage of the equipment and overvoltage protection on the highest input voltage of the equipment. The existing overvoltage and undervoltage circuit design usually adopts MOS tubes, TVS tubes and resistors and capacitors, and uses the overvoltage breakdown characteristics of TVS tubes to control the on and off of MOS tubes, thereby controlling the on and off of power supply to achieve the purpose of overvoltage and undervoltage protection. Due to the large discreteness of individual parameters of TVS tubes, their reverse breakdown voltages often vary greatly, making it difficult to achieve accurate overvoltage and undervoltage protection. For example, the publication number CN208226559U authorization announcement date 2018 12 11 is provided with a reference voltage circuit, an overvoltage protection circuit, and an undervoltage protection circuit. The reference voltage circuit is connected to the input end of the undervoltage protection circuit and the overvoltage protection circuit respectively. The overvoltage protection circuit and the undervoltage protection circuit are connected to the front-stage rectifier filter circuit. The overvoltage protection circuit and the undervoltage protection circuit are both connected to the PWM controller. Such a circuit is relatively complex in structure and its stability cannot be guaranteed. Utility Model Content

[0003] The utility model provides a controllable undervoltage and overvoltage protection circuit, which can simplify the logic structure, reduce the cost and has high reliability.

[0004] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0005] A controllable undervoltage and overvoltage protection circuit comprises a power supply access terminal connected to an external power supply and an output connection terminal for output connection, and also comprises an anti-reverse connection circuit connected to the power supply access terminal for preventing the positive and negative connections of the power supply from being reversed and causing damage to the equipment, a low-voltage power supply generating circuit connected to the output terminal of the anti-reverse connection circuit for providing a stable working voltage, a voltage comparison circuit connected to the output terminal of the anti-reverse connection circuit for determining by comparison whether the voltage at the output terminal of the anti-reverse connection circuit is overvoltage or undervoltage, and a switch circuit connected to the output terminal of the anti-reverse connection circuit, wherein the output terminal of the switch circuit is connected to the output connection terminal, the voltage comparison circuit is connected to the switch circuit through a logic circuit to form an undervoltage and overvoltage comparison protection circuit, and the low-voltage power supply generating circuit is connected to the logic circuit.

[0006] Preferably, the anti-reverse connection circuit is provided with a fifty-third MOS tube, the drain of the fifty-third MOS tube is connected to the power access terminal, the gate of the fifty-third MOS tube is connected to the ground line through the seven hundred and sixty-ninth resistor, the source of the fifty-third MOS tube is connected to the gate of the fifty-third MOS tube through the seven hundred and seventy resistor and the one hundred and twenty-ninth voltage-stabilizing diode in sequence, and the source of the fifty-third MOS tube is also connected to the gate of the fifty-third MOS tube through the seven hundred and seventy-first resistor.

[0007] Preferably, the low-voltage power supply generating circuit is provided with a reference voltage source chip, and the reference voltage source chip is provided with a 687th resistor and a 685th resistor for voltage division, and the reference voltage source chip is connected to the output end of the anti-reverse connection circuit via the 681st resistor and the 682nd resistor in sequence, and the reference voltage source chip is connected to the output end of the anti-reverse connection circuit via the 683rd resistor and the 684th resistor in sequence to form a power supply voltage dividing resistor circuit, and the reference voltage source chip is also connected to the ground wire via the 550th capacitor to form the output end of the power supply generating circuit.

[0008] Preferably, the voltage comparison circuit is provided with a voltage comparator chip, the first input terminal of the voltage comparator chip is connected to the output terminal of the anti-reverse connection circuit through the six hundred and seventy-sixth resistor and the seven hundred and fifty resistor in sequence, and the first input terminal of the voltage comparator chip is also connected to the ground wire through the six hundred and seventy-fifth resistor to form an undervoltage protection threshold circuit, the second input terminal of the voltage comparator chip is connected to the output terminal of the anti-reverse connection circuit through the six hundred and seventy-fourth resistor and the seven hundred and forty-ninth resistor in sequence, and the second input terminal of the voltage comparator chip is also connected to the ground wire through the six hundred and seventy-third resistor to form an overvoltage protection threshold circuit, the power supply terminal of the voltage comparator chip is connected to the ground wire through the five hundred and forty-ninth capacitor, and the first output terminal and the second output terminal of the voltage comparator chip are both connected to the logic circuit.

[0009] Preferably, the first input terminal of the voltage comparator chip is also connected to the ground wire through the seven hundred and thirty-first capacitor and the one hundred and twenty-eighth Zener diode, and the second input terminal of the voltage comparator chip is also connected to the ground wire through the seven hundred and thirty-second capacitor and the one hundred and twenty-seventh Zener diode.

[0010] Preferably, the logic circuit is provided with a forty-seventh MOS tube, a forty-eighth MOS tube and a forty-ninth MOS tube, the gate of the forty-seventh MOS tube is connected to the second output end of the voltage comparator chip through a five-hundred-seventy-seventh resistor, the drain of the forty-seventh MOS tube is connected to the output end of the low-voltage power supply generating circuit through a six-hundred-seventy-ninth resistor, and the source of the forty-seventh MOS tube is connected to the ground line, the gate of the forty-eighth MOS tube is connected to the drain of the forty-seventh MOS tube through a six-hundred-seventy-eighth resistor, and the connection end of the six-hundred-seventy-eighth resistor and the drain of the forty-seventh MOS tube is connected to the ground line through a seven-hundred-fifty-seventh resistor, the drain of the forty-eighth MOS tube is connected to the source of the forty-ninth MOS tube, the source of the forty-eighth MOS tube is connected to the ground line, the gate of the forty-ninth MOS tube is connected to the first output end of the voltage comparator chip through a six-hundred-seventy-seventh resistor, and the connection end of the six-hundred-seventh resistor and the first output end of the voltage comparator chip is connected to the ground line through a seven-hundred-fifty-sixth resistor, and the drain of the forty-ninth MOS tube is connected to the switch circuit.

[0011] Preferably, the switch circuit is provided with a twelfth MOS tube, the gate of the twelfth MOS tube is connected to the logic circuit through the six hundred and eighty resistor and the seven hundred and fifty-eight resistor in sequence, the gate of the twelfth MOS tube is connected to the source of the twelfth MOS tube through the three hundred and sixth resistor and is also connected to the source of the twelfth MOS tube through the one hundred and twenty-sixth voltage-stabilizing diode and the six hundred and eighty-eighth resistor in sequence, the source of the twelfth MOS tube is connected to the output end of the anti-reverse connection circuit, the drain of the twelfth MOS tube is connected to the output connection end, and the drain of the twelfth MOS tube is also connected to the ground wire through the seven hundred and thirteenth capacitor, the seven hundred and thirty capacitor and the seven hundred and twelfth capacitor respectively.

[0012] Compared with the prior art, the beneficial effects of the utility model are:

[0013] In the utility model, the voltage comparison circuit controls the operation of the switch circuit by sampling the voltage at the output end of the anti-reverse connection circuit to control the operation of the logic circuit, thereby accurately performing undervoltage and overvoltage protection, which can simplify the logic structure, reduce costs, and have strong reliability. The setting of the anti-reverse connection circuit in the utility model can prevent the positive and negative power supply from being connected in reverse and causing damage to the equipment. The setting of the low-voltage power supply generation circuit in the utility model can provide a stable voltage to ensure the stable operation of the voltage comparison circuit and the logic circuit, thereby improving the stability of the circuit operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a circuit control block diagram of the utility model;

[0015] Figure 2 It is a circuit connection diagram of the anti-reverse connection circuit in the utility model;

[0016] Figure 3 It is a circuit connection diagram of the low voltage power supply generating circuit of the utility model;

[0017] Figure 4 It is a circuit connection diagram of the voltage comparison circuit in the utility model;

[0018] Figure 5 It is a circuit connection diagram of the logic circuit in the utility model;

[0019] Figure 6 It is a circuit connection diagram of the switch circuit in the utility model. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of them. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0021] refer to Figure 1-6 A controllable undervoltage and overvoltage protection circuit includes a power access terminal VIN connected to an external power supply and an output connection terminal VOUT for output connection, and also includes an anti-reverse connection circuit 1 connected to the power access terminal VIN to prevent the positive and negative power supply from being connected in reverse and causing damage to the equipment, a low-voltage power supply generating circuit 3 connected to the output end of the anti-reverse connection circuit 1 to provide a stable working voltage, a voltage comparison circuit 4 connected to the output end of the anti-reverse connection circuit 1 to determine whether the output end voltage of the anti-reverse connection circuit 1 is overvoltage or undervoltage by comparison, and a switch circuit 2 connected to the output end of the anti-reverse connection circuit 1, the output end of the switch circuit 2 is connected to the output connection terminal VOUT, the voltage comparison circuit 4 is connected to the switch circuit 2 through a logic circuit 5 to form an undervoltage and overvoltage comparison protection circuit, and the low-voltage power supply generating circuit 3 is connected to the logic circuit 5.

[0022] The anti-reverse connection circuit 1 is provided with a fifty-third MOS transistor Q53, the drain of the fifty-third MOS transistor Q53 is connected to the power supply access terminal VIN, the gate of the fifty-third MOS transistor Q53 is connected to the ground line through the seven hundred and sixty-ninth resistor R769, the source of the fifty-third MOS transistor Q53 is connected to the gate of the fifty-third MOS transistor Q53 through the seven hundred and seventy-seventh resistor R770 and the one hundred and twenty-ninth voltage stabilizing diode D129 in sequence, and the source of the fifty-third MOS transistor Q53 is also connected to the gate of the fifty-third MOS transistor Q53 through the seven hundred and seventy-first resistor R771. In this embodiment, when the power supply access terminal VIN is connected to the positive electrode, a voltage division is formed between the seven hundred and seventy-first resistor R771 and the seven hundred and sixty-ninth resistor R769, and the fifty-third MOS transistor Q53 is turned on. When the power supply access terminal VIN is connected to the negative electrode, the fifty-third MOS transistor is turned off, thereby realizing the anti-reverse connection function. The seven hundred and seventy resistor R770 and the one hundred and twenty-ninth voltage-stabilizing diode D129 form a protection circuit, so that the VGS voltage in the fifty-third MOS tube Q53 does not exceed the rated value of the fifty-third MOS tube Q53, thereby preventing the fifty-third MOS tube Q53 from being damaged due to excessive high voltage.

[0023] The low voltage power supply generating circuit 3 is provided with a reference voltage source chip U32, and the reference voltage source chip U32 is provided with a six hundred and eighty-seventh resistor R687 and a six hundred and eighty-fifth resistor R685 for voltage division, and the reference voltage source chip U32 is connected to the output end of the anti-reverse connection circuit 1 through the six hundred and eighty-first resistor R681 and the six hundred and eighty-second resistor R682 in sequence, and the reference voltage source chip U32 is connected to the output end of the anti-reverse connection circuit 1 through the six hundred and eighty-third resistor R683 and the six hundred and eighty-fourth resistor R684 in sequence to form a power supply voltage-dividing resistor circuit, and the reference voltage source chip U32 is also connected to the ground wire through the five hundred and fifty capacitor C550 to form the output end of the power supply generating circuit. In this embodiment, the reference voltage source chip U32 outputs a DC 3.3V voltage. The power supply voltage-dividing resistor circuit can withstand a DC 70V voltage input without causing damage to the reference voltage source chip U32.

[0024] The voltage comparison circuit 4 is provided with a voltage comparator chip U42, and the first input terminal of the voltage comparator chip U42 is connected to the output terminal of the anti-reverse connection circuit 1 through the six-hundred-and-seventy-sixth resistor R676 and the seven-hundred-and-fiftieth resistor R750 in sequence, and the first input terminal of the voltage comparator chip U42 is also connected to the ground wire through the six-hundred-and-seventy-fifth resistor R675 to form an undervoltage protection threshold circuit, the second input terminal of the voltage comparator chip U42 is connected to the output terminal of the anti-reverse connection circuit 1 through the six-hundred-and-seventy-fourth resistor R674 and the seven-hundred-and-forty-ninth resistor R749 in sequence, and the second input terminal of the voltage comparator chip U42 is also connected to the ground wire through the six-hundred-and-seventy-third resistor R673 to form an overvoltage protection threshold circuit, the power supply terminal of the voltage comparator chip U42 is connected to the ground wire through the five-hundred-and-forty-ninth capacitor C549, and the first output terminal and the second output terminal of the voltage comparator chip U42 are both connected to the logic circuit 5. In this embodiment, the power supply terminal of the voltage comparator chip U42 is connected to the DC 3.3V voltage stably output by the reference voltage source chip U32, and the voltage comparator chip U42 contains a reference comparison voltage. The setting of the undervoltage protection threshold circuit and the overvoltage protection threshold circuit enables overvoltage and undervoltage comparison to be performed respectively, and the undervoltage and overvoltage threshold values ​​can be accurately controlled by adjusting the resistance value in the circuit, thereby controlling the undervoltage and overvoltage threshold values ​​to meet the power protection needs of different power circuits.

[0025] The first input terminal of the voltage comparator chip U42 is also connected to the ground through the seven hundred and thirty-first capacitor C731 and the one hundred and twenty-eighth Zener diode D128, and the second input terminal of the voltage comparator chip U42 is also connected to the ground through the seven hundred and thirty-second capacitor C732 and the one hundred and twenty-seventh Zener diode D127.

[0026] The logic circuit 5 is provided with a forty-seventh MOS tube Q47, a forty-eighth MOS tube Q48 and a forty-ninth MOS tube Q49. The gate of the forty-seventh MOS tube Q47 is connected to the second output end of the voltage comparator chip U42 through a five-hundred-seventy-seventh resistor R577, the drain of the forty-seventh MOS tube Q47 is connected to the output end of the low-voltage power supply generating circuit 3 through a six-hundred-seventy-ninth resistor R679, and the source of the forty-seventh MOS tube Q47 is connected to the ground line, the gate of the forty-eighth MOS tube Q48 is connected to the drain of the forty-seventh MOS tube Q47 through a six-hundred-seventy-eighth resistor R678, and the six-hundred-seventy-eighth resistor R679 is connected to the ground line. 8 and the connection end of the drain of the forty-seventh MOS tube Q47 are connected to the ground through the seven hundred and fifty-seventh resistor R757, the drain of the forty-eighth MOS tube Q48 is connected to the source of the forty-ninth MOS tube Q49, the source of the forty-eighth MOS tube Q48 is connected to the ground, the gate of the forty-ninth MOS tube Q49 is connected to the first output end of the voltage comparator chip U42 through the six hundred and seventy-seventh resistor R677 and the connection end of the six hundred and seventy-seventh resistor R677 and the first output end of the voltage comparator chip U42 is connected to the ground through the seven hundred and fifty-sixth resistor R756, and the drain of the forty-ninth MOS tube Q49 is connected to the switch circuit 2.

[0027] The switch circuit 2 is provided with a twelfth MOS transistor Q12, the gate of the twelfth MOS transistor Q12 is connected to the logic circuit 5 through the six-hundred-eightie resistor R680 and the seven-hundred-fifty-eight resistor R758 in sequence, the gate of the twelfth MOS transistor Q12 is connected to the source of the twelfth MOS transistor Q12 through the three-hundred-sixth resistor R306 and is also connected to the source of the twelfth MOS transistor Q12 through the one-hundred-twenty-sixth voltage-stabilizing diode D126 and the six-hundred-eighth resistor R688 in sequence, the source of the twelfth MOS transistor Q12 is connected to the output end of the anti-reverse connection circuit 1, the drain of the twelfth MOS transistor Q12 is connected to the output connection end VOUT, and the drain of the twelfth MOS transistor Q12 is also connected to the ground line through the seven-hundred-thirteenth capacitor C713, the seven-hundred-thirtieth capacitor C730 and the seven-hundred-twelfth capacitor C712 respectively. In this embodiment, the one-hundred-and-twenty-sixth voltage-stabilizing diode D126 and the six-hundred-and-eighth resistor R688 form a protection circuit to prevent the twelfth MOS tube Q12 from being damaged due to excessive VGS.

[0028] In this embodiment, when the voltage at the power supply access terminal VIN is lower than the set undervoltage threshold value, the first output terminal of the voltage comparator chip U42 outputs a low level, the 49th MOS tube Q49 is turned off, the second output terminal of the voltage comparator chip U42 outputs a low level, the 47th MOS tube Q47 is turned off, the 48th MOS tube Q48 is turned on, the 12th MOS tube Q12 is turned off, the switch circuit 2 is turned off, and the output connection terminal VOUT has no voltage output. When the voltage at the power supply access terminal VIN is between the undervoltage threshold value and the overvoltage threshold value, the first output terminal of the voltage comparator chip U42 outputs a high level, the 49th MOS tube Q49 is turned on, the second output terminal of the voltage comparator chip U42 outputs a low level, the 47th MOS tube Q47 is turned off, the 48th MOS tube Q48 is turned on, the 12th MOS tube Q12 is turned on, the switch circuit 2 is turned on, and the output connection terminal VOUT outputs a voltage. When the voltage at the power supply access terminal VIN is higher than the overvoltage threshold, the first output terminal of the voltage comparator chip U42 outputs a high level, the 49th MOS tube Q49 is turned on, the second output terminal of the voltage comparator chip U42 outputs a high level, the 47th MOS tube Q47 is turned on, the 48th MOS tube Q48 is turned off, the 12th MOS tube Q12 is turned off, the switch circuit 2 is turned off, and the output connection terminal VOUT has no voltage output. Therefore, the utility model can accurately perform undervoltage and overvoltage protection, simplify the logic structure, reduce costs, and has strong reliability.

[0029] The above are only preferred embodiments of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the present invention through the above teachings or the technology or knowledge in the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A controllable undervoltage and overvoltage protection circuit, comprising a power supply input terminal (VIN) connected to an external power supply and an output connection terminal (VOUT) for output connection, characterized in that: The invention also comprises an anti-reverse connection circuit (1) connected to a power supply input terminal (VIN) for preventing the positive and negative power supply from being connected in reverse and causing damage to the device, a low-voltage power supply generating circuit (3) connected to the output terminal of the anti-reverse connection circuit (1) for providing a stable working voltage, a voltage comparison circuit (4) connected to the output terminal of the anti-reverse connection circuit (1) for determining by comparison whether the voltage at the output terminal of the anti-reverse connection circuit (1) is overvoltage or undervoltage, and a switch circuit (2) connected to the output terminal of the anti-reverse connection circuit (1), wherein the output terminal of the switch circuit (2) is connected to the output connection terminal (VOUT), the voltage comparison circuit (4) is connected to the switch circuit (2) through a logic circuit (5) to form an undervoltage and overvoltage comparison protection circuit, and the low-voltage power supply generating circuit (3) is connected to the logic circuit (5).

2. A controllable undervoltage and overvoltage protection circuit according to claim 1, characterized in that: The anti-reverse connection circuit (1) is provided with a fifty-third MOS tube (Q53), the drain of the fifty-third MOS tube (Q53) is connected to the power supply access terminal (VIN), the gate of the fifty-third MOS tube (Q53) is connected to the ground line through a seven-hundred-sixty-ninth resistor (R769), the source of the fifty-third MOS tube (Q53) is connected to the gate of the fifty-third MOS tube (Q53) through a seven-hundred-seventy resistor (R770) and a one-hundred-twenty-ninth voltage-stabilizing diode (D129) in sequence, and the source of the fifty-third MOS tube (Q53) is also connected to the gate of the fifty-third MOS tube (Q53) through a seven-hundred-seventy-first resistor (R771).

3. The controllable undervoltage and overvoltage protection circuit according to claim 1, characterized in that: The low-voltage power supply generating circuit (3) is provided with a reference voltage source chip (U32), and the reference voltage source chip (U32) is provided with a six-hundred-eighty-seventh resistor (R687) and a six-hundred-eighty-fifth resistor (R685) for voltage division. The reference voltage source chip (U32) is connected to the output end of the anti-reverse connection circuit (1) through a six-hundred-eighty-first resistor (R681) and a six-hundred-eighty-second resistor (R682) in sequence. The reference voltage source chip (U32) is connected to the output end of the anti-reverse connection circuit (1) through a six-hundred-eighty-third resistor (R683) and a six-hundred-eighty-fourth resistor (R684) in sequence to form a power supply voltage dividing resistor circuit. The reference voltage source chip (U32) is also connected to the ground wire through a five-hundred-fiftieth capacitor (C550) to form the output end of the power supply generating circuit.

4. A controllable undervoltage and overvoltage protection circuit according to claim 1 or 3, characterized in that: The voltage comparison circuit (4) is provided with a voltage comparator chip (U42), the first input end of the voltage comparator chip (U42) is connected to the output end of the anti-reverse connection circuit (1) through the six hundred and seventy-sixth resistor (R676) and the seven hundred and fifty resistor (R750) in sequence, and the first input end of the voltage comparator chip (U42) is also connected to the ground wire through the six hundred and seventy-fifth resistor (R675) to form an undervoltage protection threshold circuit, and the second input end of the voltage comparator chip (U42) is connected to the ground wire through the six hundred and seventy-fifth resistor (R675) in sequence. The one hundred and seventy-fourth resistor (R674) and the seven hundred and forty-ninth resistor (R749) are connected to the output end of the anti-reverse connection circuit (1), and the second input end of the voltage comparator chip (U42) is also connected to the ground wire through the six hundred and seventy-third resistor (R673) to form an overvoltage protection threshold circuit, the power supply end of the voltage comparator chip (U42) is connected to the ground wire through the five hundred and forty-ninth capacitor (C549), and the first output end and the second output end of the voltage comparator chip (U42) are both connected to the logic circuit (5).

5. A controllable undervoltage and overvoltage protection circuit according to claim 4, characterized in that: The first input end of the voltage comparator chip (U42) is also connected to the ground wire through the seven hundred and thirty-first capacitor (C731) and the one hundred and twenty-eighth voltage-stabilizing diode (D128), and the second input end of the voltage comparator chip (U42) is also connected to the ground wire through the seven hundred and thirty-second capacitor (C732) and the one hundred and twenty-seventh voltage-stabilizing diode (D127).

6. A controllable undervoltage and overvoltage protection circuit according to claim 4, characterized in that: The logic circuit (5) is provided with a forty-seventh MOS tube (Q47), a forty-eighth MOS tube (Q48) and a forty-ninth MOS tube (Q49); the gate of the forty-seventh MOS tube (Q47) is connected to the second output end of the voltage comparator chip (U42) through a five-hundred-seventy-seventh resistor (R577); the drain of the forty-seventh MOS tube (Q47) is connected to the output end of the low-voltage power supply generating circuit (3) through a six-hundred-seventy-ninth resistor (R679); and the source of the forty-seventh MOS tube (Q47) is connected to the ground line; the gate of the forty-eighth MOS tube (Q48) is connected to the drain of the forty-seventh MOS tube (Q47) through a six-hundred-seventy-eighth resistor (R678); and the six-hundred-seventy-eighth resistor (R679) is connected to the ground line. The connection end of the drain of the forty-seventh MOS tube (Q47) and the forty-seventh MOS tube (Q47) is connected to the ground line through the seven hundred and fifty-seventh resistor (R757), the drain of the forty-eighth MOS tube (Q48) is connected to the source of the forty-ninth MOS tube (Q49), the source of the forty-eighth MOS tube (Q48) is connected to the ground line, the gate of the forty-ninth MOS tube (Q49) is connected to the first output end of the voltage comparator chip (U42) through the six hundred and seventy-seventh resistor (R677), and the connection end of the six hundred and seventy-seventh resistor (R677) and the first output end of the voltage comparator chip (U42) is connected to the ground line through the seven hundred and fifty-sixth resistor (R756), and the drain of the forty-ninth MOS tube (Q49) is connected to the switch circuit (2).

7. The controllable undervoltage and overvoltage protection circuit according to claim 1, characterized in that: The switch circuit (2) is provided with a twelfth MOS tube (Q12), the gate of the twelfth MOS tube (Q12) is connected to the logic circuit (5) through a six-hundred-eightieth resistor (R680) and a seven-hundred-fiftieth resistor (R758) in sequence, the gate of the twelfth MOS tube (Q12) is connected to the source of the twelfth MOS tube (Q12) through a three-hundred-sixth resistor (R306) and is also connected to the source of the twelfth MOS tube (Q12) through a one-hundred-twenty-sixth voltage-stabilizing diode (D126) and a six-hundred-eighth resistor (R758) in sequence. The eight resistors (R688) are connected to the source of the twelfth MOS tube (Q12), the source of the twelfth MOS tube (Q12) is connected to the output end of the anti-reverse connection circuit (1), the drain of the twelfth MOS tube (Q12) is connected to the output connection end (VOUT), and the drain of the twelfth MOS tube (Q12) is also connected to the ground line through the seven-hundred-thirteenth capacitor (C713), the seven-hundred-thirtieth capacitor (C730) and the seven-hundred-twelfth capacitor (C712).

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