Novel laminated LTCC (Low Temperature Co-Fired Ceramic) power divider

Abstract

The utility model discloses a novel laminated LTCC (Low Temperature Co-Fired Ceramic) power divider, which is based on an LTCC (Low Temperature Co-Fired Ceramic) technology and adopts lumped parameter model design to realize the special electrical performance requirement of the novel laminated LTCC power divider. The low-return-loss and high-reliability low-cost single-mode filter has the advantages of being low in return loss, highly consistent in amplitude and phase of output signals, high in reliability, low in cost, excellent in consistency, suitable for large-scale production and the like, and further adapts to the development trend of integration and miniaturization of new electronic components.

Description

Technical Field

[0001] The utility model discloses a power divider, in particular to a novel laminated chip LTCC power divider, which can be used for wireless connection of mobile phones, tablets, automotive electronics and various other communication devices, and belongs to the technical field of electronic components of communication equipment. Background Art

[0002] LTCC (Low Temperatrue Co-fired Ceramic) is a new material technology developed by Hughes Corporation in the United States in 1982. It is a process of making low-temperature sintered ceramic powder into a green ceramic tape with precise thickness and density, on which the required circuit pattern is made by laser drilling, micropore grouting, precision conductor paste printing and other processes, and multiple passive devices are embedded in it for lamination, and finally sintered at below 1000℃, on which ICs and active devices can be mounted, thus forming a LTCC passive / active integrated functional module.

[0003] With the development of technology, the requirements for the performance and functions of electronic components and assemblies are getting higher and higher, while the size of the products is required to be smaller and smaller. LTCC technology can meet these two requirements, so it has been widely used in the field of microelectronics. At present, filters, duplexers, power dividers, bridges, baluns and other products manufactured by LTCC technology have been widely used in consumer electronics, communications, automotive electronics, military and other markets. The current power divider is limited by the process and structure, and the size is large, which will cause the problem of large size of the electronic equipment used. Summary of the invention

[0004] In view of the above-mentioned shortcoming of the large size of the power divider in the prior art, the utility model provides a novel laminated chip LTCC power divider, which is based on LTCC (low temperature co-fired ceramic) technology and adopts a lumped parameter model design to achieve the special electrical performance requirements of a novel laminated chip LTCC power divider, and has the advantages of low return loss, highly consistent output signal amplitude and phase, high reliability, low cost, excellent consistency and suitability for large-scale production.

[0005] The utility model solves the technical problem by adopting a technical solution: a novel laminated chip LTCC power divider, the power divider includes a ceramic substrate, a connection port arranged outside the ceramic substrate and an internal circuit structure layer arranged inside the ceramic substrate, six connection ports are provided, the first port, the third port and the fifth port are ground ports, the second port is a common port, the fourth port and the sixth port are two output ports, and the internal circuit structure layers are as follows from bottom to top:

[0006] The first layer has two mutually insulated metal plane conductors printed on a ceramic dielectric substrate, which are a first metal plane conductor and a second metal plane conductor. The first metal plane conductor and the second metal plane conductor are both in a "C" shape. One end of the first metal plane conductor is connected to the sixth port through a first internal endpoint, and the other end of the first metal plane conductor is a third internal endpoint, which is connected to the first metal point column. One end of the second metal plane conductor is connected to the fourth port through a second internal endpoint, and the other end of the second metal plane conductor is a fourth internal endpoint, which is connected to the second metal point column.

[0007] The second layer has two mutually insulated metal plane conductors printed on the ceramic dielectric substrate, which are the third metal plane conductor and the fourth metal plane conductor. The third metal plane conductor and the fourth metal plane conductor are both in an "L" shape. One end of the third metal plane conductor is the fifth internal endpoint, which is connected to the third internal endpoint in the first layer through the first metal dot column. The other end of the third metal plane conductor is the seventh internal endpoint, which is connected to the third metal dot column. One end of the fourth metal plane conductor is the sixth internal endpoint, which is connected to the fourth internal endpoint in the first layer through the second metal dot column. The other end of the fourth metal plane conductor is the eighth internal endpoint, which is connected to the fourth metal dot column.

[0008] The third layer has two mutually insulated metal plane conductors printed on the ceramic dielectric substrate, which are the fifth metal plane conductor and the sixth metal plane conductor. The fifth metal plane conductor and the sixth metal plane conductor are both in an "L" shape. One end of the fifth metal plane conductor is a ninth internal terminal, which is connected to the seventh internal terminal in the second layer through the third metal dot column. The other end of the fifth metal plane conductor is an eleventh internal terminal, which is connected to the fifth metal dot column. One end of the sixth metal plane conductor is a tenth internal terminal, which is connected to the eighth internal terminal in the second layer through the fourth metal dot column. The other end of the sixth metal plane conductor is a twelfth internal terminal, which is connected to the sixth metal dot column.

[0009] The fourth layer is printed on the ceramic dielectric substrate with two mutually insulated metal plane conductors, which are the seventh metal plane conductor and the eighth metal plane conductor. The seventh metal plane conductor and the eighth metal plane conductor are both in a "U" shape. One end of the seventh metal plane conductor is the thirteenth internal terminal, which is connected to the eleventh internal terminal in the third layer through the fifth metal dot column. The other end of the seventh metal plane conductor is the fifteenth internal terminal, which is connected to the seventh metal dot column. One end of the eighth metal plane conductor is the fourteenth internal terminal, which is connected to the twelfth internal terminal in the third layer through the sixth metal dot column. The other end of the eighth metal plane conductor is the sixteenth internal terminal, which is connected to the eighth metal dot column.

[0010] The fifth layer is printed with two mutually insulated metal plane conductors on the ceramic dielectric substrate, which are a ninth metal plane conductor and a tenth metal plane conductor. The ninth metal plane conductor and the tenth metal plane conductor are both in an "L" shape. One end of the ninth metal plane conductor is a seventeenth internal terminal, which is connected to the fifteenth internal terminal in the fourth layer through the seventh metal dot column. The other end of the ninth metal plane conductor is a nineteenth internal terminal, which is connected to the ninth metal dot column. One end of the tenth metal plane conductor is an eighteenth internal terminal, which is connected to the sixteenth internal terminal in the fourth layer through the eighth metal dot column. The other end of the tenth metal plane conductor is a twentieth internal terminal, which is connected to the tenth metal dot column.

[0011] The sixth layer is printed with three mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the eleventh metal plane conductor, the twelfth metal plane conductor and the thirteenth metal plane conductor. The end of the eleventh metal plane conductor is the twenty-first internal terminal, which is connected to the nineteenth internal terminal in the fifth layer through the ninth metal dot column. The end of the twelfth metal plane conductor is the twenty-second internal terminal, which is connected to the twentieth internal terminal in the fifth layer through the tenth metal dot column. The end of the thirteenth metal plane conductor is the twenty-third internal terminal, which is connected to the second port through the twenty-third internal terminal.

[0012] The seventh layer is printed with three mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the fourteenth metal plane conductor, the fifteenth metal plane conductor and the sixteenth metal plane conductor. The end of the fourteenth metal plane conductor is the twenty-fourth internal terminal, and the fourteenth metal plane conductor is connected to the first port through the twenty-fourth internal terminal. The end of the fifteenth metal plane conductor is the twenty-fifth internal terminal, and the fifteenth metal plane conductor is connected to the third port through the twenty-fifth internal terminal. The end of the sixteenth metal plane conductor is the twenty-sixth internal terminal, and the sixteenth metal plane conductor is connected to the fifth port through the twenty-sixth internal terminal.

[0013] The eighth layer is printed with three mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the seventeenth metal plane conductor, the eighteenth metal plane conductor and the nineteenth metal plane conductor. The end of the seventeenth metal plane conductor is the twenty-seventh internal terminal, which is connected to the twenty-first internal terminal in the sixth layer through the eleventh metal dot column. The end of the eighteenth metal plane conductor is the twenty-eighth internal terminal, which is connected to the twenty-second internal terminal in the sixth layer through the twelfth metal dot column. The end of the nineteenth metal plane conductor is the twenty-ninth internal terminal, which is connected to the second port through the twenty-ninth internal terminal.

[0014] The ninth layer is printed on the ceramic dielectric substrate with two metal plane conductors, which are a twentieth metal plane conductor and a twenty-first metal plane conductor. The twentieth metal plane conductor and the twenty-first metal plane conductor are both in a "U" shape, and one end of the twentieth metal plane conductor and the twenty-first metal plane conductor are connected. One end of the twentieth metal plane conductor is a thirtieth internal terminal, and the other end of the twentieth metal plane conductor is a thirty-first internal terminal. One end of the twenty-first metal plane conductor is a thirtieth internal terminal, and the other end of the twenty-first metal plane conductor is a thirty-second internal terminal. The twentieth metal plane conductor and the twenty-first metal plane conductor are connected at the thirtieth internal terminal and connected to the second port through the thirtieth internal terminal. The thirty-first internal terminal is connected to the fifteenth metal dot column, and the thirty-second internal terminal is connected to the sixteenth metal dot column.

[0015] The tenth layer is a ceramic dielectric substrate on which two mutually insulated metal plane conductors are printed, which are a twenty-second metal plane conductor and a twenty-third metal plane conductor. The twenty-second metal plane conductor and the twenty-third metal plane conductor are both in a "U" shape. One end of the twenty-second metal plane conductor is a thirty-third internal terminal, which is connected to the thirty-first internal terminal in the ninth layer through a fifteenth metal dot column. The other end of the twenty-second metal plane conductor is a thirty-fifth internal terminal, which is connected to the seventeenth metal dot column. One end of the twenty-third metal plane conductor is a thirty-fourth internal terminal, which is connected to the thirty-second internal terminal in the ninth layer through a sixteenth metal dot column. The other end of the twenty-third metal plane conductor is a thirty-sixth internal terminal, which is connected to the eighteenth metal dot column.

[0016] The eleventh layer, two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, which are the twenty-fourth metal plane conductor and the twenty-fifth metal plane conductor, both of which are in a "U" shape, one end of the twenty-fourth metal plane conductor is the thirty-seventh internal terminal, which is connected to the thirty-fifth internal terminal in the tenth layer through the seventeenth metal dot column, the other end of the twenty-fourth metal plane conductor is the thirty-ninth internal terminal, which is connected to the nineteenth metal dot column, one end of the twenty-fifth metal plane conductor is the thirty-eighth internal terminal, which is connected to the thirty-sixth internal terminal in the tenth layer through the eighteenth metal dot column, the other end of the twenty-fifth metal plane conductor is the fortieth internal terminal, which is connected to the twentieth metal dot column;

[0017] On the twelfth layer, two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, which are the twenty-sixth metal plane conductor and the twenty-seventh metal plane conductor. Both of the twenty-sixth metal plane conductor and the twenty-seventh metal plane conductor are in an "L" shape. One end of the twenty-sixth metal plane conductor is the forty-first internal terminal, which is connected to the thirty-ninth internal terminal in the eleventh layer through the nineteenth metal dot column. The other end of the twenty-sixth metal plane conductor is the forty-third internal terminal, which is connected to the twenty-seventh internal terminal in the eighth layer through the thirteenth metal dot column. One end of the twenty-seventh metal plane conductor is the forty-second internal terminal, which is connected to the forty-second internal terminal in the eleventh layer through the twentieth metal dot column. The other end of the twenty-seventh metal plane conductor is the forty-fourth internal terminal, which is connected to the twenty-eighth internal terminal in the eighth layer through the fourteenth metal dot column.

[0018] The technical solution adopted by the utility model to solve its technical problems further includes:

[0019] The connection port is arranged outside the ceramic substrate and is a welding pad.

[0020] The said components are respectively arranged on both sides of the ceramic substrate.

[0021] The first port, the second port, the third port, the fourth port, the fifth port and the sixth port are all in a "concave" shape and are arranged on the surface of the ceramic substrate.

[0022] The metal planar conductors in the first, second, third, fourth and fifth layers are metal coils, the metal planar conductors in the sixth, seventh and eighth layers are capacitor substrates, and the metal planar conductors in the ninth, tenth, eleventh and twelfth layers are metal coils.

[0023] The beneficial effects of the utility model are as follows: the utility model is based on LTCC (low temperature co-fired ceramic) technology, adopts lumped parameter model design to realize the special electrical performance requirements of a new type of laminated chip LTCC power divider, and has the advantages of low return loss, highly consistent output signal amplitude and phase, high reliability, low cost, excellent consistency and suitability for large-scale production, and also adapts to the development trend of new electronic component integration and miniaturization.

[0024] The utility model will be further described below in conjunction with the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic diagram of the equivalent circuit of the new type of stacked chip LTCC power divider of the utility model.

[0026] Figure 2 This is a comparison diagram of S parameter results before and after adding inductors L3 and L4 to the equivalent circuit diagram of the new LTCC power divider of the utility model.

[0027] Figure 3 It is a schematic diagram of the structure of the LTCC vertical spiral inductor in the utility model.

[0028] Figure 4 It is a schematic diagram of the equivalent circuit of the LTCC vertical spiral inductor in the utility model.

[0029] Figure 5 It is a three-dimensional schematic diagram of the appearance structure of the new type of laminated LTCC power divider of the utility model.

[0030] Figure 6 This is a schematic diagram of the internal structure of the new type of stacked chip LTCC power divider of the utility model.

[0031] Figure 7 This is the S parameter electrical characteristic curve of the new type of stacked chip LTCC power divider of the utility model.

[0032] Figure 8 This is the radial consistency electrical characteristic curve of the new type of stacked chip LTCC power divider of the utility model.

[0033] Fig. 9 This is a schematic diagram of the planar structure of the first layer circuit of the utility model.

[0034] Fig.10 It is a schematic diagram of the planar structure of the point-column connection between the first and second floors and the point-column connection between the third and fourth floors of the utility model.

[0035] Fig.11 This is a schematic diagram of the planar structure of the second-layer circuit of the utility model.

[0036] Fig.12 It is a schematic diagram of the planar structure of the point column connection between the second and third floors of the utility model.

[0037] Fig.13 This is a schematic diagram of the planar structure of the third layer circuit of the utility model.

[0038] Fig.14 This is a schematic diagram of the plane structure of the fourth layer circuit of the utility model.

[0039] Fig.15 This is a schematic diagram of the planar structure of the point-column connection circuit between the fourth and fifth layers of the utility model.

[0040] Fig.16 This is a schematic diagram of the plane structure of the fifth layer circuit of the utility model.

[0041] Fig.17 It is a schematic diagram of the planar structure of the point-column connection between the fifth and sixth floors, the point-column connection between the sixth and seventh floors, the point-column connection between the seventh and eighth floors, and the point-column connection between the eighth and ninth floors of the utility model.

[0042] Fig.18 This is a schematic diagram of the planar structure of the sixth layer circuit of the utility model.

[0043] Fig.19 This is a schematic diagram of the planar structure of the seventh layer circuit of the utility model.

[0044] Fig. 20 This is a schematic diagram of the planar structure of the eighth layer circuit of the utility model.

[0045] Fig.21 This is a schematic diagram of the planar structure of the ninth layer circuit of the utility model.

[0046] Fig. 22 It is a schematic diagram of the planar structure of the point column connection between the ninth and tenth floors of the utility model.

[0047] Fig.23 This is a schematic diagram of the planar structure of the tenth layer circuit of the utility model.

[0048] Fig.24 It is a schematic diagram of the planar structure of the point column connection between the tenth and eleventh floors of the utility model.

[0049] Fig.25 This is a schematic diagram of the plane structure of the eleventh layer circuit of the utility model.

[0050] Fig.26 It is a schematic diagram of the planar structure of the point column connection between the eleventh and twelfth floors of the utility model.

[0051] Fig. 27 This is a schematic diagram of the planar structure of the twelfth circuit of the utility model. DETAILED DESCRIPTION

[0052] This embodiment is a preferred implementation mode of the utility model. Other embodiments whose principles and basic structures are the same or similar to those of this embodiment are within the protection scope of the utility model.

[0053] The utility model mainly protects a novel laminated chip LTCC power divider, which adopts a special structure of lumped parameter design, has an input port, namely port 1; two output ports, namely port 2 and port 3, and the signal is decomposed into two signals to the output port after passing through the input port. The two output signals have the advantages of low insertion loss, high isolation, and highly consistent amplitude and phase.

[0054] Please refer to the attached Figure 1 , Figure 1The invention is an equivalent circuit diagram of a novel laminated chip LTCC power divider, including capacitor C1, capacitor C2, capacitor C3, inductor L1, inductor L2, inductor L3 and inductor L4. The equivalent circuit has an input port, namely port 1, and two output ports, namely port 2 and port 3. In the utility model, port 2 is defined as the first output port, and port 3 is defined as the second output port. Inductor L1 and inductor L3 are connected in series between the input port and the first output port, inductor L2 and inductor L4 are connected in series between the input port and the second output port, capacitor C1 is connected between the input port and the ground, capacitor C2 is connected between the common end of inductor L1 and inductor L3 and the ground, and capacitor C3 is connected between the common end of inductor L2 and inductor L4 and the ground. The equivalent circuit of the utility model is two equally divided paths of a two-equal power divider, presenting a symmetrical structure, and the first output port and the second output port are two equally divided power output ports. When in use, an external isolation resistor with a resistance value of 100Ω is connected across the first output port and the second output port. The utility model is an improvement on the traditional Wilkinson power divider lumped parameter model. To achieve its higher isolation requirements, inductors L3 and L4 are added to its output link, which is equivalent to adding a matching branch, which can greatly reduce the reflected wave of the output port, thereby improving the isolation between the two ports accordingly. Capacitors C2 and C3 transmit high-frequency signals to the ground, which can also increase the isolation. In order to verify the influence of inductors L3 and L4 on the performance of the power divider circuit, the circuits before and after their addition are simulated and compared. The results are as follows: Figure 2 The solid line in the figure is the simulation result after adding inductor L3 and inductor L4, and the dotted line is the simulation result before adding. From the simulation results, it can be seen that after adding inductor L3 and inductor L4, the S parameters of the whole circuit are improved, and the relative bandwidth of the power divider is increased from 89.7% to 200% (S11<-10dB). For isolation, its bandwidth is increased from 45.1% to 62.7% (S32<-15dB).

[0055] The working state of the utility model is as follows: take the signal input from the common port ① as an example, the signal is input from port ① and then decomposed into two signals after passing through the embedded grounding capacitor C1, and outputted equally to ports ② and ③ respectively. The two output links are composed of two inductors and capacitors, wherein the inductance values ​​of inductor L1 and inductor L2 are the same, the inductance values ​​of inductor L3 and inductor L4 are the same, and the capacitance values ​​of capacitor C2 and capacitor C3 are the same, wherein the embedded inductor is the main source of insertion loss of the power divider. Resistor R1 is an external isolation resistor, which together with inductor L3 and inductor L4, serves to match the ports and increase the isolation.

[0056] In order to obtain a larger inductance value and a larger Q value at the same time, the utility model LTCC power divider adopts a three-dimensional spiral inductor. The three-dimensional spiral inductor structure is as follows Figure 3Compared with the planar inductor, the three-dimensional spiral inductor occupies a smaller area and has a larger effective inductance value. However, due to its three-dimensional structure, while providing a larger effective inductance value, the circuit itself will generate a certain amount of parasitic capacitance. The equivalent circuit is shown as follows: Figure 4 As shown. Parasitic capacitance C c The existence of is the main source of insertion loss in LTCC power dividers. In order to reduce the influence of this parasitic capacitance and the mutual coupling between inductors, the overall structure of the utility model LTCC power divider is divided into three parts, namely, the upper layer, the middle layer and the lower layer. The upper layer is two inductors L1 and L2 with larger inductance values, the middle layer is three capacitors C1, C2 and C3, and the lower layer is two inductors L3 and L4 with smaller inductance values. The three parts are at a certain distance from each other in the LTCC structure and are in a higher position relative to the ground as a whole. This can minimize the influence of the parasitic capacitance of the inductors and capacitors. At the same time, the capacitor substrate is placed between the upper and lower inductors to block the mutual inductance effect between the two inductors. However, due to its complex structure, the extraction of its parameters is mainly achieved through qualitative computer simulation.

[0057] Please refer to the attached Fig. 9 To Attachment Fig. 27 The utility model includes a ceramic substrate, a connection port arranged outside the ceramic substrate, and an internal circuit structure layer arranged inside the ceramic substrate. In this embodiment, the ceramic substrate is the main body of the utility model, and the connection port is arranged outside the ceramic substrate, which is an end electrode, that is, a pad. In this embodiment, there are six end electrodes, which are arranged on both sides of the ceramic substrate, respectively. The first port P1, the third port P3 and the fifth port P5 are ground ports, the second port P2 is a common port of the chip power divider, and the fourth port P4 and the sixth port P6 are two output ports. In this embodiment, the first port P1, the second port P2, the third port P3, the fourth port P4, the fifth port P5 and the sixth port P6 are all in a "concave" shape and are arranged on the surface of the ceramic substrate. The ceramic substrate adopts a rectangular parallelepiped structure, which is mainly composed of aluminum oxide (Al2O3), calcium oxide (CaO), magnesium oxide (MgO) and silicon oxide (SiO2). The internal circuit structure layer is distributed inside the ceramic substrate. There are twelve internal circuit structure layers in total. The internal circuit structure layers are as follows from bottom to top (with the direction in the attached figure as the direction):

[0058] The first layer is printed with two mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the first metal plane conductor 1 and the second metal plane conductor 2. The first metal plane conductor 1 and the second metal plane conductor 2 are both in a "C" shape. One end of the first metal plane conductor 1 is connected to the sixth port P6 through the first internal terminal 1a, and the other end of the first metal plane conductor 1 is the third internal terminal 1c, which is connected to the first metal point column 3. One end of the second metal plane conductor 2 is connected to the fourth port P4 through the second internal terminal 1b, and the other end of the second metal plane conductor 2 is the fourth internal terminal 1d, which is connected to the second metal point column 4.

[0059] The second layer has two mutually insulated metal plane conductors printed on the ceramic dielectric substrate, which are the third metal plane conductor 5 and the fourth metal plane conductor 6. The third metal plane conductor 5 and the fourth metal plane conductor 6 are both in an "L" shape. One end of the third metal plane conductor 5 is the fifth internal terminal 2a, which is connected to the third internal terminal 1c in the first layer through the first metal dot column 3. The other end of the third metal plane conductor 5 is the seventh internal terminal 2c, which is connected to the third metal dot column 7. One end of the fourth metal plane conductor 6 is the sixth internal terminal 2b, which is connected to the fourth internal terminal 1d in the first layer through the second metal dot column 4. The other end of the fourth metal plane conductor 6 is the eighth internal terminal 2d, which is connected to the fourth metal dot column 8.

[0060] The third layer is printed with two mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the fifth metal plane conductor 9 and the sixth metal plane conductor 10. The fifth metal plane conductor 9 and the sixth metal plane conductor 10 are both in an "L" shape. One end of the fifth metal plane conductor 9 is the ninth internal terminal 3a, which is connected to the seventh internal terminal 2c in the second layer through the third metal dot column 7. The other end of the fifth metal plane conductor 9 is the eleventh internal terminal 3c, which is connected to the fifth metal dot column 11. One end of the sixth metal plane conductor 10 is the tenth internal terminal 3b, which is connected to the eighth internal terminal 2d in the second layer through the fourth metal dot column 8. The other end of the sixth metal plane conductor 10 is the twelfth internal terminal 3d, which is connected to the sixth metal dot column 12.

[0061] The fourth layer is printed with two mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the seventh metal plane conductor 13 and the eighth metal plane conductor 14. The seventh metal plane conductor 13 and the eighth metal plane conductor 14 are both in a "U" shape. One end of the seventh metal plane conductor 13 is the thirteenth internal terminal 4a, which is connected to the eleventh internal terminal 3c in the third layer through the fifth metal dot column 11. The other end of the seventh metal plane conductor 13 is the fifteenth internal terminal 4c, which is connected to the seventh metal dot column 15. One end of the eighth metal plane conductor 14 is the fourteenth internal terminal 4b, which is connected to the twelfth internal terminal 3d in the third layer through the sixth metal dot column 12. The other end of the eighth metal plane conductor 14 is the sixteenth internal terminal 4d, which is connected to the eighth metal dot column 16.

[0062] The fifth layer is printed with two mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the ninth metal plane conductor 17 and the tenth metal plane conductor 18. The ninth metal plane conductor 17 and the tenth metal plane conductor 18 are both in an "L" shape. One end of the ninth metal plane conductor 17 is the seventeenth internal terminal 5a, which is connected to the fifteenth internal terminal 4c in the fourth layer through the seventh metal dot column 15. The other end of the ninth metal plane conductor 17 is the nineteenth internal terminal 5c, which is connected to the ninth metal dot column 19. One end of the tenth metal plane conductor 18 is the eighteenth internal terminal 5b, which is connected to the sixteenth internal terminal 4d in the fourth layer through the eighth metal dot column 16. The other end of the tenth metal plane conductor 18 is the twentieth internal terminal 5d, which is connected to the tenth metal dot column 20.

[0063] The sixth layer is printed with three mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the eleventh metal plane conductor 21, the twelfth metal plane conductor 22 and the thirteenth metal plane conductor 45. The end of the eleventh metal plane conductor 21 is the twenty-first internal terminal 6a, and the twenty-first internal terminal 6a is connected to the nineteenth internal terminal 5c in the fifth layer through the ninth metal dot column 19. The end of the twelfth metal plane conductor 22 is the twenty-second internal terminal 6b, and the twenty-second internal terminal 6b is connected to the twentieth internal terminal 5d in the fifth layer through the tenth metal dot column 20. The end of the thirteenth metal plane conductor 45 is the twenty-third internal terminal 6c, and the thirteenth metal plane conductor 45 is connected to the second port P2 through the twenty-third internal terminal 6c.

[0064] The seventh layer is printed with three mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the fourteenth metal plane conductor 25, the fifteenth metal plane conductor 26 and the sixteenth metal plane conductor 46. The end of the fourteenth metal plane conductor 25 is the twenty-fourth internal terminal 7a, and the fourteenth metal plane conductor 25 is connected to the first port P1 through the twenty-fourth internal terminal 7a. The end of the fifteenth metal plane conductor 26 is the twenty-fifth internal terminal 7b, and the fifteenth metal plane conductor 26 is connected to the third port P3 through the twenty-fifth internal terminal 7b. The end of the sixteenth metal plane conductor 46 is the twenty-sixth internal terminal 7c, and the sixteenth metal plane conductor 46 is connected to the fifth port P5 through the twenty-sixth internal terminal 7c.

[0065] The eighth layer is printed with three mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the seventeenth metal plane conductor 27, the eighteenth metal plane conductor 28 and the nineteenth metal plane conductor 47. The end of the seventeenth metal plane conductor 27 is the twenty-seventh internal terminal 8a, which is connected to the twenty-first internal terminal 6a in the sixth layer through the eleventh metal dot column 23. The end of the eighteenth metal plane conductor 28 is the twenty-eighth internal terminal 8b, which is connected to the twenty-second internal terminal 6b in the sixth layer through the twelfth metal dot column 24. The end of the nineteenth metal plane conductor 47 is the twenty-ninth internal terminal 8c, which is connected to the second port P2 through the twenty-ninth internal terminal 8c.

[0066] The ninth layer is printed with two metal plane conductors on the ceramic dielectric substrate, which are the twentieth metal plane conductor 31 and the twenty-first metal plane conductor 32. The twentieth metal plane conductor 31 and the twenty-first metal plane conductor 32 are both in a "U" shape, and one end of the twentieth metal plane conductor 31 and the second metal plane conductor 32 are connected. One end of the twentieth metal plane conductor 31 is the thirtieth internal terminal 9a, and the other end of the twentieth metal plane conductor 31 is the thirty-first internal terminal 9b. One end of the twenty-first metal plane conductor 32 is the thirtieth internal terminal 9a, and the other end of the twenty-first metal plane conductor 32 is the thirty-second internal terminal 9c. The twentieth metal plane conductor 31 and the twenty-first metal plane conductor 32 are connected at the thirtieth internal terminal 9a, and are connected to the second port P2 through the thirtieth internal terminal 9a. The thirty-first internal terminal 9b is connected to the fifteenth metal dot column 33, and the thirty-second internal terminal 9c is connected to the sixteenth metal dot column 34.

[0067] The tenth layer, two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, which are the twenty-second metal plane conductor 35 and the twenty-third metal plane conductor 36. The twenty-second metal plane conductor 35 and the twenty-third metal plane conductor 36 are both in a "U" shape. One end of the twenty-second metal plane conductor 35 is the thirty-third internal terminal 10a, which is connected to the thirty-first internal terminal 9b in the ninth layer through the fifteenth metal dot column 33. The other end of the twenty-second metal plane conductor 35 is the thirty-fifth internal terminal 10c, which is connected to the seventeenth metal dot column 37. One end of the twenty-third metal plane conductor 36 is the thirty-fourth internal terminal 10b, which is connected to the thirty-second internal terminal 9c in the ninth layer through the sixteenth metal dot column 34. The other end of the twenty-third metal plane conductor 36 is the thirty-sixth internal terminal 10d, which is connected to the eighteenth metal dot column 38.

[0068] In the eleventh layer, two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, which are the twenty-fourth metal plane conductor 39 and the twenty-fifth metal plane conductor 40. The twenty-fourth metal plane conductor 39 and the twenty-fifth metal plane conductor 40 are both in a "U" shape. One end of the twenty-fourth metal plane conductor 39 is the thirty-seventh internal terminal 11a, which is connected to the thirty-fifth internal terminal 10c in the tenth layer through the seventeenth metal dot column 37. The other end of the twenty-fourth metal plane conductor 39 is the thirty-ninth internal terminal 11c, which is connected to the nineteenth metal dot column 41. One end of the twenty-fifth metal plane conductor 40 is the thirty-eighth internal terminal 11b, which is connected to the thirty-sixth internal terminal 10d in the tenth layer through the eighteenth metal dot column 38. The other end of the twenty-fifth metal plane conductor 40 is the fortieth internal terminal 11d, which is connected to the twentieth metal dot column 42.

[0069] On the twelfth layer, two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, which are the twenty-sixth metal plane conductor 43 and the twenty-seventh metal plane conductor 44. The twenty-sixth metal plane conductor 43 and the twenty-seventh metal plane conductor 44 are both in an "L" shape. One end of the twenty-sixth metal plane conductor 43 is the forty-first internal terminal 12a, which is connected to the thirty-ninth internal terminal 11c in the eleventh layer through the nineteenth metal dot column 41. The other end of the twenty-sixth metal plane conductor 43 is the forty-third internal terminal 12c, which is connected to the twenty-seventh internal terminal 8a in the eighth layer through the thirteenth metal dot column 29. One end of the twenty-seventh metal plane conductor 44 is the forty-second internal terminal 12b, which is connected to the forty-second internal terminal 11d in the eleventh layer through the twentieth metal dot column 42. The other end of the twenty-seventh metal plane conductor 44 is the forty-fourth internal terminal 12d, which is connected to the twenty-eighth internal terminal 8b in the eighth layer through the fourteenth metal dot column 30.

[0070] Among them, the metal planar conductors in the first layer, the second layer, the third layer, the fourth layer and the fifth layer are metal coils, the metal planar conductors in the sixth layer, the seventh layer and the eighth layer are capacitor substrates, and the metal planar conductors in the ninth layer, the tenth layer, the eleventh layer and the twelfth layer are metal coils.

[0071] Please refer to the attached Figure 7 and attached Figure 8 , attached Figure 7 and attached Figure 8 This is the electrical characteristic curve of the new type of stacked chip LTCC power divider. From the figure, we can see that the insertion loss of the power divider in the entire passband 0.62GHz~1.07GHz is less than 0.45dB; the isolation is less than -15dB, and the relative bandwidth reaches 53.3%; the standing wave is less than 1.37; the amplitude difference between the two output ports is less than 0.01dB in the passband, and the phase difference is less than 0.1°, with good radiation-phase consistency.

[0072] The capacitor C1 in the equivalent circuit diagram of the present invention is composed of the thirteenth metal plane conductor 45, the sixteenth metal plane conductor 46 and the nineteenth metal plane conductor 47, the capacitor C2 is composed of the eleventh metal plane conductor 21, the fourteenth metal plane conductor 25 and the seventeenth metal plane conductor 27, the capacitor C3 is composed of the twelfth metal plane conductor 22, the fifteenth metal plane conductor 26 and the eighteenth metal plane conductor 28, and the inductor L1 is composed of the twentieth metal plane conductor 31, the twenty-second metal plane conductor 35, the twenty-fourth metal plane conductor 39 and the twenty-sixth metal plane conductor 4 3 is interconnected, inductor L2 is interconnected by twenty-first metal plane conductor 32, twenty-third metal plane conductor 36, twenty-fifth metal plane conductor 40 and twenty-seventh metal plane conductor 44, inductor L3 is interconnected by first metal plane conductor 1, third metal plane conductor 5, fifth metal plane conductor 9, seventh metal plane conductor 13 and ninth metal plane conductor 17, and inductor L4 is interconnected by second metal plane conductor 2, fourth metal plane conductor 6, sixth metal plane conductor 10, eighth metal plane conductor 14 and tenth metal plane conductor 18.

[0073] The utility model is based on LTCC (low temperature co-fired ceramic) technology and adopts lumped parameter model design to realize the special electrical performance requirements of a new type of laminated chip LTCC power divider, and has the advantages of low return loss, highly consistent output signal amplitude and phase, high reliability, low cost, excellent consistency and suitability for large-scale production. In addition, it also adapts to the development trend of new electronic component integration and miniaturization.

Claims

1. A novel laminated LTCC power divider, characterized by: The power divider comprises a ceramic substrate, a connection port arranged outside the ceramic substrate and an internal circuit structure layer arranged inside the ceramic substrate. There are six connection ports, the first port (P1), the third port (P3) and the fifth port (P5) are ground ports, the second port (P2) is a common port, the fourth port (P4) and the sixth port (P6) are two output ports, and the internal circuit structure layers are as follows from bottom to top: The first layer has two mutually insulated metal plane conductors printed on a ceramic dielectric substrate, namely a first metal plane conductor (1) and a second metal plane conductor (2). The first metal plane conductor (1) and the second metal plane conductor (2) are both in a "C" shape. One end of the first metal plane conductor (1) is connected to a sixth port (P6) via a first internal terminal (1a). The other end of the first metal plane conductor (1) is a third internal terminal (1c). The third internal terminal (1c) is connected to a first metal point column (3). One end of the second metal plane conductor (2) is connected to a fourth port (P4) via a second internal terminal (1b). The other end of the second metal plane conductor (2) is a fourth internal terminal (1d). The fourth internal terminal (1d) is connected to a second metal point column (4). The second layer has two mutually insulated metal plane conductors printed on a ceramic dielectric substrate, namely a third metal plane conductor (5) and a fourth metal plane conductor (6). The third metal plane conductor (5) and the fourth metal plane conductor (6) are both in an "L" shape. One end of the third metal plane conductor (5) is a fifth internal terminal (2a), which is connected to the third internal terminal (1c) in the first layer through a first metal dot column (3). The other end of the third metal plane conductor (5) is a seventh internal terminal (2c), which is connected to the third metal dot column (7). One end of the fourth metal plane conductor (6) is a sixth internal terminal (2b), which is connected to the fourth internal terminal (1d) in the first layer through a second metal dot column (4). The other end of the fourth metal plane conductor (6) is an eighth internal terminal (2d), which is connected to the fourth metal dot column (8). The third layer has two mutually insulated metal plane conductors printed on the ceramic dielectric substrate, namely a fifth metal plane conductor (9) and a sixth metal plane conductor (10). The fifth metal plane conductor (9) and the sixth metal plane conductor (10) are both in an "L" shape. One end of the fifth metal plane conductor (9) is a ninth internal terminal (3a), which is connected to the seventh internal terminal (2c) in the second layer through a third metal dot column (7). The other end of the fifth metal plane conductor (9) is an eleventh internal terminal (3c), which is connected to the fifth metal dot column (11). One end of the sixth metal plane conductor (10) is a tenth internal terminal (3b), which is connected to the eighth internal terminal (2d) in the second layer through a fourth metal dot column (8). The other end of the sixth metal plane conductor (10) is a twelfth internal terminal (3d), which is connected to the sixth metal dot column (12). The fourth layer has two mutually insulated metal plane conductors printed on the ceramic dielectric substrate, namely a seventh metal plane conductor (13) and an eighth metal plane conductor (14). The seventh metal plane conductor (13) and the eighth metal plane conductor (14) are both in a "U" shape. One end of the seventh metal plane conductor (13) is a thirteenth internal terminal (4a), and the thirteenth internal terminal (4a) is connected to the eleventh internal terminal (3c) in the third layer through a fifth metal dot column (11). The other end of the seventh metal plane conductor (13) is a fifteenth internal terminal (4c), and the fifteenth internal terminal (4c) is connected to the seventh metal dot column (15). One end of the eighth metal plane conductor (14) is a fourteenth internal terminal (4b), and the fourteenth internal terminal (4b) is connected to the twelfth internal terminal (3d) in the third layer through a sixth metal dot column (12). The other end of the eighth metal plane conductor (14) is a sixteenth internal terminal (4d), and the sixteenth internal terminal (4d) is connected to the eighth metal dot column (16). The fifth layer has two mutually insulated metal plane conductors printed on the ceramic dielectric substrate, namely a ninth metal plane conductor (17) and a tenth metal plane conductor (18). The ninth metal plane conductor (17) and the tenth metal plane conductor (18) are both in an "L" shape. One end of the ninth metal plane conductor (17) is a seventeenth internal terminal (5a), and the seventeenth internal terminal (5a) is connected to the fifteenth internal terminal (4c) in the fourth layer through the seventh metal dot column (15). The other end of the ninth metal plane conductor (17) is a nineteenth internal terminal (5c), and the nineteenth internal terminal (5c) is connected to the ninth metal dot column (19). One end of the tenth metal plane conductor (18) is an eighteenth internal terminal (5b), and the eighteenth internal terminal (5b) is connected to the sixteenth internal terminal (4d) in the fourth layer through the eighth metal dot column (16). The other end of the tenth metal plane conductor (18) is a twentieth internal terminal (5d), and the twentieth internal terminal (5d) is connected to the tenth metal dot column (20). The sixth layer has three mutually insulated metal plane conductors printed on a ceramic dielectric substrate, namely an eleventh metal plane conductor (21), a twelfth metal plane conductor (22) and a thirteenth metal plane conductor (45); the end of the eleventh metal plane conductor (21) is a twenty-first internal terminal (6a), and the twenty-first internal terminal (6a) is connected to the nineteenth internal terminal (5c) in the fifth layer through a ninth metal dot column (19); the end of the twelfth metal plane conductor (22) is a twenty-second internal terminal (6b), and the twenty-second internal terminal (6b) is connected to the twentieth internal terminal (5d) in the fifth layer through a tenth metal dot column (20); the end of the thirteenth metal plane conductor (45) is a twenty-third internal terminal (6c), and the thirteenth metal plane conductor (45) is connected to the second port (P2) through the twenty-third internal terminal (6c); The seventh layer has three mutually insulated metal plane conductors printed on the ceramic dielectric substrate, namely a fourteenth metal plane conductor (25), a fifteenth metal plane conductor (26) and a sixteenth metal plane conductor (46); the end of the fourteenth metal plane conductor (25) is a twenty-fourth internal terminal (7a), and the fourteenth metal plane conductor (25) is connected to the first port (P1) via the twenty-fourth internal terminal (7a); the end of the fifteenth metal plane conductor (26) is a twenty-fifth internal terminal (7b), and the fifteenth metal plane conductor (26) is connected to the third port (P3) via the twenty-fifth internal terminal (7b); the end of the sixteenth metal plane conductor (46) is a twenty-sixth internal terminal (7c), and the sixteenth metal plane conductor (46) is connected to the fifth port (P5) via the twenty-sixth internal terminal (7c); The eighth layer has three mutually insulated metal plane conductors printed on a ceramic dielectric substrate, namely a seventeenth metal plane conductor (27), an eighteenth metal plane conductor (28) and a nineteenth metal plane conductor (47); the end of the seventeenth metal plane conductor (27) is the twenty-seventh internal terminal (8a), and the twenty-seventh internal terminal (8a) is connected to the twenty-first internal terminal (6a) in the sixth layer through the eleventh metal dot column (23); the end of the eighteenth metal plane conductor (28) is the twenty-eighth internal terminal (8b), and the twenty-eighth internal terminal (8b) is connected to the twenty-second internal terminal (6b) in the sixth layer through the twelfth metal dot column (24); the end of the nineteenth metal plane conductor (47) is the twenty-ninth internal terminal (8c), and the nineteenth metal plane conductor (47) is connected to the second port (P2) through the twenty-ninth internal terminal (8c); The ninth layer has two metal plane conductors printed on the ceramic dielectric substrate, namely a twentieth metal plane conductor (31) and a twenty-first metal plane conductor (32). The twentieth metal plane conductor (31) and the twenty-first metal plane conductor (32) are both in a "U" shape, and one end of the twentieth metal plane conductor (31) and the twenty-first metal plane conductor (32) are connected. One end of the twentieth metal plane conductor (31) is the thirtieth internal terminal point (9a), and the other end of the twentieth metal plane conductor (31) is the thirty-first internal terminal point (9b). One end of the twenty-first metal plane conductor (32) is the thirtieth internal endpoint (9a), the other end of the twenty-first metal plane conductor (32) is the thirty-second internal endpoint (9c), the twentieth metal plane conductor (31) and the twenty-first metal plane conductor (32) are connected at the thirtieth internal endpoint (9a), and are connected to the second port (P2) through the thirtieth internal endpoint (9a), the thirty-first internal endpoint (9b) is connected to the fifteenth metal point column (33), and the thirty-second internal endpoint (9c) is connected to the sixteenth metal point column (34); The tenth layer has two mutually insulated metal plane conductors printed on the ceramic dielectric substrate, which are a twenty-second metal plane conductor (35) and a twenty-third metal plane conductor (36). The twenty-second metal plane conductor (35) and the twenty-third metal plane conductor (36) are both in a "U" shape. One end of the twenty-second metal plane conductor (35) is a thirty-third internal terminal (10a). The thirty-third internal terminal (10a) is connected to the thirty-first internal terminal (9b) in the ninth layer through a fifteenth metal dot column (33). The twenty-second metal plane conductor (3 5) the other end is a thirty-fifth internal terminal (10c), the thirty-fifth internal terminal (10c) is connected to the seventeenth metal dot column (37), one end of the twenty-third metal plane conductor (36) is a thirty-fourth internal terminal (10b), the thirty-fourth internal terminal (10b) is connected to the thirty-second internal terminal (9c) in the ninth layer through the sixteenth metal dot column (34), the other end of the twenty-third metal plane conductor (36) is a thirty-sixth internal terminal (10d), the thirty-sixth internal terminal (10d) is connected to the eighteenth metal dot column (38); In the eleventh layer, two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, namely, a twenty-fourth metal plane conductor (39) and a twenty-fifth metal plane conductor (40). The twenty-fourth metal plane conductor (39) and the twenty-fifth metal plane conductor (40) are both in a "U" shape. One end of the twenty-fourth metal plane conductor (39) is a thirty-seventh internal terminal (11a). The thirty-seventh internal terminal (11a) is connected to the thirty-fifth internal terminal (10c) in the tenth layer through a seventeenth metal dot column (37). (39) The other end is a thirty-ninth internal terminal (11c), and the thirty-ninth internal terminal (11c) is connected to the nineteenth metal dot column (41); one end of the twenty-fifth metal plane conductor (40) is a thirty-eighth internal terminal (11b), and the thirty-eighth internal terminal (11b) is connected to the thirty-sixth internal terminal (10d) in the tenth layer through the eighteenth metal dot column (38); the other end of the twenty-fifth metal plane conductor (40) is a fortieth internal terminal (11d), and the fortieth internal terminal (11d) is connected to the twentieth metal dot column (42); In the twelfth layer, two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, namely, a twenty-sixth metal plane conductor (43) and a twenty-seventh metal plane conductor (44). The twenty-sixth metal plane conductor (43) and the twenty-seventh metal plane conductor (44) are both in an "L" shape. One end of the twenty-sixth metal plane conductor (43) is a forty-first internal terminal (12a), and the forty-first internal terminal (12a) is connected to the thirty-ninth internal terminal (11c) in the eleventh layer through a nineteenth metal dot column (41). The other end of the twenty-sixth metal plane conductor (43) is a forty-third internal terminal (12c). ), the forty-third internal terminal (12c) is connected to the twenty-seventh internal terminal (8a) in the eighth layer through the thirteenth metal dot column (29), one end of the twenty-seventh metal plane conductor (44) is the forty-second internal terminal (12b), the forty-second internal terminal (12b) is connected to the forty-first internal terminal (11d) in the eleventh layer through the twentieth metal dot column (42), the other end of the twenty-seventh metal plane conductor (44) is the forty-fourth internal terminal (12d), the forty-fourth internal terminal (12d) is connected to the twenty-eighth internal terminal (8b) in the eighth layer through the fourteenth metal dot column (30).

2. The novel multilayer LTCC power divider according to claim 1 is characterized in that: The connection port is arranged outside the ceramic substrate and is a welding pad.

3. The novel laminated chip LTCC power divider according to claim 1 is characterized in that: The said components are respectively arranged on both sides of the ceramic substrate.

4. The novel multilayer LTCC power divider according to claim 1 is characterized in that: The first port (P1), the second port (P2), the third port (P3), the fourth port (P4), the fifth port (P5) and the sixth port (P6) are all in a "concave" shape and are arranged on the surface of the ceramic substrate.

5. The novel multilayer LTCC power divider according to claim 1 is characterized in that: The metal planar conductors in the first, second, third, fourth and fifth layers are metal coils, the metal planar conductors in the sixth, seventh and eighth layers are capacitor substrates, and the metal planar conductors in the ninth, tenth, eleventh and twelfth layers are metal coils.

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