Anti-surge circuit with low conduction impedance

Abstract

The utility model provides an anti-surge circuit with low conduction impedance. The anti-surge circuit comprises a low-impedance electron tube driving circuit and a surge control circuit which are connected in sequence, the input end of the low-impedance electron tube driving circuit is connected with the input circuit in parallel, the output end of the low-impedance electron tube driving circuit is connected with the grid electrode of the MOS tube Q1, one end of the MOS tube Q1 is connected with the capacitor C1, the other end of the capacitor C1 is grounded, and the other end of the MOS tube Q1 is connected with the positive output end of the power supply; the surge control circuit is communicated with the grid electrode of the MOS tube Q2 through a series resistor R2, the MOS tube Q2 is connected with the source electrode of the MOS tube Q1, the surge control circuit is connected with the grid electrode of the MOS tube Q3, the surge control circuit is connected with the grid electrode of the MOS tube Q1, the drain electrodes and the source electrodes of the MOS tube Q2 and the MOS tube Q3 are connected in series and then are associated with the drain electrode and the source electrode of the MOS tube Q1, and the MOS tube Q2 and the MOS tube Q3 are connected in parallel with output voltage through a capacitor C6. The anti-surge circuit provided by the utility model solves the problems of high power consumption, high heat productivity and large size of the existing anti-surge circuit.

Description

Technical Field

[0001] The utility model belongs to the technical field of electronic components, and in particular relates to a surge protection circuit with low on-resistance. Background Art

[0002] The development of the modern automobile industry has led to the widespread use of a large number of electronic devices in drones, etc. Most of these electronic devices use single-chip microcomputers. Due to the freeze or reset characteristics of single-chip microcomputers, a stable power supply system is required. Therefore, high-performance power supply design is the guarantee for the reliable operation of airborne electronic equipment.

[0003] Low on-resistance circuits with surge protection are mainly used in drone electronic equipment. Their function is to stabilize the voltage of the power supply system, reduce the circuit voltage drop during large current output, reduce heat, improve system reliability, and provide a good power environment for power facilities.

[0004] Although there are similar products on the market, they have defects such as high power consumption, high heat generation, and large size. Therefore, it is of great significance to develop this low on-resistance circuit to achieve the purpose of user convenience, improve the anti-interference ability of airborne electronic equipment, reduce product size, reduce conduction loss, and improve reliability. Utility Model Content

[0005] The utility model aims to provide a surge protection circuit with low on-resistance, which solves the problems of large power consumption, large heat generation and large volume in the existing surge protection circuit.

[0006] The technical solution adopted by the utility model is: a low on-resistance surge protection circuit, comprising a low impedance electron tube drive circuit and a surge control circuit connected in sequence; the input end of the low impedance electron tube drive circuit is connected in parallel with the input circuit, the output end of the low impedance electron tube drive circuit is connected to the gate of the MOS tube Q1, one end of the MOS tube Q1 is connected to a capacitor C1, the other end of the capacitor C1 is grounded, and the other end of the MOS tube Q1 is connected to the positive output end of the power supply;

[0007] The surge control circuit is connected to the gate of the MOS tube Q2 through the series resistor R2, the MOS tube Q2 is connected to the source of the MOS tube Q1, the surge control circuit is connected to the gate of the MOS tube Q3, the surge control circuit is connected to the gate of the MOS tube Q1, the drain and source of the MOS tube Q2 and the MOS tube Q3 are connected in series and then associated with the drain and source of the MOS tube Q1, and are connected in parallel with the output voltage through the capacitor C6.

[0008] The technical solution adopted by the utility model is also characterized by:

[0009] Furthermore, the surge control circuit includes an integrated circuit U1, a resistor R1, a resistor R3, a resistor R4, a resistor R5, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, and a transient suppressor V1. The integrated circuit U1 is connected to the MOS tube Q1 through the series resistor R1 and the capacitor C1, the integrated circuit U1 is connected to the capacitor C3, the integrated circuit U1 is connected to the resistor R3 and the resistor R5, the resistor R3 and the resistor R5 are connected in series, the resistor R3 is connected to the positive end of the output voltage, the resistor R5 is connected to the negative end of the output voltage, the integrated circuit U1 is connected to the transient suppressor V1 and the resistor R1 through the series resistor R4, the other end of the resistor R4 is connected in series with the output voltage through the capacitor C2, and the integrated circuit U1 is connected in series with the negative electrode of the output voltage through the capacitor C3.

[0010] Furthermore, the OUT interface and the SENSE sensing signal terminal of the integrated circuit U1 are both connected to the resistor R3, the DGATE interface of the integrated circuit U1 is connected to the gate of the MOS tube Q3, the SOURCE interface of the integrated circuit U1 is connected to the MOS tube Q3, the HGATE interface of the integrated circuit U1 is connected to the gate of the MOS tube Q2 through the series resistor R2, the VCC interface of the integrated circuit U1 is connected to the capacitor C1 through the series resistor R1, the SHDN interface and the UV interface of the integrated circuit U1 are both connected in series with the resistor R4, one end of the resistor R4 is connected to the transient suppressor V1, and the other end of the resistor R4 is connected in series with the negative end of the output voltage through the capacitor C2, the OV interface, the GND interface and the EAOUT interface of the integrated circuit U1 are all connected in series with the negative end of the output voltage, the FLT interface of the integrated circuit U1 is connected to the low-impedance electron tube drive circuit, the TMR interface of the integrated circuit U1 is connected to the capacitor C3, and the other end of the capacitor C3 is connected in series with the output voltage ground, the FB interface of the integrated circuit U1 is connected to the resistor R5 and the resistor R3, and the other end of the resistor R5 is connected in series with the negative end of the output voltage.

[0011] Furthermore, the transient suppressor V1 is a surge suppressor for the power supply terminal VCC of the LTC4364.

[0012] Furthermore, the MOS tube Q1 is connected in series with the output bypass capacitors C4 and C5, and the output bypass capacitors C4 and C5 are connected to the negative end of the output voltage.

[0013] Furthermore, the low impedance electron tube driving circuit adopts the integrated circuit LM5101 integrated chip, the LO pin of the integrated circuit LM5101 integrated chip is connected to the gate of the MOS tube Q1, and the VDD and GND pins of the integrated circuit LM5101 integrated chip are associated with the input voltage.

[0014] The beneficial effects of the utility model are:

[0015] The low on-resistance surge protection circuit of the utility model is a common technology and can also be used in other fields, such as hybrid vehicles, industrial control and other environments. The use of low on-resistance circuits can effectively solve the problems of anti-surge interference and high current output. Therefore, with the technology transplantation and promotion and application of this project, it will bring good social, economic and ecological benefits to the reliable operation of electronic equipment such as vehicle-mounted and airborne equipment and improve labor productivity.

[0016] The low on-resistance surge protection circuit of the utility model can withstand a surge voltage of 100V, with a duration of 500mS; a peak pulse voltage of 250V, with a duration of 50uS.

[0017] The low on-resistance surge protection circuit of the utility model adopts the technology of connecting a high-resistance (high-voltage) electron tube and a low-resistance (low-voltage) electron tube in parallel to reduce the on-resistance of the circuit, which can be as low as 2 milliohms.

[0018] The low on-resistance surge protection circuit of the utility model adopts SMT, ceramic copper clad board (DCB) and eutectic welding process technology, which effectively solves the volume, weight and heat dissipation problems of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a principle block diagram of the low on-resistance surge protection circuit of the utility model;

[0020] Figure 2 The schematic diagram of the low on-resistance surge protection circuit of the utility model is shown in FIG. DETAILED DESCRIPTION

[0021] The utility model is described in detail below with reference to the accompanying drawings and specific implementation modes.

[0022] The utility model provides a surge protection circuit with low on-resistance, such as Figure 1 As shown, it includes a low-impedance electron tube drive circuit and a surge control circuit connected in sequence; the input end of the low-impedance electron tube drive circuit is connected in parallel with the input circuit, the output end of the low-impedance electron tube drive circuit is connected to the gate of the MOS tube Q1, one end of the MOS tube Q1 is connected to a capacitor C1, the other end of the capacitor C1 is grounded, and the other end of the MOS tube Q1 is connected to the positive output end of the power supply; the surge control circuit is connected to the gate of the MOS tube Q2 through a series resistor R2, the MOS tube Q2 is connected to the source of the MOS tube Q1, the surge control circuit is connected to the gate of the MOS tube Q3, the surge control circuit is connected to the gate of the MOS tube Q1, the drains and sources of the MOS tubes Q2 and Q3 are connected in series and are associated with the drain and source of the MOS tube Q1, and are connected in parallel with the output voltage through the capacitor C6, the MOS tube Q1 is connected in series with the output bypass capacitors C4 and C5, and the output bypass capacitors C4 and C5 are connected to the negative end of the output voltage.

[0023] like Figure 2 As shown, the surge control circuit includes an integrated circuit U1, a resistor R1, a resistor R3, a resistor R4, a resistor R5, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, and a transient suppressor V1. The transient suppressor V1 is a surge suppressor for the power supply terminal VCC of LTC4364. The integrated circuit U1 is connected to the MOS tube Q1 through the series resistor R1 and the capacitor C1. The integrated circuit U1 is connected to the capacitor C3. The integrated circuit U1 is connected to the resistor R3 and the resistor R5. The resistor R3 and the resistor R5 are connected in series. The resistor R3 is connected to the positive end of the output voltage, and the resistor R5 is connected to the negative end of the output voltage. The integrated circuit U1 is connected to the transient suppressor V1 and the resistor R1 through the series resistor R4. The other end of the resistor R4 is connected in series with the output voltage through the capacitor C2. The integrated circuit U1 is connected in series with the negative electrode of the output voltage through the capacitor C3.

[0024] The OUT interface and the SENSE sensing signal terminal of the integrated circuit U1 are both connected to the resistor R3, the DGATE interface of the integrated circuit U1 is connected to the gate of the MOS tube Q3, the SOURCE interface of the integrated circuit U1 is connected to the MOS tube Q3, the HGATE interface of the integrated circuit U1 is connected to the gate of the MOS tube Q2 through the series resistor R2, the VCC interface of the integrated circuit U1 is connected to the capacitor C1 through the series resistor R1, the SHDN interface and the UV interface of the integrated circuit U1 are both connected in series with the resistor R4, one end of the resistor R4 is connected to the transient suppressor V1, and the other end of the resistor R4 is connected in series with the negative end of the output voltage through the capacitor C2, the OV interface, the GND interface and the EAOUT interface of the integrated circuit U1 are all connected in series with the negative end of the output voltage, the FLT interface of the integrated circuit U1 is connected to the low-impedance electron tube drive circuit, the TMR interface of the integrated circuit U1 is connected to the capacitor C3, and the other end of the capacitor C3 is connected in series with the output voltage ground, the FB interface of the integrated circuit U1 is connected to the resistor R5 and the resistor R3, and the other end of the resistor R5 is connected in series with the negative end of the output voltage.

[0025] The low impedance electron tube driving circuit adopts the integrated circuit LM5101 integrated chip, the LO pin of the integrated circuit LM5101 integrated chip is connected to the gate of the MOS tube Q1, and the VDD and GND pins of the integrated circuit LM5101 integrated chip are associated with the input voltage.

[0026] The utility model provides a surge protection circuit with low on-resistance, which controls an input DC source to supply power to an electrical load. When the DC source works normally, the internal high-voltage (high-impedance) electron tube and the low-voltage (low-impedance) electron tube are both normally conducted, and they are connected in parallel to supply power to the output. When a high-voltage surge occurs at the front end, the electron tube of the low-voltage (low-impedance) electron tube is turned off, while the high-voltage (high-impedance) electron tube works in a linear region, and the surge voltage is lost through heat, thereby ensuring that the voltage of the back-end equipment is within a reasonable range.

[0027] The technical performance indicators of the low on-resistance surge protection circuit of the utility model (taking DLRL as an example) are shown in Table 1.

[0028] Table 1 Technical performance indicators of surge protection circuit (DLRL as an example)

[0029]

[0030] The utility model is described in detail below with reference to the accompanying drawings and embodiments.

[0031] Example 1

[0032] The surge protection circuit with low on-resistance comprises a low-resistance electron tube driving circuit and a surge control circuit connected in sequence; the input end of the low-resistance electron tube driving circuit is connected in parallel with the input circuit, the output end of the low-resistance electron tube driving circuit is connected with the gate of a MOS tube Q1, one end of the MOS tube Q1 is connected with a capacitor C1, the other end of the capacitor C1 is grounded, and the other end of the MOS tube Q1 is connected with the positive output end of a power supply; the surge control circuit is connected with the gate of the MOS tube Q2 through a series resistor R2, the MOS tube Q2 is connected with the source of the MOS tube Q1, the surge control circuit is connected with the gate of the MOS tube Q3, the surge control circuit is connected with the gate of the MOS tube Q1, the drains and sources of the MOS tubes Q2 and Q3 are connected in series and then associated with the drain and source of the MOS tube Q1, and are connected in parallel with the output voltage through a capacitor C6, the MOS tube Q1 is connected in series with the output bypass capacitors C4 and C5, and the output bypass capacitors C4 and C5 are connected with the negative end of the output voltage.

[0033] The low impedance electron tube driving circuit adopts the integrated circuit LM5101 integrated chip, the LO pin of the integrated circuit LM5101 integrated chip is connected to the gate of the MOS tube Q1, and the VDD and GND pins of the integrated circuit LM5101 integrated chip are associated with the input voltage.

[0034] Example 2

[0035] The surge protection circuit with low on-resistance comprises a low-resistance electron tube driving circuit and a surge control circuit connected in sequence; the input end of the low-resistance electron tube driving circuit is connected in parallel with the input circuit, the output end of the low-resistance electron tube driving circuit is connected with the gate of a MOS tube Q1, one end of the MOS tube Q1 is connected with a capacitor C1, the other end of the capacitor C1 is grounded, and the other end of the MOS tube Q1 is connected with the positive output end of a power supply; the surge control circuit is connected with the gate of the MOS tube Q2 through a series resistor R2, the MOS tube Q2 is connected with the source of the MOS tube Q1, the surge control circuit is connected with the gate of the MOS tube Q3, the surge control circuit is connected with the gate of the MOS tube Q1, the drains and sources of the MOS tubes Q2 and Q3 are connected in series and then associated with the drain and source of the MOS tube Q1, and are connected in parallel with the output voltage through a capacitor C6, the MOS tube Q1 is connected in series with the output bypass capacitors C4 and C5, and the output bypass capacitors C4 and C5 are connected with the negative end of the output voltage.

[0036] The surge control circuit includes an integrated circuit U1, a resistor R1, a resistor R3, a resistor R4, a resistor R5, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, and a transient suppressor V1. The transient suppressor V1 is a surge suppressor for the power supply terminal VCC of LTC4364. The integrated circuit U1 is connected to the MOS tube Q1 through the series resistor R1 and the capacitor C1. The integrated circuit U1 is connected to the capacitor C3. The integrated circuit U1 is connected to the resistor R3 and the resistor R5. The resistor R3 and the resistor R5 are connected in series. The resistor R3 is connected to the positive end of the output voltage, and the resistor R5 is connected to the negative end of the output voltage. The integrated circuit U1 is connected to the transient suppressor V1 and the resistor R1 through the series resistor R4. The other end of the resistor R4 is connected in series with the output voltage through the capacitor C2. The integrated circuit U1 is connected in series with the negative electrode of the output voltage through the capacitor C3.

[0037] The low impedance electron tube driving circuit adopts the integrated circuit LM5101 integrated chip, the LO pin of the integrated circuit LM5101 integrated chip is connected to the gate of the MOS tube Q1, and the VDD and GND pins of the integrated circuit LM5101 integrated chip are associated with the input voltage.

[0038] Example 3

[0039] The surge protection circuit with low on-resistance comprises a low-resistance electron tube driving circuit and a surge control circuit connected in sequence; the input end of the low-resistance electron tube driving circuit is connected in parallel with the input circuit, the output end of the low-resistance electron tube driving circuit is connected with the gate of a MOS tube Q1, one end of the MOS tube Q1 is connected with a capacitor C1, the other end of the capacitor C1 is grounded, and the other end of the MOS tube Q1 is connected with the positive output end of a power supply; the surge control circuit is connected with the gate of the MOS tube Q2 through a series resistor R2, the MOS tube Q2 is connected with the source of the MOS tube Q1, the surge control circuit is connected with the gate of the MOS tube Q3, the surge control circuit is connected with the gate of the MOS tube Q1, the drains and sources of the MOS tubes Q2 and Q3 are connected in series and then associated with the drain and source of the MOS tube Q1, and are connected in parallel with the output voltage through a capacitor C6, the MOS tube Q1 is connected in series with the output bypass capacitors C4 and C5, and the output bypass capacitors C4 and C5 are connected with the negative end of the output voltage.

[0040] The surge control circuit includes an integrated circuit U1, a resistor R1, a resistor R3, a resistor R4, a resistor R5, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, and a transient suppressor V1. The transient suppressor V1 is a surge suppressor for the power supply terminal VCC of LTC4364. The integrated circuit U1 is connected to the MOS tube Q1 through the series resistor R1 and the capacitor C1. The integrated circuit U1 is connected to the capacitor C3. The integrated circuit U1 is connected to the resistor R3 and the resistor R5. The resistor R3 and the resistor R5 are connected in series. The resistor R3 is connected to the positive end of the output voltage, and the resistor R5 is connected to the negative end of the output voltage. The integrated circuit U1 is connected to the transient suppressor V1 and the resistor R1 through the series resistor R4. The other end of the resistor R4 is connected in series with the output voltage through the capacitor C2. The integrated circuit U1 is connected in series with the negative electrode of the output voltage through the capacitor C3.

[0041] The OUT interface and the SENSE sensing signal terminal of the integrated circuit U1 are both connected to the resistor R3, the DGATE interface of the integrated circuit U1 is connected to the gate of the MOS tube Q3, the SOURCE interface of the integrated circuit U1 is connected to the MOS tube Q3, the HGATE interface of the integrated circuit U1 is connected to the gate of the MOS tube Q2 through the series resistor R2, the VCC interface of the integrated circuit U1 is connected to the capacitor C1 through the series resistor R1, the SHDN interface and the UV interface of the integrated circuit U1 are both connected in series with the resistor R4, one end of the resistor R4 is connected to the transient suppressor V1, and the other end of the resistor R4 is connected in series with the negative end of the output voltage through the capacitor C2, the OV interface, the GND interface and the EAOUT interface of the integrated circuit U1 are all connected in series with the negative end of the output voltage, the FLT interface of the integrated circuit U1 is connected to the low-impedance electron tube drive circuit, the TMR interface of the integrated circuit U1 is connected to the capacitor C3, and the other end of the capacitor C3 is connected in series with the output voltage ground, the FB interface of the integrated circuit U1 is connected to the resistor R5 and the resistor R3, and the other end of the resistor R5 is connected in series with the negative end of the output voltage.

[0042] The low impedance electron tube driving circuit adopts the integrated circuit LM5101 integrated chip, the LO pin of the integrated circuit LM5101 integrated chip is connected to the gate of the MOS tube Q1, and the VDD and GND pins of the integrated circuit LM5101 integrated chip are associated with the input voltage.

[0043] The low on-resistance surge protection circuit of the utility model has the following advantages:

[0044] The surge protection circuit of the utility model incorporates corresponding TVS transient suppressors at the input and output ends of the surge protection circuit, which has a good effect on absorbing spike pulses. For power drop interference, the power supply filter capacitor is added, and a power supply chip with a wide voltage input range is selected while meeting the cost and performance index requirements.

[0045] The surge suppressor used in the surge protection circuit of the utility model is the LTC4364 surge suppressor, which can protect the load from damage by high voltage transients. By controlling the voltage drop across a Q2 N-MOSFET transmission device, the device can limit and regulate the output during overvoltage. In addition, the LTC4364 also includes a timed current limiting circuit breaker. In the event of a fault, an adjustable fault timer must end before the transmission device is turned off and automatically restarts after a delay. The LTC4364 can accurately monitor the undervoltage (UV) condition of the input power supply. The Q2 N-MOS tube remains turned off under the undervoltage condition.

[0046] At the same time, when the input is overvoltage or undervoltage, the FLT terminal of LTC4364 provides a low voltage to the drive circuit of Q1, turning off Q1 to protect Q1.

[0047] The surge controller drives the Q3 MOS tube to replace a Schottky diode used for reverse output protection and output voltage maintenance to provide reverse input protection, thereby reducing voltage drop and power loss. The LTC4364 controls the forward voltage drop across the Q3 MOS tube and minimizes reverse current transients during power failure, undervoltage or input short circuit.

[0048] The application of surge protection and spike suppression technology realizes anti-reverse connection, surge protection and spike pulse absorption. The product can withstand surge voltage of 100V, duration of 100mS; spike pulse voltage of 250V, duration of 50uS.

[0049] 2. Low on-resistance circuit

[0050] When the surge protection circuit of the utility model has a normal input, Q1, Q2 and Q3 are all normally turned on. When a surge occurs in the input, Q1 is turned off, Q2 works in the linear region, and Q3 is normally turned on.

[0051] 3. Improve integration and reduce volume:

[0052] The surge protection circuit of the utility model adopts SMT, ceramic copper clad board (DCB) and eutectic welding process technology, thereby effectively solving the volume, heat dissipation and weight problems of the product.

Claims

1. Low on-resistance surge protection circuit, characterized in that: It comprises a low-impedance electron tube drive circuit and a surge control circuit connected in sequence; the input end of the low-impedance electron tube drive circuit is connected in parallel with the input circuit, the output end of the low-impedance electron tube drive circuit is connected to the gate of the MOS tube Q1, one end of the MOS tube Q1 is connected to a capacitor C1, the other end of the capacitor C1 is grounded, and the other end of the MOS tube Q1 is connected to the positive output end of the power supply; The surge control circuit is connected to the gate of the MOS tube Q2 through the series resistor R2, the MOS tube Q2 is connected to the source of the MOS tube Q1, the surge control circuit is connected to the gate of the MOS tube Q3, the surge control circuit is connected to the gate of the MOS tube Q1, the drain and source of the MOS tube Q2 and the MOS tube Q3 are connected in series and are associated with the drain and source of the MOS tube Q1, and are connected in parallel with the output voltage through the capacitor C6.

2. The low on-resistance surge protection circuit according to claim 1, characterized in that: The surge control circuit includes an integrated circuit U1, a resistor R1, a resistor R3, a resistor R4, a resistor R5, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, and a transient suppressor V1. The integrated circuit U1 is connected to the MOS tube Q1 through the series resistor R1 and the capacitor C1. The integrated circuit U1 is connected to the capacitor C3. The integrated circuit U1 is connected to the resistor R3 and the resistor R5. The resistor R3 and the resistor R5 are connected in series. The resistor R3 is connected to the positive end of the output voltage, and the resistor R5 is connected to the negative end of the output voltage. The integrated circuit U1 is connected to the transient suppressor V1 and the resistor R1 through the series resistor R4. The other end of the resistor R4 is connected in series with the output voltage through the capacitor C2, and the integrated circuit U1 is connected in series with the negative electrode of the output voltage through the capacitor C3.

3. The surge protection circuit with low on-resistance according to claim 2, characterized in that: The OUT interface and the SENSE sensing signal terminal of the integrated circuit U1 are both connected to the resistor R3, the DGATE interface of the integrated circuit U1 is connected to the gate of the MOS tube Q3, the SOURCE interface of the integrated circuit U1 is connected to the MOS tube Q3, the HGATE interface of the integrated circuit U1 is connected to the gate of the MOS tube Q2 through the series resistor R2, the VCC interface of the integrated circuit U1 is connected to the capacitor C1 through the series resistor R1, the SHDN interface and the UV interface of the integrated circuit U1 are both connected in series with the resistor R4, one end of the resistor R4 is connected to the transient suppressor V1, and the other end of the resistor R4 is connected in series with the negative end of the output voltage through the capacitor C2, the OV interface, the GND interface and the EAOUT interface of the integrated circuit U1 are all connected in series with the negative end of the output voltage, the FLT interface of the integrated circuit U1 is connected to the low-impedance electron tube driving circuit, the TMR interface of the integrated circuit U1 is connected to the capacitor C3, and the other end of the capacitor C3 is connected in series with the output voltage ground, the FB interface of the integrated circuit U1 is connected to the resistor R5 and the resistor R3, and the other end of the resistor R5 is connected in series with the negative end of the output voltage.

4. The low on-resistance surge protection circuit according to claim 2, characterized in that: The transient suppressor V1 is a surge suppressor for the power supply terminal VCC of the LTC4364.

5. The low on-resistance surge protection circuit according to claim 1, characterized in that: The MOS tube Q1 is connected in series with output bypass capacitors C4 and C5, and the output bypass capacitors C4 and C5 are connected to the negative end of the output voltage.

6. The surge protection circuit with low on-resistance according to claim 1, characterized in that: The low-impedance electron tube driving circuit adopts an integrated circuit LM5101 integrated chip, the LO pin of the integrated circuit LM5101 integrated chip is connected to the gate of the MOS tube Q1, and the VDD and GND pins of the integrated circuit LM5101 integrated chip are associated with the input voltage.

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