Stacked image sensor chip and electronic equipment

Abstract

The utility model describes a stack type image sensor chip, which comprises a first semiconductor substrate and a second semiconductor substrate which are oppositely stacked, the first semiconductor substrate comprises a pixel substrate layer and a first bonding layer, the pixel substrate layer comprises a logic area and a pixel area, and the pixel area comprises a plurality of pixel units arranged in an array; the second semiconductor substrate at least comprises a second bonding layer, and the first semiconductor substrate and the second semiconductor substrate are in bonding connection through the first bonding layer and the second bonding layer; the first bonding layer at least comprises a first bonding part, the second bonding layer at least comprises a second bonding part, and the first bonding part and the second bonding part are patterns with hollow areas. The utility model further provides an electronic device comprising the stacked image sensor chip. According to the invention, the first bonding part and the second bonding part are provided with the hollow patterns, so that the stress of copper metal is relieved, and the condition that the performance of the image sensor is affected by the cracking of the top metal of the wafer due to overlarge stress is avoided.

Description

Technical Field

[0001] The utility model relates to the field of semiconductors, in particular to an electronic device comprising a stacked image sensor chip. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. As semiconductor technology enters the post-Moore era, in order to meet the needs of high integration and high performance, the chip structure is developing towards a three-dimensional direction, and wafer-level bonding technology has been widely used. Traditional image sensor chips use a two-dimensional architecture, in which the pixel area and the logic area are arranged in a two-dimensional plane, and a considerable part of the chip area is a non-pixel area, resulting in a limit on the number of pixels that can be set, thereby affecting the image quality. Stacked image sensor chips were thus born. In stacked image sensor chips, the hybrid bonding process, which is a key technology for wafer three-dimensional integration, is applied, and how to bond the bonding layers on multiple wafers becomes the key. Utility Model Content

[0003] In view of this, the utility model provides a stacked image sensor chip, which comprises at least a first semiconductor substrate and a second semiconductor substrate stacked opposite to each other, wherein: the first semiconductor substrate comprises a pixel substrate layer arranged on a side away from the second semiconductor substrate and a first bonding layer arranged on a side close to the second semiconductor substrate, the pixel substrate layer comprises a logic area and a pixel area, and the pixel area comprises a plurality of pixel units arranged in an array; the second semiconductor substrate comprises at least a second bonding layer arranged on a side close to the first semiconductor substrate and a functional element layer arranged on a side away from the first semiconductor substrate, the first semiconductor substrate and the second semiconductor substrate are bonded and connected via the first bonding layer and the second bonding layer; the first bonding layer comprises at least a first bonding portion located on a side away from the second semiconductor substrate and projected in the logic area along a first direction, the second bonding layer comprises at least a second bonding portion located on a side away from the first semiconductor substrate and projected in the logic area along the first direction, and both the first bonding portion and the second bonding portion are figures having hollow areas, wherein the first direction is a direction from the second semiconductor substrate to the first semiconductor substrate.

[0004] Optionally, the first bonding layer also includes a first metal routing and a first metal bonding block, and the first bonding portion is connected to the first metal bonding block through the first metal routing; the second bonding layer also includes a second metal routing and a second metal bonding block, and the second bonding portion is connected to the second metal bonding block through the second metal routing; the first metal bonding block and the second metal bonding block are in contact and bonded with each other, so that the first bonding layer and the second bonding layer are bonded to each other.

[0005] Optionally, the first bonding portion and the second bonding portion are a mesh structure.

[0006] Optionally, a plurality of bonding areas are provided on the first bonding portion and the second bonding portion to be respectively connected to the first metal wiring and the second metal wiring, and the bonding areas are located at intersections of the mesh structure.

[0007] Optionally, a size of the bonding area is larger than a size of the first metal trace and a size of the second metal trace.

[0008] Optionally, the spacing between adjacent bonding areas is twice or four times the size of the pixel unit.

[0009] Optionally, a projection of the first bonding portion along the first direction completely overlaps with a projection of the second bonding portion along the first direction.

[0010] Optionally, the first bonding layer also includes a first virtual bonding block located on a side close to the second semiconductor substrate and whose projection along the first direction is located at the pixel area, and the second bonding layer also includes a second virtual bonding block located on a side close to the first semiconductor substrate and whose projection along the first direction is located at the pixel area, and the first virtual bonding block and the second virtual bonding block are arranged to be bonded to each other.

[0011] Optionally, a distance between center points of adjacent first virtual bonding blocks is twice the size of the pixel unit; and / or a distance between center points of adjacent second virtual bonding blocks is twice the size of the pixel unit.

[0012] The present application also provides an electronic device, which includes the above-mentioned stacked image sensor chip.

[0013] Compared with the prior art, the utility model has at least the following outstanding advantages:

[0014] In the embodiment of the present application, the first bonding portion and the second bonding portion are both set to have a hollow pattern, so that during the hybrid bonding process of the first semiconductor substrate and the second semiconductor substrate, the stress of the copper metal is released through the hollow pattern, thereby avoiding the copper metal from cracking due to excessive stress, thereby affecting the performance of the image sensor chip. At the same time, the first bonding portion and the second bonding portion are set to have a hollow pattern, and the distribution density of the first bonding portion and the second bonding portion can be freely adjusted in actual design, which is beneficial to the subsequent chemical mechanical polishing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a partial cross-sectional schematic diagram of a stacked image sensor chip in the prior art;

[0016] Figure 2 It is a schematic diagram of the top metal of a wafer breaking off in the prior art;

[0017] Figure 3 is a partial cross-sectional schematic diagram of a stacked image sensor chip provided in an embodiment of the present application;

[0018] Figure 4 It is a schematic diagram of the positions of a logic area and a pixel area on a first semiconductor substrate provided by an embodiment of the present application;

[0019] Figure 5 is another schematic diagram of the positions of a logic area and a pixel area on a first semiconductor substrate provided by an embodiment of the present application;

[0020] Figure 6 This is another schematic diagram of the positions of the logic area and the pixel area on the first semiconductor substrate provided by an embodiment of the present application;

[0021] Figure 7 is a schematic structural diagram of a first bonding portion or a second bonding portion provided in an embodiment of the present application;

[0022] Figure 8 is a schematic structural diagram of another first bonding portion or second bonding portion provided in an embodiment of the present application;

[0023] Fig. 9 is a schematic structural diagram of another first bonding portion or a second bonding portion provided in an embodiment of the present application;

[0024] Fig.10 It is a partial cross-sectional schematic diagram of another stacked image sensor chip provided in an embodiment of the present application.

[0025] Component number description

[0026] 10. First semiconductor substrate

[0027] 20. Second semiconductor substrate

[0028] 110 First bonding layer

[0029] 120 pixel substrate layer

[0030] 210 Second bonding layer

[0031] 220 Functional Component Layer

[0032] 111 First bonding part

[0033] 113 First Metal Routing

[0034] 115 first metal bonding block

[0035] 212 Second bonding portion

[0036] 214 Second metal routing

[0037] 216 Second metal bonding block

[0038] LA Logical Area

[0039] PA pixel area

[0040] CA Junction Area

[0041] HA hollow area DETAILED DESCRIPTION

[0042] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0044] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0045] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0046] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0047] The stacked image sensor chip structure in the prior art is as follows: Figure 1 As shown, when the stacked image sensor chip uses hybrid bonding, the bonding area will be connected to the top metal of the first wafer and the second wafer. In the traditional process of 55nm and below, the top metal is mostly copper material with excellent conductive properties. At present, it is generally through etching the dielectric between the wafer layers and using magnetron sputtering to electroplate copper in the grooves. The inventors have found that after the copper process is completed, the copper stress is warped upward, so a layer of dielectric film will be deposited after chemical mechanical polishing to prevent cracking due to copper warping. The subsequent hybrid bonding process will actually open the dielectric layer in the bonding area, which can easily lead to the following problems: Figure 2 The copper material in the top metal layer is shown to be cracking, which in turn affects the performance of the image sensor.

[0048] Based on the above analysis, the present application embodiment provides Figure 3 The stacked image sensor chip shown includes at least a first semiconductor substrate 10 and a second semiconductor substrate 20 which are stacked opposite to each other. It can be understood that the first semiconductor substrate is a semiconductor chip provided with a pixel area, and some functional modules are provided on the second semiconductor substrate. The functional modules include some logic areas, memories, and processor circuits, etc., so as to increase the usable area of ​​the pixel unit on a single semiconductor substrate, improve the image quality, and optimize the performance of the logic elements in the logic area. In some embodiments, the second semiconductor substrate can be a chip with specific functions, such as an application-specific integrated circuit chip (ASIC), a field programmable gate array (FPGA), a dynamic random access memory (DRAM) or a static random access memory (SRAM), etc.

[0049] The first semiconductor substrate 10 includes a pixel substrate layer 120 disposed away from the second semiconductor substrate 20 and a first bonding layer 110 disposed close to the second semiconductor substrate 20. The pixel substrate layer 120 includes a logic area LA and a pixel area PA, wherein the pixel area PA includes a plurality of pixel units disposed in an array, and the plurality of pixel units in the pixel area PA may be arranged in a two-dimensional array structure, and each pixel unit may include a photodiode and a plurality of pixel transistors. Optionally, the pixel transistors include a transfer transistor, a reset transistor, a source follower transistor, and a selection transistor; the logic area LA may be provided with a logic element for processing a pixel signal from the pixel area. For example, Figure 4 As shown, the logic area LA is located on one side of the first semiconductor substrate, and the pixel area PA is located on the other side of the first semiconductor substrate; illustratively, as Figure 5 As shown, the logic area LA is located on both sides of the pixel area PA; illustratively, as Figure 6 As shown, the logic area LA is arranged around the pixel area PA. The positional relationship between the logic area LA and the pixel area PA is designed according to actual needs and is not limited here.

[0050] The second semiconductor substrate 20 at least includes a second bonding layer 210 disposed close to the first semiconductor substrate 10 and a functional element layer 220 disposed away from the first semiconductor substrate 10 , wherein the functional element layer 220 may include a portion of a logic area, a memory, a processor circuit, and the like.

[0051] The first semiconductor substrate 10 and the second semiconductor substrate 20 are bonded and connected by a first bonding layer 110 and a second bonding layer 210, wherein the first bonding layer 110 at least includes a first bonding portion 111 located at a side away from the second semiconductor substrate 20 and projected in the first direction at the logic area LA, and the second bonding layer 210 at least includes a second bonding portion 212 located at a side away from the first semiconductor substrate 10 and projected in the first direction at the logic area LA, and both the first bonding portion 111 and the second bonding portion 212 are patterns with hollow areas, wherein the first direction is a direction from the second semiconductor substrate 20 to the first semiconductor substrate 10. It can be understood that the first bonding portion 111 and the second bonding portion 212 are copper metal structures, and the electrical connection between the first semiconductor substrate 10 and the second semiconductor substrate 20 can be achieved by hybrid bonding between copper and metal.

[0052] Furthermore, the first bonding layer 110 further includes a first metal trace 113 and a first metal bonding block 115, and the first bonding portion 111 is connected to the first metal bonding block 115 through the first metal trace 113; the second bonding layer 210 further includes a second metal trace 214 and a second metal bonding block 216, and the second bonding portion 212 is connected to the second metal bonding block 216 through the second metal trace 214; the first metal bonding block 115 and the second metal bonding block 216 are in contact and bonded with each other, so that the first bonding layer 111 and the second bonding layer 212 are bonded and connected. Among them, the first metal trace 113, the first metal bonding block 115, the second metal trace 214 and the second metal bonding block 216 are also copper metal structures.

[0053] Optionally, the projection of the first bonding portion 111 along the first direction completely overlaps with the projection of the second bonding portion 212 along the first direction, that is, the first bonding portion 111 and the second bonding portion 212 have the same shape and corresponding positions, which is conducive to simplifying the process flow.

[0054] In the embodiment of the present application, the first bonding portion and the second bonding portion are both set to have a hollow pattern. During the mixed bonding process of the first semiconductor substrate and the second semiconductor substrate, the stress of the copper metal is released through the hollow pattern, thereby avoiding the copper metal from cracking due to excessive stress, thereby affecting the performance of the image sensor chip. At the same time, the first bonding portion and the second bonding portion are set to have a hollow pattern to relieve stress, so that the distribution density of the first bonding portion and the second bonding portion can be freely adjusted in actual design, which is beneficial to the subsequent chemical mechanical polishing process.

[0055] In some embodiments, in combination Figure 3 and Figure 7 As shown, the first bonding portion 111 and the second bonding portion 212 are mesh structures.

[0056] Furthermore, a plurality of bonding areas CA are provided on the first bonding portion 111 and the second bonding portion 212, HA is a hollow area, the first bonding portion 111 and the second bonding portion 212 are respectively connected to the first metal wiring 113 and the second metal wiring 214 through the bonding areas CA, and the bonding areas CA are located at the intersection of the mesh structure.

[0057] Optionally, the size of the bonding area CA is larger than the size of the first metal wiring 113 and the second metal wiring 214. It can be understood that the size here refers to the length in a direction parallel to the first semiconductor substrate or the second semiconductor substrate.

[0058] Optionally, the interval between adjacent bonding areas CA is twice or four times the size of the pixel unit.

[0059] In this embodiment, the first bonding portion and the second bonding portion are designed to be a mesh structure with a rectangular hollow area, so that the stress of the copper metal material is released through the rectangular hollow area, thereby avoiding the problem of copper metal cracking that may occur between the first semiconductor substrate and the second semiconductor substrate during the hybrid bonding process.

[0060] In other embodiments, Figure 8 As shown, the first bonding portion or the second bonding portion is designed to be in a "U-shaped" shape. Compared with the above embodiments, more area can be allocated for setting the contact area CA while ensuring that the copper metal stress is released through the hollow area HA.

[0061] In other embodiments, Fig. 9 As shown, in the first bonding part or the second bonding part, the hollow area HA is a long strip, and the contact area CA is located between adjacent long strip hollow areas. Therefore, the position and pattern of the hollow area and the bonding area can be designed according to actual needs, as long as the stress of the copper metal can be released, and no limitation is made here.

[0062] In some embodiments, Fig.10 As shown, the first bonding layer 110 also includes a first virtual bonding block 117 located on a side close to the second semiconductor substrate 20 and whose projection along the first direction is located at the pixel area PA, and the second bonding layer 210 also includes a second virtual bonding block 218 located on a side close to the first semiconductor substrate 10 and whose projection along the first direction is located at the pixel area PA, and the first virtual bonding block 117 and the second virtual bonding block 218 are arranged to be bonded to each other.

[0063] Optionally, the distance a between the center points of adjacent first virtual bonding blocks 117 is twice the pixel unit size b.

[0064] Optionally, the distance a between the center points of adjacent second virtual bonding blocks 218 is twice the pixel unit size b.

[0065] In the pixel area PA of the image sensor chip in the prior art, the wafer surface coplanar with the metal bonding block of the logic area LA is easily affected by the stress during the flattening of the metal bonding block and causes loss, thereby forming an uneven surface morphology. Excessive stress can also easily cause splitting on the wafer surface, thereby reducing the bonding strength of the two facing wafers. At the same time, the loss of the wafer surface in the pixel area PA of the image sensor chip during the flattening process will also affect the effect of the image sensor in receiving light, thereby affecting the yield and stability of the product.

[0066] Therefore, in this embodiment, by setting relative virtual metal bonding blocks in the areas of the first bonding layer and the second bonding layer corresponding to the pixel area PA and performing bonding, while ensuring the bonding strength, it is also possible to avoid the splitting of the wafer surface due to excessive stress during the polishing process, thereby affecting the effect of the pixel unit receiving light.

[0067] The present application also provides an electronic device, comprising the above-mentioned stacked image sensor chip.

[0068] The above contents are further detailed descriptions of the present invention in combination with specific preferred implementations, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A stacked image sensor chip, characterized in that: The stacked image sensor chip comprises at least a first semiconductor substrate and a second semiconductor substrate which are stacked facing each other, wherein: The first semiconductor substrate comprises a pixel substrate layer disposed away from a side of the second semiconductor substrate and a first bonding layer disposed close to a side of the second semiconductor substrate, the pixel substrate layer comprises a logic area and a pixel area, and the pixel area comprises a plurality of pixel units arranged in an array; The second semiconductor substrate at least comprises a second bonding layer disposed close to a side of the first semiconductor substrate and a functional element layer disposed away from a side of the first semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are bonded and connected via the first bonding layer and the second bonding layer; The first bonding layer at least includes a first bonding portion located on a side away from the second semiconductor substrate and whose projection along the first direction is located at the logic area, and the second bonding layer at least includes a second bonding portion located on a side away from the first semiconductor substrate and whose projection along the first direction is located at the logic area, and both the first bonding portion and the second bonding portion are figures with hollow areas, wherein the first direction is a direction from the second semiconductor substrate to the first semiconductor substrate.

2. The stacked image sensor chip according to claim 1, wherein: The first bonding layer further includes a first metal wiring and a first metal bonding block, and the first bonding portion is connected to the first metal bonding block through the first metal wiring; The second bonding layer further includes a second metal wiring and a second metal bonding block, and the second bonding portion is connected to the second metal bonding block through the second metal wiring; The first metal bonding block and the second metal bonding block are in contact and bonded with each other, so that the first bonding layer and the second bonding layer are bonded and connected.

3. The stacked image sensor chip according to claim 2, wherein: The first bonding portion and the second bonding portion are mesh structures.

4. The stacked image sensor chip according to claim 3, wherein: A plurality of bonding areas are disposed on the first bonding portion and the second bonding portion to be respectively connected to the first metal wiring and the second metal wiring, and the bonding areas are located at intersections of the mesh structure.

5. The stacked image sensor chip according to claim 4, wherein: The size of the bonding area is larger than the size of the first metal trace and the second metal trace.

6. The stacked image sensor chip according to claim 4, wherein: The spacing between adjacent bonding areas is twice or four times the size of the pixel unit.

7. The stacked image sensor chip according to claim 1, wherein: A projection of the first bonding portion along the first direction completely overlaps with a projection of the second bonding portion along the first direction.

8. The stacked image sensor chip according to claim 1, wherein: The first bonding layer also includes a first virtual bonding block located on a side close to the second semiconductor substrate and whose projection along the first direction is located at the pixel area. The second bonding layer also includes a second virtual bonding block located on a side close to the first semiconductor substrate and whose projection along the first direction is located at the pixel area. The first virtual bonding block and the second virtual bonding block are bonded to each other.

9. The stacked image sensor chip according to claim 8, wherein: The distance between the center points of adjacent first virtual bonding blocks is twice the size of the pixel unit; and / or, The distance between the center points of adjacent second virtual bonding blocks is twice the size of the pixel unit.

10. An electronic device, characterized in that: The electronic device comprises the stacked image sensor chip as described in any one of claims 1-9.

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