Package including dummy strips

Abstract

The utility model provides a package, which comprises a first crystal grain and a second crystal grain which are positioned in an encapsulation body layer; and a dummy bar in the encapsulant layer and adjacent to a gap between the first die and the second die. A method of forming a package, the method comprising: bonding a first die and a second die to a surface; attaching a dummy strip to the surface adjacent to a gap between the first die and the second die; and forming an encapsulation body layer on the first crystal grains, the second crystal grains and the dummy strips.

Description

Technical Field

[0001] The utility model relates to a package including a dummy strip. Background Art

[0002] A typical package may include multiple dies (eg, semiconductor dies) and an upper layer of molding material surrounding the multiple dies. Mechanical stresses may be generated in a package due to a variety of factors including thermal expansion, mechanical bending, and changes in the electrical properties of the material.

[0003] For example, when the temperature of a package changes, different materials in the package may expand or contract at different rates due to the different coefficients of thermal expansion (CTE) of the dissimilar materials used in the package. These changes in thermal expansion and contraction can generate stresses at the interfaces between the different materials. In cases where the stress exceeds the strength of the material, cracks may form in the package. Utility Model Content

[0004] An embodiment of the utility model provides a package, comprising: a first die and a second die, which are located in an encapsulation layer; and a dummy strip, which is located in the encapsulation layer and is adjacent to a gap between the first die and the second die.

[0005] An embodiment of the utility model provides a package, comprising: a package substrate; a package module, located on the package substrate, comprising: a first crystal grain and a second crystal grain, located in the package layer; and a dummy bar, located in the package layer and adjacent to a gap between the first crystal grain and the second crystal grain; and a package cover, located on the package module and adhered to the package substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a perspective view of a package module including a dummy bar according to one or more embodiments.

[0008] Figure 1B According to one or more embodiments Figure 1A A plan view (eg, top view) of a packaged module is shown.

[0009] Figure 1C According to one or more embodiments, Figure 1B A vertical cross-sectional view of the package module along the cutting line AA' in FIG.

[0010] Figure 1D According to one or more embodiments, Figure 1B A vertical cross-sectional view of the package module along the cutting line BB' in FIG.

[0011] Figure 2A Two vertical cross-sectional views of an intermediate structure including a dummy bar attached to a first carrier substrate (eg, a carrier wafer), a first die, and a second die are provided according to an embodiment of the present invention.

[0012] Figure 2B is a vertical cross-sectional view of an intermediate structure after grinding of an encapsulation layer according to one or more embodiments.

[0013] Figure 2C is a vertical cross-sectional view of an intermediate structure after forming a passivation layer, a connecting structure, and a through-hole according to one or more embodiments.

[0014] Figure 2D is a vertical cross-sectional view of an intermediate structure including a local silicon interconnect (LSI) die in accordance with one or more embodiments.

[0015] Figure 2E is a vertical cross-sectional view of an intermediate structure after thinning of an LSI die according to one or more embodiments.

[0016] Figure 2F is a vertical cross-sectional view of an intermediate structure including a lower molding layer according to one or more embodiments.

[0017] Figure 2G is a vertical cross-sectional view of an intermediate structure including a redistribution layer (RDL) portion and a controlled collapse chip connect (C4) bump according to one or more embodiments.

[0018] Figure 2H is a vertical cross-sectional view of an intermediate structure after peeling off the first carrier substrate according to one or more embodiments.

[0019] Figure 3 is a flow chart illustrating a method of forming a package (eg, a package module) according to one or more embodiments.

[0020] Figure 4A is a vertical cross-sectional view of a package according to one or more embodiments.

[0021] Figure 4B is a plan view (eg, top view) of a package according to one or more embodiments.

[0022] Figure 5Ais a vertical cross-sectional view of an intermediate structure including a package substrate having a package substrate upper bonding pad and a package substrate lower bonding pad according to one or more embodiments.

[0023] Figure 5B A vertical cross-sectional view illustrates an intermediate structure in which a packaging module may be mounted on a packaging substrate in accordance with one or more embodiments.

[0024] Figure 5C A vertical cross-sectional view of an intermediate structure in which a package underfill layer may be formed on a package substrate is shown, with an outline of a dummy strip superimposed on the vertical cross-sectional view, in accordance with one or more embodiments.

[0025] Figure 5D A vertical cross-sectional view of an intermediate structure in which a thermal interface material (TIM) layer may be attached to (eg, formed on) a package module, with an outline of a dummy bar superimposed on the vertical cross-sectional view, according to one or more embodiments.

[0026] Figure 5E A vertical cross-sectional view illustrates an intermediate structure in which an adhesive layer may be applied to a package substrate in accordance with one or more embodiments.

[0027] Fig. 5F A vertical cross-sectional view illustrates an intermediate structure in which a package lid may be attached to (eg, mounted on) a package substrate in accordance with one or more embodiments.

[0028] Figure 5G A vertical cross-sectional view illustrating an intermediate structure in which a plurality of solder balls may be formed on a package substrate in accordance with one or more embodiments.

[0029] Figure 6 is a flow chart illustrating a method of forming a package in accordance with one or more embodiments.

[0030] Figure 7 is a vertical cross-sectional view of a package having a first alternative design in accordance with one or more embodiments.

[0031] Fig. 8A is a plan view of a package module having a first alternative design according to one or more embodiments.

[0032] Figure 8B is a plan view of a package module having a second alternative design according to one or more embodiments.

[0033] Figure 8C is a plan view of a package module having a third alternative design according to one or more embodiments.

[0034] Fig. 9 is a perspective view of a packaging module having a fourth alternative design according to one or more embodiments. DETAILED DESCRIPTION

[0035] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0036] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another (other) component or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless expressly stated otherwise, each component having the same reference number is assumed to be of the same material composition and having a thickness within the same thickness range.

[0037] Mechanical bending can also be a source of stress in a package (e.g., a package module). Mechanical bending can occur when the package is subjected to external forces (e.g., during assembly of the package or when in use). In the event of excessive bending, the material in the package may crack and / or suffer areas of delamination. In particular, insufficient die-to-die bending strength may cause the package to suffer yield loss due to die-to-die cracks.

[0038] One or more embodiments of the present disclosure may include a package including one or more dummy bars. The dummy bars may enhance bending strength (e.g., die-to-die bending strength) and displacement in the package. The dummy bars may mitigate the risk of die-to-die cracks due to bending stress on the package and thus improve yield loss.

[0039] In at least one embodiment, the package may include a three-dimensional integrated package with a fan-out design. In at least one embodiment, the package may include a package module having a lower module portion. The lower module portion may include a lower mold layer and a perforation located in the lower mold layer. The lower module portion may also include a local silicon interconnect (LSI) die located in the lower mold layer. The package module may also include an upper module portion located on the lower module portion. The upper module portion may include an encapsulation layer (upper mold layer) and one or more die (e.g., semiconductor die such as a system on chip (SOC) die) attached to the lower module portion in the encapsulation layer.

[0040] One or more dummy bars may also be located in the encapsulation layer. The dummy bars may be located above the lower module portion. In at least one embodiment, the dummy bars may be adjacent to gaps between dies (eg, die-to-die gaps) in the upper module portion.

[0041] In at least one embodiment, the material of the dummy bar may include silicon, silicon dioxide, glass, ceramic material, metal material, etc. However, other suitable materials may also be used. In a plan view, the dummy bar may have a rectangular shape, although other shapes are also possible. The width of the gap may be in the range of 1 micron to 5000 microns (e.g., about 100 microns). The short side of the dummy bar may be in the range of 0.1 mm to 10.0 mm (e.g., about 1.2 mm), and the long side of the dummy bar may be in the range of 1 mm to 30 mm (e.g., about 6 mm). The thickness of the dummy bar may be in the range of 10 microns to 5000 microns.

[0042] In at least one embodiment, the upper surface of the dummy bar can be substantially coplanar with the upper surface of the die (e.g., semiconductor die) in the upper module portion of the package. In at least one embodiment, the distance between the dummy bar and the die can be as small as possible so that the size of the dummy bar can be as large as possible. The distance between the dummy bar and the die can depend on, for example, the die pick and place (PNP) accuracy.

[0043] A dummy bar with a large size (e.g., a large bar length) can provide better performance in the upper module portion with various gap lengths between dies. In particular, a large dummy bar size can promote improved bending strength characteristics. Therefore, the distance between the dummy bar and the edge of the lower molded portion can be as small as possible. The distance can also depend on the PNP capability for handling higher aspect ratio dies.

[0044] Figure 1Ais a perspective view of a package module 120 including a dummy bar 500 according to one or more embodiments.

[0045] Figure 1B According to one or more embodiments Figure 1A A plan view (eg, top view) of packaging module 120 is shown. Figure 1C According to one or more embodiments, Figure 1B 1 is a vertical cross-sectional view of the packaging module 120 along the cutting line AA′ in FIG. Figure 1D According to one or more embodiments, Figure 1B 1 is a vertical cross-sectional view of the package module 120 along the cutting line BB′ in FIG. The package module 120 may be included in, for example, a package (eg, a semiconductor package).

[0046] It should be noted that although the present disclosure may describe dummy bar 500 as being located in package module 120, the use of dummy bar 500 is not limited to packages or package modules having any particular structure or configuration. In particular, dummy bar 500 may be used in any package or package module having any structure or configuration.

[0047] like Figure 1A As shown, the package module 120 may include a redistribution layer (RDL) portion 10 and a lower module portion 20 located on the RDL portion 10. The lower module portion 20 may include a lower molding layer 227 and a local silicon interconnect die (LSI die) (not shown) located in the lower module portion 20. The package module 120 may also include an upper module portion 30 located on the lower module portion 20 (e.g., located on the lower molding layer 227). The upper module portion 30 may include a plurality of dies 140 attached to a surface of the lower module portion 20. The plurality of dies 140 may include a first die 141 and a second die 142 adjacent to the first die 141 in the x-direction. The LSI die in the lower module portion 20 may electrically couple the first die 141 to the second die 142.

[0048] It should be noted that although packaging module 120 is shown as including a specific number of dies 140 with a specific arrangement, the number of dies 140 and the arrangement of dies 140 are not limited to any specific number and arrangement. Specifically, packaging module 120 may include any number and arrangement of dies 140.

[0049] The first die 141 and the second die 142 may be separated by a gap GD2D (e.g., a die-to-die gap) in the upper module portion 30. The upper module portion 30 may also include one or more dummy bars 500 (e.g., dummy dies) adjacent to the gap GD2D. The dummy bars 500 may be located above the lower module portion 20. The center of the dummy bar 500 in the x-direction may be substantially aligned with the center of the gap GD2D in the x-direction. Figure 1A As shown, in at least one embodiment, the package module 120 may include a pair of dummy bars 500 located on opposite sides of the gap GD2D in the y direction. The thickness T500 of the dummy bars 500 may be in the range of 10 μm to 5000 μm. The upper surface of the upper module portion 30 may be at least partially composed of the upper surface of the dummy bars 500, the upper surface of the first die 141, and the upper surface of the second die 142.

[0050] The upper module portion 30 may also include an encapsulant layer 127 (e.g., a molding material layer). The dummy bar 500, the first die 141, and the second die 142 may be located in the encapsulant layer 127 (e.g., encapsulated by the encapsulant layer 127). The encapsulant layer 127 may be located in the gap GD2D. The encapsulant layer 127 may also be located between the dummy bar 500 and the first die 141 and the second die 142 in the y-direction, and between the dummy bar 500 and the edge of the lower module portion 20 in the y-direction. The upper surface of the encapsulant layer 127 may also be substantially coplanar with the upper surface of the dummy bar 500, the upper surface of the first die 141, and the upper surface of the second die 142. Therefore, the height H1 of the upper surface of the encapsulant layer 127 (e.g., measured from the RDL portion 10) may be substantially equal to the height H2 of the upper surface of the dummy bar 500.

[0051] It should be noted that although Figure 1A The dummy bar 500 is shown as having an upper surface substantially coplanar with the upper surface of the encapsulation layer 127, the upper surface of the first die 141, and the upper surface of the second die 142, but the configuration and orientation of the dummy bar 500 are not limited to Figure 1A In at least one embodiment, the upper surface of the dummy bar 500 may be lower than the upper surface of the encapsulant layer 127. In at least one embodiment, the dummy bar 500 may be attached to the lower module portion 20.

[0052] The dummy bar 500 may enhance bending strength (e.g., die-to-die bending strength) and displacement in the package module 120. The dummy bar 500 may help reduce the risk of die-to-die cracks (e.g., cracks in the encapsulation layer 127 in or around the die-to-die gap GD2D) due to bending stress on the package module 120 (e.g., bending stress on the package including the package module 120), and thus improve yield loss.

[0053] Reference Figure 1B , for ease of understanding, Figure 1B The encapsulation body layer 127 is omitted in FIG. 1 . The outline of the LSI die 200 in the lower module portion 20 is indicated by a dotted line in order to understand the position of the dummy bar 500 relative to the position of the LSI die 200 .

[0054] like Figure 1B As shown, LSI die 200 may be located below die 140. Specifically, the center of LSI die 200 in the x direction may be substantially aligned with the center of gap GD2D in the x direction. In a plan view, dummy bar 500 may be formed outside LSI die 200. Although Figure 1B The example in FIG. 1 includes a pair of dummy bars 500 located on opposite sides of the gap GD2D in the y-direction, but a greater or lesser number of dummy bars 500 may also be used in the packaging module 120 within the scope of the present disclosure.

[0055] In a plan view, the dummy bar 500 may have a rectangular shape, although other shapes such as a circle, an ellipse, a polygon, etc. may also be used. The dummy bar 500 may have a long side having a length L1 perpendicular to the longitudinal direction of the gap GD2D (e.g., the y direction). The dummy bar 500 may have a short side having a length L2 parallel to the longitudinal direction of the gap GD2D. The width D1 of the gap GD2D may be in the range of 1 micron to 5000 microns (e.g., about 100 microns), but wider or narrower widths D1 are also within the scope of the present disclosure. The dummy bar 500 may have a long side perpendicular to the longitudinal direction of the gap GD2D (e.g., the y direction) and a short side parallel to the longitudinal direction of the gap GD2D. The long side of the dummy bar 500 may have a length L1 in the range of 1 mm to 30 mm (e.g., about 6 mm), and the short side of the dummy bar 500 may have a length L2 in the range of 0.1 mm to 10.0 mm (e.g., about 1.2 mm). Other ranges of L1 and L2 are also within the scope of the present disclosure. The dummy bar 500 with a large size (e.g., a large length L1) can provide better performance in the case where the gap GD2D between the dies 141, 142 has various widths D1 in the upper module portion 30. Specifically, the large size of the dummy bar 500 can be conducive to the improvement of bending strength.

[0056] The lower module portion 20 may have a substantially rectangular shape in a plan view. The lower module portion 20 may have a long side perpendicular to the longitudinal direction of the gap GD2D and a short side parallel to the longitudinal direction of the gap GD2D. The long side of the lower module portion 20 may have a length L3 in the range of 10 mm to 1000 mm (e.g., about 45 mm), and the short side of the lower module portion 20 may have a length L4 in the range of 5 mm to 500 mm (e.g., about 23 mm). The ratio of the length L3 of the lower module portion 20 to the length L1 of the dummy bar 500 may be in the range of 1.5 to 15. Other ranges of L3 and L4 are also within the scope of the present disclosure.

[0057] The distance D2 between the die 141, 142 and the edge of the lower module portion 20 (e.g., in the y direction) may be in the range of 0.1 mm to 10 mm (e.g., about 1.74 mm). The ratio of the distance D2 to the length L2 of the dummy bar 500 may be in the range of 1.5 to 5. The distance D3 between the die 141, 142 (collectively referred to as the die 140) and the edge of the lower module portion 20 (e.g., in the x direction) may be in the range of 100 microns to 1000 microns (e.g., about 280 microns). The distance D4 between the dummy bar 500 and the die 140 (e.g., in the y direction) may be in the range of 0.1 mm to 5 mm. The distance D4 may be configured to be as small as possible so that the size of the dummy bar 500 may be as large as possible. The distance D5 between the dummy bar 500 and the edge of the lower module portion 20 (e.g., in the y direction) may also be in the range of 0.1 mm to 5 mm. In at least one embodiment, distance D5 may be greater than distance D4. Distance D4 and distance D5 may depend on die pick and place (PNP) accuracy (e.g., PNP capability for processing dies with higher aspect ratios). Other ranges of D2 to D5 are also within the scope of the present disclosure.

[0058] In at least one embodiment, the dummy bar 500 may be centered on the gap GD2D (e.g., in the x-direction) (e.g., the center of the dummy bar 500 in the x-direction may be substantially aligned with the center of the gap GD2D in the x-direction). When the dummy bar 500 is centered on the gap GD2D, better bending strength improvement may be provided. Regardless of whether the package module 120 includes dies 140 of the same length in the x-direction or dies 140 of different lengths in the x-direction, the dummy bar 500 may be centered on the gap GD2D.

[0059] Reference Figure 1C, the RDL portion 10 is not necessarily limited to any particular material or configuration. The RDL portion 10 may include, for example, an organic material (e.g., a dielectric polymer), an inorganic material (e.g., silicon), a glass substrate, etc. In at least one embodiment, the RDL portion 10 may include a plurality of polymer layers 12 and a plurality of redistribution layers 12a that are alternately stacked. The number of polymer layers 12 and / or the number of redistribution layers 12a in the RDL portion 10 are not limited by the present disclosure.

[0060] In at least one embodiment, the polymer layer 12 may include, for example, polyimide (PI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO) or any other suitable polymer-based dielectric material. In some embodiments, the redistribution layer 12a may include a conductive material. The conductive material may include a metal, such as copper, aluminum, nickel, titanium, a combination thereof, or other suitable metals.

[0061] The redistribution layer 12a may include a metal connection structure, i.e., a metal structure that provides electrical connections between nodes in the structure. The redistribution layer 12a may include a metal seed layer and a metal filling material located on the metal seed layer. The metal seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer may have a thickness in the range of 50 nanometers to 500 nanometers, and the copper seed layer may have a thickness in the range of 50 nanometers to 500 nanometers. The metal filling material used for the redistribution layer 12a may include copper, nickel, or copper and nickel. Other suitable metal filling materials are also within the scope of the present disclosure. The thickness of the metal filling material deposited for each redistribution layer 12a may be in the range of 2 microns to 40 microns, for example, 4 microns to 10 microns, although smaller or larger thicknesses may also be used.

[0062] In at least one embodiment, the redistribution layer 12a may include a plurality of traces (lines) and a plurality of vias connecting the plurality of traces to each other. The traces may be located on the polymer layer 12, respectively, and may extend in the x-direction (first horizontal direction) and the y-direction (second horizontal direction) on the upper surface of the polymer layer 12.

[0063] A chip-side passivation layer (not shown) may be formed on the chip-side surface of the RDL portion 10. The chip-side passivation layer may include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0064] One or more chip side bonding pads (not shown) may be formed in the chip side passivation layer on the chip side surface of the RDL portion 10. The chip side passivation layer may at least partially cover the chip side bonding pads. That is, the chip side bonding pads may be at least partially exposed on the chip side surface of the RDL portion 10. The chip side bonding pads may be connected to the redistribution layer 12a. The chip side bonding pads may include, for example, one or more layers, and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0065] A board-side passivation layer 14 may be formed on the board-side surface of the RDL portion 10. The board-side passivation layer 14 may also include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials. One or more board-side bonding pads 14a may be located on the board-side surface of the RDL portion 10. The board-side bonding pads 14a may be bonded to and electrically connected to the redistribution layer 12a. The board-side bonding pads 14a may be located in the board-side passivation layer 14. The board-side passivation layer 14 may at least partially cover the board-side bonding pads 14a. That is, the board-side bonding pads 14a may be at least partially exposed on the board-side surface of the RDL portion 10. The board-side bonding pad 14a may also include, for example, one or more layers and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.) Other suitable metal materials are also within the scope of the present disclosure.

[0066] One or more integrated passive devices (IPDs) (not shown) may also be present on the board side surface of the RDL portion 10. The IPD may be bonded to and electrically connected to the redistribution layer 12a. The IPD may be located in the board side passivation layer 14. The IPD may include an exposed portion protruding from the board side passivation layer 14. The IPD may include one or more electronic components (e.g., resistors, capacitors, inductors, coils, chokes, microstrip lines, impedance matching components, balanced-unbalanced converters, etc.). The IPD may be electrically coupled to the die 140 by the RDL portion 10.

[0067] like Figure 1CAs further shown, a plurality of controlled collapse chip connection (C4) bumps 121 may be respectively connected to the board side bonding pads 14a on the board side surface of the RDL portion 10. In at least one embodiment, the C4 bumps 121 may include an underbump metallurgy (UBM) layer located on the board side bonding pads 14a. The C4 bumps 121 may also include contact pads 121a (e.g., copper / nickel contact pads) located on the UBM layer and solder bumps 121b (e.g., SnAg solder bumps) located on the contact pads 121a. The C4 bumps 121 may enable the package module 120 to be connected to a substrate such as a package substrate.

[0068] The length of the lower module portion 20 in the x-direction may be substantially the same as the length of the RDL portion 10 in the x-direction (see Figure 1C ). The width of the lower module portion 20 in the y direction may be substantially the same as the width of the RDL portion 10 in the y direction. The thickness of the lower module portion 20 in the z direction may be greater than the thickness of the RDL portion 10.

[0069] The lower module portion 20 may include a lower molding layer 227 (e.g., an encapsulation layer) formed on the RDL portion 10. In at least one embodiment, the lower molding layer 227 may be formed of a curable material that can be cured to form a hard solid structure. The lower molding layer 227 may include, for example, an epoxy molding compound (EMC). In at least one embodiment, the lower molding layer 227 may include a polymeric material and specifically an epoxy-based polymeric material. Other suitable molding materials may be used.

[0070] In at least one embodiment, the lower molding layer 227 may have a CTE substantially similar to the CTE of the RDL portion 10. In at least one embodiment, the lower molding layer 227 may include an additive material (e.g., a filler material) for improving the properties (e.g., thermal conductivity, CTE, etc.) of the lower molding layer 227. The additive material may include, for example, metal powder, metal oxide powder, etc. Other materials in the lower molding layer 227 are also within the scope of the present disclosure.

[0071] The lower module portion 20 may also include one or more local silicon interconnect (LSI) die 200. A package module bottom fill layer 229 may be formed around the LSI die 200. The package module bottom fill layer 229 may be formed of an epoxy-based polymer material. The lower molding layer 227 may be formed to surround the LSI die 200 and the package module bottom fill layer 229 in the x-direction and the y-direction. In at least one embodiment, the LSI die 200 and the package module bottom fill layer 229 may be substantially embedded in the lower molding layer 227.

[0072] The LSI die 200 may be connected to the RDL portion 10 (e.g., by oxide-oxide bonding, metal-metal bonding, etc.). The LSI die 200 may include one or more vias 202 bonded to chip-side bonding pads (not shown) and / or the redistribution layer 12a in the RDL portion 10. Thus, the LSI die 200 may be electrically coupled to the RDL portion 10.

[0073] The LSI die 200 may include one or more metal traces and metal vias (not shown) as interconnect structures for interconnecting the die 140 in the package module 120. Specifically, the LSI die 200 may include one or more interconnect structures for connecting the first die 141 to the second die 142. In at least one embodiment, the interconnect structure may provide high wiring density die-to-die interconnects by multiple layers of sub-micron metal (e.g., copper) wires. The interconnect structure may enable the LSI die 200 to adapt to a variety of different connection architectures (e.g., SoC to SoC, SoC to chiplet, SoC to high bandwidth memory (HBM), etc.). The interconnect structure may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0074] The lower module portion 20 may also integrate additional components, such as a separate IPD (not shown). In at least one embodiment, an IPD may be located in the lower molding layer 227 below one or more of the dies 140 to support signal communications.

[0075] The lower module portion 20 may also include one or more through-holes 206 (e.g., through molding vias (TMVs)) in the lower molding layer 227. The through-holes 206 may provide direct coupling between the RDL portion 10 and the die 140 in the upper module portion 30. The through-holes 206 may include, for example, one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0076] The lower module portion 20 may also include one or more passivation layers 260 (e.g., oxide layers, nitride layers, etc.) located on the chip-side surface of the lower module portion 20. The passivation layer 260 may be located on the lower molding layer 227 and the package module underfill layer 229. The through-hole 206 may or may not extend through the passivation layer 260 and electrically couple to the die 140 in the upper module portion 30.

[0077] The lower module portion 20 may also include a bonding pad 255 in the lower molding layer 227. The lower module portion 20 may also include a conductive connector 55 located in the passivation layer 260 and connected to the bonding pad 255. The conductive connector 55 may be connected to a die bonding pad 155 on the semiconductor die 140. The bonding pad 255, the conductive connector 55, and the die bonding pad 155 may together form a connection structure 275 for electrically connecting the die 140 to the lower module portion 20. Each of the bonding pad 255, the conductive connector 55, and the die bonding pad 155 may include, for example, one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0078] The lower module portion 20 may also include one or more micro bumps 228 on the chip side surface of the LSI die 200. The micro bumps 228 may be connected to the through-holes 202 in the LSI die 200. One or more of the connection structures 275 in the passivation layer 260 may be connected to the micro bumps 228, so that the die 140 in the upper module portion 30 can be electrically coupled to the LSI die 200.

[0079] The microbumps 228 may each include a copper pillar and a solder bump on the copper pillar. The microbumps 228 may be bonded (eg, by the solder bumps) to metal contacts on the chip side surface of the LSI die 200. A package module underfill layer 229 may be formed around the microbumps 228.

[0080] The length of the upper module portion 30 in the x-direction may be substantially the same as the length of the lower module portion 20 in the x-direction. The width of the upper module portion 30 in the y-direction may be substantially the same as the width of the lower module portion 20 in the y-direction. The thickness T30 of the upper module portion 30 in the z-direction may be greater than the thickness T20 of the lower module portion 20.

[0081] The upper module portion 30 may include a die 140 attached to the chip-side surface of the lower module portion 20. Specifically, the die 140 may be attached to the passivation layer 260 on the chip-side surface of the lower module portion 20. In general, the thickness of each of the die 140 in the z-direction may be substantially the same. Therefore, the upper surface of each of the first die 141 and the second die 142 may be substantially coplanar (e.g., formed in the same xy plane) and collectively referred to as a die upper surface 140a. The die 140 may be attached to the lower module portion 20 such that the center of the gap GD2D in the x-direction may be substantially aligned with the center of the LSI die 200 in the x-direction.

[0082] Each of the dies 140 may include, for example, a single die, a system-on-chip (SOC) die, or a system-on-integrated-chip (SoIC) die, and may be implemented by a chip-on-wafer-on-substrate technology or an integrated fan-out on substrate technology.Specifically, each of the dies 140 may include, for example, a semiconductor chip or chiplet for high performance computing (HPC) applications, artificial intelligence (AI) applications, and fifth generation (5G) cellular network applications, a logic die (e.g., a mobile application processor, a microcontroller, etc.), or a memory die (e.g., a high bandwidth memory (HBM) die, a hybrid memory cube (HMC), a dynamic random access memory (DRAM) die, a wide input / output (I / O) die, a magnetic random access memory (M-RAM) die, a resistive random access memory (R-RAM) die, a NAND die, a static random access memory (SRAM) die, etc.), a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a field-programmable gate array (FPGA) chip, or a microcontroller. The invention relates to an embodiment of the present invention and the invention relates to an array (FPGA) chip, a network chip, an application-specific integrated circuit (ASIC) chip, an artificial intelligence / deep neural network (AI / DNN) accelerator chip, a coprocessor, an accelerator, an on-chip memory buffer, a high data rate transceiver die, an I / O interface die, an IPD die, a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), a monolithic three-dimensional heterogeneous chiplet stacking die, etc.Other dies are also within the scope of this disclosure.

[0083] In at least one embodiment, each of the first die 141 and the second die 142 may include a main die (e.g., a SOC die). In at least one embodiment, at least one of the die 140 may include a main die (e.g., a SOC die), and at least one of the die 140 may include an auxiliary die (e.g., a memory / SOC die, an HBM die, etc.).

[0084] The encapsulation layer 127 may be formed around the die 140 and the dummy bar 500 (see Figure 1A ), and has outer sidewalls substantially aligned with the outer sidewalls of the lower module portion 20 and the RDL portion 10. The encapsulant layer 127 may also have a substantially uniform (e.g., flat) upper surface, and be substantially coplanar with the upper surface 140a of the die 140. The encapsulant layer 127 may be formed on the sidewalls (inner sidewalls and outer sidewalls) of each of the die 140. The encapsulant layer 127 may be bonded to the sidewalls of each of the die 140, the passivation layer 260, and the lower molding layer 227.

[0085] In at least one embodiment, the encapsulant layer 127 may be formed of a curable material that can be cured to form a hard solid structure. The encapsulant layer 127 may include, for example, an epoxy molding compound (EMC). In at least one embodiment, the encapsulant layer 127 may include a material substantially similar to the package module bottom fill layer 229 and / or substantially similar to the lower molding layer 227 in the lower module portion 20. In at least one embodiment, the encapsulant layer 127 may include a polymeric material and, in particular, an epoxy-based polymeric material. Other suitable molding materials may be used.

[0086] In at least one embodiment, the encapsulant layer 127 may have a CTE substantially similar to the CTE of the lower module portion 20 and / or the CTE of the RDL portion 10. In at least one embodiment, the encapsulant layer 127 may include an added material (e.g., a filler material) for improving the properties (e.g., thermal conductivity, CTE, etc.) of the encapsulant layer 127. The added material may include, for example, metal powder, metal oxide powder, etc. Other materials in the encapsulant layer 127 are also within the scope of the present disclosure.

[0087] Reference Figure 1D , the dummy bar 500 may be near the edge of the lower module portion 20 (eg, see Figure 1B ) is located in the encapsulation layer 127. Therefore, if Figure 1DAs shown, the upper module portion 30 and the lower module portion 20 may include few or no functional components around the dummy bar 500. The upper surface of the dummy bar 500 may be exposed at the upper surface of the encapsulant layer 127. However, in at least one embodiment, the dummy bar 500 may be substantially surrounded by the encapsulant layer 127 on all sides (e.g., embedded in the encapsulant layer 127). In at least one embodiment, the encapsulant layer 127 may be bonded to all sides of the dummy bar 500. In at least one embodiment, the dummy bar 500 may be bonded to the upper surface of the lower module portion 20 by an adhesive layer (e.g., silicone adhesive, epoxy adhesive, etc.).

[0088] The dummy bar 500 may be non-functional and may be formed of a variety of materials, such as silicon, silicon dioxide, glass, ceramic materials, metallic materials, etc. Other suitable materials may be used for the dummy bar 500. In at least one embodiment, the dummy bar 500 may have substantially the same CTE as the encapsulant layer 127. For example, the dummy bar 500 may be added to provide structural stability.

[0089] FIG. 2A to FIG. 2H Various intermediate structures are shown in a method of forming package module 120 according to one or more embodiments. Figure 2A Two vertical cross-sectional views of an intermediate structure according to an embodiment of the present invention are provided, the intermediate structure including a dummy bar 500 , a first die 141 , and a second die 142 attached to a first carrier substrate 1 (eg, a carrier wafer).

[0090] The first carrier substrate 1 may include a circular wafer or a rectangular wafer. The lateral dimensions of the first carrier substrate 1 (e.g., the diameter of a circular wafer or the side of a rectangular wafer) may be in the range of 100 mm to 500 mm, for example, 200 mm to 400 mm, although smaller and larger lateral dimensions may also be used. The first carrier substrate 1 may include a semiconductor substrate, an insulating substrate, or a conductive substrate. The first carrier substrate 1 may be transparent or opaque. The thickness of the first carrier substrate 1 may be sufficient to provide mechanical support for the array of interposers to be formed thereon. For example, the thickness of the first carrier substrate 1 may be in the range of 60 microns to 1 mm, although smaller and larger thicknesses may also be used.

[0091] The adhesive layer 5 may be applied to the top surface of the first carrier substrate 1. In one embodiment, the first carrier substrate 1 may include an optically transparent material such as glass or sapphire. In this embodiment, the adhesive layer 5 may include a light-to-heat conversion (LTHC) layer. The LTHC layer is a solvent-based coating applied using a spin coating method. The LTHC layer may form a layer that converts ultraviolet light into heat, causing the LTHC layer to lose adhesion. Alternatively, the adhesive layer 5 may include a thermally decomposable adhesive material. For example, the adhesive layer 5 may include an acrylic pressure-sensitive adhesive that decomposes at high temperatures. The peeling temperature of the thermally decomposable adhesive material may be in the range of 150° C. to 400° C. Other suitable thermally decomposable adhesive materials that decompose at other temperatures are also within the scope of the present disclosure.

[0092] like Figure 2A As shown in the upper portion of , the first die 141 and the second die 142 may be placed on the adhesive layer 5 by an electromechanical pick and place (PNP) machine. The first die 141 and the second die 142 may be placed on the adhesive layer in an inverted orientation. That is, the bulk semiconductor portions of the first die 141 and the second die 142 may be attached to the adhesive layer 5. The active regions of the first die 141 and the second die 142 opposite to the bulk semiconductor portions and connected to the die bonding pads 155 may be positioned away from the adhesive layer 5.

[0093] like Figure 2A As shown in the lower part of , the dummy bar 500 may also be placed on the adhesive layer 5 by an electromechanical pick and place (PNP) machine. The dummy bar 500 may be placed on the adhesive layer 5 so that the dummy bar 500 is located between the first die 141 and the second die 142 and the edge of the encapsulation layer 127 formed subsequently in the y direction. In addition, the dummy bar 500 may be placed on the adhesive layer 5 so that the dummy bar 500 is adjacent to the gap GD2D in the y direction. Specifically, the dummy bar 500 may be placed on the adhesive layer 5 so that the center point C500 of the dummy bar 500 in the x direction is substantially aligned with the center point CGD2D of the gap GD2D in the x direction. It should be noted that the dummy bar 500 may be placed on the adhesive layer before or after the first die 141 and the second die 142 are placed on the adhesive layer 5.

[0094] After placing the first die 141, the second die 142, and the dummy bar 500 on the adhesive layer 5, an encapsulant material (epoxy polymer material (e.g., epoxy molding compound (EMC))) for forming the encapsulant layer 127 may be deposited. The encapsulant layer 127 may be formed by performing an over-molding process and then performing a grinding (e.g., planarization) process.

[0095] Specifically, the encapsulant material may be deposited on the first die 141, the second die 142, and the dummy bar 500 on the adhesive layer 5 by a suitable deposition process. The encapsulant material may be deposited on and around the first die 141, the second die 142, and the dummy bar 500 to fill the gaps between the first die 141, the second die 142, and the dummy bar 500. The encapsulant material may encapsulate the first die 141, the second die 142, and the dummy bar 500 (for example, in the x-direction and the y-direction). Specifically, the encapsulant material may fill the gap GD2D between the first die 141 and the second die 142.

[0096] For example, the encapsulant material for the encapsulant layer 127 may be deposited by a deposition process such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), spin coating, lamination or other suitable deposition techniques. After depositing the encapsulant material, the encapsulant material may be cured in a box oven at about 150° C. for about 90 minutes to form an encapsulant layer 127 having sufficient hardness and mechanical strength.

[0097] Figure 2B is a vertical cross-sectional view of an intermediate structure after grinding the encapsulant layer 127 according to one or more embodiments. After the encapsulant layer 127 has been cured, a grinding process may then be performed to reduce the height of the upper surface of the encapsulant layer 127. Specifically, a planarization process may be performed on the upper surface of the encapsulant layer 127 until the upper surface of the die bonding pad 155 is exposed through the encapsulant layer 127. The grinding process may include, for example, a mechanical grinding process and / or a chemical mechanical polishing (CMP) process.

[0098] Figure 2C 2 is a vertical cross-sectional view of an intermediate structure after forming a passivation layer 260, a connection structure 275, and a through-hole 206 according to one or more embodiments. The passivation layer 260 may be deposited on the first die 141, the second die 142, and the encapsulation layer 127. The passivation layer 260 may be deposited, for example, by a deposition process such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), spin coating, lamination, or other suitable deposition techniques.

[0099] After the passivation layer 260 has been cured, a photolithographic process may be performed to form the conductive connectors 55 and the bonding pads 255. The photolithographic process may include forming a patterned photoresist mask (not shown) on the passivation layer 260 and etching (e.g., wet etching, dry etching, etc.) the upper surface of the passivation layer 260 exposed by the openings in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0100] One or more metal layers including metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.) may then be deposited on the passivation layer 260. Specifically, a metal layer may be formed in the openings in the passivation layer 260 to form the conductive connector 55. The metal layer may then be patterned by a lithography process to form the bonding pads 255. The lithography process may include forming a patterned photoresist mask (not shown) on the metal material and etching (e.g., wet etching, dry etching, etc.) the upper surface of the metal material exposed by the openings in the photoresist mask to form the bonding pads 255. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during an etching process.

[0101] In at least one embodiment, the bonding pad 255 may include an under bump metal (UBM) layer stack. For example, the UBM layer stack may be formed by depositing (by a suitable deposition process) a metal layer stack such as Cr / Cr-Cu / Cu / Au, Cr / Cr-Cu / Cu, TiW / Cr / Cu, Ti / Ni / Au, and Cr / Cu / Au. Other suitable materials are also within the scope of the present disclosure. The thickness of the UBM layer stack may be in the range of 5 microns to 60 microns, such as 10 microns to 30 microns, although lesser and greater thicknesses may also be used.

[0102] Then, the through-hole 206 (e.g., through-mold via (TMV)) may be formed, for example, by an electroplating process (e.g., a copper electroplating process). In at least one embodiment, the electroplating process may form a metal pillar (e.g., a copper pillar) on the UBM layer stack. The electroplating process may be performed at least until the height of the metal pillar (e.g., a copper pillar) formed by the electroplating process is greater than the final height of the through-hole 206.

[0103] Figure 2D2 is a vertical cross-sectional view of an intermediate structure including an LSI die 200 according to one or more embodiments. The LSI die 200 may be placed on the passivation layer 260, for example, using an electromechanical pick and place (PNP) machine. The LSI die 200 may be connected to the connection structures 275 on the first die 141 and the second die 142 by microbumps 228 (e.g., microbump contacts).

[0104] In at least one embodiment, the microbump 228 may include a two-dimensional array of microbumps 228, and the LSI die 200 may be connected to each of the first die 141 and the second die 142 by chip connection (C2) bonding (e.g., solder bonding). After the microbumps 228 on the LSI die 200 are disposed on the corresponding die bonding pads 155 in the first die 141 and the second die 142, a C2 bonding process of reflowing the solder portion of the microbumps 228 may be performed. Alternatively, the LSI die 200 may be mounted on the first die 141 and the second die 142 by a hybrid bonding process (e.g., metal-metal bonding, oxide-oxide bonding). It should be noted that the LSI die 200 may be mounted on the RDL portion 10 before or after forming the through-hole 206.

[0105] Then, the package module underfill layer 229 may be applied by depositing and / or injecting the epoxy polymer material onto the passivation layer 260. The epoxy polymer material may be applied onto the passivation layer 260 so as to be formed under the LSI die 200 and around the micro bumps 228. In at least one embodiment, the epoxy polymer material may substantially fill all gaps between the LSI die 200 and the passivation layer 260. Then, the epoxy polymer material may be cured, for example, at about 150° C. in a box oven for about 90 minutes to form a package module underfill layer 229 having sufficient hardness and mechanical strength.

[0106] Figure 2E 2 is a vertical cross-sectional view of an intermediate structure after thinning of the LSI die 200 according to one or more embodiments. For example, the LSI die 200 may be thinned by performing a mechanical grinding process (and / or a chemical mechanical polishing (CMP) process) on the upper surface (e.g., bulk semiconductor surface) of the LSI die 200. After the grinding process, the height of the upper surface of the LSI die 200 may remain above the height of the upper surface of the through-hole 206. Other suitable thinning techniques are also within the scope of the present disclosure.

[0107] Figure 2F 2 is a vertical cross-sectional view of an intermediate structure including a lower mold layer 227 according to one or more embodiments. The encapsulation layer 127 may be formed substantially similarly to the above-described manner (e.g., see Figure 2AThe lower molding layer 227 is formed by the method of . Figure 2F As shown, the lower molding layer 227 may be formed by performing an overmolding process followed by a planarization process. Specifically, the lower molding layer 227 may include an epoxy polymer material (e.g., epoxy molding compound (EMC)). The lower molding layer 227 may be deposited on the passivation layer 260 and fill in the gap between the LSI die 200 and the through-hole 206. The lower molding layer 227 may encapsulate the LSI die 200 and the through-hole 206 (e.g., in the x-direction and the y-direction). For example, the molding material for the lower molding layer 227 may be deposited by a deposition process such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), spin coating, lamination, or other suitable deposition techniques.

[0108] The lower mold layer 227 may be deposited to completely cover the LSI die 200 and the through-hole 206. After the lower mold layer 227 has been cured, a planarization process (e.g., chemical mechanical planarization / polishing (CMP)) may then be used to make the upper surface of the lower mold layer 227 coplanar with the upper surface of the LSI die 200 and the upper surface of the through-hole 206. Specifically, the planarization process may be performed on the upper surface of the lower mold layer 227 until the upper surface of the LSI die 200 and the upper surface of the through-hole 206 are exposed through the lower mold layer 227. The planarization process may include, for example, a mechanical grinding process and / or a CMP process.

[0109] Figure 2G 1 is a vertical cross-sectional view of an intermediate structure including an RDL portion 10 and a C4 bump 121 according to one or more embodiments. The RDL portion 10 may be formed by alternately forming a plurality of dielectric layers 12 and a plurality of redistribution layers 12a on a planarized surface of the lower molding layer 227 and on an upper surface of the LSI die 200. It should be noted that although Figure 2G Three dielectric layers 12 and three redistribution layers 12 a are shown, but more or less dielectric layers 12 and redistribution layers 12 a are also within the scope of the present disclosure.

[0110] For example, each dielectric layer 12 can be formed by depositing (e.g., by CVD, PVD or other suitable deposition techniques) a layer of dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB) or polybenzobisoxazole (PBO). Other suitable materials are also within the scope of the present disclosure. The thickness of the dielectric polymer material layer can be in the range of 4 microns to 60 microns, although smaller and larger thicknesses can also be used. The dielectric layer 12 can then be patterned by a lithography process to form a via hole in the dielectric layer 12. The lithography process can include forming a patterned photoresist mask (not shown) on the dielectric material layer and etching (e.g., wet etching, dry etching, etc.) the upper surface of the dielectric material exposed by the opening in the photoresist mask. The photoresist mask can then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0111] Then, a redistribution layer 12a (e.g., metal traces and metal vias) may be formed on the dielectric layer 12. For example, the redistribution layer 12a may be formed by depositing (e.g., by CVD, PVD, or other suitable deposition techniques) one or more metal material (e.g., copper, aluminum, nickel, titanium, combinations thereof, or other suitable metals) layers on the dielectric layer 12 and in the dielectric window holes formed by patterning the dielectric layer 12. Then, the redistribution layer 12a may be patterned by a lithography process. The lithography process may include forming a patterned photoresist mask (not shown) on the metal material layer and etching (e.g., wet etching, dry etching, etc.) the upper surface of the metal material exposed by the opening in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0112] Then, a board-side bonding pad 14a may be formed on the uppermost dielectric layer 12. The board-side bonding pad 14a may be formed by depositing (e.g., by CVD, PVD or other suitable deposition techniques) one or more metal layers, the one or more metal layers comprising metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Then, the metal layer may be patterned by a lithography process to form the board-side bonding pad 14a. The lithography process may include forming a patterned photoresist mask (not shown) on the metal material and etching (e.g., wet etching, dry etching, etc.) the upper surface of the metal material exposed by the opening in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0113] In at least one embodiment, the board-side bonding pad 14a may include an under-bump metallization (UBM) layer stack. The order of the material layers within the UBM layer stack may be selected so that the solder material portion may subsequently be bonded to a portion of the bottom surface of the UBM layer stack. Layer stacks that may be used for the UBM layer stack include, but are not limited to, stacks of Cr / Cr-Cu / Cu / Au, Cr / Cr-Cu / Cu, TiW / Cr / Cu, Ti / Ni / Au, and Cr / Cu / Au. Other suitable materials are also within the scope of the present disclosure. The thickness of the UBM layer stack may be in the range of 5 microns to 60 microns, for example, 10 microns to 30 microns, although smaller and larger thicknesses may also be used. A photoresist layer may be applied over the UBM layer stack, and the photoresist layer may be photolithographically patterned to form an array of discrete patterned photoresist material portions. An etching process may be performed to remove the unmasked portions of the UBM layer stack. The etching process may be an isotropic etching process or an anisotropic etching process. The remaining portion of the UBM layer stack may form the board-side bonding pad 14a. In at least one embodiment, the board-side bonding pads 14 a may be arranged in a two-dimensional array (eg, a two-dimensional periodic array), such as a rectangular periodic array.

[0114] Then, a board-side passivation layer 14 may be formed on the board-side surface of the RDL portion 10 and on the board-side bonding pads 14a. The board-side passivation layer may be formed by depositing (e.g., by CVD, PVD, or other suitable deposition techniques) one or more layers of passivation materials, the passivation materials including silicon oxide, silicon nitride, low-k dielectric materials such as carbon-doped oxides, very low-k dielectric materials such as porous carbon-doped silicon dioxide, combinations thereof, or other suitable materials. Then, the passivation material may be planarized (e.g., by wet etching, dry etching, chemical mechanical polishing (CMP), etc.) to form the board-side passivation layer 14.

[0115] An opening may be formed in the board-side passivation layer 14 (e.g., by a lithography process). Then, the plurality of C4 bumps 121 may be formed on the board-side bonding pads 14a through the opening in the board-side passivation layer 14. For example, the C4 bumps 121 may be formed by first forming contact pads 121a (e.g., copper / nickel contact pads) on the UBM layer through an electroplating process. Then, solder bumps 121b (e.g., SnAg solder bumps) may be formed on the contact pads 121a.

[0116] Figure 2H is a vertical cross-sectional view of an intermediate structure after peeling off the first carrier substrate 1 according to one or more embodiments.

[0117] After forming the C4 bumps 121, the first carrier substrate 1 may be peeled off from the intermediate structure. For example, the peeling off of the first carrier substrate 1 may be performed by deactivating the adhesive layer 5. For example, the adhesive layer 5 may be deactivated by thermal annealing at high temperature (e.g., for thermally deactivated adhesive materials) or by exposing the adhesive layer to ultraviolet light (e.g., for ultraviolet deactivated adhesive materials).

[0118] A plurality of package modules 120 may be formed simultaneously in a wafer-level process. After the first carrier substrate 1 is peeled off, a singulation process may be performed to singulate the package modules 120. For example, the singulation process may be performed by sawing the upper module portion 30, the lower module portion 20, and the RDL portion 10 along dicing lines using a dicing saw. The dicing lines may be located around the entire perimeter of the package module 120 and sufficiently far from the dummy bar 500 (e.g., greater than 0.1 mm).

[0119] Figure 3 1 is a flow chart illustrating a method of forming a package (e.g., package module 120) according to one or more embodiments. Step 310 includes attaching a first die and a second die to a surface. Step 320 includes attaching a dummy bar to the surface adjacent to a gap between the first die and the second die. Step 330 includes forming an encapsulation layer on the first die, the second die, and the dummy bar.

[0120] Figure 4A and Figure 4B A package 100 including a package module 120 is shown in accordance with one or more embodiments. Figure 4A is a vertical cross-sectional view of a package 100 according to one or more embodiments. Figure 4B is a plan view (eg, top view) of a package 100 according to one or more embodiments. Figure 4A The vertical section view is along Figure 4B The line B-B' is intercepted.

[0121] like Figure 4AAs shown, the package 100 may include a package substrate 110, a package module 120 located on the package substrate 110, and a package cover 130 located on the package module 120. The package substrate 110 may include a core- or core-less substrate. In at least one embodiment, for example, the package substrate 110 may include a core 112, a package substrate upper dielectric layer 114 formed on the core 112 (e.g., a first side or chip side of the package substrate 110), and a package substrate lower dielectric layer 116 formed on the core 112 (e.g., a second side or board side of the package substrate 110). Specifically, the package substrate 110 may include a build-up film substrate (e.g., an Ajinomoto build-up film (ABF) substrate). That is, in at least one embodiment, each of the package substrate upper dielectric layer 114 and the package substrate lower dielectric layer 116 may be described as an ABF layer.

[0122] The core 112 may help provide rigidity to the package substrate 110. The core 112 may include, for example, an epoxy resin (e.g., bismaleimide triazine epoxy (BT epoxy)) and / or a woven glass laminate. Alternatively or additionally, the core 112 may include an organic material, such as a polymer material. In particular, the core 112 may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the scope of the present disclosure.

[0123] The core 112 may include one or more through-holes 112a. The through-holes 112a may extend from the lower surface of the core 112 to the upper surface of the core 112. The through-holes 112a may enable electrical connection between the upper dielectric layer 114 of the package substrate and the lower dielectric layer 116 of the package substrate. The through-holes 112a may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0124] The upper package substrate dielectric layer 114 may be formed on the upper surface of the core 112. The upper package substrate dielectric layer 114 may include a plurality of layers, and in particular, may include a constituent film (e.g., ABF). The upper package substrate dielectric layer 114 may also include an organic material, such as a polymer material. In particular, the upper package substrate dielectric layer 114 may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the scope of the present disclosure.

[0125] The upper package substrate dielectric layer 114 may include one or more upper package substrate bonding pads 114a located on the chip side surface of the upper package substrate dielectric layer 114. Specifically, the upper package substrate bonding pads 114a may be exposed on the chip side surface of the upper package substrate dielectric layer 114. The upper package substrate dielectric layer 114 may also include one or more metal interconnect structures 114b. The metal interconnect structure 114b may be connected to the upper package substrate bonding pads 114a and the through-holes 112a in the core 112. The metal interconnect structure 114b may include a metal layer (e.g., a copper trace) and a metal via connecting the metal layer. The upper package substrate bonding pads 114a and the metal interconnect structure 114b may include, for example, one or more layers, and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0126] A package substrate upper passivation layer 110a may be formed on the chip side surface of the package substrate upper dielectric layer 114. The package substrate upper passivation layer 110a may partially cover the package substrate upper bonding pad 114a. The package substrate upper passivation layer 110a may include silicon oxide, silicon nitride, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0127] The package substrate lower dielectric layer 116 may be formed on the lower surface of the core 112. The package substrate lower dielectric layer 116 may also include multiple layers, and specifically, may include a constituent film (e.g., ABF). The package substrate lower dielectric layer 116 may also include an organic material, such as a polymer material. Specifically, the package substrate lower dielectric layer 116 may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the scope of the present disclosure.

[0128] The package substrate lower dielectric layer 116 may include one or more package substrate lower bonding pads 116a located on the board side surface of the package substrate lower dielectric layer 116. Specifically, the package substrate lower bonding pads 116a may be exposed on the board side surface of the package substrate lower dielectric layer 116. The package substrate lower dielectric layer 116 may also include one or more metal interconnect structures 116b. The metal interconnect structure 116b may be connected to the package substrate lower bonding pad 116a and the through hole 112a in the core 112. The metal interconnect structure 116b may include a metal layer (e.g., a copper trace) and a metal via connecting the metal layer. The package substrate lower bonding pad 116a and the metal interconnect structure 116b may include, for example, one or more layers, and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the scope of the present disclosure.

[0129] A package substrate lower passivation layer 110b may be formed on the board side surface of the package substrate lower dielectric layer 116. The package substrate lower passivation layer 110b may partially cover the package substrate lower bonding pad 116a.

[0130] The package substrate lower passivation layer 110 b may include silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0131] A ball-grid array (BGA) including a plurality of solder balls 110c may be formed on the board side surface of the lower dielectric layer 116 of the package substrate. The solder balls 110c may enable the package 100 to be securely mounted on a substrate such as a printed circuit board (PCB) and electrically coupled to the PCB substrate. The solder balls 110c may contact the lower bonding pads 116a of the package substrate, respectively. Therefore, the solder balls 110c may be electrically connected to the upper bonding pads 114a of the package substrate through the metal interconnect structure 116b, the through-hole 112a, and the metal interconnect structure 114b.

[0132] The package module 120 may be connected to the package substrate 110 by means of C4 bumps 121 on the board side surface of the RDL portion 10. Specifically, the C4 bumps 121 may be bonded (e.g., using solder reflow, compression bonding, thermal compression bonding, etc.) to the package substrate upper bonding pads 114a of the package substrate 110. Figure 4A As shown, the length of the packaging substrate 110 in the x direction may be greater than the length of the packaging module 120 in the x direction. The width of the packaging substrate 110 in the y direction may also be greater than the width of the packaging module 120 in the y direction.

[0133] A packaging underfill layer 119 may be formed on the packaging substrate 110 below and around the packaging module 120. The packaging underfill layer 119 may also be formed around the C4 bumps 121. The packaging underfill layer 119 may thereby securely fix the packaging module 120 to the packaging substrate 110. The packaging underfill layer 119 may be substantially similar to the packaging module underfill layer 229 (see Figure 1C The package bottom filling layer 119 may be formed of an epoxy-based polymer material.

[0134] The package 100 may further include a thermal interface material (TIM) layer 170 located on the package module 120. The TIM layer 170 may be located on the upper surface of the encapsulation layer 127 and on the upper surface 140a of the die 140. The TIM layer 170 may include, for example, a TIM paste, a gel TIM, a graphite TIM, a metal TIM, a solder TIM, and a carbon nanotube TIM. In at least one embodiment, the TIM layer 170 may include a film-type TIM layer. In at least one embodiment, the TIM layer 170 may include an indium-based, silver-based, and / or solder-based. Other types of TIMs are also within the scope of the present disclosure. In at least one embodiment, the TIM layer 170 may have a thickness in the range of 50 microns to 500 microns (e.g., the maximum thickness in the z direction).

[0135] The TIM layer 170 may be formed on the package module 120 to help dissipate heat generated during operation of the package 100 (e.g., operation of the die 140). The TIM layer 170 may be bonded to the package module 120, for example, by a thermally conductive adhesive. The TIM layer 170 may have a low bulk thermal resistance and high thermal conductivity. The bond-line-thickness (BLT) (e.g., the distance between the package lid 130 and the package module 120) may be less than about 100 microns, although larger or smaller distances may be used.

[0136] The package cover 130 may be located on the TIM layer 170 and connected to the package module 120. The package cover 130 may include a plate portion 130p formed on the package module 120 and a foot portion 130a located around the outer periphery of the plate portion 130p. The foot portion 130a may be fixed to the package substrate 110 by the adhesive layer 160. The plate portion 130p may contact at least a portion of the TIM layer 170. In one or more embodiments, the plate portion 130p may directly contact the entire upper surface of the TIM layer 170. The TIM layer 170 may be compressed between the plate portion 130p and the package module 120. Specifically, the TIM layer 170 may be compressed between the plate portion 130p and the upper surface of the encapsulation layer 127 and between the plate portion 130p and the upper surface 140a of the die 140.

[0137] The package cover 130 may be formed of, for example, metal, ceramic, or polymer material. The plate portion 130p of the package cover 130 may have a plate shape (eg, a planar shape) and be substantially parallel to the upper surface of the package substrate 110. The plate portion 130p may be, for example, Figure 4A The plate portion 130p may include an outer sidewall substantially aligned with the outer sidewall of the foot portion 130a. The plate portion 130p may include a center portion substantially aligned with the center portion of the package module 120 in the z direction. The plate portion 130p may include a substantially flat upper surface and a bottom surface. Alternatively, the plate portion 130p may also include a bottom step region (not shown) that may protrude from the bottom surface and contact the TIM layer 170.

[0138] The adhesive layer 160 may be formed on the package substrate 110 near the sidewall of the package module 120. The adhesive layer 160 may bond the foot portion 130a of the package cover 130 to the package substrate 110. The thickness of the adhesive layer 160 may be in the range of 50 microns to 200 microns. The adhesive layer 160 may include, for example, a silicone adhesive (e.g., including aluminum oxide, zinc oxide, resin, etc.) or an epoxy adhesive. Other suitable adhesives may be used. The adhesive layer 160 may contact the recessed upper surface of the backside metal layer or the upper molding material layer.

[0139] Refer again Figure 4B , for ease of understanding, Figure 4B The plate portion 130p of the package cover 130 and the TIM layer 170 are omitted. Figure 4B As shown, the packaging substrate 110 may have a rectangular shape in a plan view. The center of the packaging module 120 in the x-direction and the y-direction may be substantially aligned with the center of the packaging substrate 110 in the x-direction and the y-direction. The packaging substrate 110 may include a long side substantially parallel to the long side of the packaging module 120 and a short side substantially parallel to the short side of the packaging module 120.

[0140] The foot portion 130a of the package cover 130 may also include a long side substantially parallel to the long side of the package module 120 and a short side substantially parallel to the short side of the package module 120. The foot portion 130a of the package cover 130 may be continuously attached to the package substrate 110 around the entire periphery of the package module 120. In at least one embodiment, the distance D6 between the package module 120 and the foot portion 130a may be substantially uniform around the entire periphery of the package module 120. In at least one embodiment, the distance D7 between the foot portion 130a and each of the dummy bars 500 in the package module 120 may be substantially the same. The dummy bars 500 may also be positioned equidistantly in the x-direction between the opposing inner sidewalls of the foot portion 130a.

[0141] FIG. 5A to FIG. 5G Various intermediate structures are shown in a method of forming package 100 in accordance with one or more embodiments. Figure 5A is a vertical cross-sectional view of an intermediate structure including a package substrate 110 having a package substrate upper bonding pad 114a and a package substrate lower bonding pad 116a according to one or more embodiments. A package substrate 110 including a core 112, a package substrate upper dielectric layer 114, and a package substrate lower dielectric layer 116 may be provided.

[0142] The package substrate upper bonding pad 114a may be formed, for example, on the uppermost dielectric layer of the package substrate upper dielectric layer 114. The package substrate upper bonding pad 114a may be formed to contact the metal interconnect structure 114b. The package substrate upper bonding pad 114a may be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive materials) on the upper surface of the package substrate upper dielectric layer 114. Then, the metal layer may be patterned by etching (e.g., by wet etching, dry etching, etc.) to form the package substrate upper bonding pad 114a. Other suitable metal layer materials and etching processes may also be within the scope of the present disclosure.

[0143] The package substrate lower bonding pad 116a may be formed, for example, on the lowermost dielectric layer of the package substrate lower dielectric layer 116. The package substrate lower bonding pad 116a may be formed to contact the metal interconnect structure 116b. The package substrate lower bonding pad 116a may be formed in a manner similar to the manner in which the package substrate upper bonding pad 114a is formed (e.g., depositing a metal layer, patterning the metal layer by etching, etc.).

[0144] After formation, the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a may be optionally subjected to a surface roughening process (e.g., copper zarazara (CZ) process). In the surface roughening process, the surface of the package substrate upper bonding pad 114a (e.g., copper surface) and the surface of the package substrate lower bonding pad 116a (e.g., copper surface) may be etched by an organic acid-based micro-etching solution to produce an ultra-roughened surface (e.g., copper surface). The unique roughened copper surface morphology of the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a may help achieve high copper-to-resin adhesion.

[0145] Then, a package substrate upper passivation layer 110a and a package substrate lower passivation layer 110b may be formed on the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively. In at least one embodiment, the package substrate upper passivation layer 110a may include a solder resist layer (e.g., a polymer material), also referred to as a solder mask. The package substrate upper passivation layer 110a may also be referred to as an upper solder resist layer 110a, and the package substrate lower passivation layer 110b may also be referred to as a lower solder resist layer 110b.

[0146] The upper passivation layer 110a of the package substrate and the lower passivation layer 110b of the package substrate may be applied simultaneously. The upper passivation layer 110a of the package substrate and the lower passivation layer 110b of the package substrate may be applied, for example, as a liquid photo-imageable film. The liquid photo-imageable film may be applied, for example, by screen printing or spraying the liquid photo-imageable film onto the surface of the package substrate 110. The liquid photo-imageable film may be applied over the upper bonding pad 114a of the package substrate and the lower bonding pad 116a of the package substrate. Alternatively, the upper passivation layer 110a of the package substrate and the lower passivation layer 110b of the package substrate may be applied as a dry film photo-imageable film, which may be vacuum laminated onto the surface of the package substrate 110 and over the upper bonding pad 114a of the package substrate and the lower bonding pad 116a of the package substrate, respectively. Alternatively or additionally, the package substrate upper passivation layer 110 a and the package substrate lower passivation layer 110 b may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination or other suitable deposition techniques.

[0147] The package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b may be applied to have a thickness slightly greater than the thickness of the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively. Alternatively, the package substrate upper passivation layer 110a and the package substrate lower passivation layer 110b may be applied to have upper surfaces substantially coplanar with upper surfaces of the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively.

[0148] Then, an opening O110a may be formed in the upper passivation layer 110a of the package substrate to expose the upper surface of the upper bonding pad 114a of the package substrate. An opening O110b may be formed in the lower passivation layer 110b of the package substrate to expose the upper surface of the lower bonding pad 116a of the package substrate. For example, the opening O110a and the opening O110b may be formed by using a lithography process. In at least one embodiment, the opening O110a and the opening O110b may be formed in a separate lithography process.

[0149] The lithography process (e.g., process) for forming the opening O110a may include forming a patterned photoresist mask (not shown) on the package substrate upper passivation layer 110a and etching (e.g., wet etching, dry etching, etc.) the upper surface of the package substrate upper passivation layer 110a exposed by the opening in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0150] The lithography process (e.g., multiple processes) for forming the opening O110b may include forming a patterned photoresist mask (not shown) on the package substrate lower passivation layer 110b and etching (e.g., wet etching, dry etching, etc.) the upper surface of the package substrate lower passivation layer 110b exposed by the opening in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during the etching process.

[0151] After the opening O110a is formed in the upper passivation layer 110a of the package substrate and the opening O110b is formed in the lower passivation layer 110b of the package substrate, the upper passivation layer 110a (upper solder resist layer) of the package substrate and the lower passivation layer 110b (lower solder resist layer) of the package substrate can be cured, for example, by thermal curing or ultraviolet (UV) curing.

[0152] Figure 5B A vertical cross-sectional view of an intermediate structure in which a package module 120 may be mounted on a package substrate 110 according to one or more embodiments is shown. The package module 120 may be mounted on the package substrate 110, for example, by a flip chip bonding (FCB) process. The package module 120 may be positioned on the package substrate 110, for example, by a electromechanical pick and place (PNP) machine. Then, the C4 bumps 121 on the package module 120 may be lowered onto the package substrate upper bonding pads 114a of the package substrate 110 and heated to collapse the C4 bumps 121 and bond the C4 bumps 121 to the package substrate upper bonding pads 114a.

[0153] Figure 5C FIG. 1 shows a vertical cross-sectional view of an intermediate structure in which a package underfill layer 119 may be formed on a package substrate 110 according to one or more embodiments, wherein the outline of a dummy bar 500 is superimposed on the vertical cross-sectional view. The package underfill layer 119 may be formed of an epoxy-based polymer material. Figure 5CAs shown, a package underfill layer 119 may be formed (e.g., injected) under and around the package module 120 and the C4 bumps 121 to the package substrate 110. The package underfill layer 119 may then be cured in a box oven at a temperature in a range of 120° C. to 180° C. for a time in a range of 60 minutes to 120 minutes to provide the package underfill layer 119 with sufficient hardness and mechanical strength.

[0154] Figure 5D A vertical cross-sectional view of an intermediate structure in which a TIM layer 170 may be attached to (e.g., formed on) a packaging module 120 according to one or more embodiments is shown, with an outline of a dummy bar 500 superimposed on the vertical cross-sectional view. The TIM layer 170 may include, for example, a gel TIM, a graphite TIM, a metal TIM, a solder TIM, and a carbon nanotube TIM. The TIM layer 170 may be attached to the upper surface of the packaging module 120 (or the bottom surface of the TIM layer 170) by applying a thermally conductive adhesive to the upper surface of the packaging module 120 (or the bottom surface of the TIM layer 170) and then pressing the TIM layer 170 onto the packaging module 120.

[0155] Figure 5E A vertical cross-sectional view of an intermediate structure in which an adhesive layer 160 may be applied to a packaging substrate 110 according to one or more embodiments is shown. The adhesive layer 160 may be dispensed onto the packaging substrate 110 using a dispensing tool (e.g., an automatic dispensing tool). The dispensing tool may dispense the adhesive layer 160 around the frame shape of the packaging module 120. When applied, the adhesive layer 160 may be sufficiently rigid to form a semi-solid bead on the surface of the packaging substrate 110. In at least one embodiment, the viscosity of each adhesive layer 160 may be 50,000 centipoise (cp) or greater when applied. The shape of the semi-solid bead may remain substantially unchanged between the time it is applied by the dispensing tool and the time when the packaging cover 130 is later attached. The position of the frame shape of the adhesive layer 160 may correspond to the position of the foot portion 130a of the packaging cover 130 (e.g., see Figure 4B ). Pressing the packaging cover 130 onto the adhesive layer 160 may deform the adhesive layer 160 .

[0156] Fig. 5FA vertical cross-sectional view of an intermediate structure in which a package cover 130 can be attached to (e.g., mounted on) a package substrate 110 according to one or more embodiments is shown. After forming the package cover 130, for example, by milling using a computer numerical control (CNC) milling machine or by molding or stamping, the package cover 130 can be attached to the package substrate 110. In at least one embodiment, the package substrate 110 with the package module 120 can be placed on a surface. Then, the package cover 130 can be positioned on the package substrate 110, for example, by a electromechanical pick and place (PNP) machine. Then, the package cover 130 can be lowered under the package module 120 and onto the package substrate 110. Then, the foot portion 130a of the package cover 130 can be aligned with the adhesive layer 160 formed on the package substrate 110. Then, the package cover 130 may be pressed downward by applying a pressing force on the package cover 130 , so that the foot portion 130 a of the package cover 130 may be attached to the package substrate 110 through the adhesive layer 160 .

[0157] Alternatively, the package cover 130 may be inverted (e.g., flipped) and placed on a surface (e.g., a flat surface), and the package substrate 110 having the package module 120 may be inverted and inserted into the package cover 130. Then, the package substrate 110 and the package module 120 may be pressed by applying a pressing force into the package cover 130, so that the foot portion 130a of the package cover 130 may be attached to the package substrate 110 through the adhesive layer 160. The pressing force may continue to be applied so that the bottom surface of the plate portion 130p contacts the TIM layer 170. The pressing force may cause the TIM layer 170 to be compressed by the bottom surface of the plate portion 130p.

[0158] The package cover 130 may be clamped to the package substrate 110 for a period of time to allow the adhesive layer 160 to cure and form a secure bond between the package substrate 110 and the package cover 130. The clamping of the package cover 130 to the package substrate 110 may be performed, for example, by using a heat clamp module. The heat clamp module may apply a uniform force on the upper surface of the package cover 130. In one or more embodiments, the heat clamp module may apply a pressing force to the package cover 130.

[0159] Figure 5GA vertical cross-sectional view of an intermediate structure in which a plurality of solder balls 110c may be formed on a package substrate 110 according to one or more embodiments is shown. The plurality of solder balls 110c may be formed on a lower bonding pad 116a of the package substrate through an opening O110b in a lower passivation layer 110b of the package substrate. The solder balls 110c may be formed, for example, by an electroplating process. For example, the solder balls 110c may be formed to be located below the foot portion 130a and below the package module 120 and between the foot portion 130a and the package module 120. The plurality of solder balls 110c may constitute a ball grid array (BGA), which may enable the package 100 to be securely mounted (e.g., by surface mount technology (SMT)) on a substrate such as a printed circuit board and electrically coupled to the substrate. Forming the solder balls 110c may complete the formation of the package 100.

[0160] Figure 6 1 is a flow chart showing a method of forming a package 100 according to one or more embodiments. Step 610 includes attaching a package module to a package substrate, wherein the package module includes a first die and a second die in an encapsulation layer and a dummy bar in the encapsulation layer and adjacent to a gap between the first die and the second die. Step 620 includes forming an adhesive layer around the package module on the package substrate. Step 630 includes attaching a package cover to the package substrate by the adhesive layer.

[0161] Figure 7 FIG. 1 is a vertical cross-sectional view of a package 100 having a first alternative design according to one or more embodiments. The package 100 having the first alternative design may have a substantially similar Figure 4A 100. However, in an alternative design, the package 100 may also include an outer mold layer 702 formed around the package module 120. The outer mold layer 702 may include a material substantially similar to the material of the lower mold layer 227 and the encapsulation body layer 127 (e.g., epoxy molding compound). In at least one embodiment, the package module 120 may be substantially embedded in the outer mold layer 702. In at least one embodiment, the outer mold layer 702 may be formed on all sides of the package module 120 except for the bottom surface of the package module 120 that is attached to the package substrate 110. The plate portion 130p of the package cover 130 may be attached to the upper surface of the outer mold layer 702 by a thermal layer 770 (e.g., thermal paste, thermal adhesive, etc.).

[0162] The package 100 may also include one or more capacitors 704 attached to the chip side surface of the package substrate 110. The capacitors 704 may include, for example, multi-layer ceramic capacitors (MLCCs). The capacitors 704 may be located near the package module 120 and embedded in the outer mold layer 702. In at least one embodiment, the capacitors 704 may be electrically coupled to the package module 120 by the package substrate 110.

[0163] The package 100 may also include one or more integrated passive devices (IPDs) 706. The IPDs 706 may be located in (e.g., embedded in) the core 112 of the package substrate 110. The IPDs 706 may include one or more electronic components (e.g., resistors, capacitors, inductors, coils, chokes, microstrip lines, impedance matching components, baluns, etc.). The IPDs 706 may be electrically coupled to the die 140, for example, by the metal interconnect structure 114b, the package substrate upper bonding pads 114a, the RDL portion 10, and the lower module portion 20.

[0164] FIG. 8A to FIG. 8C is a plan view (top view) of a packaging module 120 having an alternative design according to one or more embodiments. Fig. 8A is a plan view of a package module 120 having a first alternative design according to one or more embodiments. In the first alternative design, the dummy bar 500 may have a square shape in plan view. Figure 8B is a plan view of a package module 120 having a second alternative design according to one or more embodiments. In the second alternative design, the dummy bar 500 may have a cross shape in plan view. Figure 8C is a plan view of a package module 120 having a third alternative design according to one or more embodiments. In the third alternative design, the dummy bar 500 may have a T-shape in plan view.

[0165] Fig. 9 FIG. 1 is a perspective view of a packaging module 120 having a fourth alternative design according to one or more embodiments. Fig. 9 As shown, in the fourth alternative design, the dummy strip 500 may have a thickness T500 that is substantially the same as the thickness of the die 140. The thickness T500 of the dummy strip 500 may also be substantially the same as the thickness of the encapsulation layer 127. With this embodiment, the surface of the dummy strip 500 may be planarized in the planarization step of the encapsulation layer 127 (see, for example, Figure 2B ).

[0166] In at least one embodiment, the dummy bar 500 may be attached to the lower molding layer 227 of the lower module portion 20 by an adhesive. In this case, the height H2 of the upper surface of the dummy bar 500 may be substantially equal to the height H1 of the upper surface of the encapsulant layer 127 (e.g., the upper surface of the upper module portion 30, the upper surface 140a of the die 140), or less than the height H1 of the upper surface of the encapsulant layer 127. In at least one embodiment, the ratio of the height of the upper surface of the encapsulant layer 127 to the height of the upper surface of the dummy bar 500 may be in the range of 1 to 10.

[0167] Now refer to Figures 1A to 9, the package 100 may include: a first die 141 and a second die 142, located in the encapsulation layer 127; and a dummy bar 500, located in the encapsulation layer 127 and adjacent to the gap GD2D between the first die and the second die 142. In one embodiment, the second die 142 may be adjacent to the first die 141 in the first direction, the gap GD2D extends longitudinally in a second direction perpendicular to the first direction, and the center of the dummy bar 500 in the first direction may be substantially aligned with the center of the gap GD2D in the first direction. In one embodiment, the dummy bar 500 may include a rectangular shape in a plan view and include a long side in the first direction and a short side in the second direction. The length of the long side of the dummy bar 500 may be in the range of 1 mm to 30 mm, and the length of the short side of the dummy bar 500 may be in the range of 0.1 mm to 10.0 mm. In one embodiment, the ratio of the length of the encapsulation layer 127 in the first direction to the length of the long side of the dummy bar 500 may be in the range of 1.5 to 15. In one embodiment, the encapsulant layer 127 may be located in the gap GD2D, and the dummy bar 500 may be adjacent to the encapsulant layer 127 in the second direction. In one embodiment, the thickness T500 of the dummy bar 500 may be in a range of 10 micrometers to 5000 micrometers. In one embodiment, the dummy bar 500 may include a silicon bar. In one embodiment, the ratio of the height of the upper surface of the encapsulant layer to the height of the upper surface of the dummy bar 500 may be in a range of 1 to 10. In one embodiment, the upper surface of the dummy bar 500 may be substantially coplanar with the upper surfaces of the first die 141 and the second die 142. In one embodiment, the package 100 may further include a package module 120, the package module 120 including: a lower module portion 20 including a lower mold layer 227 and a local silicon interconnect (LSI) die 200 located in the lower mold layer 227; and an upper module portion 30 located on the lower module portion 20 and including an encapsulant layer 127 and a first die 141, a second die 142, and a dummy bar 500 located in the encapsulant layer 127. In one embodiment, the dummy bar 500 may be mounted on the lower mold layer 227 of the lower module portion 20 and may be separated from the first die 141 and the second die 142 in a second direction. In one embodiment, the LSI die 200 may be configured to connect the first die 141 and the second die 142, and the gap is located above the LSI die 200 in a third direction perpendicular to the first direction and the second direction. In one embodiment, the encapsulant layer 127 may contact the lower molding layer 227 between the dummy bar 500 and the first and second dies 141 and 142 and between the dummy bar 500 and an edge of the lower molding layer 227 .

[0168] Refer again Figures 1A to 9, a method of forming the package 100 may include: attaching the first die 141 and the second die 142 to a surface; attaching the dummy bar 500 to the surface adjacent to the gap GD2D between the first die 141 and the second die 142; and forming the encapsulation layer 127 on the first die 141, the second die 142, and the dummy bar 500. In one embodiment, attaching the first die 141 and the second die 142 may include: attaching the first die 141 and the second die 142 such that the second die 142 may be adjacent to the first die 141 in a first direction and the gap GD2D extends longitudinally in a second direction perpendicular to the first direction. In one embodiment, attaching the dummy bar 500 may include: attaching the dummy bar 500 such that the center of the dummy bar 500 in the first direction may be substantially aligned with the center of the gap GD2D in the first direction, and such that the long side of the dummy bar 500 extends in the first direction and the short side of the dummy bar 500 extends in the second direction. In one embodiment, forming the encapsulant layer 127 may include forming the encapsulant layer 127 in the gap GD2D such that the dummy bar 500 may be adjacent to the encapsulant layer 127 in the second direction. In one embodiment, the method may also include forming a packaging module 120, the packaging module 120 including: a lower module portion 20, including a lower mold layer 227 and a local silicon interconnect (LSI) die 200 located in the lower mold layer 227; and an upper module portion 30, located on the lower module portion 20, wherein the bonding of the first die 141 and the second die 142 may include bonding the first die 141 and the second die 142 to the surface of the lower mold layer 227, the bonding of the dummy bar 500 may include bonding the dummy bar 500 to the surface of the lower mold layer 227, and forming the encapsulation layer 127 may include forming the encapsulation layer 127 on the first die 141, the second die 142 and the dummy bar 500 in the upper module portion 30.

[0169] Refer again Figures 1A to 9 The package 100 may include: a package substrate 110; a package module 120 located on the package substrate 110, including a first grain 141 and a second grain 142 located in the encapsulation layer 127, and a dummy strip 500 located in the encapsulation layer 127 and adjacent to a gap GD2D between the first grain 141 and the second grain 142; and a package cover 130 located on the package module 120 and adhered to the package substrate 110.

[0170] The above-described embodiments may provide a packaging module 120, a package 100, and a method of forming the packaging module 120 and the package 100, which may have the advantage of improving bending strength (e.g., flexural strength) and bending displacement (e.g., flexural displacement). Specifically, under bending stress (e.g., flexural stress applied downward near the gap GD2D), the packaging module 120 including one or more dummy bars 500 may have greater bending strength (e.g., at least an increase of 18%) and bending displacement (e.g., at least an increase of 21%) compared to a packaging module without the dummy bar 500. Therefore, the dummy bar 500 may increase the rigidity of the packaging module 120, and thereby help reduce the risk of die-to-die cracks (e.g., cracks in the encapsulation layer 127 in or around the gap GD2D) due to bending stress (e.g., flexural stress) on the packaging module 120, and thus improve yield loss.

[0171] According to some embodiments of the present disclosure, a package includes: a first die and a second die located in an encapsulation layer; and a dummy bar located in the encapsulation layer and adjacent to a gap between the first die and the second die.

[0172] In some embodiments, the second die is adjacent to the first die in a first direction, the gap extends longitudinally in a second direction perpendicular to the first direction, and a center of the dummy bar in the first direction is substantially aligned with a center of the gap in the first direction.

[0173] In some embodiments, the dummy bar comprises a rectangular shape in a plan view, and includes a long side in the first direction and a short side in the second direction.

[0174] In some embodiments, the length of the long side of the dummy bar is in a range from 1 mm to 30 mm, and the length of the short side of the dummy bar is in a range from 0.1 mm to 10.0 mm.

[0175] In some embodiments, a ratio of a length of the encapsulant layer in the first direction to the length of the long side of the dummy bar is in a range of 1.5 to 15.

[0176] In some embodiments, the encapsulant layer is located in the gap, and the dummy bar is adjacent to the encapsulant layer in the second direction.

[0177] In some embodiments, the thickness of the dummy strip is in a range from 10 micrometers to 5000 micrometers.

[0178] In some embodiments, the dummy strip comprises a silicon strip.

[0179] In some embodiments, a ratio of a height of an upper surface of the encapsulant layer to a height of an upper surface of the dummy bar is in a range of 1-10.

[0180] In some embodiments, an upper surface of the dummy bar is substantially coplanar with upper surfaces of the first die and the second die.

[0181] In some embodiments, the package also includes: a packaging module, including: a lower module portion, including a lower molding layer and a local silicon interconnect (LSI) die located in the lower molding layer; and an upper module portion, located on the lower module portion, and including the encapsulation layer and the first die, the second die, and the dummy strip located in the encapsulation layer.

[0182] In some embodiments, the dummy bar is mounted on the lower molding layer of the lower module portion and is separated from the first die and the second die in a second direction.

[0183] In some embodiments, the LSI die is configured to connect the first die and the second die, and the gap is located above the LSI die in a third direction perpendicular to the first direction and the second direction.

[0184] In some embodiments, the encapsulant layer contacts the lower molding layer between the dummy bar and the first and second dies and between the dummy bar and an edge of the lower molding layer.

[0185] According to some embodiments of the present disclosure, a method for forming a package includes: bonding a first die and a second die to a surface; bonding a dummy bar to the surface adjacent to a gap between the first die and the second die; and forming an encapsulation layer on the first die, the second die, and the dummy bar.

[0186] In some embodiments, the bonding of the first die and the second die includes bonding the first die and the second die such that the second die is adjacent to the first die in a first direction and the gap extends longitudinally in a second direction perpendicular to the first direction.

[0187] In some embodiments, the fitting of the dummy bar includes fitting the dummy bar so that the center of the dummy bar in the first direction is substantially aligned with the center of the gap in the first direction, and so that the long side of the dummy bar extends in the first direction and the short side of the dummy bar extends in the second direction.

[0188] In some embodiments, the forming the encapsulant layer includes forming the encapsulant layer in the gap such that the dummy bar is adjacent to the encapsulant layer in the second direction.

[0189] In some embodiments, the method also includes: forming a packaging module, the packaging module including: a lower module portion, including a lower molding layer and a local silicon interconnect (LSI) die located in the lower molding layer; and an upper module portion, located on the lower module portion, wherein the bonding of the first die and the second die includes bonding the first die and the second die to the surface of the lower molding layer, the bonding of the dummy bar includes bonding the dummy bar to the surface of the lower molding layer, and the forming of the encapsulation layer includes forming the encapsulation layer on the first die, the second die and the dummy bar in the upper module portion.

[0190] According to some embodiments of the present disclosure, a package includes: a packaging substrate; a packaging module located on the packaging substrate, including: a first grain and a second grain located in the encapsulation layer; and a dummy bar located in the encapsulation layer and adjacent to a gap between the first grain and the second grain; and a packaging cover located on the packaging module and adhered to the packaging substrate.

[0191] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them herein without departing from the spirit and scope of the present disclosure.

Claims

1. A package, characterized in that: include: The first crystal grain and the second crystal grain are located in the encapsulation layer; as well as A dummy strip is located in the encapsulation layer and is adjacent to a gap between the first crystal grain and the second crystal grain.

2. The package according to claim 1, characterized in that The second die is adjacent to the first die in a first direction, the gap extends longitudinally in a second direction perpendicular to the first direction, and a center of the dummy bar in the first direction is substantially aligned with a center of the gap in the first direction.

3. The package according to claim 2, characterized in that The dummy bar includes a rectangular shape in a plan view, and includes long sides in the first direction and short sides in the second direction.

4. The package according to claim 2, characterized in that The encapsulant layer is located in the gap, and the dummy bar is adjacent to the encapsulant layer in the second direction.

5. The package according to claim 1, characterized in that The thickness of the dummy strip is in the range of 10 micrometers to 5000 micrometers.

6. The package according to claim 1, characterized in that The dummy strip includes a silicon strip.

7. The package according to claim 1, characterized in that A ratio of a height of an upper surface of the encapsulant layer to a height of an upper surface of the dummy bar is in a range of 1 to 10.

8. The package according to claim 1, characterized in that The upper surface of the dummy strip is substantially coplanar with upper surfaces of the first die and the second die.

9. The package according to claim 1, characterized in that Also includes: Package module, including: a lower module portion, comprising a lower molding layer and a local silicon interconnect (LSI) die located in the lower molding layer; as well as The upper module part is located on the lower module part and includes the encapsulation layer and the first die, the second die and the dummy strip located in the encapsulation layer.

10. A package, characterized in that: include: Package substrate; The packaging module is located on the packaging substrate and includes: The first die and the second die are located in the encapsulation layer; and a dummy bar located in the encapsulation layer and adjacent to a gap between the first die and the second die; and The packaging cover is located on the packaging module and adhered to the packaging substrate.

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