Semiconductor device

Abstract

A semiconductor device includes a first channel region of a transistor disposed over a fin, which may include a semiconductor material extending in a first direction. A gate structure pads the first channel region and extends over the isolation region in a second direction perpendicular to the first direction, and a first portion of the gate structure extends downwardly into an indentation in an upper surface of the isolation region. The device also includes an epitaxial structure embedded in the fin on either side of the first channel region, the epitaxial structure laterally surrounded by the first interlayer dielectric.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography techniques to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise to be solved. Utility Model Content

[0004] One embodiment of the present disclosure is a semiconductor device including a first channel region of a transistor disposed above a fin, the fin including a semiconductor material extending in a first direction. A gate structure lining the first channel region and extending above an isolation region in a second direction perpendicular to the first direction, a first portion of the gate structure extending downwardly into a recess in an upper surface of the isolation region. The semiconductor device also includes an epitaxial structure embedded in the fin on either side of the first channel region, the epitaxial structure being laterally surrounded by a first interlayer dielectric.

[0005] Another embodiment of the present disclosure is a semiconductor device including a semiconductor fin extending in a first direction. A gate structure lines a channel region of the semiconductor fin and extends above an isolation region in a second direction perpendicular to the first direction, and a first portion of the gate structure extends downward into a recess in an upper surface of the isolation region. The semiconductor device also includes an epitaxial structure embedded in the semiconductor fin and on one side of the channel region, the epitaxial structure being laterally surrounded by an interlayer dielectric. The semiconductor device also includes a spacer separating the epitaxial structure from the gate structure.

[0006] Another embodiment of the present disclosure is a semiconductor device including a channel region of a transistor disposed above a fin, the fin including a semiconductor material extending in a first direction. A gate structure lining the channel region and extending above an isolation region in a second direction perpendicular to the first direction, a first portion of the gate structure extending downwardly into a recess in an upper surface of the isolation region, wherein the recess has a rounded tip shape. The semiconductor device also includes an epitaxial structure embedded in the fin and on one side of the channel region, the epitaxial structure being laterally surrounded by an interlayer dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of this disclosure are in the attachedFigure 1 The following detailed description is best understood when read together. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 illustrates an example of a nanostructured field effect transistor (nanoFET) in a three-dimensional view according to some embodiments;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Figure 8C , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.16D , Fig.16E , Fig.16F , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B , Fig. 20C , Fig.20D , Fig.21A , Fig. 21B , Fig. 21C , Fig.21D , Fig.22A , Fig. 22B , Fig. 22C ,and Fig.22D is a cross-sectional view of an intermediate stage in fabricating a nano-FET according to some embodiments;

[0010] Fig.23A , Fig. 23B , Fig.23C ,and Fig.23D is a cross-sectional view of a nano-FET according to some embodiments;

[0011] Fig.24 illustrates an example of a field-effect transistor (FET) in a three-dimensional view according to some embodiments;

[0012] Fig.25A , Fig.25B , Fig.25C , Fig.26A , Fig.26B ,and Fig.26C is a cross-sectional view of an intermediate stage in fabricating a nanoFET according to some embodiments.

[0013]

Explanation of symbols

[0014] 20: Separator

[0015] 50:Substrate

[0016] 50N: n-type region

[0017] 50P: p-type region

[0018] 51A-51C: first semiconductor layer

[0019] 52A-52C: First nanostructure

[0020] 53A-53C: Second semiconductor layer

[0021] 54A-54C: Second nanostructure

[0022] 55: Nanostructure

[0023] 56: Stacked semiconductor structure

[0024] 56F: Fins

[0025] 56M: Table fins

[0026] 60: dummy dielectric layer

[0027] 66: Fins

[0028] 68: Isolation Area / STI Area

[0029] 70: dummy dielectric layer

[0030] 71: Dummy gate dielectric

[0031] 72: Virtual gate layer

[0032] 74: Mask layer

[0033] 76: dummy gate

[0034] 78:Mask

[0035] 80: First spacer layer

[0036] 81: first spacer

[0037] 81',81": sublayer

[0038] 82: Second spacer layer

[0039] 83: Second spacer

[0040] 86: First groove

[0041] 88: Sidewall groove

[0042] 90: first inner spacer

[0043] 92: epitaxial source / drain region (source / drain region)

[0044] 92A: first semiconductor material layer

[0045] 92B: Second semiconductor material layer

[0046] 92C: third semiconductor material layer

[0047] 94: Contact Etch Stop Layer (CESL)

[0048] 96: First interlayer dielectric (ILD)

[0049] 97: Hard Mask

[0050] 98: Second groove

[0051] 100: Gate dielectric layer

[0052] 102: Gate electrode / gate structure

[0053] 104: Gate mask

[0054] 106: Second ILD

[0055] 108: The third groove

[0056] 110: Silicide region

[0057] 112: Contact

[0058] 114: Contact

[0059] 152: Fins

[0060] 158: Channel Area

[0061] A: Vertical arrow

[0062] A5: The fifth arrow

[0063] A8: The eighth arrow

[0064] CO: Dashed rectangle

[0065] d1: dotted line

[0066] F16F: Dashed line frame

[0067] F18N: Dashed line frame

[0068] F18P: Dashed line frame

[0069] w1,w2: width

[0070] h1,h2: height

[0071] D1,D2: distance

[0072] θ1,θ2: interface angle DETAILED DESCRIPTION

[0073] The following disclosure provides many different embodiments, or examples, for implementing the different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0074] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0075] Embodiments are described below in the specific context of a die including nanoFETs. However, various embodiments may be applied to die including other types of transistors (e.g., finfield effect transistors (FinFETs), planar transistors, or the like) instead of or in combination with nanoFETs.

[0076] In a dummy gate replacement process, when the dummy gate is removed to form a gate opening, the isolation region underlying the dummy gate may be exposed. The gate spacer may then be trimmed to increase the aspect ratio of the gate opening. In the trimming process, the exposed isolation region may be etched. However, since the trimming process is performed on thin vertical spacers and exposed isolation regions, etchant consumption is uneven and the isolation region may be damaged, reducing its effectiveness. An embodiment provides a free radical treatment process to oxidize the spacer layer, which provides a uniform top-to-bottom oxide layer on the spacer layer. Uniform etchant consumption is then achieved with a smoother surface and less loss in the isolation region.

[0077] Figure 1 An example of a nanoFET (e.g., a nanowire FET, a nanosheet FET (nanoFET), or the like) in a three-dimensional view according to some embodiments is illustrated. The nanoFET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, or the like) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 acts as a channel region of the nanoFET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. An isolation region 68 is disposed between adjacent fins 66, and the fins 66 may protrude from above and between adjacent isolation regions 68. Although the isolation region 68 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate or a combination of a semiconductor substrate and an isolation region. In addition, although the bottom portion of the fin 66 is illustrated as being a single material that is continuous with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or a plurality of materials. In this context, the fin 66 refers to the portion extending between adjacent isolation regions 68.

[0078] The gate dielectric layer 100 is over the top surface of the fin 66 and along the top surface, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is over the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on opposite sides of the gate dielectric layer 100 and the gate electrode 102 on the fin 66. The source / drain regions 92 may be referred to as a source or a drain, individually or collectively depending on the context.

[0079] Figure 1Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of gate electrode 102 and in a direction, for example, perpendicular to the direction of current flow between epitaxial source / drain regions 92 of the nanoFET. Cross section BB' is perpendicular to cross section AA' and parallel to the longitudinal axis of fin 66 of the nanoFET and in a direction of current flow, for example, between epitaxial source / drain regions 92 of the nanoFET. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions of the nanoFET. Cross section D-D' is parallel to cross section BB' and extends between epitaxial source / drain regions 92 and between columns of adjacent nanostructures 55. For clarity, subsequent figures refer to these reference cross sections.

[0080] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices such as planar FETs or in fin field-effect transistors (FinFETs).

[0081] Figures 2 to 20C is a cross-sectional view of an intermediate stage in fabricating a nanoFET according to some embodiments. Figures 2 to 4 , Figure 5A , Fig. 6A , Fig.13A , Fig.14A , Fig.15A , Fig.17A , Fig.18A , Fig.18B , Fig.19A , Fig. 20A , Fig.21A ,and Fig.22A Diagram Figure 1 Reference cross section AA' shown in . Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 11C , Fig. 12B , Fig.12D , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.19B , Fig. 20B , Fig. 21B ,and Fig. 22B Diagram Figure 1 Reference cross section BB' shown in . Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig. 13C , Fig. 20C , Fig. 21C ,and Fig. 22C Diagram Figure 1 Reference cross section CC' shown in . Figure 5B , Figure 6C , Figure 7C , Figure 8C , Fig.12E , Fig.13D , Fig. 14C , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.16D , Fig.16E , Fig.16F , Fig.19C , Fig.20D , Fig.21D ,and Fig.22D Diagram Figure 1 Reference cross section DD' shown in .

[0082] exist Figure 2 A substrate 50 is provided in. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally speaking, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof.

[0083] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nanoFET; the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nanoFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separation element 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0084] Further in Figure 2 In the embodiment of the present invention, a multilayer stack 64 is formed above a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustration purposes and as discussed in more detail below, the second semiconductor layer 53 will be removed and the first semiconductor layer 51 will be patterned to form a channel region of a nanoFET in the p-type region 50P. In addition, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form a channel region of a nanoFET in the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanoFET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in the p-type region 50P.

[0085] In still other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanoFET in both the n-type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon, or another semiconductor material) and may be formed simultaneously. Fig.23A , Fig. 23B ,and Fig.23C The structure resulting from such an embodiment is shown, for example, where the channel regions in both the p-type region 50P and the n-type region 50N include silicon.

[0086] For illustrative purposes, the multilayer stack 64 is illustrated as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of the first semiconductor layer 51 and the second semiconductor layer 53. Each of the layers of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nanoFET, such as silicon germanium, or the like; the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nanoFET, such as silicon, silicon carbon, or the like. For illustrative purposes, the multilayer stack 64 is illustrated as having a bottommost semiconductor layer suitable for a p-type nanoFET. In some embodiments, the multilayer stack 64 may be formed so that the bottommost layer is a semiconductor layer suitable for an n-type nanoFET.

[0087] The first semiconductor material and the second semiconductor material may be materials having high etching selectivity to each other. In this way, the first semiconductor layer 51 of the first semiconductor material in the n-type region 50N can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type nanoFET. Similarly, the second semiconductor layer 53 of the second semiconductor material in the p-type region 50P can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type nanoFET.

[0088] Reference now Figure 3According to some embodiments, fins 66 are formed in substrate 50 and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 may be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. Etching may be anisotropic. Forming nanostructure 55 by etching multilayer stack 64 may further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and define second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructure 52 and second nanostructure 54 may further be collectively referred to as nanostructure 55.

[0089] The fins 66 and nanostructures 55 may be patterned by any suitable method. For example, one or more optical lithography processes, including double patterning or multiple patterning processes, may be used to pattern the fins 66 and nanostructures 55. In general, the double patterning or multiple patterning process combines optical lithography with a self-aligned process, thereby allowing the production of patterns having, for example, a smaller pitch than that obtainable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 66.

[0090] Fin 66 and nanostructure 55 together may be referred to as stacked semiconductor structure 56 or stacked fins, including mesa fin 56M and fin 56F. Mesa fin 56M is similar to fin 56F, however, it is formed wider than fin 56F. Mesa fin 56M is capable of outputting a larger power yield due to its larger size. It should be noted that although each of fin 66 and nanostructure 55 is illustrated as having a uniform width over its entire height, in other embodiments, fin 66 and / or nanostructure 55 may have tapered sidewalls so that the width of each of fin 66 and / or nanostructure 55 increases continuously in a direction toward substrate 50. In such embodiments, each of nanostructure 55 may have different widths and be trapezoidal in shape.

[0091] exist Figure 4, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66, and the nanostructure 55 and between adjacent fins 66. The insulating material may be an oxide, nitride, or the like, or a combination thereof, such as silicon oxide, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (CVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material is formed so that an excess of the insulating material covers the nanostructure 55. Although the insulating material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not illustrated separately) may first be formed along the surface of the substrate 50, the fin 66, and the nanostructure 55. Thereafter, a fill material may be formed over the liner, such as discussed above.

[0092] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like. The planarization process exposes the nanostructure 55 so that the top surface of the nanostructure 55 and the insulating material are flush after the planarization process is completed.

[0093] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (such as a dish shape), or a combination thereof as shown. The top surface of the STI region 68 may be formed to be flat, convex, and / or concave by appropriate etching. An acceptable etching process may be used to recess the STI region 68, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than etching the material of the fins 66 and the nanostructures 55). For example, oxide removal such as using dilute hydrofluoric acid (dHF) may be used.

[0094] The above about Figures 2 to 4The process described is only one example of how to form the fins 66 and nanostructures 55. In some embodiments, a masking and epitaxial growth process may be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structure, the epitaxially grown material may be in-situ doped during growth, which may avoid prior and / or subsequent implantation, although in-situ doping and implantation doping may be used together.

[0095] In addition, for illustrative purposes, the first semiconductor layer 51 (and the resulting nanostructure 52) and the second semiconductor layer 53 (and the resulting nanostructure 54) are illustrated and discussed herein as including the same material in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials in the p-type region 50P and the n-type region 50N, or may be formed in a different order.

[0096] In addition, Figure 4 In the embodiment having different well types, a photoresist or other mask (not shown separately) may be used to achieve different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist may be formed over the fins 66 and the STI region 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using acceptable optical lithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted in the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, or the like implanted in the region at a concentration of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist may be removed, such as by an acceptable ashing process.

[0097] After or before implanting the p-type region 50P, a photoresist or other mask (not separately shown) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable optical lithography technique. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region 50N, and the photoresist may act as a mask to substantially prevent the p-type impurity from being implanted in the p-type region 50P. The p-type impurity may be boron, boron fluoride, indium, or the like implanted in the region at a concentration of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist may be removed, such as by an acceptable ashing process.

[0098] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implantation damage and activate implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation, although in-situ doping and implantation doping may be used together.

[0099] exist Figure 5A and Figure 5B In the embodiment of the present invention, a dummy dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, such as by CMP. The mask layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from the group consisting of amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing alternative materials. The dummy gate layer 72 may be made of other materials that have high etch selectivity to the etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed on the n-type region 50N and the p-type region 50P. It should be noted that for illustrative purposes, the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited so that the dummy dielectric layer 70 covers the STI region 68, so that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0100] Fig. 6A Figures 18C through 18C illustrate various additional steps in fabricating an example device. Figure 6C , Fig. 7A , Figure 7C , Fig. 8A , Figure 8C , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig.12E , Fig.13A , Fig. 13C , Fig.13D , Fig.14A , Fig. 14C , Fig.15A , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.16D , Fig.16E , Fig.16F , Fig.19C , Fig. 20C , Fig.20D , Fig. 21C , Fig.21D , Fig. 22C ,and Fig.22D Features in the n-type region 50N or the p-type region 50P are shown. Fig. 6A , Figure 6B ,and Figure 6C In the process, the mask layer 74 (see Figure 5A and Figure 5B ) is patterned to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the individual channel regions of the fins 66. The pattern of the mask 78 can be used to physically separate each of the dummy gates 76 from adjacent dummy gates 76. The dummy gates 76 can also have a length direction that is substantially perpendicular to the length direction of the individual fins 66.

[0101] exist Fig. 7A , Figure 7B ,and Figure 7C In the embodiment, the first spacer layer 80 and the second spacer layer 82 are respectively formed on Fig. 6A , Figure 6B ,and Figure 6C The first spacer layer 80 and the second spacer layer 82 will then be patterned to act as spacers for forming self-aligned source / drain regions. Fig. 7A , Figure 7B ,and Figure 7C, a first spacer 80 is formed on the top surface of the STI region 68; on the top surface and sidewalls of the fin 66, the nanostructure 55, and the mask 78; and on the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. A second spacer 82 is deposited over the first spacer 80. The first spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited using a technique such as thermal oxidation or by CVD, ALD, or the like. The second spacer 82 may be formed of a material having a different etch rate than the material of the first spacer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.

[0102] After forming the first spacer layer 80 and before forming the second spacer layer 82, an implantation for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above Figure 4 In the implant discussed in the above, a mask such as a photoresist may be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of a suitable type (e.g., p-type) may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of a suitable type (e.g., n-type) may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a range of about 1x10 15 Atom / cm 3 About 1x10 19 Atom / cm 3 Annealing can be used to repair implant damage and activate implanted impurities.

[0103] exist Fig. 8A , Figure 8B ,and Figure 8C, the first spacer 80 and the second spacer 82 are etched to form a first spacer 81 and a second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 act as self-aligned subsequently formed source and drain regions, and protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer 80 and the second spacer 82 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of the second spacer 82 has a different etching rate than the material of the first spacer 80, so that the first spacer 80 can be used as an etching stop layer when the second spacer 82 is patterned, and so that the second spacer 82 can act as a mask when the first spacer 80 is patterned. For example, an anisotropic etching process may be used to etch the second spacer layer 82, wherein the first spacer layer 80 acts as an etch stop layer, and wherein the remaining portion of the second spacer layer 82 forms the second spacer 83, such as Fig. 8A Thereafter, the second spacer 83 acts as a mask while etching the exposed portion of the first spacer layer 80 to form the first spacer 81, as shown in FIG. Fig. 8A as shown in .

[0104] like Fig. 8A As shown in FIG. 1 , the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B and Figure 8C As shown in , in some embodiments, the second spacer layer 82 may be removed from above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy dielectric layer 60. In other embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0105] It should be noted that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be patterned before depositing the second spacer layer 82), additional spacers may be formed and removed, and / or the like. Furthermore, different structures and steps may be used to form n-type and p-type devices.

[0106] exist Fig. 9A and Fig. 9BIn some embodiments, a first recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. The epitaxial source / drain region will then be formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. Fig. 9A , the top surface of the STI region 68 may be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 may be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68; or the like. The first recess 86 may be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, or the like. During the etching process for forming the first recess 86, the first spacer 81, the second spacer 83, and the mask 78 shield portions of the fin 66, the nanostructure 55, and the substrate 50. A single etching process or multiple etching processes may be used to etch each layer in the nanostructure 55 and / or the fin 66. After the first recess 86 reaches the desired depth, a timed etching process may be used to terminate the etching of the first recess 86.

[0107] exist Fig. 10A and Fig. 10B In the embodiment, the portion of the sidewalls of the layer of the multilayer stack 64 formed of the first semiconductor material (e.g., the first nanostructure 52) exposed by the first recess 86 is etched to form the sidewall recess 88 in the n-type region 50N, and the portion of the sidewalls of the layer of the multilayer stack 64 formed of the second semiconductor material (e.g., the second nanostructure 54) exposed by the first recess 86 is etched to form the sidewall recess 88 in the p-type region 50P. Fig. 10B, the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall recess 88 are shown as straight, but the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process, such as a wet etch or the like. A mask (not shown) may be used to protect the p-type region 50P while the first nanostructure 52 is etched using an etchant selective to the first semiconductor material, so that the second nanostructure 54 and the substrate 50 remain relatively unetched in the n-type region 50N compared to the first nanostructure 52. Similarly, a mask (not shown) may be used to protect the n-type region 50N while the second nanostructure 54 is etched using an etchant selective to the second semiconductor material, so that the first nanostructure 52 and the substrate 50 remain relatively unetched in the p-type region 50P compared to the second nanostructure 54. In embodiments where the first nanostructure 52 includes, for example, SiGe, and the second nanostructure 54 includes, for example, Si or SiC, a dry etching process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch the sidewalls of the first nanostructure 52 in the n-type region 50N, and a wet or dry etching process with hydrogen fluoride, another fluorine-based etchant, or the like may be used to etch the sidewalls of the second nanostructure 54 in the p-type region 50P.

[0108] exist FIG. 11A to FIG. 11C In the embodiment, the first inner spacer 90 is formed in the sidewall groove 88. The first inner spacer 90 can be formed by Fig. 10A and Fig. 10B 8. The first inner spacer 90 is formed by depositing an inner spacer layer (not shown separately) over the structure shown in . The first inner spacer 90 acts as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced by corresponding gate structures.

[0109] The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, although any suitable material may be used, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are illustrated as being flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and flush with the sidewalls of the first nanostructure 52 in the p-type region 50P, the outer sidewalls of the first inner spacer 90 may extend beyond or be recessed from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0110] In addition, although the outer side wall of the first inner partition 90 is Fig. 11B , but the outer sidewalls of the first inner spacer 90 may be concave or convex. As an example, Fig. 11C An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54 in the n-type region 50N. An embodiment is also shown in which the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the first nanostructure 52 in the p-type region 50P. The inner spacer layer can be etched by an anisotropic etching process such as RIE, NBE, or the like. The first inner spacer 90 can be used to prevent subsequent etching processes (such as etching processes used to form gate structures) from etched to subsequently formed source / drain regions (such as those described below with respect to FIG. 12A to FIG. 12E The epitaxial source / drain region 92 in question is damaged.

[0111] exist FIG. 12A to FIG. 12E In the embodiment, the epitaxial source / drain region 92 is formed in the first recess 86. In some embodiments, the source / drain region 92 can apply strain to the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. Fig. 12B As shown in FIG. 8 , epitaxial source / drain regions 92 are formed in first recesses 86 such that each dummy gate 76 is disposed between respective adjacent pairs of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate epitaxial source / drain regions 92 from dummy gates 76, and first inner spacers 90 are used to separate epitaxial source / drain regions 92 from nanostructures 55 by an appropriate lateral distance so that epitaxial source / drain regions 92 do not short circuit with a subsequently formed gate of the resulting nanoFET.

[0112] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by shielding the p-type region 50P (e.g., PMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 may include any acceptable material suitable for n-type nanoFETs. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 92 may have a surface that protrudes from the individual upper surfaces of the nanostructure 55 and may have a small facet.

[0113] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by shielding the n-type region 50N (e.g., an NMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 may include any acceptable material suitable for a p-type nanoFET. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source / drain region 92 may include a material that applies compressive strain to the first nanostructure 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain region 92 may also have a surface that protrudes from a respective surface of the multilayer stack 64 and may have a small facet.

[0114] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / source regions, similar to the process for forming lightly doped source / drain regions discussed previously, followed by annealing. The source / drain regions may have a thickness of about 1x10 19 Atom / cm 3 With about 1x10 21 Atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be in-situ doped during growth.

[0115] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surface of epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, such as Fig. 12A In other embodiments, after the epitaxy process is completed, adjacent epitaxy source / drain regions 92 remain separated, such as Fig. 12C As shown in Fig. 12A and Fig. 12C In the embodiment shown in , the first spacer 81 can be formed to the top surface of the STI region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 can cover the portion of the sidewall of the nanostructure 55 that further blocks the epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 can be adjusted to remove the spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 68.

[0116] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited above the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited above the second semiconductor material layer 92B.

[0117] Fig.12D An embodiment is shown in the figure, wherein the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Fig.12D As shown in FIG. 5 , the epitaxial source / drain region 92 may be formed to contact the first inner spacer 90 and may extend over the sidewalls of the second nanostructure 54 in the n-type region 50N and the sidewalls of the first nanostructure 52 in the p-type region 50P.

[0118] Fig.12E The source / drain regions 92 shown may be merged between the fins 66, such as Fig. 12A The merged source / drain region 92 is shown in Fig.12E In some embodiments, Fig. 12C As shown in , source / drain regions 92 may not be merged together.

[0119] exist FIG. 13A to FIG. 13D In the embodiment, the first interlayer dielectric (ILD) 96 is deposited on Fig. 6A , Fig. 12B ,and Fig. 12A Above the structure shown in ( 7A to 12D The process will not change Fig. 6A). The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass, undoped silica glass, or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacer 81. The CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material overlying the first ILD 96.

[0120] exist FIG. 14A to FIG. 14C In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within process variations. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81. In some embodiments, such as Fig. 14B As shown in FIG. 5 , in the n-type region 50N, for example, the first ILD 96 may be recessed by an etching process, and a hard mask 97 may be deposited over the first ILD 96. In other embodiments, the hard mask 97 may be omitted, such as shown in the p-type region 50P. The hard mask 97 may be formed using any suitable material, such as silicon nitride, by any suitable process, such as CVD, followed by a planarization process such as a CMP process to level the upper surface of the material, and similar processes to those discussed for the CESL 94. Fig. 14C A call out box comprising an enlarged view of the illustrated dashed rectangle CO is shown.

[0121] exist FIG. 15A to FIG. 15CIn the embodiment of the present invention, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps to form a second recess 98. The portion of the dummy dielectric layer 60 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and the dummy dielectric layer 60 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas, and the dry etching process selectively etches the dummy gate 76 at a faster rate than etching the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or covers a portion of the nanostructure 55, which serves as a channel region in the subsequently completed nanoFET. The portion of the nanostructure 55 that serves as the channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During the removal, when etching the dummy gate 76, the dummy dielectric layer 60 can be used as an etch stop layer. After removing the dummy gate 76, the dummy dielectric layer 60 can then be removed. Fig. 15C 1 and 2 further include a call-out frame of a dashed rectangle CO, which illustrates an enlarged view of removing the dummy gate 76 and forming the second groove 98. An additional process is performed on the second groove 98 to thin the first spacer 81.

[0122] FIG. 16A to FIG. 16F The process of trimming the first spacer 81 is shown. FIG. 16A to FIG. 16E The icons of each Fig. 15C Continuous process on the call out box. Fig.16F Diagram Fig.16D 6F. As described above, if conventional techniques are used to trim the first spacer 81, the etchant will attack the STI region 68 before it is consumed by the etching reaction. For example, if an oxygen plasma process is used to oxidize the first spacer 81, it is difficult for the plasma effluent including ions and radicals to reach the bottom of the second recess 98, resulting in top-to-bottom non-uniformity in the oxide layer of the first spacer 81. When an etchant is used to remove the oxide, the oxide removal is non-uniform, and more etchant may attack the bottom STI region 68, resulting in useless STI loss and the risk of leakage current through mushroom-shaped depressions and large surface roughness.

[0123] exist Fig.16A, a first free radical treatment process is performed on the first spacer 81, resulting in the formation of an oxide sublayer 81' from the exposed surface of the first spacer 81. The exposed surface of the first nanostructure 52 in the p-type region 50P and the exposed surface of the second nanostructure 54 in the n-type region 50N can also be oxidized by the first free radical treatment process. The first free radical treatment process utilizes free radicals R* of oxygen (O2), nitrogen (N2), hydrogen (H2), or a mixture thereof. The free radicals R* can be formed by generating a plasma of a processing gas or a gas mixture. The process of forming the plasma generates ions and free radicals of the processing gas or gas mixture. The effluent of the plasma can pass through a grounded gas distribution plate, which neutralizes the ions and reduces the energy of the free radicals R*. The remaining effluent can pass through one or more additional gas distribution plates to further neutralize the ions and reduce the energy of the free radicals. When the remaining free radicals R* reach the second recess 98, they combine with the exposed surface including the first spacer 81 to oxidize the sublayer 81' of the first spacer 81. This is an example of how free radicals can be formed. Other processes may be used, such as by remote excitation. The flow rate of the gas or gas mixture may be between about 100 seem and 10,000 seem, the pressure may be between about 0.01 Torr and 10 Torr, and the process temperature may be between about 100°C and 500°C.

[0124] exist Fig. 16B In the embodiment of the present invention, an etching process such as wet etching or dry etching can be used to remove the oxide sublayer 81', leaving the laterally thinned first spacer 81. If wet etching is used, the wet etching can be performed using any suitable etchant (for example, diluted HF). If dry etching is used, the dry etching can be performed by any suitable etchant (for example, HF vapor or NF3 or a mixture thereof). As a result of the first free radical treatment process and etching, the first spacer 81 can be thinned by about 0.5 to 5 nm. In addition to thinning the first spacer 81, the exposed oxidized surfaces of the first nanostructure 52 and the second nanostructure 54 can also be trimmed. Etching also causes a groove to be formed in the upper surface (exposed surface) of the STI region 68.

[0125] exist Fig. 16C In the embodiment of the present invention, a second free radical treatment process may be used to thin the first spacer 81 a second time. The second free radical treatment process is similar to the first free radical treatment process, and in some embodiments, the same gas or gas mixture as the first free radical treatment process may be used. In other embodiments, a different gas or gas mixture may be used. The second free radical treatment process oxidizes the sublayer 81" of the first spacer 81.

[0126] exist Fig.16DIn the embodiment of the present invention, another etch may be used to remove the oxide sublayer 81″, leaving the laterally thinned first spacer 81. The etch may be similar to the first etch of the oxide sublayer 81′, which may be a wet etch or a dry etch using a suitable etchant. As a result of the first free radical treatment process and the etch, the first spacer 81 may be thinned an additional amount of about 0.5 to 5 nm, for a total thinning of about 1 nm to about 10 nm. In addition to thinning the first spacer 81, the exposed oxidized surfaces of the first nanostructure 52 and the second nanostructure 54 may also be trimmed. Due to the use of a free radical oxidation process, the upper surface of the STI region 68 suffers less damage than when a conventional trimming process is used. The etch also causes the trench in the (exposed) surface above the STI region 68 to be deepened.

[0127] exist Fig.16E In the embodiment of the present invention, a gate dielectric layer 100 may be formed in the second groove 98. More details on forming the gate dielectric layer 100 are provided below.

[0128] Fig.16F yes Fig.16D Enlarged view of the dashed box F16F. Fig.16F The dashed line d1 in FIG. 5 represents where mushrooming may occur when a conventional trimming process is used instead of the embodiment process. Fig.16F Also indicated are the width w1 (measured vertically from the bottom of the second recess 98) at a first height h1=5 nm and the width w2 (measured vertically from the bottom of the second recess 98) at a second height h2=20 nm. Due to the better bottom profile and preservation of the STI region 68, the difference of w2-w1 is a positive number that can be between about 0.5 nm and 10 nm, indicating a rounded tip of the second recess 98. Conventional trimming processes will typically produce a negative difference, indicating a mushroom-shaped tip of the second recess 98. Although these relationships are used to describe the second recess 98, it should be understood that these same relationships apply to the subsequently formed gate electrode.

[0129] exist FIG. 17A to FIG. 17B , the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed, and the second recess 98 is extended. The first nanostructure 52 may be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process (such as wet etching or the like) using an etchant selective to the material of the first nanostructure 52, and the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In an embodiment where the first nanostructure 52 includes, for example, SiGe and the second nanostructures 54A-54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the first nanostructure 52 in the n-type region 50N. Fig.16A The dashed box F18N and F18P will be combined Fig.18A and Fig.18B for a more detailed discussion.

[0130] The second nanostructures 54 in the p-type region 50P may be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process (such as a wet etch or the like) using an etchant that is selective to the material of the second nanostructures 54, leaving the first nanostructures 52, the substrate 50, and the STI regions 68 relatively unetched compared to the second nanostructures 54. In embodiments where the second nanostructures 54 include, for example, SiGe and the first nanostructures 52 include, for example, Si or SiC, hydrogen fluoride, another fluorine-based etchant, or the like may be used to remove the second nanostructures 54 in the p-type region 50P.

[0131] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P may be formed simultaneously, for example, by removing the first nanostructure 52 in both the n-type region 50N and the p-type region 50P, or by removing the second nanostructure 54 in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions of the n-type nanoFET and the p-type nanoFET may have the same material composition, such as silicon, silicon germanium, or the like. Fig.23A , Fig. 23B , Fig.23C ,and Fig.23D The structure resulting from such an embodiment is shown, where the channel regions in the p-type region 50P and the n-type region 50N are provided by the second nanostructure 54 and comprise silicon, for example.

[0132] like Fig.17A As shown in FIG. 1 , in the n-type region 50N, the second nanostructure 54C has been thinned from the top, and the exposed portion of the second nanostructure 54 and the fin 66 has been thinned from the top. FIG. 16A to FIG. 16F Similarly, in the p-type region 50P, the exposed portions of the first nanostructure 52 and the fin 66 have been slightly narrowed by the oxidation and etching processes. FIG. 16A to FIG. 16F The quartz crystal is slightly narrowed due to the oxidation and etching process. Fig.17A The dashed box F18N and F18P will be combined Fig.18A and Fig.18B for a more detailed discussion.

[0133] Fig.18A and Fig.18B They are Fig.17A Enlarged view of the dashed boxes F18N and F18P. Fig.18A and Fig.18BEach is marked with vertical arrows A5 and A8. These are the fifth arrow A and the eighth arrow A, which are vertical measurements taken from the upper surface of the fin 66 to the surface of the STI region 68 between the two fins 66. Starting from the edge of the fin 66, the measurement can be taken at regular intervals, such as once every 1nm. The average STI loss is the average of the measurement of arrow A. The embodiment process provides an STI loss between about 0nm and 20nm, such as between about 6nm and 14nm. A conventional process will result in an STI loss between about 20nm and 40nm. The embodiment process can provide an STI loss reduction that is between 30% and 65% of the STI loss of a typical process.

[0134] The measurement of arrow A can also measure the roughness of the surface of STI region 68. The standard deviation of the measurement of arrow A can be calculated. 3-σ (three standard deviations) of the standard deviation can be considered to represent the roughness of the surface of STI region 68. The embodiment process provides a roughness between about 0 nm and 5 nm. A conventional process will result in a roughness between about 5 nm and 10 nm at 3-σ. The embodiment process can provide a roughness improvement that is between 25% and 75% of the roughness produced by a typical process.

[0135] exist Fig.18A and Fig.18B In FIG, interface angles θ1 and θ2 represent the angles produced by taking a line from the top edge of fin 66 to the uppermost interface of the sidewall of fin 66 and the sidewall of STI region 68 and comparing the line to a horizontal reference. The embodiment process provides interface angles θ1 and θ2 between about 50° and 80°. Since more significant STI loss is achieved using conventional processes, conventional processes result in interface angles θ1 and θ2 between about 80° and 90°. The embodiment process provides a smoother transition from the sidewall of fin 66 to the upper surface of STI region 68. Also in Fig.18A and Fig.18B , the exposed portions of the sidewalls of fin 66 have distances D1 and D2, respectively. The embodiment process provides sidewall exposures, wherein distances D1 and D2 are each between about 0 and 10 nm, such as between about 2 nm and 8 nm. Conventional processes will result in sidewall exposures, wherein the distances D1 and D2 of the sidewall exposures will be between about 10 nm and 20 nm. The sidewall exposures produced by the embodiment process are between 10% and 75% of the sidewall exposures produced by typical processes.

[0136] exist FIG. 19A to FIG. 19C, a gate dielectric layer 100 and a gate electrode 102 are formed to form a replacement gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the n-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the second nanostructure 54, and in the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 68.

[0137] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The formation method of the gate dielectric layer 100 may include molecular-beam deposition (MBD), ALD, PECVD, and the like.

[0138] The gate electrode 102 is deposited over the gate dielectric layer 100 and fills the remaining portion of the second recess 98. The gate electrode 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although Fig.17A and Fig. 17B , a single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of liner layers, any number of work function tuning layers, and filler materials. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent ones of the second nanostructures 54 in the n-type region 50N and between the second nanostructure 54A and the substrate 50, and may be deposited between adjacent ones of the first nanostructures 52 in the p-type region 50P.

[0139] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by different processes, such that the gate dielectric layer 100 may be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region may be formed by different processes, such that the gate electrode 102 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0140] After filling the second recess 98, a planarization process such as CMP may be performed to remove excess portions of the material of the gate dielectric layer 100 and the gate electrode 102 that are above the top surface of the first ILD 96. The material of the gate electrode 102 and the remaining portion of the gate dielectric layer 100 thus form a replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure."

[0141] exist FIG. 20A to FIG. 20D In the embodiment, the gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed to form a groove directly above the gate structure and between the opposing portions of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or the like) is filled in the groove, followed by a planarization process to remove excess portions of the dielectric material extending above the first ILD 96. A gate contact (such as described below) is subsequently formed. Fig.23A and Fig. 23B The gate contact 114 in question penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102 .

[0142] like FIG. 20A to FIG. 20D As further shown in FIG. 1 , a second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method such as CVD, PECVD, or the like.

[0143] exist FIG. 21A to FIG. 21DIn the embodiment of the present invention, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108 that exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process (such as RIE, NBE, or the like). In some embodiments, the third recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; the gate mask 104 can be etched using a second etching process; and then the CESL 94 can be etched using a third etching process. A mask such as a photoresist can be formed over the second ILD 106 and patterned to shield portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the third recess 108 extends into the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the third recess 108 may be flush with the epitaxial source / drain region 92 and / or the gate structure (e.g., at the same level, or at the same distance from the substrate), or lower than the epitaxial source / drain region 92 and / or the gate structure (e.g., closer to the substrate). Fig.19B The third recess 108 is illustrated as exposing the epitaxial source / drain region 92 and the gate structure in the same cross-section, but in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross-sections, thereby reducing the risk of shorting contacts formed subsequently. After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (not shown) capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source / drain region 92, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof, over the exposed portion of the epitaxial source / drain region 92 to form a silicide or germanide region, and then performing a thermal annealing process to form the silicide region 110. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, the silicide region 110 may also be a germanide region, or a silicon germanium region (eg, a region including silicide and germanide). In an embodiment, the silicide region 110 includes TiSi and has a thickness ranging from about 2 nm to about 10 nm.

[0144] Next, in FIG. 22A to FIG. 22DIn the third recess 108, contacts 112 and 114 (also referred to as contact plugs) are formed. The contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to an underlying conductive feature (e.g., the gate structure 102 and / or the silicide region 110 in the illustrated embodiment). The contact 114 is electrically coupled to the gate structure 102 and may be referred to as a gate contact, and the contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0145] FIG. 23A to FIG. 23D A cross-sectional view of a device according to some alternative embodiments is shown. Fig.23A Diagram Figure 1 Reference cross section AA' shown in . Fig. 23B Diagram Figure 1 Reference cross section BB' shown in . Fig.23C Diagram Figure 1 Reference cross section CC' shown in . Fig.23D Diagram Figure 1 The reference cross section D-D' is shown in FIG. 23A to FIG. 23D The same reference numerals indicate FIG. 22A to FIG. 22D The same components are formed by the same process. FIG. 23A to FIG. 23C In the embodiment, the channel regions in the n-type region 50N and the p-type region 50P include the same material. For example, the second nanostructure 54 including silicon provides a channel region for the p-type nanoFET in the p-type region 50P and the n-type nanoFET in the n-type region 50N. FIG. 23A to FIG. 23D The structure of can be formed, for example, by simultaneously removing the first nanostructure 52 from both the p-type region 50P and the n-type region 50N; depositing the gate dielectric layer 100 and the gate electrode 102P (e.g., suitable for the gate electrode of the p-type nanoFET) around the second nanostructure 54 in the p-type region 50P; and depositing the gate dielectric layer 100 and the gate electrode 102N (e.g., suitable for the gate electrode of the n-type nanoFET) around the second nanostructure 54 in the n-type region 50N. In such embodiments, as described above, the material of the epitaxial source / drain region 92 may be different in the n-type region 50N than in the p-type region 50P.

[0146] The above-mentioned processes for nano FETs can also be applied to FinFET devices. Fig.24An example of a FinFET in a three-dimensional view according to some embodiments is illustrated. The same reference numerals are used for the same elements, and it should be understood that the materials and processes used to form such elements may be the same or similar to the materials and processes described above. The FinFET includes a fin 152 on a substrate 50 (e.g., a semiconductor substrate). An isolation region 68 is disposed in the substrate 50, and the fin 152 protrudes from above and between adjacent isolation regions 68. Although the isolation region 68 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may be used to refer to only a semiconductor substrate or a semiconductor substrate including an isolation region. In addition, although the fin 152 is illustrated as a single material continuous with the substrate 50, the fin 152 and / or the substrate 50 may include a single material or a plurality of materials. In this context, the fin 152 refers to a portion extending between adjacent isolation regions 68.

[0147] The gate dielectric layer 100 is along the sidewalls of the fin 152 and over the top surface of the fin 152, and the gate electrode 102 is over the gate dielectric layer 100. The source / drain region 92 is disposed in the opposite side of the fin 152 relative to the gate dielectric layer 100 and the gate electrode 102. The source / drain region 92 may be referred to as a source or a drain, individually or collectively depending on the context. Fig.24 The reference cross section used in the subsequent figures is further illustrated. The cross section AA' is along the longitudinal axis of the gate electrode 102 and in a direction perpendicular to the current flow direction between the source / drain regions 92 of the FinFET, for example. The cross section AA' is similar to Figure 1 The cross section BB' is perpendicular to the cross section AA' and is along the longitudinal axis of the fin 152 and in the direction of current flow between the source / drain regions 92 of the FinFET, for example. The cross section BB' is similar to Figure 1 The cross section CC' is parallel to the cross section AA' and extends through the source / drain region 92 of the FinFET. The cross section CC' is similar to Figure 1 The cross section D-D' is also perpendicular to the cross section A-A', parallel to the cross section B-B', and between adjacent source / drain regions 92. The cross section D-D' is similar to Figure 1 For clarity, the subsequent figures refer to these reference cross sections. FinFETs can be n-type transistors or p-type transistors, and the materials and doping discussed above can be used in FinFETs in a comparable manner, depending on the type of transistor formed.

[0148] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices, such as planar FETs, nanostructure (e.g., nanosheets, nanowires, gate-all-around, or the like) field effect transistors (NSFETs), or the like.

[0149] refer to Fig.25A , Fig.25B ,and Fig.25C , Fig.25A Along Fig.24 Reference cross section A-A', Fig.25B Along the reference cross section BB', Fig.25C Along the reference cross section D-D'. FIG. 25A to FIG. 25C In the embodiment of the present invention, the substrate 50 may be patterned to form the fins 152. The patterning may be performed using the same method as described above with respect to Figure 3 The STI region 68 may be formed, flush, and recessed so that the channel region 158 protrudes from the STI region 68, similar to the above description of the process used to form the fin 66. Figure 4 A dummy dielectric layer 60 may be deposited over the channel region 158 and along the STI region 68, followed by a dummy gate electrode layer and a dummy mask layer, similar to the above description of Figure 5A and Figure 5B Next, the dummy mask layer may be patterned to form a dummy gate stack including a dummy dielectric layer 60, a dummy gate electrode, and a dummy mask, similar to the above description of FIG. 6A to FIG. 6C Gate spacers, such as first spacer 81 and second spacer 83, may be formed similarly to those described with respect to 7A to 7C as well as FIG. 8A to FIG. 8C Next, a groove may be formed in the fin 152, similar to the FIG. 9A to FIG. 9B As described above, the source / drain regions 92 may be formed in the recesses, similar to those described above with respect to the nanostructures 55. FIG. 12A to FIG. 12E CESL 94 may be formed over the mask and source / drain regions 92, followed by formation of a first ILD 96, similar to that described with respect to FIG. 13A to FIG. 13D Next, the first ILD 96 may be leveled and the gate mask removed to expose the dummy gate electrode, similar to the example of FIG. FIG. 14A to FIG. 14C as described.

[0150] Next, the dummy gate electrode may be removed to form a second recess 98. Next, the above steps of FIG. 16A to FIG. 16FThe process described thins the first spacer 81 by oxidizing the layer of the first spacer 81 using a free radical process, followed by an etching process to remove the oxide layer of the first spacer 81. The free radical process may then be repeated, followed by another etching process to further thin the first spacer 81. Because the first spacer 81 is thinned using the embodiment process, material loss in the STI region 68 may be mitigated or reduced.

[0151] refer to Fig.26A , Fig.26B ,and Fig.26C , Fig.26A Along Fig.24 Reference cross section A-A', Fig.26B Along the reference cross section BB', Fig.26C Along the reference cross section D-D'. FIG. 26A to FIG. 26C In the embodiment, a gate dielectric 100 is deposited, and a gate electrode 102 is deposited. Depending on whether the FinFET is an n-type transistor or a p-type transistor, an appropriate work function layer may be included, as described above with respect to FIG. 19A to FIG. 19C Next, the gate electrode 102 may be recessed and a gate mask 104 may be formed thereon, followed by a second ILD 106, similar to the FIG. 20A to FIG. 20D Openings for source / drain contacts 112 and gate contacts 114 may be formed similar to those described with respect to FIG. 21A to FIG. 21D Next, source / drain contacts 112 and gate contacts 114 may be formed in the openings, similar to those described with respect to FIG. 22A to FIG. 22D as described.

[0152] Embodiments may achieve advantages. For example, embodiments may reduce STI loss during a spacer trimming process that provides a reduced height-to-width aspect ratio for forming a gate electrode. In particular, in embodiments utilizing larger mesa-type fins, reduced STI loss helps reduce leakage current, which would otherwise be more difficult to control due to the large volume of the mesa-type fins. By controlling STI loss, leakage current in conventional fins may also be reduced. In addition to reducing STI loss, the sidewall spacers are thinned in a more uniform manner from top to bottom, thereby obtaining consistent results from self-thinning. In addition, the surface smoothness of the STI structure is increased. Additionally, during the trimming process, because STI loss is reduced, the sidewall exposure of the fin above the interface between the STI region and the fin is reduced, and the associated angle between the point where the STI region interfaces with the sidewall and the upper surface of the fin is also reduced.

[0153] One embodiment of the present disclosure is a method of making a semiconductor device, including removing a dummy gate above a semiconductor fin to reveal a spacer of a pad opening. The method also includes oxidizing an outer layer of the spacer by a free radical treatment process to form an oxide layer of the spacer. The method also includes etching the oxide layer of the spacer to remove the oxide layer. The method also includes forming a replacement metal gate in the opening. In an embodiment, the free radical treatment process utilizes free radicals generated by a gas or gas mixture based on oxygen, nitrogen, or hydrogen. In an embodiment, the method may include: after etching the oxide layer of the spacer, performing a second free radical treatment process to form a second oxide layer of the spacer; and etching the second oxide layer of the spacer to remove the second oxide layer. In an embodiment, etching the oxide layer removes a portion of the isolation region at the bottom of the opening. In an embodiment, the thickness of the removed portion is between 0nm and 20nm on average. In an embodiment, after removing a portion of the isolation region, the remaining portion of the isolation region is disposed at the bottom trench of the opening, wherein the surface roughness of the remaining portion of the isolation region is between 0nm and 5nm. In an embodiment, removing the dummy gate exposes a channel region of the semiconductor fin, and the method may include: oxidizing the exposed surface of the channel region by a radical treatment process to form an oxide layer of the channel region; and trimming the channel region by etching the oxide layer of the channel region by the same process as etching the oxide layer of the spacer. Before forming the replacement metal gate, the opening width at 5 nm above the bottom of the opening is the first width, and the opening width at 20 nm above the bottom of the opening is the second width, wherein the second width minus the first width is between 0.5 nm and 10 nm.

[0154] Another embodiment of the present disclosure is a method of making a semiconductor device, comprising performing a radical oxidation process on a first vertical liner of an opening, the radical oxidation process oxidizing a first layer of the first vertical liner. The method also includes etching the first layer to remove the first layer, and reducing the aspect ratio of the opening by etching the first layer. The method also includes depositing a gate dielectric on the first vertical liner in the opening. The method also includes depositing a gate electrode above the gate dielectric. In an embodiment, the opening exposes an isolation region, and the method may include etching the isolation region to form a trench in the isolation region, wherein the process of etching the isolation region is performed in the same process as etching the first layer. In an embodiment, the trench has an average depth between 0nm and 20nm, and the average depth is non-zero. In an embodiment, etching the isolation region exposes a sidewall of the semiconductor fin by a non-zero distance between 0nm and 10nm. In an embodiment, the angle from the interface of the isolation region and the sidewall to a point on the sidewall is between 50° and 80°. In an embodiment, after etching the first layer, the opening has a positive bias, and the bottom of the opening has a rounded tip shape.

[0155] Another embodiment of the present disclosure is a semiconductor device including a first channel region of a transistor disposed above a fin, the fin may include semiconductor material extending in a first direction. A gate structure lines the first channel region and extends above an isolation region in a second direction perpendicular to the first direction, a first portion of the gate structure extending downwardly into a recess in an upper surface of the isolation region. The device also includes an epitaxial structure embedded on either side of the first channel region in the fin, the epitaxial structure being laterally surrounded by a first interlayer dielectric. In an embodiment, the first distance is the sidewall-to-sidewall distance of the gate structure at a position 5 nm above the bottom surface of the gate structure; the second distance is the sidewall-to-sidewall distance of the gate structure at a position 20 nm above the bottom surface of the gate structure; and the second distance minus the first distance is between 0.5 nm and 10 nm. In an embodiment, the gate structure extends from the first channel region to a second channel region of an adjacent transistor, wherein an average loss of the isolation region below the gate structure is between 0 nm and 20 nm. In an embodiment, the roughness of the isolation region below the gate structure is between 0 nm and 5 nm. In an embodiment, the first ray has an endpoint at an upper interface between the isolation region and the fin and a second point at a top edge of the fin; and wherein the angle between the first ray and a horizontal reference is between 50° and 80°. In an embodiment, the sidewall of the fin is exposed from the isolation region by a distance between about 0 nm and 10 nm.

[0156] Another embodiment of the present disclosure is a semiconductor device including a semiconductor fin extending in a first direction. A gate structure lines a channel region of the semiconductor fin and extends above an isolation region in a second direction perpendicular to the first direction, and a first portion of the gate structure extends downward into a recess in an upper surface of the isolation region. The semiconductor device also includes an epitaxial structure embedded in the semiconductor fin and on one side of the channel region, the epitaxial structure being laterally surrounded by an interlayer dielectric, and the semiconductor device further includes a spacer separating the epitaxial structure from the gate structure. In some embodiments, the isolation region is a shallow trench isolation region.

[0157] Another embodiment of the present disclosure is a semiconductor device including a channel region of a transistor disposed above a fin, the fin may include a semiconductor material extending in a first direction. A gate structure lines the channel region and extends above an isolation region in a second direction perpendicular to the first direction, a first portion of the gate structure extending downward into a recess in an upper surface of the isolation region, wherein the recess has a rounded tip shape. The semiconductor device also includes an epitaxial structure embedded in the fin and on one side of the channel region, the epitaxial structure being laterally surrounded by an interlayer dielectric. In some embodiments, the channel region includes a plurality of nanostructures.

[0158] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: A first channel region of a transistor disposed above a fin, the fin comprising a semiconductor material extending in a first direction; A gate structure lining the first channel region and extending in a second direction perpendicular to the first direction over an isolation region, a first portion of the gate structure extending downwardly into a recess in an upper surface of the isolation region; and An epitaxial structure is embedded in the fin on either side of the first channel region and is laterally surrounded by a first interlayer dielectric.

2. The semiconductor device according to claim 1, wherein A first distance is the sidewall-to-sidewall distance of the gate structure at a position 5nm above a bottom surface of the gate structure; a second distance is the sidewall-to-sidewall distance of the gate structure at a position 20nm above the bottom surface of the gate structure; and the second distance minus the first distance is between 0.5nm and 10nm.

3. The semiconductor device according to claim 1, wherein: The gate structure extends from the first channel region to a second channel region of an adjacent transistor, and an average loss of the isolation region below the gate structure is between 0 nm and 20 nm.

4. The semiconductor device according to claim 1, wherein: The roughness of the isolation region below the gate structure is between 0 nm and 5 nm.

5. The semiconductor device according to claim 1, wherein: A first ray has an endpoint at an upper interface between the isolation region and the fin and a second point at a top edge of the fin; and an angle between the first ray and a horizontal reference is between 50° and 80°.

6. The semiconductor device according to claim 1, wherein: A sidewall of the fin is exposed from the isolation region by a distance between 0 nm and 10 nm.

7. A semiconductor device, characterized in that: Include: A semiconductor fin extending in a first direction; A gate structure lining a channel region of the semiconductor fin and extending in a second direction perpendicular to the first direction over an isolation region, a first portion of the gate structure extending downwardly into a recess in an upper surface of the isolation region; an epitaxial structure, the epitaxial structure being embedded in the semiconductor fin and on one side of the channel region, the epitaxial structure being laterally surrounded by an interlayer dielectric; and A spacer separates the epitaxial structure from the gate structure.

8. The semiconductor device according to claim 7, wherein: The isolation region is a shallow trench isolation region.

9. A semiconductor device, characterized in that: Include: A channel region of a transistor disposed above a fin, the fin comprising a semiconductor material extending in a first direction; a gate structure lining the channel region and extending in a second direction perpendicular to the first direction over an isolation region, a first portion of the gate structure extending downward into a recess in an upper surface of the isolation region, wherein the recess has a rounded tip shape; and An epitaxial structure is embedded in the fin and on one side of the channel region, and the epitaxial structure is laterally surrounded by an interlayer dielectric.

10. The semiconductor device according to claim 9, wherein: The channel region includes a plurality of nanostructures.

Images